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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/clk.h>
12#include <linux/version.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/io.h>
22#include <linux/list.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/of.h>
26#include <linux/acpi.h>
27#include <linux/pinctrl/consumer.h>
28#include <linux/reset.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32#include <linux/usb/of.h>
33#include <linux/usb/otg.h>
34
35#include "core.h"
36#include "gadget.h"
37#include "io.h"
38
39#include "debug.h"
40
41#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
42
43/**
44 * dwc3_get_dr_mode - Validates and sets dr_mode
45 * @dwc: pointer to our context structure
46 */
47static int dwc3_get_dr_mode(struct dwc3 *dwc)
48{
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
51 unsigned int hw_mode;
52
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
55
56 mode = dwc->dr_mode;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
58
59 switch (hw_mode) {
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
62 dev_err(dev,
63 "Controller does not support host mode.\n");
64 return -EINVAL;
65 }
66 mode = USB_DR_MODE_PERIPHERAL;
67 break;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
70 dev_err(dev,
71 "Controller does not support device mode.\n");
72 return -EINVAL;
73 }
74 mode = USB_DR_MODE_HOST;
75 break;
76 default:
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
81
82 /*
83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
84 * mode. If the controller supports DRD but the dr_mode is not
85 * specified or set to OTG, then set the mode to peripheral.
86 */
87 if (mode == USB_DR_MODE_OTG &&
88 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
89 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
90 !DWC3_VER_IS_PRIOR(DWC3, 330A))
91 mode = USB_DR_MODE_PERIPHERAL;
92 }
93
94 if (mode != dwc->dr_mode) {
95 dev_warn(dev,
96 "Configuration mismatch. dr_mode forced to %s\n",
97 mode == USB_DR_MODE_HOST ? "host" : "gadget");
98
99 dwc->dr_mode = mode;
100 }
101
102 return 0;
103}
104
105void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
106{
107 u32 reg;
108
109 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
110 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
111 reg |= DWC3_GCTL_PRTCAPDIR(mode);
112 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
113
114 dwc->current_dr_role = mode;
115}
116
117static int dwc3_core_soft_reset(struct dwc3 *dwc);
118
119static void __dwc3_set_mode(struct work_struct *work)
120{
121 struct dwc3 *dwc = work_to_dwc(work);
122 unsigned long flags;
123 int ret;
124 u32 reg;
125
126 mutex_lock(&dwc->mutex);
127
128 pm_runtime_get_sync(dwc->dev);
129
130 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
131 dwc3_otg_update(dwc, 0);
132
133 if (!dwc->desired_dr_role)
134 goto out;
135
136 if (dwc->desired_dr_role == dwc->current_dr_role)
137 goto out;
138
139 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
140 goto out;
141
142 switch (dwc->current_dr_role) {
143 case DWC3_GCTL_PRTCAP_HOST:
144 dwc3_host_exit(dwc);
145 break;
146 case DWC3_GCTL_PRTCAP_DEVICE:
147 dwc3_gadget_exit(dwc);
148 dwc3_event_buffers_cleanup(dwc);
149 break;
150 case DWC3_GCTL_PRTCAP_OTG:
151 dwc3_otg_exit(dwc);
152 spin_lock_irqsave(&dwc->lock, flags);
153 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
154 spin_unlock_irqrestore(&dwc->lock, flags);
155 dwc3_otg_update(dwc, 1);
156 break;
157 default:
158 break;
159 }
160
161 /* For DRD host or device mode only */
162 if (dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG) {
163 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
164 reg |= DWC3_GCTL_CORESOFTRESET;
165 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
166
167 /*
168 * Wait for internal clocks to synchronized. DWC_usb31 and
169 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
170 * keep it consistent across different IPs, let's wait up to
171 * 100ms before clearing GCTL.CORESOFTRESET.
172 */
173 msleep(100);
174
175 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
176 reg &= ~DWC3_GCTL_CORESOFTRESET;
177 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
178 }
179
180 spin_lock_irqsave(&dwc->lock, flags);
181
182 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
183
184 spin_unlock_irqrestore(&dwc->lock, flags);
185
186 switch (dwc->desired_dr_role) {
187 case DWC3_GCTL_PRTCAP_HOST:
188 ret = dwc3_host_init(dwc);
189 if (ret) {
190 dev_err(dwc->dev, "failed to initialize host\n");
191 } else {
192 if (dwc->usb2_phy)
193 otg_set_vbus(dwc->usb2_phy->otg, true);
194 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
195 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
196 if (dwc->dis_split_quirk) {
197 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
198 reg |= DWC3_GUCTL3_SPLITDISABLE;
199 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
200 }
201 }
202 break;
203 case DWC3_GCTL_PRTCAP_DEVICE:
204 dwc3_core_soft_reset(dwc);
205
206 dwc3_event_buffers_setup(dwc);
207
208 if (dwc->usb2_phy)
209 otg_set_vbus(dwc->usb2_phy->otg, false);
210 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
211 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
212
213 ret = dwc3_gadget_init(dwc);
214 if (ret)
215 dev_err(dwc->dev, "failed to initialize peripheral\n");
216 break;
217 case DWC3_GCTL_PRTCAP_OTG:
218 dwc3_otg_init(dwc);
219 dwc3_otg_update(dwc, 0);
220 break;
221 default:
222 break;
223 }
224
225out:
226 pm_runtime_mark_last_busy(dwc->dev);
227 pm_runtime_put_autosuspend(dwc->dev);
228 mutex_unlock(&dwc->mutex);
229}
230
231void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
232{
233 unsigned long flags;
234
235 if (dwc->dr_mode != USB_DR_MODE_OTG)
236 return;
237
238 spin_lock_irqsave(&dwc->lock, flags);
239 dwc->desired_dr_role = mode;
240 spin_unlock_irqrestore(&dwc->lock, flags);
241
242 queue_work(system_freezable_wq, &dwc->drd_work);
243}
244
245u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
246{
247 struct dwc3 *dwc = dep->dwc;
248 u32 reg;
249
250 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
251 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
252 DWC3_GDBGFIFOSPACE_TYPE(type));
253
254 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
255
256 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
257}
258
259/**
260 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
261 * @dwc: pointer to our context structure
262 */
263static int dwc3_core_soft_reset(struct dwc3 *dwc)
264{
265 u32 reg;
266 int retries = 1000;
267
268 /*
269 * We're resetting only the device side because, if we're in host mode,
270 * XHCI driver will reset the host block. If dwc3 was configured for
271 * host-only mode, then we can return early.
272 */
273 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
274 return 0;
275
276 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
277 reg |= DWC3_DCTL_CSFTRST;
278 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
279
280 /*
281 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
282 * is cleared only after all the clocks are synchronized. This can
283 * take a little more than 50ms. Set the polling rate at 20ms
284 * for 10 times instead.
285 */
286 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
287 retries = 10;
288
289 do {
290 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
291 if (!(reg & DWC3_DCTL_CSFTRST))
292 goto done;
293
294 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
295 msleep(20);
296 else
297 udelay(1);
298 } while (--retries);
299
300 return -ETIMEDOUT;
301
302done:
303 /*
304 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
305 * is cleared, we must wait at least 50ms before accessing the PHY
306 * domain (synchronization delay).
307 */
308 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
309 msleep(50);
310
311 return 0;
312}
313
314/*
315 * dwc3_frame_length_adjustment - Adjusts frame length if required
316 * @dwc3: Pointer to our controller context structure
317 */
318static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
319{
320 u32 reg;
321 u32 dft;
322
323 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
324 return;
325
326 if (dwc->fladj == 0)
327 return;
328
329 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
330 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
331 if (dft != dwc->fladj) {
332 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
333 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
334 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
335 }
336}
337
338/**
339 * dwc3_free_one_event_buffer - Frees one event buffer
340 * @dwc: Pointer to our controller context structure
341 * @evt: Pointer to event buffer to be freed
342 */
343static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
344 struct dwc3_event_buffer *evt)
345{
346 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
347}
348
349/**
350 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
351 * @dwc: Pointer to our controller context structure
352 * @length: size of the event buffer
353 *
354 * Returns a pointer to the allocated event buffer structure on success
355 * otherwise ERR_PTR(errno).
356 */
357static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
358 unsigned length)
359{
360 struct dwc3_event_buffer *evt;
361
362 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
363 if (!evt)
364 return ERR_PTR(-ENOMEM);
365
366 evt->dwc = dwc;
367 evt->length = length;
368 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
369 if (!evt->cache)
370 return ERR_PTR(-ENOMEM);
371
372 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
373 &evt->dma, GFP_KERNEL);
374 if (!evt->buf)
375 return ERR_PTR(-ENOMEM);
376
377 return evt;
378}
379
380/**
381 * dwc3_free_event_buffers - frees all allocated event buffers
382 * @dwc: Pointer to our controller context structure
383 */
384static void dwc3_free_event_buffers(struct dwc3 *dwc)
385{
386 struct dwc3_event_buffer *evt;
387
388 evt = dwc->ev_buf;
389 if (evt)
390 dwc3_free_one_event_buffer(dwc, evt);
391}
392
393/**
394 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
395 * @dwc: pointer to our controller context structure
396 * @length: size of event buffer
397 *
398 * Returns 0 on success otherwise negative errno. In the error case, dwc
399 * may contain some buffers allocated but not all which were requested.
400 */
401static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
402{
403 struct dwc3_event_buffer *evt;
404
405 evt = dwc3_alloc_one_event_buffer(dwc, length);
406 if (IS_ERR(evt)) {
407 dev_err(dwc->dev, "can't allocate event buffer\n");
408 return PTR_ERR(evt);
409 }
410 dwc->ev_buf = evt;
411
412 return 0;
413}
414
415/**
416 * dwc3_event_buffers_setup - setup our allocated event buffers
417 * @dwc: pointer to our controller context structure
418 *
419 * Returns 0 on success otherwise negative errno.
420 */
421int dwc3_event_buffers_setup(struct dwc3 *dwc)
422{
423 struct dwc3_event_buffer *evt;
424
425 evt = dwc->ev_buf;
426 evt->lpos = 0;
427 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
428 lower_32_bits(evt->dma));
429 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
430 upper_32_bits(evt->dma));
431 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
432 DWC3_GEVNTSIZ_SIZE(evt->length));
433 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
434
435 return 0;
436}
437
438void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
439{
440 struct dwc3_event_buffer *evt;
441
442 evt = dwc->ev_buf;
443
444 evt->lpos = 0;
445
446 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
447 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
448 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
449 | DWC3_GEVNTSIZ_SIZE(0));
450 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
451}
452
453static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
454{
455 if (!dwc->has_hibernation)
456 return 0;
457
458 if (!dwc->nr_scratch)
459 return 0;
460
461 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
462 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
463 if (!dwc->scratchbuf)
464 return -ENOMEM;
465
466 return 0;
467}
468
469static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
470{
471 dma_addr_t scratch_addr;
472 u32 param;
473 int ret;
474
475 if (!dwc->has_hibernation)
476 return 0;
477
478 if (!dwc->nr_scratch)
479 return 0;
480
481 /* should never fall here */
482 if (!WARN_ON(dwc->scratchbuf))
483 return 0;
484
485 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
486 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
487 DMA_BIDIRECTIONAL);
488 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
489 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
490 ret = -EFAULT;
491 goto err0;
492 }
493
494 dwc->scratch_addr = scratch_addr;
495
496 param = lower_32_bits(scratch_addr);
497
498 ret = dwc3_send_gadget_generic_command(dwc,
499 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
500 if (ret < 0)
501 goto err1;
502
503 param = upper_32_bits(scratch_addr);
504
505 ret = dwc3_send_gadget_generic_command(dwc,
506 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
507 if (ret < 0)
508 goto err1;
509
510 return 0;
511
512err1:
513 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
514 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
515
516err0:
517 return ret;
518}
519
520static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
521{
522 if (!dwc->has_hibernation)
523 return;
524
525 if (!dwc->nr_scratch)
526 return;
527
528 /* should never fall here */
529 if (!WARN_ON(dwc->scratchbuf))
530 return;
531
532 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
533 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
534 kfree(dwc->scratchbuf);
535}
536
537static void dwc3_core_num_eps(struct dwc3 *dwc)
538{
539 struct dwc3_hwparams *parms = &dwc->hwparams;
540
541 dwc->num_eps = DWC3_NUM_EPS(parms);
542}
543
544static void dwc3_cache_hwparams(struct dwc3 *dwc)
545{
546 struct dwc3_hwparams *parms = &dwc->hwparams;
547
548 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
549 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
550 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
551 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
552 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
553 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
554 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
555 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
556 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
557
558 if (DWC3_IP_IS(DWC32))
559 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
560}
561
562static int dwc3_core_ulpi_init(struct dwc3 *dwc)
563{
564 int intf;
565 int ret = 0;
566
567 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
568
569 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
570 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
571 dwc->hsphy_interface &&
572 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
573 ret = dwc3_ulpi_init(dwc);
574
575 return ret;
576}
577
578/**
579 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
580 * @dwc: Pointer to our controller context structure
581 *
582 * Returns 0 on success. The USB PHY interfaces are configured but not
583 * initialized. The PHY interfaces and the PHYs get initialized together with
584 * the core in dwc3_core_init.
585 */
586static int dwc3_phy_setup(struct dwc3 *dwc)
587{
588 unsigned int hw_mode;
589 u32 reg;
590
591 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
592
593 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
594
595 /*
596 * Make sure UX_EXIT_PX is cleared as that causes issues with some
597 * PHYs. Also, this bit is not supposed to be used in normal operation.
598 */
599 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
600
601 /*
602 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
603 * to '0' during coreConsultant configuration. So default value
604 * will be '0' when the core is reset. Application needs to set it
605 * to '1' after the core initialization is completed.
606 */
607 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
608 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
609
610 /*
611 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
612 * power-on reset, and it can be set after core initialization, which is
613 * after device soft-reset during initialization.
614 */
615 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
616 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
617
618 if (dwc->u2ss_inp3_quirk)
619 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
620
621 if (dwc->dis_rxdet_inp3_quirk)
622 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
623
624 if (dwc->req_p1p2p3_quirk)
625 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
626
627 if (dwc->del_p1p2p3_quirk)
628 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
629
630 if (dwc->del_phy_power_chg_quirk)
631 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
632
633 if (dwc->lfps_filter_quirk)
634 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
635
636 if (dwc->rx_detect_poll_quirk)
637 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
638
639 if (dwc->tx_de_emphasis_quirk)
640 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
641
642 if (dwc->dis_u3_susphy_quirk)
643 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
644
645 if (dwc->dis_del_phy_power_chg_quirk)
646 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
647
648 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
649
650 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
651
652 /* Select the HS PHY interface */
653 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
654 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
655 if (dwc->hsphy_interface &&
656 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
657 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
658 break;
659 } else if (dwc->hsphy_interface &&
660 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
661 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
662 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
663 } else {
664 /* Relying on default value. */
665 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
666 break;
667 }
668 fallthrough;
669 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
670 default:
671 break;
672 }
673
674 switch (dwc->hsphy_mode) {
675 case USBPHY_INTERFACE_MODE_UTMI:
676 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
677 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
678 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
679 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
680 break;
681 case USBPHY_INTERFACE_MODE_UTMIW:
682 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
683 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
684 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
685 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
686 break;
687 default:
688 break;
689 }
690
691 /*
692 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
693 * '0' during coreConsultant configuration. So default value will
694 * be '0' when the core is reset. Application needs to set it to
695 * '1' after the core initialization is completed.
696 */
697 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
698 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
699
700 /*
701 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
702 * power-on reset, and it can be set after core initialization, which is
703 * after device soft-reset during initialization.
704 */
705 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
706 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
707
708 if (dwc->dis_u2_susphy_quirk)
709 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
710
711 if (dwc->dis_enblslpm_quirk)
712 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
713 else
714 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
715
716 if (dwc->dis_u2_freeclk_exists_quirk)
717 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
718
719 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
720
721 return 0;
722}
723
724static void dwc3_core_exit(struct dwc3 *dwc)
725{
726 dwc3_event_buffers_cleanup(dwc);
727
728 usb_phy_shutdown(dwc->usb2_phy);
729 usb_phy_shutdown(dwc->usb3_phy);
730 phy_exit(dwc->usb2_generic_phy);
731 phy_exit(dwc->usb3_generic_phy);
732
733 usb_phy_set_suspend(dwc->usb2_phy, 1);
734 usb_phy_set_suspend(dwc->usb3_phy, 1);
735 phy_power_off(dwc->usb2_generic_phy);
736 phy_power_off(dwc->usb3_generic_phy);
737 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
738 reset_control_assert(dwc->reset);
739}
740
741static bool dwc3_core_is_valid(struct dwc3 *dwc)
742{
743 u32 reg;
744
745 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
746 dwc->ip = DWC3_GSNPS_ID(reg);
747
748 /* This should read as U3 followed by revision number */
749 if (DWC3_IP_IS(DWC3)) {
750 dwc->revision = reg;
751 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
752 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
753 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
754 } else {
755 return false;
756 }
757
758 return true;
759}
760
761static void dwc3_core_setup_global_control(struct dwc3 *dwc)
762{
763 u32 hwparams4 = dwc->hwparams.hwparams4;
764 u32 reg;
765
766 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
767 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
768
769 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
770 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
771 /**
772 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
773 * issue which would cause xHCI compliance tests to fail.
774 *
775 * Because of that we cannot enable clock gating on such
776 * configurations.
777 *
778 * Refers to:
779 *
780 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
781 * SOF/ITP Mode Used
782 */
783 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
784 dwc->dr_mode == USB_DR_MODE_OTG) &&
785 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
786 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
787 else
788 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
789 break;
790 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
791 /* enable hibernation here */
792 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
793
794 /*
795 * REVISIT Enabling this bit so that host-mode hibernation
796 * will work. Device-mode hibernation is not yet implemented.
797 */
798 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
799 break;
800 default:
801 /* nothing */
802 break;
803 }
804
805 /* check if current dwc3 is on simulation board */
806 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
807 dev_info(dwc->dev, "Running with FPGA optimizations\n");
808 dwc->is_fpga = true;
809 }
810
811 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
812 "disable_scramble cannot be used on non-FPGA builds\n");
813
814 if (dwc->disable_scramble_quirk && dwc->is_fpga)
815 reg |= DWC3_GCTL_DISSCRAMBLE;
816 else
817 reg &= ~DWC3_GCTL_DISSCRAMBLE;
818
819 if (dwc->u2exit_lfps_quirk)
820 reg |= DWC3_GCTL_U2EXIT_LFPS;
821
822 /*
823 * WORKAROUND: DWC3 revisions <1.90a have a bug
824 * where the device can fail to connect at SuperSpeed
825 * and falls back to high-speed mode which causes
826 * the device to enter a Connect/Disconnect loop
827 */
828 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
829 reg |= DWC3_GCTL_U2RSTECN;
830
831 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
832}
833
834static int dwc3_core_get_phy(struct dwc3 *dwc);
835static int dwc3_core_ulpi_init(struct dwc3 *dwc);
836
837/* set global incr burst type configuration registers */
838static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
839{
840 struct device *dev = dwc->dev;
841 /* incrx_mode : for INCR burst type. */
842 bool incrx_mode;
843 /* incrx_size : for size of INCRX burst. */
844 u32 incrx_size;
845 u32 *vals;
846 u32 cfg;
847 int ntype;
848 int ret;
849 int i;
850
851 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
852
853 /*
854 * Handle property "snps,incr-burst-type-adjustment".
855 * Get the number of value from this property:
856 * result <= 0, means this property is not supported.
857 * result = 1, means INCRx burst mode supported.
858 * result > 1, means undefined length burst mode supported.
859 */
860 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
861 if (ntype <= 0)
862 return;
863
864 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
865 if (!vals) {
866 dev_err(dev, "Error to get memory\n");
867 return;
868 }
869
870 /* Get INCR burst type, and parse it */
871 ret = device_property_read_u32_array(dev,
872 "snps,incr-burst-type-adjustment", vals, ntype);
873 if (ret) {
874 kfree(vals);
875 dev_err(dev, "Error to get property\n");
876 return;
877 }
878
879 incrx_size = *vals;
880
881 if (ntype > 1) {
882 /* INCRX (undefined length) burst mode */
883 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
884 for (i = 1; i < ntype; i++) {
885 if (vals[i] > incrx_size)
886 incrx_size = vals[i];
887 }
888 } else {
889 /* INCRX burst mode */
890 incrx_mode = INCRX_BURST_MODE;
891 }
892
893 kfree(vals);
894
895 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
896 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
897 if (incrx_mode)
898 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
899 switch (incrx_size) {
900 case 256:
901 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
902 break;
903 case 128:
904 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
905 break;
906 case 64:
907 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
908 break;
909 case 32:
910 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
911 break;
912 case 16:
913 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
914 break;
915 case 8:
916 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
917 break;
918 case 4:
919 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
920 break;
921 case 1:
922 break;
923 default:
924 dev_err(dev, "Invalid property\n");
925 break;
926 }
927
928 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
929}
930
931/**
932 * dwc3_core_init - Low-level initialization of DWC3 Core
933 * @dwc: Pointer to our controller context structure
934 *
935 * Returns 0 on success otherwise negative errno.
936 */
937static int dwc3_core_init(struct dwc3 *dwc)
938{
939 unsigned int hw_mode;
940 u32 reg;
941 int ret;
942
943 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
944
945 /*
946 * Write Linux Version Code to our GUID register so it's easy to figure
947 * out which kernel version a bug was found.
948 */
949 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
950
951 ret = dwc3_phy_setup(dwc);
952 if (ret)
953 goto err0;
954
955 if (!dwc->ulpi_ready) {
956 ret = dwc3_core_ulpi_init(dwc);
957 if (ret)
958 goto err0;
959 dwc->ulpi_ready = true;
960 }
961
962 if (!dwc->phys_ready) {
963 ret = dwc3_core_get_phy(dwc);
964 if (ret)
965 goto err0a;
966 dwc->phys_ready = true;
967 }
968
969 usb_phy_init(dwc->usb2_phy);
970 usb_phy_init(dwc->usb3_phy);
971 ret = phy_init(dwc->usb2_generic_phy);
972 if (ret < 0)
973 goto err0a;
974
975 ret = phy_init(dwc->usb3_generic_phy);
976 if (ret < 0) {
977 phy_exit(dwc->usb2_generic_phy);
978 goto err0a;
979 }
980
981 ret = dwc3_core_soft_reset(dwc);
982 if (ret)
983 goto err1;
984
985 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
986 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
987 if (!dwc->dis_u3_susphy_quirk) {
988 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
989 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
990 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
991 }
992
993 if (!dwc->dis_u2_susphy_quirk) {
994 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
995 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
996 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
997 }
998 }
999
1000 dwc3_core_setup_global_control(dwc);
1001 dwc3_core_num_eps(dwc);
1002
1003 ret = dwc3_setup_scratch_buffers(dwc);
1004 if (ret)
1005 goto err1;
1006
1007 /* Adjust Frame Length */
1008 dwc3_frame_length_adjustment(dwc);
1009
1010 dwc3_set_incr_burst_type(dwc);
1011
1012 usb_phy_set_suspend(dwc->usb2_phy, 0);
1013 usb_phy_set_suspend(dwc->usb3_phy, 0);
1014 ret = phy_power_on(dwc->usb2_generic_phy);
1015 if (ret < 0)
1016 goto err2;
1017
1018 ret = phy_power_on(dwc->usb3_generic_phy);
1019 if (ret < 0)
1020 goto err3;
1021
1022 ret = dwc3_event_buffers_setup(dwc);
1023 if (ret) {
1024 dev_err(dwc->dev, "failed to setup event buffers\n");
1025 goto err4;
1026 }
1027
1028 /*
1029 * ENDXFER polling is available on version 3.10a and later of
1030 * the DWC_usb3 controller. It is NOT available in the
1031 * DWC_usb31 controller.
1032 */
1033 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1034 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1035 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1036 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1037 }
1038
1039 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1040 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1041
1042 /*
1043 * Enable hardware control of sending remote wakeup
1044 * in HS when the device is in the L1 state.
1045 */
1046 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1047 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1048
1049 if (dwc->dis_tx_ipgap_linecheck_quirk)
1050 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1051
1052 if (dwc->parkmode_disable_ss_quirk)
1053 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1054
1055 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1056 }
1057
1058 if (dwc->dr_mode == USB_DR_MODE_HOST ||
1059 dwc->dr_mode == USB_DR_MODE_OTG) {
1060 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1061
1062 /*
1063 * Enable Auto retry Feature to make the controller operating in
1064 * Host mode on seeing transaction errors(CRC errors or internal
1065 * overrun scenerios) on IN transfers to reply to the device
1066 * with a non-terminating retry ACK (i.e, an ACK transcation
1067 * packet with Retry=1 & Nump != 0)
1068 */
1069 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1070
1071 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1072 }
1073
1074 /*
1075 * Must config both number of packets and max burst settings to enable
1076 * RX and/or TX threshold.
1077 */
1078 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1079 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1080 u8 rx_maxburst = dwc->rx_max_burst_prd;
1081 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1082 u8 tx_maxburst = dwc->tx_max_burst_prd;
1083
1084 if (rx_thr_num && rx_maxburst) {
1085 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1086 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1087
1088 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1089 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1090
1091 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1092 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1093
1094 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1095 }
1096
1097 if (tx_thr_num && tx_maxburst) {
1098 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1099 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1100
1101 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1102 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1103
1104 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1105 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1106
1107 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1108 }
1109 }
1110
1111 return 0;
1112
1113err4:
1114 phy_power_off(dwc->usb3_generic_phy);
1115
1116err3:
1117 phy_power_off(dwc->usb2_generic_phy);
1118
1119err2:
1120 usb_phy_set_suspend(dwc->usb2_phy, 1);
1121 usb_phy_set_suspend(dwc->usb3_phy, 1);
1122
1123err1:
1124 usb_phy_shutdown(dwc->usb2_phy);
1125 usb_phy_shutdown(dwc->usb3_phy);
1126 phy_exit(dwc->usb2_generic_phy);
1127 phy_exit(dwc->usb3_generic_phy);
1128
1129err0a:
1130 dwc3_ulpi_exit(dwc);
1131
1132err0:
1133 return ret;
1134}
1135
1136static int dwc3_core_get_phy(struct dwc3 *dwc)
1137{
1138 struct device *dev = dwc->dev;
1139 struct device_node *node = dev->of_node;
1140 int ret;
1141
1142 if (node) {
1143 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1144 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1145 } else {
1146 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1147 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1148 }
1149
1150 if (IS_ERR(dwc->usb2_phy)) {
1151 ret = PTR_ERR(dwc->usb2_phy);
1152 if (ret == -ENXIO || ret == -ENODEV) {
1153 dwc->usb2_phy = NULL;
1154 } else {
1155 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1156 }
1157 }
1158
1159 if (IS_ERR(dwc->usb3_phy)) {
1160 ret = PTR_ERR(dwc->usb3_phy);
1161 if (ret == -ENXIO || ret == -ENODEV) {
1162 dwc->usb3_phy = NULL;
1163 } else {
1164 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1165 }
1166 }
1167
1168 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1169 if (IS_ERR(dwc->usb2_generic_phy)) {
1170 ret = PTR_ERR(dwc->usb2_generic_phy);
1171 if (ret == -ENOSYS || ret == -ENODEV) {
1172 dwc->usb2_generic_phy = NULL;
1173 } else {
1174 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1175 }
1176 }
1177
1178 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1179 if (IS_ERR(dwc->usb3_generic_phy)) {
1180 ret = PTR_ERR(dwc->usb3_generic_phy);
1181 if (ret == -ENOSYS || ret == -ENODEV) {
1182 dwc->usb3_generic_phy = NULL;
1183 } else {
1184 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1185 }
1186 }
1187
1188 return 0;
1189}
1190
1191static int dwc3_core_init_mode(struct dwc3 *dwc)
1192{
1193 struct device *dev = dwc->dev;
1194 int ret;
1195
1196 switch (dwc->dr_mode) {
1197 case USB_DR_MODE_PERIPHERAL:
1198 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1199
1200 if (dwc->usb2_phy)
1201 otg_set_vbus(dwc->usb2_phy->otg, false);
1202 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1203 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1204
1205 ret = dwc3_gadget_init(dwc);
1206 if (ret)
1207 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1208 break;
1209 case USB_DR_MODE_HOST:
1210 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1211
1212 if (dwc->usb2_phy)
1213 otg_set_vbus(dwc->usb2_phy->otg, true);
1214 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1215 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1216
1217 ret = dwc3_host_init(dwc);
1218 if (ret)
1219 return dev_err_probe(dev, ret, "failed to initialize host\n");
1220 break;
1221 case USB_DR_MODE_OTG:
1222 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1223 ret = dwc3_drd_init(dwc);
1224 if (ret)
1225 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1226 break;
1227 default:
1228 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1229 return -EINVAL;
1230 }
1231
1232 return 0;
1233}
1234
1235static void dwc3_core_exit_mode(struct dwc3 *dwc)
1236{
1237 switch (dwc->dr_mode) {
1238 case USB_DR_MODE_PERIPHERAL:
1239 dwc3_gadget_exit(dwc);
1240 break;
1241 case USB_DR_MODE_HOST:
1242 dwc3_host_exit(dwc);
1243 break;
1244 case USB_DR_MODE_OTG:
1245 dwc3_drd_exit(dwc);
1246 break;
1247 default:
1248 /* do nothing */
1249 break;
1250 }
1251
1252 /* de-assert DRVVBUS for HOST and OTG mode */
1253 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1254}
1255
1256static void dwc3_get_properties(struct dwc3 *dwc)
1257{
1258 struct device *dev = dwc->dev;
1259 u8 lpm_nyet_threshold;
1260 u8 tx_de_emphasis;
1261 u8 hird_threshold;
1262 u8 rx_thr_num_pkt_prd;
1263 u8 rx_max_burst_prd;
1264 u8 tx_thr_num_pkt_prd;
1265 u8 tx_max_burst_prd;
1266 const char *usb_psy_name;
1267 int ret;
1268
1269 /* default to highest possible threshold */
1270 lpm_nyet_threshold = 0xf;
1271
1272 /* default to -3.5dB de-emphasis */
1273 tx_de_emphasis = 1;
1274
1275 /*
1276 * default to assert utmi_sleep_n and use maximum allowed HIRD
1277 * threshold value of 0b1100
1278 */
1279 hird_threshold = 12;
1280
1281 dwc->maximum_speed = usb_get_maximum_speed(dev);
1282 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1283 dwc->dr_mode = usb_get_dr_mode(dev);
1284 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1285
1286 dwc->sysdev_is_parent = device_property_read_bool(dev,
1287 "linux,sysdev_is_parent");
1288 if (dwc->sysdev_is_parent)
1289 dwc->sysdev = dwc->dev->parent;
1290 else
1291 dwc->sysdev = dwc->dev;
1292
1293 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1294 if (ret >= 0) {
1295 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1296 if (!dwc->usb_psy)
1297 dev_err(dev, "couldn't get usb power supply\n");
1298 }
1299
1300 dwc->has_lpm_erratum = device_property_read_bool(dev,
1301 "snps,has-lpm-erratum");
1302 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1303 &lpm_nyet_threshold);
1304 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1305 "snps,is-utmi-l1-suspend");
1306 device_property_read_u8(dev, "snps,hird-threshold",
1307 &hird_threshold);
1308 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1309 "snps,dis-start-transfer-quirk");
1310 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1311 "snps,usb3_lpm_capable");
1312 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1313 "snps,usb2-lpm-disable");
1314 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1315 "snps,usb2-gadget-lpm-disable");
1316 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1317 &rx_thr_num_pkt_prd);
1318 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1319 &rx_max_burst_prd);
1320 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1321 &tx_thr_num_pkt_prd);
1322 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1323 &tx_max_burst_prd);
1324
1325 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1326 "snps,disable_scramble_quirk");
1327 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1328 "snps,u2exit_lfps_quirk");
1329 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1330 "snps,u2ss_inp3_quirk");
1331 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1332 "snps,req_p1p2p3_quirk");
1333 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1334 "snps,del_p1p2p3_quirk");
1335 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1336 "snps,del_phy_power_chg_quirk");
1337 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1338 "snps,lfps_filter_quirk");
1339 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1340 "snps,rx_detect_poll_quirk");
1341 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1342 "snps,dis_u3_susphy_quirk");
1343 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1344 "snps,dis_u2_susphy_quirk");
1345 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1346 "snps,dis_enblslpm_quirk");
1347 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1348 "snps,dis-u1-entry-quirk");
1349 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1350 "snps,dis-u2-entry-quirk");
1351 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1352 "snps,dis_rxdet_inp3_quirk");
1353 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1354 "snps,dis-u2-freeclk-exists-quirk");
1355 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1356 "snps,dis-del-phy-power-chg-quirk");
1357 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1358 "snps,dis-tx-ipgap-linecheck-quirk");
1359 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1360 "snps,parkmode-disable-ss-quirk");
1361
1362 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1363 "snps,tx_de_emphasis_quirk");
1364 device_property_read_u8(dev, "snps,tx_de_emphasis",
1365 &tx_de_emphasis);
1366 device_property_read_string(dev, "snps,hsphy_interface",
1367 &dwc->hsphy_interface);
1368 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1369 &dwc->fladj);
1370
1371 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1372 "snps,dis_metastability_quirk");
1373
1374 dwc->dis_split_quirk = device_property_read_bool(dev,
1375 "snps,dis-split-quirk");
1376
1377 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1378 dwc->tx_de_emphasis = tx_de_emphasis;
1379
1380 dwc->hird_threshold = hird_threshold;
1381
1382 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1383 dwc->rx_max_burst_prd = rx_max_burst_prd;
1384
1385 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1386 dwc->tx_max_burst_prd = tx_max_burst_prd;
1387
1388 dwc->imod_interval = 0;
1389}
1390
1391/* check whether the core supports IMOD */
1392bool dwc3_has_imod(struct dwc3 *dwc)
1393{
1394 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1395 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1396 DWC3_IP_IS(DWC32);
1397}
1398
1399static void dwc3_check_params(struct dwc3 *dwc)
1400{
1401 struct device *dev = dwc->dev;
1402 unsigned int hwparam_gen =
1403 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1404
1405 /* Check for proper value of imod_interval */
1406 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1407 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1408 dwc->imod_interval = 0;
1409 }
1410
1411 /*
1412 * Workaround for STAR 9000961433 which affects only version
1413 * 3.00a of the DWC_usb3 core. This prevents the controller
1414 * interrupt from being masked while handling events. IMOD
1415 * allows us to work around this issue. Enable it for the
1416 * affected version.
1417 */
1418 if (!dwc->imod_interval &&
1419 DWC3_VER_IS(DWC3, 300A))
1420 dwc->imod_interval = 1;
1421
1422 /* Check the maximum_speed parameter */
1423 switch (dwc->maximum_speed) {
1424 case USB_SPEED_FULL:
1425 case USB_SPEED_HIGH:
1426 break;
1427 case USB_SPEED_SUPER:
1428 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1429 dev_warn(dev, "UDC doesn't support Gen 1\n");
1430 break;
1431 case USB_SPEED_SUPER_PLUS:
1432 if ((DWC3_IP_IS(DWC32) &&
1433 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1434 (!DWC3_IP_IS(DWC32) &&
1435 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1436 dev_warn(dev, "UDC doesn't support SSP\n");
1437 break;
1438 default:
1439 dev_err(dev, "invalid maximum_speed parameter %d\n",
1440 dwc->maximum_speed);
1441 fallthrough;
1442 case USB_SPEED_UNKNOWN:
1443 switch (hwparam_gen) {
1444 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1445 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1446 break;
1447 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1448 if (DWC3_IP_IS(DWC32))
1449 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1450 else
1451 dwc->maximum_speed = USB_SPEED_SUPER;
1452 break;
1453 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1454 dwc->maximum_speed = USB_SPEED_HIGH;
1455 break;
1456 default:
1457 dwc->maximum_speed = USB_SPEED_SUPER;
1458 break;
1459 }
1460 break;
1461 }
1462
1463 /*
1464 * Currently the controller does not have visibility into the HW
1465 * parameter to determine the maximum number of lanes the HW supports.
1466 * If the number of lanes is not specified in the device property, then
1467 * set the default to support dual-lane for DWC_usb32 and single-lane
1468 * for DWC_usb31 for super-speed-plus.
1469 */
1470 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1471 switch (dwc->max_ssp_rate) {
1472 case USB_SSP_GEN_2x1:
1473 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1474 dev_warn(dev, "UDC only supports Gen 1\n");
1475 break;
1476 case USB_SSP_GEN_1x2:
1477 case USB_SSP_GEN_2x2:
1478 if (DWC3_IP_IS(DWC31))
1479 dev_warn(dev, "UDC only supports single lane\n");
1480 break;
1481 case USB_SSP_GEN_UNKNOWN:
1482 default:
1483 switch (hwparam_gen) {
1484 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1485 if (DWC3_IP_IS(DWC32))
1486 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1487 else
1488 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1489 break;
1490 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1491 if (DWC3_IP_IS(DWC32))
1492 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1493 break;
1494 }
1495 break;
1496 }
1497 }
1498}
1499
1500static int dwc3_probe(struct platform_device *pdev)
1501{
1502 struct device *dev = &pdev->dev;
1503 struct resource *res, dwc_res;
1504 struct dwc3 *dwc;
1505
1506 int ret;
1507
1508 void __iomem *regs;
1509
1510 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1511 if (!dwc)
1512 return -ENOMEM;
1513
1514 dwc->dev = dev;
1515
1516 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1517 if (!res) {
1518 dev_err(dev, "missing memory resource\n");
1519 return -ENODEV;
1520 }
1521
1522 dwc->xhci_resources[0].start = res->start;
1523 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1524 DWC3_XHCI_REGS_END;
1525 dwc->xhci_resources[0].flags = res->flags;
1526 dwc->xhci_resources[0].name = res->name;
1527
1528 /*
1529 * Request memory region but exclude xHCI regs,
1530 * since it will be requested by the xhci-plat driver.
1531 */
1532 dwc_res = *res;
1533 dwc_res.start += DWC3_GLOBALS_REGS_START;
1534
1535 regs = devm_ioremap_resource(dev, &dwc_res);
1536 if (IS_ERR(regs))
1537 return PTR_ERR(regs);
1538
1539 dwc->regs = regs;
1540 dwc->regs_size = resource_size(&dwc_res);
1541
1542 dwc3_get_properties(dwc);
1543
1544 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1545 if (ret)
1546 return ret;
1547
1548 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1549 if (IS_ERR(dwc->reset))
1550 return PTR_ERR(dwc->reset);
1551
1552 if (dev->of_node) {
1553 ret = devm_clk_bulk_get_all(dev, &dwc->clks);
1554 if (ret == -EPROBE_DEFER)
1555 return ret;
1556 /*
1557 * Clocks are optional, but new DT platforms should support all
1558 * clocks as required by the DT-binding.
1559 */
1560 if (ret < 0)
1561 dwc->num_clks = 0;
1562 else
1563 dwc->num_clks = ret;
1564
1565 }
1566
1567 ret = reset_control_deassert(dwc->reset);
1568 if (ret)
1569 return ret;
1570
1571 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1572 if (ret)
1573 goto assert_reset;
1574
1575 if (!dwc3_core_is_valid(dwc)) {
1576 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1577 ret = -ENODEV;
1578 goto disable_clks;
1579 }
1580
1581 platform_set_drvdata(pdev, dwc);
1582 dwc3_cache_hwparams(dwc);
1583
1584 spin_lock_init(&dwc->lock);
1585 mutex_init(&dwc->mutex);
1586
1587 pm_runtime_set_active(dev);
1588 pm_runtime_use_autosuspend(dev);
1589 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1590 pm_runtime_enable(dev);
1591 ret = pm_runtime_get_sync(dev);
1592 if (ret < 0)
1593 goto err1;
1594
1595 pm_runtime_forbid(dev);
1596
1597 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1598 if (ret) {
1599 dev_err(dwc->dev, "failed to allocate event buffers\n");
1600 ret = -ENOMEM;
1601 goto err2;
1602 }
1603
1604 ret = dwc3_get_dr_mode(dwc);
1605 if (ret)
1606 goto err3;
1607
1608 ret = dwc3_alloc_scratch_buffers(dwc);
1609 if (ret)
1610 goto err3;
1611
1612 ret = dwc3_core_init(dwc);
1613 if (ret) {
1614 dev_err_probe(dev, ret, "failed to initialize core\n");
1615 goto err4;
1616 }
1617
1618 dwc3_check_params(dwc);
1619 dwc3_debugfs_init(dwc);
1620
1621 ret = dwc3_core_init_mode(dwc);
1622 if (ret)
1623 goto err5;
1624
1625 pm_runtime_put(dev);
1626
1627 return 0;
1628
1629err5:
1630 dwc3_debugfs_exit(dwc);
1631 dwc3_event_buffers_cleanup(dwc);
1632
1633 usb_phy_shutdown(dwc->usb2_phy);
1634 usb_phy_shutdown(dwc->usb3_phy);
1635 phy_exit(dwc->usb2_generic_phy);
1636 phy_exit(dwc->usb3_generic_phy);
1637
1638 usb_phy_set_suspend(dwc->usb2_phy, 1);
1639 usb_phy_set_suspend(dwc->usb3_phy, 1);
1640 phy_power_off(dwc->usb2_generic_phy);
1641 phy_power_off(dwc->usb3_generic_phy);
1642
1643 dwc3_ulpi_exit(dwc);
1644
1645err4:
1646 dwc3_free_scratch_buffers(dwc);
1647
1648err3:
1649 dwc3_free_event_buffers(dwc);
1650
1651err2:
1652 pm_runtime_allow(&pdev->dev);
1653
1654err1:
1655 pm_runtime_put_sync(&pdev->dev);
1656 pm_runtime_disable(&pdev->dev);
1657
1658disable_clks:
1659 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1660assert_reset:
1661 reset_control_assert(dwc->reset);
1662
1663 if (dwc->usb_psy)
1664 power_supply_put(dwc->usb_psy);
1665
1666 return ret;
1667}
1668
1669static int dwc3_remove(struct platform_device *pdev)
1670{
1671 struct dwc3 *dwc = platform_get_drvdata(pdev);
1672
1673 pm_runtime_get_sync(&pdev->dev);
1674
1675 dwc3_core_exit_mode(dwc);
1676 dwc3_debugfs_exit(dwc);
1677
1678 dwc3_core_exit(dwc);
1679 dwc3_ulpi_exit(dwc);
1680
1681 pm_runtime_disable(&pdev->dev);
1682 pm_runtime_put_noidle(&pdev->dev);
1683 pm_runtime_set_suspended(&pdev->dev);
1684
1685 dwc3_free_event_buffers(dwc);
1686 dwc3_free_scratch_buffers(dwc);
1687
1688 if (dwc->usb_psy)
1689 power_supply_put(dwc->usb_psy);
1690
1691 return 0;
1692}
1693
1694#ifdef CONFIG_PM
1695static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1696{
1697 int ret;
1698
1699 ret = reset_control_deassert(dwc->reset);
1700 if (ret)
1701 return ret;
1702
1703 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1704 if (ret)
1705 goto assert_reset;
1706
1707 ret = dwc3_core_init(dwc);
1708 if (ret)
1709 goto disable_clks;
1710
1711 return 0;
1712
1713disable_clks:
1714 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1715assert_reset:
1716 reset_control_assert(dwc->reset);
1717
1718 return ret;
1719}
1720
1721static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1722{
1723 unsigned long flags;
1724 u32 reg;
1725
1726 switch (dwc->current_dr_role) {
1727 case DWC3_GCTL_PRTCAP_DEVICE:
1728 if (pm_runtime_suspended(dwc->dev))
1729 break;
1730 spin_lock_irqsave(&dwc->lock, flags);
1731 dwc3_gadget_suspend(dwc);
1732 spin_unlock_irqrestore(&dwc->lock, flags);
1733 synchronize_irq(dwc->irq_gadget);
1734 dwc3_core_exit(dwc);
1735 break;
1736 case DWC3_GCTL_PRTCAP_HOST:
1737 if (!PMSG_IS_AUTO(msg)) {
1738 dwc3_core_exit(dwc);
1739 break;
1740 }
1741
1742 /* Let controller to suspend HSPHY before PHY driver suspends */
1743 if (dwc->dis_u2_susphy_quirk ||
1744 dwc->dis_enblslpm_quirk) {
1745 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1746 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1747 DWC3_GUSB2PHYCFG_SUSPHY;
1748 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1749
1750 /* Give some time for USB2 PHY to suspend */
1751 usleep_range(5000, 6000);
1752 }
1753
1754 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1755 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1756 break;
1757 case DWC3_GCTL_PRTCAP_OTG:
1758 /* do nothing during runtime_suspend */
1759 if (PMSG_IS_AUTO(msg))
1760 break;
1761
1762 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1763 spin_lock_irqsave(&dwc->lock, flags);
1764 dwc3_gadget_suspend(dwc);
1765 spin_unlock_irqrestore(&dwc->lock, flags);
1766 synchronize_irq(dwc->irq_gadget);
1767 }
1768
1769 dwc3_otg_exit(dwc);
1770 dwc3_core_exit(dwc);
1771 break;
1772 default:
1773 /* do nothing */
1774 break;
1775 }
1776
1777 return 0;
1778}
1779
1780static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1781{
1782 unsigned long flags;
1783 int ret;
1784 u32 reg;
1785
1786 switch (dwc->current_dr_role) {
1787 case DWC3_GCTL_PRTCAP_DEVICE:
1788 ret = dwc3_core_init_for_resume(dwc);
1789 if (ret)
1790 return ret;
1791
1792 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1793 spin_lock_irqsave(&dwc->lock, flags);
1794 dwc3_gadget_resume(dwc);
1795 spin_unlock_irqrestore(&dwc->lock, flags);
1796 break;
1797 case DWC3_GCTL_PRTCAP_HOST:
1798 if (!PMSG_IS_AUTO(msg)) {
1799 ret = dwc3_core_init_for_resume(dwc);
1800 if (ret)
1801 return ret;
1802 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1803 break;
1804 }
1805 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1806 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1807 if (dwc->dis_u2_susphy_quirk)
1808 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1809
1810 if (dwc->dis_enblslpm_quirk)
1811 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1812
1813 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1814
1815 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1816 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1817 break;
1818 case DWC3_GCTL_PRTCAP_OTG:
1819 /* nothing to do on runtime_resume */
1820 if (PMSG_IS_AUTO(msg))
1821 break;
1822
1823 ret = dwc3_core_init_for_resume(dwc);
1824 if (ret)
1825 return ret;
1826
1827 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1828
1829 dwc3_otg_init(dwc);
1830 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1831 dwc3_otg_host_init(dwc);
1832 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1833 spin_lock_irqsave(&dwc->lock, flags);
1834 dwc3_gadget_resume(dwc);
1835 spin_unlock_irqrestore(&dwc->lock, flags);
1836 }
1837
1838 break;
1839 default:
1840 /* do nothing */
1841 break;
1842 }
1843
1844 return 0;
1845}
1846
1847static int dwc3_runtime_checks(struct dwc3 *dwc)
1848{
1849 switch (dwc->current_dr_role) {
1850 case DWC3_GCTL_PRTCAP_DEVICE:
1851 if (dwc->connected)
1852 return -EBUSY;
1853 break;
1854 case DWC3_GCTL_PRTCAP_HOST:
1855 default:
1856 /* do nothing */
1857 break;
1858 }
1859
1860 return 0;
1861}
1862
1863static int dwc3_runtime_suspend(struct device *dev)
1864{
1865 struct dwc3 *dwc = dev_get_drvdata(dev);
1866 int ret;
1867
1868 if (dwc3_runtime_checks(dwc))
1869 return -EBUSY;
1870
1871 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1872 if (ret)
1873 return ret;
1874
1875 device_init_wakeup(dev, true);
1876
1877 return 0;
1878}
1879
1880static int dwc3_runtime_resume(struct device *dev)
1881{
1882 struct dwc3 *dwc = dev_get_drvdata(dev);
1883 int ret;
1884
1885 device_init_wakeup(dev, false);
1886
1887 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1888 if (ret)
1889 return ret;
1890
1891 switch (dwc->current_dr_role) {
1892 case DWC3_GCTL_PRTCAP_DEVICE:
1893 dwc3_gadget_process_pending_events(dwc);
1894 break;
1895 case DWC3_GCTL_PRTCAP_HOST:
1896 default:
1897 /* do nothing */
1898 break;
1899 }
1900
1901 pm_runtime_mark_last_busy(dev);
1902
1903 return 0;
1904}
1905
1906static int dwc3_runtime_idle(struct device *dev)
1907{
1908 struct dwc3 *dwc = dev_get_drvdata(dev);
1909
1910 switch (dwc->current_dr_role) {
1911 case DWC3_GCTL_PRTCAP_DEVICE:
1912 if (dwc3_runtime_checks(dwc))
1913 return -EBUSY;
1914 break;
1915 case DWC3_GCTL_PRTCAP_HOST:
1916 default:
1917 /* do nothing */
1918 break;
1919 }
1920
1921 pm_runtime_mark_last_busy(dev);
1922 pm_runtime_autosuspend(dev);
1923
1924 return 0;
1925}
1926#endif /* CONFIG_PM */
1927
1928#ifdef CONFIG_PM_SLEEP
1929static int dwc3_suspend(struct device *dev)
1930{
1931 struct dwc3 *dwc = dev_get_drvdata(dev);
1932 int ret;
1933
1934 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1935 if (ret)
1936 return ret;
1937
1938 pinctrl_pm_select_sleep_state(dev);
1939
1940 return 0;
1941}
1942
1943static int dwc3_resume(struct device *dev)
1944{
1945 struct dwc3 *dwc = dev_get_drvdata(dev);
1946 int ret;
1947
1948 pinctrl_pm_select_default_state(dev);
1949
1950 ret = dwc3_resume_common(dwc, PMSG_RESUME);
1951 if (ret)
1952 return ret;
1953
1954 pm_runtime_disable(dev);
1955 pm_runtime_set_active(dev);
1956 pm_runtime_enable(dev);
1957
1958 return 0;
1959}
1960
1961static void dwc3_complete(struct device *dev)
1962{
1963 struct dwc3 *dwc = dev_get_drvdata(dev);
1964 u32 reg;
1965
1966 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
1967 dwc->dis_split_quirk) {
1968 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
1969 reg |= DWC3_GUCTL3_SPLITDISABLE;
1970 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
1971 }
1972}
1973#else
1974#define dwc3_complete NULL
1975#endif /* CONFIG_PM_SLEEP */
1976
1977static const struct dev_pm_ops dwc3_dev_pm_ops = {
1978 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1979 .complete = dwc3_complete,
1980 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1981 dwc3_runtime_idle)
1982};
1983
1984#ifdef CONFIG_OF
1985static const struct of_device_id of_dwc3_match[] = {
1986 {
1987 .compatible = "snps,dwc3"
1988 },
1989 {
1990 .compatible = "synopsys,dwc3"
1991 },
1992 { },
1993};
1994MODULE_DEVICE_TABLE(of, of_dwc3_match);
1995#endif
1996
1997#ifdef CONFIG_ACPI
1998
1999#define ACPI_ID_INTEL_BSW "808622B7"
2000
2001static const struct acpi_device_id dwc3_acpi_match[] = {
2002 { ACPI_ID_INTEL_BSW, 0 },
2003 { },
2004};
2005MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2006#endif
2007
2008static struct platform_driver dwc3_driver = {
2009 .probe = dwc3_probe,
2010 .remove = dwc3_remove,
2011 .driver = {
2012 .name = "dwc3",
2013 .of_match_table = of_match_ptr(of_dwc3_match),
2014 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2015 .pm = &dwc3_dev_pm_ops,
2016 },
2017};
2018
2019module_platform_driver(dwc3_driver);
2020
2021MODULE_ALIAS("platform:dwc3");
2022MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2023MODULE_LICENSE("GPL v2");
2024MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");