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1// SPDX-License-Identifier: GPL-2.0
2/**
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/clk.h>
12#include <linux/version.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/io.h>
22#include <linux/list.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/of.h>
26#include <linux/acpi.h>
27#include <linux/pinctrl/consumer.h>
28#include <linux/reset.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32#include <linux/usb/of.h>
33#include <linux/usb/otg.h>
34
35#include "core.h"
36#include "gadget.h"
37#include "io.h"
38
39#include "debug.h"
40
41#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
42
43/**
44 * dwc3_get_dr_mode - Validates and sets dr_mode
45 * @dwc: pointer to our context structure
46 */
47static int dwc3_get_dr_mode(struct dwc3 *dwc)
48{
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
51 unsigned int hw_mode;
52
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
55
56 mode = dwc->dr_mode;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
58
59 switch (hw_mode) {
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
62 dev_err(dev,
63 "Controller does not support host mode.\n");
64 return -EINVAL;
65 }
66 mode = USB_DR_MODE_PERIPHERAL;
67 break;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
70 dev_err(dev,
71 "Controller does not support device mode.\n");
72 return -EINVAL;
73 }
74 mode = USB_DR_MODE_HOST;
75 break;
76 default:
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
81
82 /*
83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
84 * mode. If the controller supports DRD but the dr_mode is not
85 * specified or set to OTG, then set the mode to peripheral.
86 */
87 if (mode == USB_DR_MODE_OTG &&
88 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
89 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
90 !DWC3_VER_IS_PRIOR(DWC3, 330A))
91 mode = USB_DR_MODE_PERIPHERAL;
92 }
93
94 if (mode != dwc->dr_mode) {
95 dev_warn(dev,
96 "Configuration mismatch. dr_mode forced to %s\n",
97 mode == USB_DR_MODE_HOST ? "host" : "gadget");
98
99 dwc->dr_mode = mode;
100 }
101
102 return 0;
103}
104
105void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
106{
107 u32 reg;
108
109 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
110 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
111 reg |= DWC3_GCTL_PRTCAPDIR(mode);
112 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
113
114 dwc->current_dr_role = mode;
115}
116
117static void __dwc3_set_mode(struct work_struct *work)
118{
119 struct dwc3 *dwc = work_to_dwc(work);
120 unsigned long flags;
121 int ret;
122
123 if (dwc->dr_mode != USB_DR_MODE_OTG)
124 return;
125
126 pm_runtime_get_sync(dwc->dev);
127
128 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
129 dwc3_otg_update(dwc, 0);
130
131 if (!dwc->desired_dr_role)
132 goto out;
133
134 if (dwc->desired_dr_role == dwc->current_dr_role)
135 goto out;
136
137 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
138 goto out;
139
140 switch (dwc->current_dr_role) {
141 case DWC3_GCTL_PRTCAP_HOST:
142 dwc3_host_exit(dwc);
143 break;
144 case DWC3_GCTL_PRTCAP_DEVICE:
145 dwc3_gadget_exit(dwc);
146 dwc3_event_buffers_cleanup(dwc);
147 break;
148 case DWC3_GCTL_PRTCAP_OTG:
149 dwc3_otg_exit(dwc);
150 spin_lock_irqsave(&dwc->lock, flags);
151 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
152 spin_unlock_irqrestore(&dwc->lock, flags);
153 dwc3_otg_update(dwc, 1);
154 break;
155 default:
156 break;
157 }
158
159 spin_lock_irqsave(&dwc->lock, flags);
160
161 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
162
163 spin_unlock_irqrestore(&dwc->lock, flags);
164
165 switch (dwc->desired_dr_role) {
166 case DWC3_GCTL_PRTCAP_HOST:
167 ret = dwc3_host_init(dwc);
168 if (ret) {
169 dev_err(dwc->dev, "failed to initialize host\n");
170 } else {
171 if (dwc->usb2_phy)
172 otg_set_vbus(dwc->usb2_phy->otg, true);
173 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
174 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
175 }
176 break;
177 case DWC3_GCTL_PRTCAP_DEVICE:
178 dwc3_event_buffers_setup(dwc);
179
180 if (dwc->usb2_phy)
181 otg_set_vbus(dwc->usb2_phy->otg, false);
182 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
183 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
184
185 ret = dwc3_gadget_init(dwc);
186 if (ret)
187 dev_err(dwc->dev, "failed to initialize peripheral\n");
188 break;
189 case DWC3_GCTL_PRTCAP_OTG:
190 dwc3_otg_init(dwc);
191 dwc3_otg_update(dwc, 0);
192 break;
193 default:
194 break;
195 }
196
197out:
198 pm_runtime_mark_last_busy(dwc->dev);
199 pm_runtime_put_autosuspend(dwc->dev);
200}
201
202void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
203{
204 unsigned long flags;
205
206 spin_lock_irqsave(&dwc->lock, flags);
207 dwc->desired_dr_role = mode;
208 spin_unlock_irqrestore(&dwc->lock, flags);
209
210 queue_work(system_freezable_wq, &dwc->drd_work);
211}
212
213u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
214{
215 struct dwc3 *dwc = dep->dwc;
216 u32 reg;
217
218 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
219 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
220 DWC3_GDBGFIFOSPACE_TYPE(type));
221
222 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
223
224 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
225}
226
227/**
228 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
229 * @dwc: pointer to our context structure
230 */
231static int dwc3_core_soft_reset(struct dwc3 *dwc)
232{
233 u32 reg;
234 int retries = 1000;
235 int ret;
236
237 usb_phy_init(dwc->usb2_phy);
238 usb_phy_init(dwc->usb3_phy);
239 ret = phy_init(dwc->usb2_generic_phy);
240 if (ret < 0)
241 return ret;
242
243 ret = phy_init(dwc->usb3_generic_phy);
244 if (ret < 0) {
245 phy_exit(dwc->usb2_generic_phy);
246 return ret;
247 }
248
249 /*
250 * We're resetting only the device side because, if we're in host mode,
251 * XHCI driver will reset the host block. If dwc3 was configured for
252 * host-only mode, then we can return early.
253 */
254 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
255 return 0;
256
257 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
258 reg |= DWC3_DCTL_CSFTRST;
259 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
260
261 /*
262 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
263 * is cleared only after all the clocks are synchronized. This can
264 * take a little more than 50ms. Set the polling rate at 20ms
265 * for 10 times instead.
266 */
267 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
268 retries = 10;
269
270 do {
271 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
272 if (!(reg & DWC3_DCTL_CSFTRST))
273 goto done;
274
275 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
276 msleep(20);
277 else
278 udelay(1);
279 } while (--retries);
280
281 phy_exit(dwc->usb3_generic_phy);
282 phy_exit(dwc->usb2_generic_phy);
283
284 return -ETIMEDOUT;
285
286done:
287 /*
288 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
289 * is cleared, we must wait at least 50ms before accessing the PHY
290 * domain (synchronization delay).
291 */
292 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
293 msleep(50);
294
295 return 0;
296}
297
298/*
299 * dwc3_frame_length_adjustment - Adjusts frame length if required
300 * @dwc3: Pointer to our controller context structure
301 */
302static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
303{
304 u32 reg;
305 u32 dft;
306
307 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
308 return;
309
310 if (dwc->fladj == 0)
311 return;
312
313 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
314 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
315 if (dft != dwc->fladj) {
316 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
317 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
318 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
319 }
320}
321
322/**
323 * dwc3_free_one_event_buffer - Frees one event buffer
324 * @dwc: Pointer to our controller context structure
325 * @evt: Pointer to event buffer to be freed
326 */
327static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
328 struct dwc3_event_buffer *evt)
329{
330 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
331}
332
333/**
334 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
335 * @dwc: Pointer to our controller context structure
336 * @length: size of the event buffer
337 *
338 * Returns a pointer to the allocated event buffer structure on success
339 * otherwise ERR_PTR(errno).
340 */
341static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
342 unsigned length)
343{
344 struct dwc3_event_buffer *evt;
345
346 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
347 if (!evt)
348 return ERR_PTR(-ENOMEM);
349
350 evt->dwc = dwc;
351 evt->length = length;
352 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
353 if (!evt->cache)
354 return ERR_PTR(-ENOMEM);
355
356 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
357 &evt->dma, GFP_KERNEL);
358 if (!evt->buf)
359 return ERR_PTR(-ENOMEM);
360
361 return evt;
362}
363
364/**
365 * dwc3_free_event_buffers - frees all allocated event buffers
366 * @dwc: Pointer to our controller context structure
367 */
368static void dwc3_free_event_buffers(struct dwc3 *dwc)
369{
370 struct dwc3_event_buffer *evt;
371
372 evt = dwc->ev_buf;
373 if (evt)
374 dwc3_free_one_event_buffer(dwc, evt);
375}
376
377/**
378 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
379 * @dwc: pointer to our controller context structure
380 * @length: size of event buffer
381 *
382 * Returns 0 on success otherwise negative errno. In the error case, dwc
383 * may contain some buffers allocated but not all which were requested.
384 */
385static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
386{
387 struct dwc3_event_buffer *evt;
388
389 evt = dwc3_alloc_one_event_buffer(dwc, length);
390 if (IS_ERR(evt)) {
391 dev_err(dwc->dev, "can't allocate event buffer\n");
392 return PTR_ERR(evt);
393 }
394 dwc->ev_buf = evt;
395
396 return 0;
397}
398
399/**
400 * dwc3_event_buffers_setup - setup our allocated event buffers
401 * @dwc: pointer to our controller context structure
402 *
403 * Returns 0 on success otherwise negative errno.
404 */
405int dwc3_event_buffers_setup(struct dwc3 *dwc)
406{
407 struct dwc3_event_buffer *evt;
408
409 evt = dwc->ev_buf;
410 evt->lpos = 0;
411 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
412 lower_32_bits(evt->dma));
413 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
414 upper_32_bits(evt->dma));
415 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
416 DWC3_GEVNTSIZ_SIZE(evt->length));
417 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
418
419 return 0;
420}
421
422void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
423{
424 struct dwc3_event_buffer *evt;
425
426 evt = dwc->ev_buf;
427
428 evt->lpos = 0;
429
430 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
431 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
432 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
433 | DWC3_GEVNTSIZ_SIZE(0));
434 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
435}
436
437static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
438{
439 if (!dwc->has_hibernation)
440 return 0;
441
442 if (!dwc->nr_scratch)
443 return 0;
444
445 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
446 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
447 if (!dwc->scratchbuf)
448 return -ENOMEM;
449
450 return 0;
451}
452
453static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
454{
455 dma_addr_t scratch_addr;
456 u32 param;
457 int ret;
458
459 if (!dwc->has_hibernation)
460 return 0;
461
462 if (!dwc->nr_scratch)
463 return 0;
464
465 /* should never fall here */
466 if (!WARN_ON(dwc->scratchbuf))
467 return 0;
468
469 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
470 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
471 DMA_BIDIRECTIONAL);
472 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
473 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
474 ret = -EFAULT;
475 goto err0;
476 }
477
478 dwc->scratch_addr = scratch_addr;
479
480 param = lower_32_bits(scratch_addr);
481
482 ret = dwc3_send_gadget_generic_command(dwc,
483 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
484 if (ret < 0)
485 goto err1;
486
487 param = upper_32_bits(scratch_addr);
488
489 ret = dwc3_send_gadget_generic_command(dwc,
490 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
491 if (ret < 0)
492 goto err1;
493
494 return 0;
495
496err1:
497 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
498 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
499
500err0:
501 return ret;
502}
503
504static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
505{
506 if (!dwc->has_hibernation)
507 return;
508
509 if (!dwc->nr_scratch)
510 return;
511
512 /* should never fall here */
513 if (!WARN_ON(dwc->scratchbuf))
514 return;
515
516 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
517 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
518 kfree(dwc->scratchbuf);
519}
520
521static void dwc3_core_num_eps(struct dwc3 *dwc)
522{
523 struct dwc3_hwparams *parms = &dwc->hwparams;
524
525 dwc->num_eps = DWC3_NUM_EPS(parms);
526}
527
528static void dwc3_cache_hwparams(struct dwc3 *dwc)
529{
530 struct dwc3_hwparams *parms = &dwc->hwparams;
531
532 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
533 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
534 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
535 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
536 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
537 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
538 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
539 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
540 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
541}
542
543static int dwc3_core_ulpi_init(struct dwc3 *dwc)
544{
545 int intf;
546 int ret = 0;
547
548 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
549
550 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
551 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
552 dwc->hsphy_interface &&
553 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
554 ret = dwc3_ulpi_init(dwc);
555
556 return ret;
557}
558
559/**
560 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
561 * @dwc: Pointer to our controller context structure
562 *
563 * Returns 0 on success. The USB PHY interfaces are configured but not
564 * initialized. The PHY interfaces and the PHYs get initialized together with
565 * the core in dwc3_core_init.
566 */
567static int dwc3_phy_setup(struct dwc3 *dwc)
568{
569 unsigned int hw_mode;
570 u32 reg;
571
572 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
573
574 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
575
576 /*
577 * Make sure UX_EXIT_PX is cleared as that causes issues with some
578 * PHYs. Also, this bit is not supposed to be used in normal operation.
579 */
580 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
581
582 /*
583 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
584 * to '0' during coreConsultant configuration. So default value
585 * will be '0' when the core is reset. Application needs to set it
586 * to '1' after the core initialization is completed.
587 */
588 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
589 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
590
591 /*
592 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
593 * power-on reset, and it can be set after core initialization, which is
594 * after device soft-reset during initialization.
595 */
596 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
597 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
598
599 if (dwc->u2ss_inp3_quirk)
600 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
601
602 if (dwc->dis_rxdet_inp3_quirk)
603 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
604
605 if (dwc->req_p1p2p3_quirk)
606 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
607
608 if (dwc->del_p1p2p3_quirk)
609 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
610
611 if (dwc->del_phy_power_chg_quirk)
612 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
613
614 if (dwc->lfps_filter_quirk)
615 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
616
617 if (dwc->rx_detect_poll_quirk)
618 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
619
620 if (dwc->tx_de_emphasis_quirk)
621 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
622
623 if (dwc->dis_u3_susphy_quirk)
624 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
625
626 if (dwc->dis_del_phy_power_chg_quirk)
627 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
628
629 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
630
631 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
632
633 /* Select the HS PHY interface */
634 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
635 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
636 if (dwc->hsphy_interface &&
637 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
638 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
639 break;
640 } else if (dwc->hsphy_interface &&
641 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
642 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
643 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
644 } else {
645 /* Relying on default value. */
646 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
647 break;
648 }
649 fallthrough;
650 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
651 default:
652 break;
653 }
654
655 switch (dwc->hsphy_mode) {
656 case USBPHY_INTERFACE_MODE_UTMI:
657 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
658 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
659 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
660 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
661 break;
662 case USBPHY_INTERFACE_MODE_UTMIW:
663 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
664 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
665 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
666 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
667 break;
668 default:
669 break;
670 }
671
672 /*
673 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
674 * '0' during coreConsultant configuration. So default value will
675 * be '0' when the core is reset. Application needs to set it to
676 * '1' after the core initialization is completed.
677 */
678 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
679 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
680
681 /*
682 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
683 * power-on reset, and it can be set after core initialization, which is
684 * after device soft-reset during initialization.
685 */
686 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
687 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
688
689 if (dwc->dis_u2_susphy_quirk)
690 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
691
692 if (dwc->dis_enblslpm_quirk)
693 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
694 else
695 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
696
697 if (dwc->dis_u2_freeclk_exists_quirk)
698 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
699
700 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
701
702 return 0;
703}
704
705static void dwc3_core_exit(struct dwc3 *dwc)
706{
707 dwc3_event_buffers_cleanup(dwc);
708
709 usb_phy_shutdown(dwc->usb2_phy);
710 usb_phy_shutdown(dwc->usb3_phy);
711 phy_exit(dwc->usb2_generic_phy);
712 phy_exit(dwc->usb3_generic_phy);
713
714 usb_phy_set_suspend(dwc->usb2_phy, 1);
715 usb_phy_set_suspend(dwc->usb3_phy, 1);
716 phy_power_off(dwc->usb2_generic_phy);
717 phy_power_off(dwc->usb3_generic_phy);
718 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
719 reset_control_assert(dwc->reset);
720}
721
722static bool dwc3_core_is_valid(struct dwc3 *dwc)
723{
724 u32 reg;
725
726 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
727 dwc->ip = DWC3_GSNPS_ID(reg);
728
729 /* This should read as U3 followed by revision number */
730 if (DWC3_IP_IS(DWC3)) {
731 dwc->revision = reg;
732 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
733 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
734 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
735 } else {
736 return false;
737 }
738
739 return true;
740}
741
742static void dwc3_core_setup_global_control(struct dwc3 *dwc)
743{
744 u32 hwparams4 = dwc->hwparams.hwparams4;
745 u32 reg;
746
747 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
748 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
749
750 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
751 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
752 /**
753 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
754 * issue which would cause xHCI compliance tests to fail.
755 *
756 * Because of that we cannot enable clock gating on such
757 * configurations.
758 *
759 * Refers to:
760 *
761 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
762 * SOF/ITP Mode Used
763 */
764 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
765 dwc->dr_mode == USB_DR_MODE_OTG) &&
766 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
767 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
768 else
769 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
770 break;
771 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
772 /* enable hibernation here */
773 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
774
775 /*
776 * REVISIT Enabling this bit so that host-mode hibernation
777 * will work. Device-mode hibernation is not yet implemented.
778 */
779 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
780 break;
781 default:
782 /* nothing */
783 break;
784 }
785
786 /* check if current dwc3 is on simulation board */
787 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
788 dev_info(dwc->dev, "Running with FPGA optimizations\n");
789 dwc->is_fpga = true;
790 }
791
792 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
793 "disable_scramble cannot be used on non-FPGA builds\n");
794
795 if (dwc->disable_scramble_quirk && dwc->is_fpga)
796 reg |= DWC3_GCTL_DISSCRAMBLE;
797 else
798 reg &= ~DWC3_GCTL_DISSCRAMBLE;
799
800 if (dwc->u2exit_lfps_quirk)
801 reg |= DWC3_GCTL_U2EXIT_LFPS;
802
803 /*
804 * WORKAROUND: DWC3 revisions <1.90a have a bug
805 * where the device can fail to connect at SuperSpeed
806 * and falls back to high-speed mode which causes
807 * the device to enter a Connect/Disconnect loop
808 */
809 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
810 reg |= DWC3_GCTL_U2RSTECN;
811
812 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
813}
814
815static int dwc3_core_get_phy(struct dwc3 *dwc);
816static int dwc3_core_ulpi_init(struct dwc3 *dwc);
817
818/* set global incr burst type configuration registers */
819static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
820{
821 struct device *dev = dwc->dev;
822 /* incrx_mode : for INCR burst type. */
823 bool incrx_mode;
824 /* incrx_size : for size of INCRX burst. */
825 u32 incrx_size;
826 u32 *vals;
827 u32 cfg;
828 int ntype;
829 int ret;
830 int i;
831
832 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
833
834 /*
835 * Handle property "snps,incr-burst-type-adjustment".
836 * Get the number of value from this property:
837 * result <= 0, means this property is not supported.
838 * result = 1, means INCRx burst mode supported.
839 * result > 1, means undefined length burst mode supported.
840 */
841 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
842 if (ntype <= 0)
843 return;
844
845 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
846 if (!vals) {
847 dev_err(dev, "Error to get memory\n");
848 return;
849 }
850
851 /* Get INCR burst type, and parse it */
852 ret = device_property_read_u32_array(dev,
853 "snps,incr-burst-type-adjustment", vals, ntype);
854 if (ret) {
855 kfree(vals);
856 dev_err(dev, "Error to get property\n");
857 return;
858 }
859
860 incrx_size = *vals;
861
862 if (ntype > 1) {
863 /* INCRX (undefined length) burst mode */
864 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
865 for (i = 1; i < ntype; i++) {
866 if (vals[i] > incrx_size)
867 incrx_size = vals[i];
868 }
869 } else {
870 /* INCRX burst mode */
871 incrx_mode = INCRX_BURST_MODE;
872 }
873
874 kfree(vals);
875
876 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
877 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
878 if (incrx_mode)
879 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
880 switch (incrx_size) {
881 case 256:
882 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
883 break;
884 case 128:
885 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
886 break;
887 case 64:
888 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
889 break;
890 case 32:
891 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
892 break;
893 case 16:
894 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
895 break;
896 case 8:
897 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
898 break;
899 case 4:
900 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
901 break;
902 case 1:
903 break;
904 default:
905 dev_err(dev, "Invalid property\n");
906 break;
907 }
908
909 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
910}
911
912/**
913 * dwc3_core_init - Low-level initialization of DWC3 Core
914 * @dwc: Pointer to our controller context structure
915 *
916 * Returns 0 on success otherwise negative errno.
917 */
918static int dwc3_core_init(struct dwc3 *dwc)
919{
920 unsigned int hw_mode;
921 u32 reg;
922 int ret;
923
924 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
925
926 /*
927 * Write Linux Version Code to our GUID register so it's easy to figure
928 * out which kernel version a bug was found.
929 */
930 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
931
932 /* Handle USB2.0-only core configuration */
933 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
934 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
935 if (dwc->maximum_speed == USB_SPEED_SUPER)
936 dwc->maximum_speed = USB_SPEED_HIGH;
937 }
938
939 ret = dwc3_phy_setup(dwc);
940 if (ret)
941 goto err0;
942
943 if (!dwc->ulpi_ready) {
944 ret = dwc3_core_ulpi_init(dwc);
945 if (ret)
946 goto err0;
947 dwc->ulpi_ready = true;
948 }
949
950 if (!dwc->phys_ready) {
951 ret = dwc3_core_get_phy(dwc);
952 if (ret)
953 goto err0a;
954 dwc->phys_ready = true;
955 }
956
957 ret = dwc3_core_soft_reset(dwc);
958 if (ret)
959 goto err0a;
960
961 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
962 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
963 if (!dwc->dis_u3_susphy_quirk) {
964 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
965 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
966 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
967 }
968
969 if (!dwc->dis_u2_susphy_quirk) {
970 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
971 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
972 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
973 }
974 }
975
976 dwc3_core_setup_global_control(dwc);
977 dwc3_core_num_eps(dwc);
978
979 ret = dwc3_setup_scratch_buffers(dwc);
980 if (ret)
981 goto err1;
982
983 /* Adjust Frame Length */
984 dwc3_frame_length_adjustment(dwc);
985
986 dwc3_set_incr_burst_type(dwc);
987
988 usb_phy_set_suspend(dwc->usb2_phy, 0);
989 usb_phy_set_suspend(dwc->usb3_phy, 0);
990 ret = phy_power_on(dwc->usb2_generic_phy);
991 if (ret < 0)
992 goto err2;
993
994 ret = phy_power_on(dwc->usb3_generic_phy);
995 if (ret < 0)
996 goto err3;
997
998 ret = dwc3_event_buffers_setup(dwc);
999 if (ret) {
1000 dev_err(dwc->dev, "failed to setup event buffers\n");
1001 goto err4;
1002 }
1003
1004 /*
1005 * ENDXFER polling is available on version 3.10a and later of
1006 * the DWC_usb3 controller. It is NOT available in the
1007 * DWC_usb31 controller.
1008 */
1009 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1010 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1011 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1012 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1013 }
1014
1015 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1016 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1017
1018 /*
1019 * Enable hardware control of sending remote wakeup
1020 * in HS when the device is in the L1 state.
1021 */
1022 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1023 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1024
1025 if (dwc->dis_tx_ipgap_linecheck_quirk)
1026 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1027
1028 if (dwc->parkmode_disable_ss_quirk)
1029 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1030
1031 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1032 }
1033
1034 if (dwc->dr_mode == USB_DR_MODE_HOST ||
1035 dwc->dr_mode == USB_DR_MODE_OTG) {
1036 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1037
1038 /*
1039 * Enable Auto retry Feature to make the controller operating in
1040 * Host mode on seeing transaction errors(CRC errors or internal
1041 * overrun scenerios) on IN transfers to reply to the device
1042 * with a non-terminating retry ACK (i.e, an ACK transcation
1043 * packet with Retry=1 & Nump != 0)
1044 */
1045 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1046
1047 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1048 }
1049
1050 /*
1051 * Must config both number of packets and max burst settings to enable
1052 * RX and/or TX threshold.
1053 */
1054 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1055 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1056 u8 rx_maxburst = dwc->rx_max_burst_prd;
1057 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1058 u8 tx_maxburst = dwc->tx_max_burst_prd;
1059
1060 if (rx_thr_num && rx_maxburst) {
1061 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1062 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1063
1064 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1065 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1066
1067 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1068 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1069
1070 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1071 }
1072
1073 if (tx_thr_num && tx_maxburst) {
1074 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1075 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1076
1077 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1078 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1079
1080 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1081 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1082
1083 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1084 }
1085 }
1086
1087 return 0;
1088
1089err4:
1090 phy_power_off(dwc->usb3_generic_phy);
1091
1092err3:
1093 phy_power_off(dwc->usb2_generic_phy);
1094
1095err2:
1096 usb_phy_set_suspend(dwc->usb2_phy, 1);
1097 usb_phy_set_suspend(dwc->usb3_phy, 1);
1098
1099err1:
1100 usb_phy_shutdown(dwc->usb2_phy);
1101 usb_phy_shutdown(dwc->usb3_phy);
1102 phy_exit(dwc->usb2_generic_phy);
1103 phy_exit(dwc->usb3_generic_phy);
1104
1105err0a:
1106 dwc3_ulpi_exit(dwc);
1107
1108err0:
1109 return ret;
1110}
1111
1112static int dwc3_core_get_phy(struct dwc3 *dwc)
1113{
1114 struct device *dev = dwc->dev;
1115 struct device_node *node = dev->of_node;
1116 int ret;
1117
1118 if (node) {
1119 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1120 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1121 } else {
1122 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1123 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1124 }
1125
1126 if (IS_ERR(dwc->usb2_phy)) {
1127 ret = PTR_ERR(dwc->usb2_phy);
1128 if (ret == -ENXIO || ret == -ENODEV) {
1129 dwc->usb2_phy = NULL;
1130 } else if (ret == -EPROBE_DEFER) {
1131 return ret;
1132 } else {
1133 dev_err(dev, "no usb2 phy configured\n");
1134 return ret;
1135 }
1136 }
1137
1138 if (IS_ERR(dwc->usb3_phy)) {
1139 ret = PTR_ERR(dwc->usb3_phy);
1140 if (ret == -ENXIO || ret == -ENODEV) {
1141 dwc->usb3_phy = NULL;
1142 } else if (ret == -EPROBE_DEFER) {
1143 return ret;
1144 } else {
1145 dev_err(dev, "no usb3 phy configured\n");
1146 return ret;
1147 }
1148 }
1149
1150 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1151 if (IS_ERR(dwc->usb2_generic_phy)) {
1152 ret = PTR_ERR(dwc->usb2_generic_phy);
1153 if (ret == -ENOSYS || ret == -ENODEV) {
1154 dwc->usb2_generic_phy = NULL;
1155 } else if (ret == -EPROBE_DEFER) {
1156 return ret;
1157 } else {
1158 dev_err(dev, "no usb2 phy configured\n");
1159 return ret;
1160 }
1161 }
1162
1163 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1164 if (IS_ERR(dwc->usb3_generic_phy)) {
1165 ret = PTR_ERR(dwc->usb3_generic_phy);
1166 if (ret == -ENOSYS || ret == -ENODEV) {
1167 dwc->usb3_generic_phy = NULL;
1168 } else if (ret == -EPROBE_DEFER) {
1169 return ret;
1170 } else {
1171 dev_err(dev, "no usb3 phy configured\n");
1172 return ret;
1173 }
1174 }
1175
1176 return 0;
1177}
1178
1179static int dwc3_core_init_mode(struct dwc3 *dwc)
1180{
1181 struct device *dev = dwc->dev;
1182 int ret;
1183
1184 switch (dwc->dr_mode) {
1185 case USB_DR_MODE_PERIPHERAL:
1186 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1187
1188 if (dwc->usb2_phy)
1189 otg_set_vbus(dwc->usb2_phy->otg, false);
1190 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1191 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1192
1193 ret = dwc3_gadget_init(dwc);
1194 if (ret) {
1195 if (ret != -EPROBE_DEFER)
1196 dev_err(dev, "failed to initialize gadget\n");
1197 return ret;
1198 }
1199 break;
1200 case USB_DR_MODE_HOST:
1201 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1202
1203 if (dwc->usb2_phy)
1204 otg_set_vbus(dwc->usb2_phy->otg, true);
1205 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1206 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1207
1208 ret = dwc3_host_init(dwc);
1209 if (ret) {
1210 if (ret != -EPROBE_DEFER)
1211 dev_err(dev, "failed to initialize host\n");
1212 return ret;
1213 }
1214 break;
1215 case USB_DR_MODE_OTG:
1216 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1217 ret = dwc3_drd_init(dwc);
1218 if (ret) {
1219 if (ret != -EPROBE_DEFER)
1220 dev_err(dev, "failed to initialize dual-role\n");
1221 return ret;
1222 }
1223 break;
1224 default:
1225 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1226 return -EINVAL;
1227 }
1228
1229 return 0;
1230}
1231
1232static void dwc3_core_exit_mode(struct dwc3 *dwc)
1233{
1234 switch (dwc->dr_mode) {
1235 case USB_DR_MODE_PERIPHERAL:
1236 dwc3_gadget_exit(dwc);
1237 break;
1238 case USB_DR_MODE_HOST:
1239 dwc3_host_exit(dwc);
1240 break;
1241 case USB_DR_MODE_OTG:
1242 dwc3_drd_exit(dwc);
1243 break;
1244 default:
1245 /* do nothing */
1246 break;
1247 }
1248
1249 /* de-assert DRVVBUS for HOST and OTG mode */
1250 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1251}
1252
1253static void dwc3_get_properties(struct dwc3 *dwc)
1254{
1255 struct device *dev = dwc->dev;
1256 u8 lpm_nyet_threshold;
1257 u8 tx_de_emphasis;
1258 u8 hird_threshold;
1259 u8 rx_thr_num_pkt_prd;
1260 u8 rx_max_burst_prd;
1261 u8 tx_thr_num_pkt_prd;
1262 u8 tx_max_burst_prd;
1263
1264 /* default to highest possible threshold */
1265 lpm_nyet_threshold = 0xf;
1266
1267 /* default to -3.5dB de-emphasis */
1268 tx_de_emphasis = 1;
1269
1270 /*
1271 * default to assert utmi_sleep_n and use maximum allowed HIRD
1272 * threshold value of 0b1100
1273 */
1274 hird_threshold = 12;
1275
1276 dwc->maximum_speed = usb_get_maximum_speed(dev);
1277 dwc->dr_mode = usb_get_dr_mode(dev);
1278 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1279
1280 dwc->sysdev_is_parent = device_property_read_bool(dev,
1281 "linux,sysdev_is_parent");
1282 if (dwc->sysdev_is_parent)
1283 dwc->sysdev = dwc->dev->parent;
1284 else
1285 dwc->sysdev = dwc->dev;
1286
1287 dwc->has_lpm_erratum = device_property_read_bool(dev,
1288 "snps,has-lpm-erratum");
1289 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1290 &lpm_nyet_threshold);
1291 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1292 "snps,is-utmi-l1-suspend");
1293 device_property_read_u8(dev, "snps,hird-threshold",
1294 &hird_threshold);
1295 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1296 "snps,dis-start-transfer-quirk");
1297 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1298 "snps,usb3_lpm_capable");
1299 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1300 "snps,usb2-lpm-disable");
1301 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1302 &rx_thr_num_pkt_prd);
1303 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1304 &rx_max_burst_prd);
1305 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1306 &tx_thr_num_pkt_prd);
1307 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1308 &tx_max_burst_prd);
1309
1310 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1311 "snps,disable_scramble_quirk");
1312 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1313 "snps,u2exit_lfps_quirk");
1314 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1315 "snps,u2ss_inp3_quirk");
1316 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1317 "snps,req_p1p2p3_quirk");
1318 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1319 "snps,del_p1p2p3_quirk");
1320 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1321 "snps,del_phy_power_chg_quirk");
1322 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1323 "snps,lfps_filter_quirk");
1324 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1325 "snps,rx_detect_poll_quirk");
1326 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1327 "snps,dis_u3_susphy_quirk");
1328 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1329 "snps,dis_u2_susphy_quirk");
1330 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1331 "snps,dis_enblslpm_quirk");
1332 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1333 "snps,dis-u1-entry-quirk");
1334 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1335 "snps,dis-u2-entry-quirk");
1336 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1337 "snps,dis_rxdet_inp3_quirk");
1338 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1339 "snps,dis-u2-freeclk-exists-quirk");
1340 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1341 "snps,dis-del-phy-power-chg-quirk");
1342 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1343 "snps,dis-tx-ipgap-linecheck-quirk");
1344 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1345 "snps,parkmode-disable-ss-quirk");
1346
1347 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1348 "snps,tx_de_emphasis_quirk");
1349 device_property_read_u8(dev, "snps,tx_de_emphasis",
1350 &tx_de_emphasis);
1351 device_property_read_string(dev, "snps,hsphy_interface",
1352 &dwc->hsphy_interface);
1353 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1354 &dwc->fladj);
1355
1356 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1357 "snps,dis_metastability_quirk");
1358
1359 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1360 dwc->tx_de_emphasis = tx_de_emphasis;
1361
1362 dwc->hird_threshold = hird_threshold;
1363
1364 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1365 dwc->rx_max_burst_prd = rx_max_burst_prd;
1366
1367 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1368 dwc->tx_max_burst_prd = tx_max_burst_prd;
1369
1370 dwc->imod_interval = 0;
1371}
1372
1373/* check whether the core supports IMOD */
1374bool dwc3_has_imod(struct dwc3 *dwc)
1375{
1376 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1377 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1378 DWC3_IP_IS(DWC32);
1379}
1380
1381static void dwc3_check_params(struct dwc3 *dwc)
1382{
1383 struct device *dev = dwc->dev;
1384
1385 /* Check for proper value of imod_interval */
1386 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1387 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1388 dwc->imod_interval = 0;
1389 }
1390
1391 /*
1392 * Workaround for STAR 9000961433 which affects only version
1393 * 3.00a of the DWC_usb3 core. This prevents the controller
1394 * interrupt from being masked while handling events. IMOD
1395 * allows us to work around this issue. Enable it for the
1396 * affected version.
1397 */
1398 if (!dwc->imod_interval &&
1399 DWC3_VER_IS(DWC3, 300A))
1400 dwc->imod_interval = 1;
1401
1402 /* Check the maximum_speed parameter */
1403 switch (dwc->maximum_speed) {
1404 case USB_SPEED_LOW:
1405 case USB_SPEED_FULL:
1406 case USB_SPEED_HIGH:
1407 case USB_SPEED_SUPER:
1408 case USB_SPEED_SUPER_PLUS:
1409 break;
1410 default:
1411 dev_err(dev, "invalid maximum_speed parameter %d\n",
1412 dwc->maximum_speed);
1413 fallthrough;
1414 case USB_SPEED_UNKNOWN:
1415 /* default to superspeed */
1416 dwc->maximum_speed = USB_SPEED_SUPER;
1417
1418 /*
1419 * default to superspeed plus if we are capable.
1420 */
1421 if ((DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) &&
1422 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1423 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1424 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1425
1426 break;
1427 }
1428}
1429
1430static int dwc3_probe(struct platform_device *pdev)
1431{
1432 struct device *dev = &pdev->dev;
1433 struct resource *res, dwc_res;
1434 struct dwc3 *dwc;
1435
1436 int ret;
1437
1438 void __iomem *regs;
1439
1440 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1441 if (!dwc)
1442 return -ENOMEM;
1443
1444 dwc->dev = dev;
1445
1446 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1447 if (!res) {
1448 dev_err(dev, "missing memory resource\n");
1449 return -ENODEV;
1450 }
1451
1452 dwc->xhci_resources[0].start = res->start;
1453 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1454 DWC3_XHCI_REGS_END;
1455 dwc->xhci_resources[0].flags = res->flags;
1456 dwc->xhci_resources[0].name = res->name;
1457
1458 /*
1459 * Request memory region but exclude xHCI regs,
1460 * since it will be requested by the xhci-plat driver.
1461 */
1462 dwc_res = *res;
1463 dwc_res.start += DWC3_GLOBALS_REGS_START;
1464
1465 regs = devm_ioremap_resource(dev, &dwc_res);
1466 if (IS_ERR(regs))
1467 return PTR_ERR(regs);
1468
1469 dwc->regs = regs;
1470 dwc->regs_size = resource_size(&dwc_res);
1471
1472 dwc3_get_properties(dwc);
1473
1474 dwc->reset = devm_reset_control_array_get(dev, true, true);
1475 if (IS_ERR(dwc->reset))
1476 return PTR_ERR(dwc->reset);
1477
1478 if (dev->of_node) {
1479 ret = devm_clk_bulk_get_all(dev, &dwc->clks);
1480 if (ret == -EPROBE_DEFER)
1481 return ret;
1482 /*
1483 * Clocks are optional, but new DT platforms should support all
1484 * clocks as required by the DT-binding.
1485 */
1486 if (ret < 0)
1487 dwc->num_clks = 0;
1488 else
1489 dwc->num_clks = ret;
1490
1491 }
1492
1493 ret = reset_control_deassert(dwc->reset);
1494 if (ret)
1495 return ret;
1496
1497 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1498 if (ret)
1499 goto assert_reset;
1500
1501 if (!dwc3_core_is_valid(dwc)) {
1502 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1503 ret = -ENODEV;
1504 goto disable_clks;
1505 }
1506
1507 platform_set_drvdata(pdev, dwc);
1508 dwc3_cache_hwparams(dwc);
1509
1510 spin_lock_init(&dwc->lock);
1511
1512 pm_runtime_set_active(dev);
1513 pm_runtime_use_autosuspend(dev);
1514 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1515 pm_runtime_enable(dev);
1516 ret = pm_runtime_get_sync(dev);
1517 if (ret < 0)
1518 goto err1;
1519
1520 pm_runtime_forbid(dev);
1521
1522 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1523 if (ret) {
1524 dev_err(dwc->dev, "failed to allocate event buffers\n");
1525 ret = -ENOMEM;
1526 goto err2;
1527 }
1528
1529 ret = dwc3_get_dr_mode(dwc);
1530 if (ret)
1531 goto err3;
1532
1533 ret = dwc3_alloc_scratch_buffers(dwc);
1534 if (ret)
1535 goto err3;
1536
1537 ret = dwc3_core_init(dwc);
1538 if (ret) {
1539 if (ret != -EPROBE_DEFER)
1540 dev_err(dev, "failed to initialize core: %d\n", ret);
1541 goto err4;
1542 }
1543
1544 dwc3_check_params(dwc);
1545
1546 ret = dwc3_core_init_mode(dwc);
1547 if (ret)
1548 goto err5;
1549
1550 dwc3_debugfs_init(dwc);
1551 pm_runtime_put(dev);
1552
1553 return 0;
1554
1555err5:
1556 dwc3_event_buffers_cleanup(dwc);
1557 dwc3_ulpi_exit(dwc);
1558
1559err4:
1560 dwc3_free_scratch_buffers(dwc);
1561
1562err3:
1563 dwc3_free_event_buffers(dwc);
1564
1565err2:
1566 pm_runtime_allow(&pdev->dev);
1567
1568err1:
1569 pm_runtime_put_sync(&pdev->dev);
1570 pm_runtime_disable(&pdev->dev);
1571
1572disable_clks:
1573 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1574assert_reset:
1575 reset_control_assert(dwc->reset);
1576
1577 return ret;
1578}
1579
1580static int dwc3_remove(struct platform_device *pdev)
1581{
1582 struct dwc3 *dwc = platform_get_drvdata(pdev);
1583
1584 pm_runtime_get_sync(&pdev->dev);
1585
1586 dwc3_debugfs_exit(dwc);
1587 dwc3_core_exit_mode(dwc);
1588
1589 dwc3_core_exit(dwc);
1590 dwc3_ulpi_exit(dwc);
1591
1592 pm_runtime_put_sync(&pdev->dev);
1593 pm_runtime_allow(&pdev->dev);
1594 pm_runtime_disable(&pdev->dev);
1595
1596 dwc3_free_event_buffers(dwc);
1597 dwc3_free_scratch_buffers(dwc);
1598
1599 return 0;
1600}
1601
1602#ifdef CONFIG_PM
1603static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1604{
1605 int ret;
1606
1607 ret = reset_control_deassert(dwc->reset);
1608 if (ret)
1609 return ret;
1610
1611 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1612 if (ret)
1613 goto assert_reset;
1614
1615 ret = dwc3_core_init(dwc);
1616 if (ret)
1617 goto disable_clks;
1618
1619 return 0;
1620
1621disable_clks:
1622 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1623assert_reset:
1624 reset_control_assert(dwc->reset);
1625
1626 return ret;
1627}
1628
1629static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1630{
1631 unsigned long flags;
1632 u32 reg;
1633
1634 switch (dwc->current_dr_role) {
1635 case DWC3_GCTL_PRTCAP_DEVICE:
1636 if (pm_runtime_suspended(dwc->dev))
1637 break;
1638 spin_lock_irqsave(&dwc->lock, flags);
1639 dwc3_gadget_suspend(dwc);
1640 spin_unlock_irqrestore(&dwc->lock, flags);
1641 synchronize_irq(dwc->irq_gadget);
1642 dwc3_core_exit(dwc);
1643 break;
1644 case DWC3_GCTL_PRTCAP_HOST:
1645 if (!PMSG_IS_AUTO(msg)) {
1646 dwc3_core_exit(dwc);
1647 break;
1648 }
1649
1650 /* Let controller to suspend HSPHY before PHY driver suspends */
1651 if (dwc->dis_u2_susphy_quirk ||
1652 dwc->dis_enblslpm_quirk) {
1653 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1654 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1655 DWC3_GUSB2PHYCFG_SUSPHY;
1656 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1657
1658 /* Give some time for USB2 PHY to suspend */
1659 usleep_range(5000, 6000);
1660 }
1661
1662 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1663 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1664 break;
1665 case DWC3_GCTL_PRTCAP_OTG:
1666 /* do nothing during runtime_suspend */
1667 if (PMSG_IS_AUTO(msg))
1668 break;
1669
1670 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1671 spin_lock_irqsave(&dwc->lock, flags);
1672 dwc3_gadget_suspend(dwc);
1673 spin_unlock_irqrestore(&dwc->lock, flags);
1674 synchronize_irq(dwc->irq_gadget);
1675 }
1676
1677 dwc3_otg_exit(dwc);
1678 dwc3_core_exit(dwc);
1679 break;
1680 default:
1681 /* do nothing */
1682 break;
1683 }
1684
1685 return 0;
1686}
1687
1688static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1689{
1690 unsigned long flags;
1691 int ret;
1692 u32 reg;
1693
1694 switch (dwc->current_dr_role) {
1695 case DWC3_GCTL_PRTCAP_DEVICE:
1696 ret = dwc3_core_init_for_resume(dwc);
1697 if (ret)
1698 return ret;
1699
1700 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1701 spin_lock_irqsave(&dwc->lock, flags);
1702 dwc3_gadget_resume(dwc);
1703 spin_unlock_irqrestore(&dwc->lock, flags);
1704 break;
1705 case DWC3_GCTL_PRTCAP_HOST:
1706 if (!PMSG_IS_AUTO(msg)) {
1707 ret = dwc3_core_init_for_resume(dwc);
1708 if (ret)
1709 return ret;
1710 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1711 break;
1712 }
1713 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1714 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1715 if (dwc->dis_u2_susphy_quirk)
1716 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1717
1718 if (dwc->dis_enblslpm_quirk)
1719 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1720
1721 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1722
1723 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1724 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1725 break;
1726 case DWC3_GCTL_PRTCAP_OTG:
1727 /* nothing to do on runtime_resume */
1728 if (PMSG_IS_AUTO(msg))
1729 break;
1730
1731 ret = dwc3_core_init(dwc);
1732 if (ret)
1733 return ret;
1734
1735 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1736
1737 dwc3_otg_init(dwc);
1738 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1739 dwc3_otg_host_init(dwc);
1740 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1741 spin_lock_irqsave(&dwc->lock, flags);
1742 dwc3_gadget_resume(dwc);
1743 spin_unlock_irqrestore(&dwc->lock, flags);
1744 }
1745
1746 break;
1747 default:
1748 /* do nothing */
1749 break;
1750 }
1751
1752 return 0;
1753}
1754
1755static int dwc3_runtime_checks(struct dwc3 *dwc)
1756{
1757 switch (dwc->current_dr_role) {
1758 case DWC3_GCTL_PRTCAP_DEVICE:
1759 if (dwc->connected)
1760 return -EBUSY;
1761 break;
1762 case DWC3_GCTL_PRTCAP_HOST:
1763 default:
1764 /* do nothing */
1765 break;
1766 }
1767
1768 return 0;
1769}
1770
1771static int dwc3_runtime_suspend(struct device *dev)
1772{
1773 struct dwc3 *dwc = dev_get_drvdata(dev);
1774 int ret;
1775
1776 if (dwc3_runtime_checks(dwc))
1777 return -EBUSY;
1778
1779 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1780 if (ret)
1781 return ret;
1782
1783 device_init_wakeup(dev, true);
1784
1785 return 0;
1786}
1787
1788static int dwc3_runtime_resume(struct device *dev)
1789{
1790 struct dwc3 *dwc = dev_get_drvdata(dev);
1791 int ret;
1792
1793 device_init_wakeup(dev, false);
1794
1795 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1796 if (ret)
1797 return ret;
1798
1799 switch (dwc->current_dr_role) {
1800 case DWC3_GCTL_PRTCAP_DEVICE:
1801 dwc3_gadget_process_pending_events(dwc);
1802 break;
1803 case DWC3_GCTL_PRTCAP_HOST:
1804 default:
1805 /* do nothing */
1806 break;
1807 }
1808
1809 pm_runtime_mark_last_busy(dev);
1810
1811 return 0;
1812}
1813
1814static int dwc3_runtime_idle(struct device *dev)
1815{
1816 struct dwc3 *dwc = dev_get_drvdata(dev);
1817
1818 switch (dwc->current_dr_role) {
1819 case DWC3_GCTL_PRTCAP_DEVICE:
1820 if (dwc3_runtime_checks(dwc))
1821 return -EBUSY;
1822 break;
1823 case DWC3_GCTL_PRTCAP_HOST:
1824 default:
1825 /* do nothing */
1826 break;
1827 }
1828
1829 pm_runtime_mark_last_busy(dev);
1830 pm_runtime_autosuspend(dev);
1831
1832 return 0;
1833}
1834#endif /* CONFIG_PM */
1835
1836#ifdef CONFIG_PM_SLEEP
1837static int dwc3_suspend(struct device *dev)
1838{
1839 struct dwc3 *dwc = dev_get_drvdata(dev);
1840 int ret;
1841
1842 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1843 if (ret)
1844 return ret;
1845
1846 pinctrl_pm_select_sleep_state(dev);
1847
1848 return 0;
1849}
1850
1851static int dwc3_resume(struct device *dev)
1852{
1853 struct dwc3 *dwc = dev_get_drvdata(dev);
1854 int ret;
1855
1856 pinctrl_pm_select_default_state(dev);
1857
1858 ret = dwc3_resume_common(dwc, PMSG_RESUME);
1859 if (ret)
1860 return ret;
1861
1862 pm_runtime_disable(dev);
1863 pm_runtime_set_active(dev);
1864 pm_runtime_enable(dev);
1865
1866 return 0;
1867}
1868#endif /* CONFIG_PM_SLEEP */
1869
1870static const struct dev_pm_ops dwc3_dev_pm_ops = {
1871 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1872 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1873 dwc3_runtime_idle)
1874};
1875
1876#ifdef CONFIG_OF
1877static const struct of_device_id of_dwc3_match[] = {
1878 {
1879 .compatible = "snps,dwc3"
1880 },
1881 {
1882 .compatible = "synopsys,dwc3"
1883 },
1884 { },
1885};
1886MODULE_DEVICE_TABLE(of, of_dwc3_match);
1887#endif
1888
1889#ifdef CONFIG_ACPI
1890
1891#define ACPI_ID_INTEL_BSW "808622B7"
1892
1893static const struct acpi_device_id dwc3_acpi_match[] = {
1894 { ACPI_ID_INTEL_BSW, 0 },
1895 { },
1896};
1897MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1898#endif
1899
1900static struct platform_driver dwc3_driver = {
1901 .probe = dwc3_probe,
1902 .remove = dwc3_remove,
1903 .driver = {
1904 .name = "dwc3",
1905 .of_match_table = of_match_ptr(of_dwc3_match),
1906 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1907 .pm = &dwc3_dev_pm_ops,
1908 },
1909};
1910
1911module_platform_driver(dwc3_driver);
1912
1913MODULE_ALIAS("platform:dwc3");
1914MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1915MODULE_LICENSE("GPL v2");
1916MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");