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1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "ar9003_mac.h"
19#include "ar9003_2p2_initvals.h"
20#include "ar9485_initvals.h"
21#include "ar9340_initvals.h"
22#include "ar9330_1p1_initvals.h"
23#include "ar9330_1p2_initvals.h"
24
25/* General hardware code for the AR9003 hadware family */
26
27/*
28 * The AR9003 family uses a new INI format (pre, core, post
29 * arrays per subsystem). This provides support for the
30 * AR9003 2.2 chipsets.
31 */
32static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
33{
34 if (AR_SREV_9330_11(ah)) {
35 /* mac */
36 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
37 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
38 ar9331_1p1_mac_core,
39 ARRAY_SIZE(ar9331_1p1_mac_core), 2);
40 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
41 ar9331_1p1_mac_postamble,
42 ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
43
44 /* bb */
45 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
46 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
47 ar9331_1p1_baseband_core,
48 ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
49 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
50 ar9331_1p1_baseband_postamble,
51 ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
52
53 /* radio */
54 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
55 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
56 ar9331_1p1_radio_core,
57 ARRAY_SIZE(ar9331_1p1_radio_core), 2);
58 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
59
60 /* soc */
61 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
62 ar9331_1p1_soc_preamble,
63 ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
64 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
65 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
66 ar9331_1p1_soc_postamble,
67 ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
68
69 /* rx/tx gain */
70 INIT_INI_ARRAY(&ah->iniModesRxGain,
71 ar9331_common_rx_gain_1p1,
72 ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
73 INIT_INI_ARRAY(&ah->iniModesTxGain,
74 ar9331_modes_lowest_ob_db_tx_gain_1p1,
75 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
76 5);
77
78 /* additional clock settings */
79 if (ah->is_clk_25mhz)
80 INIT_INI_ARRAY(&ah->iniModesAdditional,
81 ar9331_1p1_xtal_25M,
82 ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
83 else
84 INIT_INI_ARRAY(&ah->iniModesAdditional,
85 ar9331_1p1_xtal_40M,
86 ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
87 } else if (AR_SREV_9330_12(ah)) {
88 /* mac */
89 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
90 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
91 ar9331_1p2_mac_core,
92 ARRAY_SIZE(ar9331_1p2_mac_core), 2);
93 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
94 ar9331_1p2_mac_postamble,
95 ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
96
97 /* bb */
98 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
99 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
100 ar9331_1p2_baseband_core,
101 ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
102 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
103 ar9331_1p2_baseband_postamble,
104 ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
105
106 /* radio */
107 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
108 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
109 ar9331_1p2_radio_core,
110 ARRAY_SIZE(ar9331_1p2_radio_core), 2);
111 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
112
113 /* soc */
114 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
115 ar9331_1p2_soc_preamble,
116 ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
117 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
118 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
119 ar9331_1p2_soc_postamble,
120 ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
121
122 /* rx/tx gain */
123 INIT_INI_ARRAY(&ah->iniModesRxGain,
124 ar9331_common_rx_gain_1p2,
125 ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
126 INIT_INI_ARRAY(&ah->iniModesTxGain,
127 ar9331_modes_lowest_ob_db_tx_gain_1p2,
128 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
129 5);
130
131 /* additional clock settings */
132 if (ah->is_clk_25mhz)
133 INIT_INI_ARRAY(&ah->iniModesAdditional,
134 ar9331_1p2_xtal_25M,
135 ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
136 else
137 INIT_INI_ARRAY(&ah->iniModesAdditional,
138 ar9331_1p2_xtal_40M,
139 ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
140 } else if (AR_SREV_9340(ah)) {
141 /* mac */
142 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
143 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
144 ar9340_1p0_mac_core,
145 ARRAY_SIZE(ar9340_1p0_mac_core), 2);
146 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
147 ar9340_1p0_mac_postamble,
148 ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
149
150 /* bb */
151 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
152 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
153 ar9340_1p0_baseband_core,
154 ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
155 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
156 ar9340_1p0_baseband_postamble,
157 ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
158
159 /* radio */
160 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
161 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
162 ar9340_1p0_radio_core,
163 ARRAY_SIZE(ar9340_1p0_radio_core), 2);
164 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
165 ar9340_1p0_radio_postamble,
166 ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
167
168 /* soc */
169 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
170 ar9340_1p0_soc_preamble,
171 ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
172 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
173 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
174 ar9340_1p0_soc_postamble,
175 ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
176
177 /* rx/tx gain */
178 INIT_INI_ARRAY(&ah->iniModesRxGain,
179 ar9340Common_wo_xlna_rx_gain_table_1p0,
180 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
181 5);
182 INIT_INI_ARRAY(&ah->iniModesTxGain,
183 ar9340Modes_high_ob_db_tx_gain_table_1p0,
184 ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
185 5);
186
187 INIT_INI_ARRAY(&ah->iniModesAdditional,
188 ar9340Modes_fast_clock_1p0,
189 ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
190 3);
191
192 INIT_INI_ARRAY(&ah->iniModesAdditional_40M,
193 ar9340_1p0_radio_core_40M,
194 ARRAY_SIZE(ar9340_1p0_radio_core_40M),
195 2);
196 } else if (AR_SREV_9485_11(ah)) {
197 /* mac */
198 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
199 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
200 ar9485_1_1_mac_core,
201 ARRAY_SIZE(ar9485_1_1_mac_core), 2);
202 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
203 ar9485_1_1_mac_postamble,
204 ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
205
206 /* bb */
207 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
208 ARRAY_SIZE(ar9485_1_1), 2);
209 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
210 ar9485_1_1_baseband_core,
211 ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
212 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
213 ar9485_1_1_baseband_postamble,
214 ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
215
216 /* radio */
217 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
218 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
219 ar9485_1_1_radio_core,
220 ARRAY_SIZE(ar9485_1_1_radio_core), 2);
221 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
222 ar9485_1_1_radio_postamble,
223 ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
224
225 /* soc */
226 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
227 ar9485_1_1_soc_preamble,
228 ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
229 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
230 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
231
232 /* rx/tx gain */
233 INIT_INI_ARRAY(&ah->iniModesRxGain,
234 ar9485Common_wo_xlna_rx_gain_1_1,
235 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
236 INIT_INI_ARRAY(&ah->iniModesTxGain,
237 ar9485_modes_lowest_ob_db_tx_gain_1_1,
238 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
239 5);
240
241 /* Load PCIE SERDES settings from INI */
242
243 /* Awake Setting */
244
245 INIT_INI_ARRAY(&ah->iniPcieSerdes,
246 ar9485_1_1_pcie_phy_clkreq_disable_L1,
247 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
248 2);
249
250 /* Sleep Setting */
251
252 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
253 ar9485_1_1_pcie_phy_clkreq_disable_L1,
254 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
255 2);
256 } else {
257 /* mac */
258 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
259 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
260 ar9300_2p2_mac_core,
261 ARRAY_SIZE(ar9300_2p2_mac_core), 2);
262 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
263 ar9300_2p2_mac_postamble,
264 ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
265
266 /* bb */
267 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
268 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
269 ar9300_2p2_baseband_core,
270 ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
271 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
272 ar9300_2p2_baseband_postamble,
273 ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
274
275 /* radio */
276 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
277 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
278 ar9300_2p2_radio_core,
279 ARRAY_SIZE(ar9300_2p2_radio_core), 2);
280 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
281 ar9300_2p2_radio_postamble,
282 ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
283
284 /* soc */
285 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
286 ar9300_2p2_soc_preamble,
287 ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
288 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
289 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
290 ar9300_2p2_soc_postamble,
291 ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
292
293 /* rx/tx gain */
294 INIT_INI_ARRAY(&ah->iniModesRxGain,
295 ar9300Common_rx_gain_table_2p2,
296 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
297 INIT_INI_ARRAY(&ah->iniModesTxGain,
298 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
299 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
300 5);
301
302 /* Load PCIE SERDES settings from INI */
303
304 /* Awake Setting */
305
306 INIT_INI_ARRAY(&ah->iniPcieSerdes,
307 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
308 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
309 2);
310
311 /* Sleep Setting */
312
313 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
314 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
315 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
316 2);
317
318 /* Fast clock modal settings */
319 INIT_INI_ARRAY(&ah->iniModesAdditional,
320 ar9300Modes_fast_clock_2p2,
321 ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
322 3);
323 }
324}
325
326static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
327{
328 switch (ar9003_hw_get_tx_gain_idx(ah)) {
329 case 0:
330 default:
331 if (AR_SREV_9330_12(ah))
332 INIT_INI_ARRAY(&ah->iniModesTxGain,
333 ar9331_modes_lowest_ob_db_tx_gain_1p2,
334 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
335 5);
336 else if (AR_SREV_9330_11(ah))
337 INIT_INI_ARRAY(&ah->iniModesTxGain,
338 ar9331_modes_lowest_ob_db_tx_gain_1p1,
339 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
340 5);
341 else if (AR_SREV_9340(ah))
342 INIT_INI_ARRAY(&ah->iniModesTxGain,
343 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
344 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
345 5);
346 else if (AR_SREV_9485_11(ah))
347 INIT_INI_ARRAY(&ah->iniModesTxGain,
348 ar9485_modes_lowest_ob_db_tx_gain_1_1,
349 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
350 5);
351 else
352 INIT_INI_ARRAY(&ah->iniModesTxGain,
353 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
354 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
355 5);
356 break;
357 case 1:
358 if (AR_SREV_9330_12(ah))
359 INIT_INI_ARRAY(&ah->iniModesTxGain,
360 ar9331_modes_high_ob_db_tx_gain_1p2,
361 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
362 5);
363 else if (AR_SREV_9330_11(ah))
364 INIT_INI_ARRAY(&ah->iniModesTxGain,
365 ar9331_modes_high_ob_db_tx_gain_1p1,
366 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
367 5);
368 else if (AR_SREV_9340(ah))
369 INIT_INI_ARRAY(&ah->iniModesTxGain,
370 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
371 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
372 5);
373 else if (AR_SREV_9485_11(ah))
374 INIT_INI_ARRAY(&ah->iniModesTxGain,
375 ar9485Modes_high_ob_db_tx_gain_1_1,
376 ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
377 5);
378 else
379 INIT_INI_ARRAY(&ah->iniModesTxGain,
380 ar9300Modes_high_ob_db_tx_gain_table_2p2,
381 ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
382 5);
383 break;
384 case 2:
385 if (AR_SREV_9330_12(ah))
386 INIT_INI_ARRAY(&ah->iniModesTxGain,
387 ar9331_modes_low_ob_db_tx_gain_1p2,
388 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
389 5);
390 else if (AR_SREV_9330_11(ah))
391 INIT_INI_ARRAY(&ah->iniModesTxGain,
392 ar9331_modes_low_ob_db_tx_gain_1p1,
393 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
394 5);
395 else if (AR_SREV_9340(ah))
396 INIT_INI_ARRAY(&ah->iniModesTxGain,
397 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
398 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
399 5);
400 else if (AR_SREV_9485_11(ah))
401 INIT_INI_ARRAY(&ah->iniModesTxGain,
402 ar9485Modes_low_ob_db_tx_gain_1_1,
403 ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
404 5);
405 else
406 INIT_INI_ARRAY(&ah->iniModesTxGain,
407 ar9300Modes_low_ob_db_tx_gain_table_2p2,
408 ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
409 5);
410 break;
411 case 3:
412 if (AR_SREV_9330_12(ah))
413 INIT_INI_ARRAY(&ah->iniModesTxGain,
414 ar9331_modes_high_power_tx_gain_1p2,
415 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
416 5);
417 else if (AR_SREV_9330_11(ah))
418 INIT_INI_ARRAY(&ah->iniModesTxGain,
419 ar9331_modes_high_power_tx_gain_1p1,
420 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
421 5);
422 else if (AR_SREV_9340(ah))
423 INIT_INI_ARRAY(&ah->iniModesTxGain,
424 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
425 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
426 5);
427 else if (AR_SREV_9485_11(ah))
428 INIT_INI_ARRAY(&ah->iniModesTxGain,
429 ar9485Modes_high_power_tx_gain_1_1,
430 ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
431 5);
432 else
433 INIT_INI_ARRAY(&ah->iniModesTxGain,
434 ar9300Modes_high_power_tx_gain_table_2p2,
435 ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
436 5);
437 break;
438 }
439}
440
441static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
442{
443 switch (ar9003_hw_get_rx_gain_idx(ah)) {
444 case 0:
445 default:
446 if (AR_SREV_9330_12(ah))
447 INIT_INI_ARRAY(&ah->iniModesRxGain,
448 ar9331_common_rx_gain_1p2,
449 ARRAY_SIZE(ar9331_common_rx_gain_1p2),
450 2);
451 else if (AR_SREV_9330_11(ah))
452 INIT_INI_ARRAY(&ah->iniModesRxGain,
453 ar9331_common_rx_gain_1p1,
454 ARRAY_SIZE(ar9331_common_rx_gain_1p1),
455 2);
456 else if (AR_SREV_9340(ah))
457 INIT_INI_ARRAY(&ah->iniModesRxGain,
458 ar9340Common_rx_gain_table_1p0,
459 ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
460 2);
461 else if (AR_SREV_9485_11(ah))
462 INIT_INI_ARRAY(&ah->iniModesRxGain,
463 ar9485Common_wo_xlna_rx_gain_1_1,
464 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
465 2);
466 else
467 INIT_INI_ARRAY(&ah->iniModesRxGain,
468 ar9300Common_rx_gain_table_2p2,
469 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
470 2);
471 break;
472 case 1:
473 if (AR_SREV_9330_12(ah))
474 INIT_INI_ARRAY(&ah->iniModesRxGain,
475 ar9331_common_wo_xlna_rx_gain_1p2,
476 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
477 2);
478 else if (AR_SREV_9330_11(ah))
479 INIT_INI_ARRAY(&ah->iniModesRxGain,
480 ar9331_common_wo_xlna_rx_gain_1p1,
481 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
482 2);
483 else if (AR_SREV_9340(ah))
484 INIT_INI_ARRAY(&ah->iniModesRxGain,
485 ar9340Common_wo_xlna_rx_gain_table_1p0,
486 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
487 2);
488 else if (AR_SREV_9485_11(ah))
489 INIT_INI_ARRAY(&ah->iniModesRxGain,
490 ar9485Common_wo_xlna_rx_gain_1_1,
491 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
492 2);
493 else
494 INIT_INI_ARRAY(&ah->iniModesRxGain,
495 ar9300Common_wo_xlna_rx_gain_table_2p2,
496 ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
497 2);
498 break;
499 }
500}
501
502/* set gain table pointers according to values read from the eeprom */
503static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
504{
505 ar9003_tx_gain_table_apply(ah);
506 ar9003_rx_gain_table_apply(ah);
507}
508
509/*
510 * Helper for ASPM support.
511 *
512 * Disable PLL when in L0s as well as receiver clock when in L1.
513 * This power saving option must be enabled through the SerDes.
514 *
515 * Programming the SerDes must go through the same 288 bit serial shift
516 * register as the other analog registers. Hence the 9 writes.
517 */
518static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
519 int restore,
520 int power_off)
521{
522 if (ah->is_pciexpress != true || ah->aspm_enabled != true)
523 return;
524
525 /* Nothing to do on restore for 11N */
526 if (!restore) {
527 /* set bit 19 to allow forcing of pcie core into L1 state */
528 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
529
530 /* Several PCIe massages to ensure proper behaviour */
531 if (ah->config.pcie_waen)
532 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
533 else
534 REG_WRITE(ah, AR_WA, ah->WARegVal);
535 }
536
537 /*
538 * Configire PCIE after Ini init. SERDES values now come from ini file
539 * This enables PCIe low power mode.
540 */
541 if (ah->config.pcieSerDesWrite) {
542 unsigned int i;
543 struct ar5416IniArray *array;
544
545 array = power_off ? &ah->iniPcieSerdes :
546 &ah->iniPcieSerdesLowPower;
547
548 for (i = 0; i < array->ia_rows; i++) {
549 REG_WRITE(ah,
550 INI_RA(array, i, 0),
551 INI_RA(array, i, 1));
552 }
553 }
554}
555
556/* Sets up the AR9003 hardware familiy callbacks */
557void ar9003_hw_attach_ops(struct ath_hw *ah)
558{
559 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
560 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
561
562 priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
563 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
564
565 ops->config_pci_powersave = ar9003_hw_configpcipowersave;
566
567 ar9003_hw_attach_phy_ops(ah);
568 ar9003_hw_attach_calib_ops(ah);
569 ar9003_hw_attach_mac_ops(ah);
570}
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "ar9003_mac.h"
19#include "ar9003_2p2_initvals.h"
20#include "ar9003_buffalo_initvals.h"
21#include "ar9485_initvals.h"
22#include "ar9340_initvals.h"
23#include "ar9330_1p1_initvals.h"
24#include "ar9330_1p2_initvals.h"
25#include "ar955x_1p0_initvals.h"
26#include "ar9580_1p0_initvals.h"
27#include "ar9462_2p0_initvals.h"
28#include "ar9462_2p1_initvals.h"
29#include "ar9565_1p0_initvals.h"
30#include "ar9565_1p1_initvals.h"
31#include "ar953x_initvals.h"
32#include "ar956x_initvals.h"
33
34/* General hardware code for the AR9003 hadware family */
35
36/*
37 * The AR9003 family uses a new INI format (pre, core, post
38 * arrays per subsystem). This provides support for the
39 * AR9003 2.2 chipsets.
40 */
41static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
42{
43 if (AR_SREV_9330_11(ah)) {
44 /* mac */
45 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
46 ar9331_1p1_mac_core);
47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
48 ar9331_1p1_mac_postamble);
49
50 /* bb */
51 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
52 ar9331_1p1_baseband_core);
53 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
54 ar9331_1p1_baseband_postamble);
55
56 /* radio */
57 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
58 ar9331_1p1_radio_core);
59
60 /* soc */
61 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
62 ar9331_1p1_soc_preamble);
63 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
64 ar9331_1p1_soc_postamble);
65
66 /* rx/tx gain */
67 INIT_INI_ARRAY(&ah->iniModesRxGain,
68 ar9331_common_rx_gain_1p1);
69 INIT_INI_ARRAY(&ah->iniModesTxGain,
70 ar9331_modes_lowest_ob_db_tx_gain_1p1);
71
72 /* Japan 2484 Mhz CCK */
73 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
74 ar9331_1p1_baseband_core_txfir_coeff_japan_2484);
75
76 /* additional clock settings */
77 if (ah->is_clk_25mhz)
78 INIT_INI_ARRAY(&ah->iniAdditional,
79 ar9331_1p1_xtal_25M);
80 else
81 INIT_INI_ARRAY(&ah->iniAdditional,
82 ar9331_1p1_xtal_40M);
83 } else if (AR_SREV_9330_12(ah)) {
84 /* mac */
85 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
86 ar9331_1p2_mac_core);
87 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
88 ar9331_1p2_mac_postamble);
89
90 /* bb */
91 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
92 ar9331_1p2_baseband_core);
93 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
94 ar9331_1p2_baseband_postamble);
95
96 /* radio */
97 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
98 ar9331_1p2_radio_core);
99
100 /* soc */
101 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
102 ar9331_1p2_soc_preamble);
103 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
104 ar9331_1p2_soc_postamble);
105
106 /* rx/tx gain */
107 INIT_INI_ARRAY(&ah->iniModesRxGain,
108 ar9331_common_rx_gain_1p2);
109 INIT_INI_ARRAY(&ah->iniModesTxGain,
110 ar9331_modes_lowest_ob_db_tx_gain_1p2);
111
112 /* Japan 2484 Mhz CCK */
113 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
114 ar9331_1p2_baseband_core_txfir_coeff_japan_2484);
115
116 /* additional clock settings */
117 if (ah->is_clk_25mhz)
118 INIT_INI_ARRAY(&ah->iniAdditional,
119 ar9331_1p2_xtal_25M);
120 else
121 INIT_INI_ARRAY(&ah->iniAdditional,
122 ar9331_1p2_xtal_40M);
123 } else if (AR_SREV_9340(ah)) {
124 /* mac */
125 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
126 ar9340_1p0_mac_core);
127 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
128 ar9340_1p0_mac_postamble);
129
130 /* bb */
131 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
132 ar9340_1p0_baseband_core);
133 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
134 ar9340_1p0_baseband_postamble);
135
136 /* radio */
137 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
138 ar9340_1p0_radio_core);
139 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
140 ar9340_1p0_radio_postamble);
141
142 /* soc */
143 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
144 ar9340_1p0_soc_preamble);
145 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
146 ar9340_1p0_soc_postamble);
147
148 /* rx/tx gain */
149 INIT_INI_ARRAY(&ah->iniModesRxGain,
150 ar9340Common_wo_xlna_rx_gain_table_1p0);
151 INIT_INI_ARRAY(&ah->iniModesTxGain,
152 ar9340Modes_high_ob_db_tx_gain_table_1p0);
153
154 INIT_INI_ARRAY(&ah->iniModesFastClock,
155 ar9340Modes_fast_clock_1p0);
156 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
157 ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
158 INIT_INI_ARRAY(&ah->ini_dfs,
159 ar9340_1p0_baseband_postamble_dfs_channel);
160
161 if (!ah->is_clk_25mhz)
162 INIT_INI_ARRAY(&ah->iniAdditional,
163 ar9340_1p0_radio_core_40M);
164 } else if (AR_SREV_9485_11_OR_LATER(ah)) {
165 /* mac */
166 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
167 ar9485_1_1_mac_core);
168 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
169 ar9485_1_1_mac_postamble);
170
171 /* bb */
172 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
173 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
174 ar9485_1_1_baseband_core);
175 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
176 ar9485_1_1_baseband_postamble);
177
178 /* radio */
179 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
180 ar9485_1_1_radio_core);
181 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
182 ar9485_1_1_radio_postamble);
183
184 /* soc */
185 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
186 ar9485_1_1_soc_preamble);
187
188 /* rx/tx gain */
189 INIT_INI_ARRAY(&ah->iniModesRxGain,
190 ar9485Common_wo_xlna_rx_gain_1_1);
191 INIT_INI_ARRAY(&ah->iniModesTxGain,
192 ar9485_modes_lowest_ob_db_tx_gain_1_1);
193
194 /* Japan 2484 Mhz CCK */
195 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
196 ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
197
198 if (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) {
199 INIT_INI_ARRAY(&ah->iniPcieSerdes,
200 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
201 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
202 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
203 } else {
204 INIT_INI_ARRAY(&ah->iniPcieSerdes,
205 ar9485_1_1_pcie_phy_clkreq_disable_L1);
206 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
207 ar9485_1_1_pcie_phy_clkreq_disable_L1);
208 }
209 } else if (AR_SREV_9462_21(ah)) {
210 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
211 ar9462_2p1_mac_core);
212 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
213 ar9462_2p1_mac_postamble);
214 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
215 ar9462_2p1_baseband_core);
216 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
217 ar9462_2p1_baseband_postamble);
218 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
219 ar9462_2p1_radio_core);
220 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
221 ar9462_2p1_radio_postamble);
222 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
223 ar9462_2p1_radio_postamble_sys2ant);
224 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
225 ar9462_2p1_soc_preamble);
226 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
227 ar9462_2p1_soc_postamble);
228 INIT_INI_ARRAY(&ah->iniModesRxGain,
229 ar9462_2p1_common_rx_gain);
230 INIT_INI_ARRAY(&ah->iniModesFastClock,
231 ar9462_2p1_modes_fast_clock);
232 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
233 ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
234
235 /* Awake -> Sleep Setting */
236 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
237 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
238 INIT_INI_ARRAY(&ah->iniPcieSerdes,
239 ar9462_2p1_pciephy_clkreq_disable_L1);
240 }
241
242 /* Sleep -> Awake Setting */
243 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
244 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
245 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
246 ar9462_2p1_pciephy_clkreq_disable_L1);
247 }
248 } else if (AR_SREV_9462_20(ah)) {
249
250 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
251 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
252 ar9462_2p0_mac_postamble);
253
254 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
255 ar9462_2p0_baseband_core);
256 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
257 ar9462_2p0_baseband_postamble);
258
259 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
260 ar9462_2p0_radio_core);
261 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
262 ar9462_2p0_radio_postamble);
263 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
264 ar9462_2p0_radio_postamble_sys2ant);
265
266 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
267 ar9462_2p0_soc_preamble);
268 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
269 ar9462_2p0_soc_postamble);
270
271 INIT_INI_ARRAY(&ah->iniModesRxGain,
272 ar9462_2p0_common_rx_gain);
273
274 /* Awake -> Sleep Setting */
275 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
276 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
277 INIT_INI_ARRAY(&ah->iniPcieSerdes,
278 ar9462_2p0_pciephy_clkreq_disable_L1);
279 }
280
281 /* Sleep -> Awake Setting */
282 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
283 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
284 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
285 ar9462_2p0_pciephy_clkreq_disable_L1);
286 }
287
288 /* Fast clock modal settings */
289 INIT_INI_ARRAY(&ah->iniModesFastClock,
290 ar9462_2p0_modes_fast_clock);
291
292 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
293 ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
294 } else if (AR_SREV_9550(ah)) {
295 /* mac */
296 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
297 ar955x_1p0_mac_core);
298 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
299 ar955x_1p0_mac_postamble);
300
301 /* bb */
302 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
303 ar955x_1p0_baseband_core);
304 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
305 ar955x_1p0_baseband_postamble);
306
307 /* radio */
308 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
309 ar955x_1p0_radio_core);
310 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
311 ar955x_1p0_radio_postamble);
312
313 /* soc */
314 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
315 ar955x_1p0_soc_preamble);
316 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
317 ar955x_1p0_soc_postamble);
318
319 /* rx/tx gain */
320 INIT_INI_ARRAY(&ah->iniModesRxGain,
321 ar955x_1p0_common_wo_xlna_rx_gain_table);
322 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
323 ar955x_1p0_common_wo_xlna_rx_gain_bounds);
324 INIT_INI_ARRAY(&ah->iniModesTxGain,
325 ar955x_1p0_modes_xpa_tx_gain_table);
326
327 /* Fast clock modal settings */
328 INIT_INI_ARRAY(&ah->iniModesFastClock,
329 ar955x_1p0_modes_fast_clock);
330 } else if (AR_SREV_9531(ah)) {
331 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
332 qca953x_1p0_mac_core);
333 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
334 qca953x_1p0_mac_postamble);
335 if (AR_SREV_9531_20(ah)) {
336 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
337 qca953x_2p0_baseband_core);
338 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
339 qca953x_2p0_baseband_postamble);
340 } else {
341 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
342 qca953x_1p0_baseband_core);
343 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
344 qca953x_1p0_baseband_postamble);
345 }
346 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
347 qca953x_1p0_radio_core);
348 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
349 qca953x_1p0_radio_postamble);
350 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
351 qca953x_1p0_soc_preamble);
352 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
353 qca953x_1p0_soc_postamble);
354
355 if (AR_SREV_9531_20(ah)) {
356 INIT_INI_ARRAY(&ah->iniModesRxGain,
357 qca953x_2p0_common_wo_xlna_rx_gain_table);
358 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
359 qca953x_2p0_common_wo_xlna_rx_gain_bounds);
360 } else {
361 INIT_INI_ARRAY(&ah->iniModesRxGain,
362 qca953x_1p0_common_wo_xlna_rx_gain_table);
363 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
364 qca953x_1p0_common_wo_xlna_rx_gain_bounds);
365 }
366
367 if (AR_SREV_9531_20(ah))
368 INIT_INI_ARRAY(&ah->iniModesTxGain,
369 qca953x_2p0_modes_no_xpa_tx_gain_table);
370 else if (AR_SREV_9531_11(ah))
371 INIT_INI_ARRAY(&ah->iniModesTxGain,
372 qca953x_1p1_modes_no_xpa_tx_gain_table);
373 else
374 INIT_INI_ARRAY(&ah->iniModesTxGain,
375 qca953x_1p0_modes_no_xpa_tx_gain_table);
376
377 INIT_INI_ARRAY(&ah->iniModesFastClock,
378 qca953x_1p0_modes_fast_clock);
379 } else if (AR_SREV_9561(ah)) {
380 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
381 qca956x_1p0_mac_core);
382 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
383 qca956x_1p0_mac_postamble);
384
385 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
386 qca956x_1p0_baseband_core);
387 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
388 qca956x_1p0_baseband_postamble);
389
390 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
391 qca956x_1p0_radio_core);
392 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
393 qca956x_1p0_radio_postamble);
394
395 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
396 qca956x_1p0_soc_preamble);
397 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
398 qca956x_1p0_soc_postamble);
399
400 INIT_INI_ARRAY(&ah->iniModesRxGain,
401 qca956x_1p0_common_wo_xlna_rx_gain_table);
402 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
403 qca956x_1p0_common_wo_xlna_rx_gain_bounds);
404 INIT_INI_ARRAY(&ah->iniModesTxGain,
405 qca956x_1p0_modes_no_xpa_tx_gain_table);
406
407 INIT_INI_ARRAY(&ah->ini_dfs,
408 qca956x_1p0_baseband_postamble_dfs_channel);
409 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
410 qca956x_1p0_baseband_core_txfir_coeff_japan_2484);
411 INIT_INI_ARRAY(&ah->iniModesFastClock,
412 qca956x_1p0_modes_fast_clock);
413 } else if (AR_SREV_9580(ah)) {
414 /* mac */
415 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
416 ar9580_1p0_mac_core);
417 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
418 ar9580_1p0_mac_postamble);
419
420 /* bb */
421 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
422 ar9580_1p0_baseband_core);
423 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
424 ar9580_1p0_baseband_postamble);
425
426 /* radio */
427 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
428 ar9580_1p0_radio_core);
429 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
430 ar9580_1p0_radio_postamble);
431
432 /* soc */
433 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
434 ar9580_1p0_soc_preamble);
435 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
436 ar9580_1p0_soc_postamble);
437
438 /* rx/tx gain */
439 INIT_INI_ARRAY(&ah->iniModesRxGain,
440 ar9580_1p0_rx_gain_table);
441 INIT_INI_ARRAY(&ah->iniModesTxGain,
442 ar9580_1p0_low_ob_db_tx_gain_table);
443
444 INIT_INI_ARRAY(&ah->iniModesFastClock,
445 ar9580_1p0_modes_fast_clock);
446 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
447 ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
448 INIT_INI_ARRAY(&ah->ini_dfs,
449 ar9580_1p0_baseband_postamble_dfs_channel);
450 } else if (AR_SREV_9565_11_OR_LATER(ah)) {
451 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
452 ar9565_1p1_mac_core);
453 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
454 ar9565_1p1_mac_postamble);
455
456 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
457 ar9565_1p1_baseband_core);
458 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
459 ar9565_1p1_baseband_postamble);
460
461 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
462 ar9565_1p1_radio_core);
463 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
464 ar9565_1p1_radio_postamble);
465
466 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
467 ar9565_1p1_soc_preamble);
468 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
469 ar9565_1p1_soc_postamble);
470
471 INIT_INI_ARRAY(&ah->iniModesRxGain,
472 ar9565_1p1_Common_rx_gain_table);
473 INIT_INI_ARRAY(&ah->iniModesTxGain,
474 ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
475
476 /* Awake -> Sleep Setting */
477 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
478 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
479 INIT_INI_ARRAY(&ah->iniPcieSerdes,
480 ar9565_1p1_pciephy_clkreq_disable_L1);
481 }
482
483 /* Sleep -> Awake Setting */
484 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
485 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
486 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
487 ar9565_1p1_pciephy_clkreq_disable_L1);
488 }
489
490 INIT_INI_ARRAY(&ah->iniModesFastClock,
491 ar9565_1p1_modes_fast_clock);
492 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
493 ar9565_1p1_baseband_core_txfir_coeff_japan_2484);
494 } else if (AR_SREV_9565(ah)) {
495 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
496 ar9565_1p0_mac_core);
497 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
498 ar9565_1p0_mac_postamble);
499
500 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
501 ar9565_1p0_baseband_core);
502 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
503 ar9565_1p0_baseband_postamble);
504
505 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
506 ar9565_1p0_radio_core);
507 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
508 ar9565_1p0_radio_postamble);
509
510 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
511 ar9565_1p0_soc_preamble);
512 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
513 ar9565_1p0_soc_postamble);
514
515 INIT_INI_ARRAY(&ah->iniModesRxGain,
516 ar9565_1p0_Common_rx_gain_table);
517 INIT_INI_ARRAY(&ah->iniModesTxGain,
518 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table);
519
520 /* Awake -> Sleep Setting */
521 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
522 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
523 INIT_INI_ARRAY(&ah->iniPcieSerdes,
524 ar9565_1p0_pciephy_clkreq_disable_L1);
525 }
526
527 /* Sleep -> Awake Setting */
528 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
529 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
530 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
531 ar9565_1p0_pciephy_clkreq_disable_L1);
532 }
533
534 INIT_INI_ARRAY(&ah->iniModesFastClock,
535 ar9565_1p0_modes_fast_clock);
536 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
537 ar9565_1p0_baseband_core_txfir_coeff_japan_2484);
538 } else {
539 /* mac */
540 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
541 ar9300_2p2_mac_core);
542 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
543 ar9300_2p2_mac_postamble);
544
545 /* bb */
546 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
547 ar9300_2p2_baseband_core);
548 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
549 ar9300_2p2_baseband_postamble);
550
551 /* radio */
552 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
553 ar9300_2p2_radio_core);
554 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
555 ar9300_2p2_radio_postamble);
556
557 /* soc */
558 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
559 ar9300_2p2_soc_preamble);
560 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
561 ar9300_2p2_soc_postamble);
562
563 /* rx/tx gain */
564 INIT_INI_ARRAY(&ah->iniModesRxGain,
565 ar9300Common_rx_gain_table_2p2);
566 INIT_INI_ARRAY(&ah->iniModesTxGain,
567 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
568
569 /* Load PCIE SERDES settings from INI */
570
571 /* Awake Setting */
572
573 INIT_INI_ARRAY(&ah->iniPcieSerdes,
574 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
575
576 /* Sleep Setting */
577
578 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
579 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
580
581 /* Fast clock modal settings */
582 INIT_INI_ARRAY(&ah->iniModesFastClock,
583 ar9300Modes_fast_clock_2p2);
584 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
585 ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
586 INIT_INI_ARRAY(&ah->ini_dfs,
587 ar9300_2p2_baseband_postamble_dfs_channel);
588 }
589}
590
591static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
592{
593 if (AR_SREV_9330_12(ah))
594 INIT_INI_ARRAY(&ah->iniModesTxGain,
595 ar9331_modes_lowest_ob_db_tx_gain_1p2);
596 else if (AR_SREV_9330_11(ah))
597 INIT_INI_ARRAY(&ah->iniModesTxGain,
598 ar9331_modes_lowest_ob_db_tx_gain_1p1);
599 else if (AR_SREV_9340(ah))
600 INIT_INI_ARRAY(&ah->iniModesTxGain,
601 ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
602 else if (AR_SREV_9485_11_OR_LATER(ah))
603 INIT_INI_ARRAY(&ah->iniModesTxGain,
604 ar9485_modes_lowest_ob_db_tx_gain_1_1);
605 else if (AR_SREV_9550(ah))
606 INIT_INI_ARRAY(&ah->iniModesTxGain,
607 ar955x_1p0_modes_xpa_tx_gain_table);
608 else if (AR_SREV_9531_10(ah))
609 INIT_INI_ARRAY(&ah->iniModesTxGain,
610 qca953x_1p0_modes_xpa_tx_gain_table);
611 else if (AR_SREV_9531_11(ah))
612 INIT_INI_ARRAY(&ah->iniModesTxGain,
613 qca953x_1p1_modes_xpa_tx_gain_table);
614 else if (AR_SREV_9531_20(ah))
615 INIT_INI_ARRAY(&ah->iniModesTxGain,
616 qca953x_2p0_modes_xpa_tx_gain_table);
617 else if (AR_SREV_9561(ah))
618 INIT_INI_ARRAY(&ah->iniModesTxGain,
619 qca956x_1p0_modes_xpa_tx_gain_table);
620 else if (AR_SREV_9580(ah))
621 INIT_INI_ARRAY(&ah->iniModesTxGain,
622 ar9580_1p0_lowest_ob_db_tx_gain_table);
623 else if (AR_SREV_9462_21(ah))
624 INIT_INI_ARRAY(&ah->iniModesTxGain,
625 ar9462_2p1_modes_low_ob_db_tx_gain);
626 else if (AR_SREV_9462_20(ah))
627 INIT_INI_ARRAY(&ah->iniModesTxGain,
628 ar9462_2p0_modes_low_ob_db_tx_gain);
629 else if (AR_SREV_9565_11(ah))
630 INIT_INI_ARRAY(&ah->iniModesTxGain,
631 ar9565_1p1_modes_low_ob_db_tx_gain_table);
632 else if (AR_SREV_9565(ah))
633 INIT_INI_ARRAY(&ah->iniModesTxGain,
634 ar9565_1p0_modes_low_ob_db_tx_gain_table);
635 else
636 INIT_INI_ARRAY(&ah->iniModesTxGain,
637 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
638}
639
640static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
641{
642 if (AR_SREV_9330_12(ah))
643 INIT_INI_ARRAY(&ah->iniModesTxGain,
644 ar9331_modes_high_ob_db_tx_gain_1p2);
645 else if (AR_SREV_9330_11(ah))
646 INIT_INI_ARRAY(&ah->iniModesTxGain,
647 ar9331_modes_high_ob_db_tx_gain_1p1);
648 else if (AR_SREV_9340(ah))
649 INIT_INI_ARRAY(&ah->iniModesTxGain,
650 ar9340Modes_high_ob_db_tx_gain_table_1p0);
651 else if (AR_SREV_9485_11_OR_LATER(ah))
652 INIT_INI_ARRAY(&ah->iniModesTxGain,
653 ar9485Modes_high_ob_db_tx_gain_1_1);
654 else if (AR_SREV_9580(ah))
655 INIT_INI_ARRAY(&ah->iniModesTxGain,
656 ar9580_1p0_high_ob_db_tx_gain_table);
657 else if (AR_SREV_9550(ah))
658 INIT_INI_ARRAY(&ah->iniModesTxGain,
659 ar955x_1p0_modes_no_xpa_tx_gain_table);
660 else if (AR_SREV_9531(ah)) {
661 if (AR_SREV_9531_20(ah))
662 INIT_INI_ARRAY(&ah->iniModesTxGain,
663 qca953x_2p0_modes_no_xpa_tx_gain_table);
664 else if (AR_SREV_9531_11(ah))
665 INIT_INI_ARRAY(&ah->iniModesTxGain,
666 qca953x_1p1_modes_no_xpa_tx_gain_table);
667 else
668 INIT_INI_ARRAY(&ah->iniModesTxGain,
669 qca953x_1p0_modes_no_xpa_tx_gain_table);
670 } else if (AR_SREV_9561(ah))
671 INIT_INI_ARRAY(&ah->iniModesTxGain,
672 qca956x_1p0_modes_no_xpa_tx_gain_table);
673 else if (AR_SREV_9462_21(ah))
674 INIT_INI_ARRAY(&ah->iniModesTxGain,
675 ar9462_2p1_modes_high_ob_db_tx_gain);
676 else if (AR_SREV_9462_20(ah))
677 INIT_INI_ARRAY(&ah->iniModesTxGain,
678 ar9462_2p0_modes_high_ob_db_tx_gain);
679 else if (AR_SREV_9565_11(ah))
680 INIT_INI_ARRAY(&ah->iniModesTxGain,
681 ar9565_1p1_modes_high_ob_db_tx_gain_table);
682 else if (AR_SREV_9565(ah))
683 INIT_INI_ARRAY(&ah->iniModesTxGain,
684 ar9565_1p0_modes_high_ob_db_tx_gain_table);
685 else
686 INIT_INI_ARRAY(&ah->iniModesTxGain,
687 ar9300Modes_high_ob_db_tx_gain_table_2p2);
688}
689
690static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
691{
692 if (AR_SREV_9330_12(ah))
693 INIT_INI_ARRAY(&ah->iniModesTxGain,
694 ar9331_modes_low_ob_db_tx_gain_1p2);
695 else if (AR_SREV_9330_11(ah))
696 INIT_INI_ARRAY(&ah->iniModesTxGain,
697 ar9331_modes_low_ob_db_tx_gain_1p1);
698 else if (AR_SREV_9340(ah))
699 INIT_INI_ARRAY(&ah->iniModesTxGain,
700 ar9340Modes_low_ob_db_tx_gain_table_1p0);
701 else if (AR_SREV_9531_11(ah))
702 INIT_INI_ARRAY(&ah->iniModesTxGain,
703 qca953x_1p1_modes_no_xpa_low_power_tx_gain_table);
704 else if (AR_SREV_9485_11_OR_LATER(ah))
705 INIT_INI_ARRAY(&ah->iniModesTxGain,
706 ar9485Modes_low_ob_db_tx_gain_1_1);
707 else if (AR_SREV_9580(ah))
708 INIT_INI_ARRAY(&ah->iniModesTxGain,
709 ar9580_1p0_low_ob_db_tx_gain_table);
710 else if (AR_SREV_9561(ah))
711 INIT_INI_ARRAY(&ah->iniModesTxGain,
712 qca956x_1p0_modes_no_xpa_low_ob_db_tx_gain_table);
713 else if (AR_SREV_9565_11(ah))
714 INIT_INI_ARRAY(&ah->iniModesTxGain,
715 ar9565_1p1_modes_low_ob_db_tx_gain_table);
716 else if (AR_SREV_9565(ah))
717 INIT_INI_ARRAY(&ah->iniModesTxGain,
718 ar9565_1p0_modes_low_ob_db_tx_gain_table);
719 else
720 INIT_INI_ARRAY(&ah->iniModesTxGain,
721 ar9300Modes_low_ob_db_tx_gain_table_2p2);
722}
723
724static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
725{
726 if (AR_SREV_9330_12(ah))
727 INIT_INI_ARRAY(&ah->iniModesTxGain,
728 ar9331_modes_high_power_tx_gain_1p2);
729 else if (AR_SREV_9330_11(ah))
730 INIT_INI_ARRAY(&ah->iniModesTxGain,
731 ar9331_modes_high_power_tx_gain_1p1);
732 else if (AR_SREV_9340(ah))
733 INIT_INI_ARRAY(&ah->iniModesTxGain,
734 ar9340Modes_high_power_tx_gain_table_1p0);
735 else if (AR_SREV_9485_11_OR_LATER(ah))
736 INIT_INI_ARRAY(&ah->iniModesTxGain,
737 ar9485Modes_high_power_tx_gain_1_1);
738 else if (AR_SREV_9580(ah))
739 INIT_INI_ARRAY(&ah->iniModesTxGain,
740 ar9580_1p0_high_power_tx_gain_table);
741 else if (AR_SREV_9565_11(ah))
742 INIT_INI_ARRAY(&ah->iniModesTxGain,
743 ar9565_1p1_modes_high_power_tx_gain_table);
744 else if (AR_SREV_9565(ah))
745 INIT_INI_ARRAY(&ah->iniModesTxGain,
746 ar9565_1p0_modes_high_power_tx_gain_table);
747 else {
748 if (ah->config.tx_gain_buffalo)
749 INIT_INI_ARRAY(&ah->iniModesTxGain,
750 ar9300Modes_high_power_tx_gain_table_buffalo);
751 else
752 INIT_INI_ARRAY(&ah->iniModesTxGain,
753 ar9300Modes_high_power_tx_gain_table_2p2);
754 }
755}
756
757static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
758{
759 if (AR_SREV_9340(ah))
760 INIT_INI_ARRAY(&ah->iniModesTxGain,
761 ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
762 else if (AR_SREV_9580(ah))
763 INIT_INI_ARRAY(&ah->iniModesTxGain,
764 ar9580_1p0_mixed_ob_db_tx_gain_table);
765 else if (AR_SREV_9462_21(ah))
766 INIT_INI_ARRAY(&ah->iniModesTxGain,
767 ar9462_2p1_modes_mix_ob_db_tx_gain);
768 else if (AR_SREV_9462_20(ah))
769 INIT_INI_ARRAY(&ah->iniModesTxGain,
770 ar9462_2p0_modes_mix_ob_db_tx_gain);
771 else
772 INIT_INI_ARRAY(&ah->iniModesTxGain,
773 ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
774}
775
776static void ar9003_tx_gain_table_mode5(struct ath_hw *ah)
777{
778 if (AR_SREV_9485_11_OR_LATER(ah))
779 INIT_INI_ARRAY(&ah->iniModesTxGain,
780 ar9485Modes_green_ob_db_tx_gain_1_1);
781 else if (AR_SREV_9580(ah))
782 INIT_INI_ARRAY(&ah->iniModesTxGain,
783 ar9580_1p0_type5_tx_gain_table);
784 else if (AR_SREV_9561(ah))
785 INIT_INI_ARRAY(&ah->iniModesTxGain,
786 qca956x_1p0_modes_no_xpa_green_tx_gain_table);
787 else if (AR_SREV_9300_22(ah))
788 INIT_INI_ARRAY(&ah->iniModesTxGain,
789 ar9300Modes_type5_tx_gain_table_2p2);
790}
791
792static void ar9003_tx_gain_table_mode6(struct ath_hw *ah)
793{
794 if (AR_SREV_9340(ah))
795 INIT_INI_ARRAY(&ah->iniModesTxGain,
796 ar9340Modes_low_ob_db_and_spur_tx_gain_table_1p0);
797 else if (AR_SREV_9485_11_OR_LATER(ah))
798 INIT_INI_ARRAY(&ah->iniModesTxGain,
799 ar9485Modes_green_spur_ob_db_tx_gain_1_1);
800 else if (AR_SREV_9580(ah))
801 INIT_INI_ARRAY(&ah->iniModesTxGain,
802 ar9580_1p0_type6_tx_gain_table);
803}
804
805static void ar9003_tx_gain_table_mode7(struct ath_hw *ah)
806{
807 if (AR_SREV_9340(ah))
808 INIT_INI_ARRAY(&ah->iniModesTxGain,
809 ar9340_cus227_tx_gain_table_1p0);
810}
811
812typedef void (*ath_txgain_tab)(struct ath_hw *ah);
813
814static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
815{
816 static const ath_txgain_tab modes[] = {
817 ar9003_tx_gain_table_mode0,
818 ar9003_tx_gain_table_mode1,
819 ar9003_tx_gain_table_mode2,
820 ar9003_tx_gain_table_mode3,
821 ar9003_tx_gain_table_mode4,
822 ar9003_tx_gain_table_mode5,
823 ar9003_tx_gain_table_mode6,
824 ar9003_tx_gain_table_mode7,
825 };
826 int idx = ar9003_hw_get_tx_gain_idx(ah);
827
828 if (idx >= ARRAY_SIZE(modes))
829 idx = 0;
830
831 modes[idx](ah);
832}
833
834static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
835{
836 if (AR_SREV_9330_12(ah))
837 INIT_INI_ARRAY(&ah->iniModesRxGain,
838 ar9331_common_rx_gain_1p2);
839 else if (AR_SREV_9330_11(ah))
840 INIT_INI_ARRAY(&ah->iniModesRxGain,
841 ar9331_common_rx_gain_1p1);
842 else if (AR_SREV_9340(ah))
843 INIT_INI_ARRAY(&ah->iniModesRxGain,
844 ar9340Common_rx_gain_table_1p0);
845 else if (AR_SREV_9485_11_OR_LATER(ah))
846 INIT_INI_ARRAY(&ah->iniModesRxGain,
847 ar9485_common_rx_gain_1_1);
848 else if (AR_SREV_9550(ah)) {
849 INIT_INI_ARRAY(&ah->iniModesRxGain,
850 ar955x_1p0_common_rx_gain_table);
851 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
852 ar955x_1p0_common_rx_gain_bounds);
853 } else if (AR_SREV_9531(ah)) {
854 INIT_INI_ARRAY(&ah->iniModesRxGain,
855 qca953x_1p0_common_rx_gain_table);
856 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
857 qca953x_1p0_common_rx_gain_bounds);
858 } else if (AR_SREV_9561(ah)) {
859 INIT_INI_ARRAY(&ah->iniModesRxGain,
860 qca956x_1p0_common_rx_gain_table);
861 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
862 qca956x_1p0_common_rx_gain_bounds);
863 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
864 qca956x_1p0_xlna_only);
865 } else if (AR_SREV_9580(ah))
866 INIT_INI_ARRAY(&ah->iniModesRxGain,
867 ar9580_1p0_rx_gain_table);
868 else if (AR_SREV_9462_21(ah))
869 INIT_INI_ARRAY(&ah->iniModesRxGain,
870 ar9462_2p1_common_rx_gain);
871 else if (AR_SREV_9462_20(ah))
872 INIT_INI_ARRAY(&ah->iniModesRxGain,
873 ar9462_2p0_common_rx_gain);
874 else if (AR_SREV_9565_11(ah))
875 INIT_INI_ARRAY(&ah->iniModesRxGain,
876 ar9565_1p1_Common_rx_gain_table);
877 else if (AR_SREV_9565(ah))
878 INIT_INI_ARRAY(&ah->iniModesRxGain,
879 ar9565_1p0_Common_rx_gain_table);
880 else
881 INIT_INI_ARRAY(&ah->iniModesRxGain,
882 ar9300Common_rx_gain_table_2p2);
883}
884
885static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
886{
887 if (AR_SREV_9330_12(ah))
888 INIT_INI_ARRAY(&ah->iniModesRxGain,
889 ar9331_common_wo_xlna_rx_gain_1p2);
890 else if (AR_SREV_9330_11(ah))
891 INIT_INI_ARRAY(&ah->iniModesRxGain,
892 ar9331_common_wo_xlna_rx_gain_1p1);
893 else if (AR_SREV_9340(ah))
894 INIT_INI_ARRAY(&ah->iniModesRxGain,
895 ar9340Common_wo_xlna_rx_gain_table_1p0);
896 else if (AR_SREV_9485_11_OR_LATER(ah))
897 INIT_INI_ARRAY(&ah->iniModesRxGain,
898 ar9485Common_wo_xlna_rx_gain_1_1);
899 else if (AR_SREV_9462_21(ah))
900 INIT_INI_ARRAY(&ah->iniModesRxGain,
901 ar9462_2p1_common_wo_xlna_rx_gain);
902 else if (AR_SREV_9462_20(ah))
903 INIT_INI_ARRAY(&ah->iniModesRxGain,
904 ar9462_2p0_common_wo_xlna_rx_gain);
905 else if (AR_SREV_9550(ah)) {
906 INIT_INI_ARRAY(&ah->iniModesRxGain,
907 ar955x_1p0_common_wo_xlna_rx_gain_table);
908 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
909 ar955x_1p0_common_wo_xlna_rx_gain_bounds);
910 } else if (AR_SREV_9531_10(ah) || AR_SREV_9531_11(ah)) {
911 INIT_INI_ARRAY(&ah->iniModesRxGain,
912 qca953x_1p0_common_wo_xlna_rx_gain_table);
913 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
914 qca953x_1p0_common_wo_xlna_rx_gain_bounds);
915 } else if (AR_SREV_9531_20(ah)) {
916 INIT_INI_ARRAY(&ah->iniModesRxGain,
917 qca953x_2p0_common_wo_xlna_rx_gain_table);
918 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
919 qca953x_2p0_common_wo_xlna_rx_gain_bounds);
920 } else if (AR_SREV_9561(ah)) {
921 INIT_INI_ARRAY(&ah->iniModesRxGain,
922 qca956x_1p0_common_wo_xlna_rx_gain_table);
923 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
924 qca956x_1p0_common_wo_xlna_rx_gain_bounds);
925 } else if (AR_SREV_9580(ah))
926 INIT_INI_ARRAY(&ah->iniModesRxGain,
927 ar9580_1p0_wo_xlna_rx_gain_table);
928 else if (AR_SREV_9565_11(ah))
929 INIT_INI_ARRAY(&ah->iniModesRxGain,
930 ar9565_1p1_common_wo_xlna_rx_gain_table);
931 else if (AR_SREV_9565(ah))
932 INIT_INI_ARRAY(&ah->iniModesRxGain,
933 ar9565_1p0_common_wo_xlna_rx_gain_table);
934 else
935 INIT_INI_ARRAY(&ah->iniModesRxGain,
936 ar9300Common_wo_xlna_rx_gain_table_2p2);
937}
938
939static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
940{
941 if (AR_SREV_9462_21(ah)) {
942 INIT_INI_ARRAY(&ah->iniModesRxGain,
943 ar9462_2p1_common_mixed_rx_gain);
944 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
945 ar9462_2p1_baseband_core_mix_rxgain);
946 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
947 ar9462_2p1_baseband_postamble_mix_rxgain);
948 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
949 ar9462_2p1_baseband_postamble_5g_xlna);
950 } else if (AR_SREV_9462_20(ah)) {
951 INIT_INI_ARRAY(&ah->iniModesRxGain,
952 ar9462_2p0_common_mixed_rx_gain);
953 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
954 ar9462_2p0_baseband_core_mix_rxgain);
955 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
956 ar9462_2p0_baseband_postamble_mix_rxgain);
957 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
958 ar9462_2p0_baseband_postamble_5g_xlna);
959 }
960}
961
962static void ar9003_rx_gain_table_mode3(struct ath_hw *ah)
963{
964 if (AR_SREV_9462_21(ah)) {
965 INIT_INI_ARRAY(&ah->iniModesRxGain,
966 ar9462_2p1_common_5g_xlna_only_rxgain);
967 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
968 ar9462_2p1_baseband_postamble_5g_xlna);
969 } else if (AR_SREV_9462_20(ah)) {
970 INIT_INI_ARRAY(&ah->iniModesRxGain,
971 ar9462_2p0_common_5g_xlna_only_rxgain);
972 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
973 ar9462_2p0_baseband_postamble_5g_xlna);
974 }
975}
976
977static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
978{
979 switch (ar9003_hw_get_rx_gain_idx(ah)) {
980 case 0:
981 default:
982 ar9003_rx_gain_table_mode0(ah);
983 break;
984 case 1:
985 ar9003_rx_gain_table_mode1(ah);
986 break;
987 case 2:
988 ar9003_rx_gain_table_mode2(ah);
989 break;
990 case 3:
991 ar9003_rx_gain_table_mode3(ah);
992 break;
993 }
994}
995
996/* set gain table pointers according to values read from the eeprom */
997static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
998{
999 ar9003_tx_gain_table_apply(ah);
1000 ar9003_rx_gain_table_apply(ah);
1001}
1002
1003/*
1004 * Helper for ASPM support.
1005 *
1006 * Disable PLL when in L0s as well as receiver clock when in L1.
1007 * This power saving option must be enabled through the SerDes.
1008 *
1009 * Programming the SerDes must go through the same 288 bit serial shift
1010 * register as the other analog registers. Hence the 9 writes.
1011 */
1012static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
1013 bool power_off)
1014{
1015 unsigned int i;
1016 struct ar5416IniArray *array;
1017
1018 /*
1019 * Increase L1 Entry Latency. Some WB222 boards don't have
1020 * this change in eeprom/OTP.
1021 *
1022 */
1023 if (AR_SREV_9462(ah)) {
1024 u32 val = ah->config.aspm_l1_fix;
1025 if ((val & 0xff000000) == 0x17000000) {
1026 val &= 0x00ffffff;
1027 val |= 0x27000000;
1028 REG_WRITE(ah, 0x570c, val);
1029 }
1030 }
1031
1032 /* Nothing to do on restore for 11N */
1033 if (!power_off /* !restore */) {
1034 /* set bit 19 to allow forcing of pcie core into L1 state */
1035 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
1036 REG_WRITE(ah, AR_WA, ah->WARegVal);
1037 }
1038
1039 /*
1040 * Configure PCIE after Ini init. SERDES values now come from ini file
1041 * This enables PCIe low power mode.
1042 */
1043 array = power_off ? &ah->iniPcieSerdes :
1044 &ah->iniPcieSerdesLowPower;
1045
1046 for (i = 0; i < array->ia_rows; i++) {
1047 REG_WRITE(ah,
1048 INI_RA(array, i, 0),
1049 INI_RA(array, i, 1));
1050 }
1051}
1052
1053static void ar9003_hw_init_hang_checks(struct ath_hw *ah)
1054{
1055 /*
1056 * All chips support detection of BB/MAC hangs.
1057 */
1058 ah->config.hw_hang_checks |= HW_BB_WATCHDOG;
1059 ah->config.hw_hang_checks |= HW_MAC_HANG;
1060
1061 /*
1062 * This is not required for AR9580 1.0
1063 */
1064 if (AR_SREV_9300_22(ah))
1065 ah->config.hw_hang_checks |= HW_PHYRESTART_CLC_WAR;
1066
1067 if (AR_SREV_9330(ah))
1068 ah->bb_watchdog_timeout_ms = 85;
1069 else
1070 ah->bb_watchdog_timeout_ms = 25;
1071}
1072
1073/*
1074 * MAC HW hang check
1075 * =================
1076 *
1077 * Signature: dcu_chain_state is 0x6 and dcu_complete_state is 0x1.
1078 *
1079 * The state of each DCU chain (mapped to TX queues) is available from these
1080 * DMA debug registers:
1081 *
1082 * Chain 0 state : Bits 4:0 of AR_DMADBG_4
1083 * Chain 1 state : Bits 9:5 of AR_DMADBG_4
1084 * Chain 2 state : Bits 14:10 of AR_DMADBG_4
1085 * Chain 3 state : Bits 19:15 of AR_DMADBG_4
1086 * Chain 4 state : Bits 24:20 of AR_DMADBG_4
1087 * Chain 5 state : Bits 29:25 of AR_DMADBG_4
1088 * Chain 6 state : Bits 4:0 of AR_DMADBG_5
1089 * Chain 7 state : Bits 9:5 of AR_DMADBG_5
1090 * Chain 8 state : Bits 14:10 of AR_DMADBG_5
1091 * Chain 9 state : Bits 19:15 of AR_DMADBG_5
1092 *
1093 * The DCU chain state "0x6" means "WAIT_FRDONE" - wait for TX frame to be done.
1094 */
1095
1096#define NUM_STATUS_READS 50
1097
1098static bool ath9k_hw_verify_hang(struct ath_hw *ah, unsigned int queue)
1099{
1100 u32 dma_dbg_chain, dma_dbg_complete;
1101 u8 dcu_chain_state, dcu_complete_state;
1102 int i;
1103
1104 for (i = 0; i < NUM_STATUS_READS; i++) {
1105 if (queue < 6)
1106 dma_dbg_chain = REG_READ(ah, AR_DMADBG_4);
1107 else
1108 dma_dbg_chain = REG_READ(ah, AR_DMADBG_5);
1109
1110 dma_dbg_complete = REG_READ(ah, AR_DMADBG_6);
1111
1112 dcu_chain_state = (dma_dbg_chain >> (5 * queue)) & 0x1f;
1113 dcu_complete_state = dma_dbg_complete & 0x3;
1114
1115 if ((dcu_chain_state != 0x6) || (dcu_complete_state != 0x1))
1116 return false;
1117 }
1118
1119 ath_dbg(ath9k_hw_common(ah), RESET,
1120 "MAC Hang signature found for queue: %d\n", queue);
1121
1122 return true;
1123}
1124
1125static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah)
1126{
1127 u32 dma_dbg_4, dma_dbg_5, dma_dbg_6, chk_dbg;
1128 u8 dcu_chain_state, dcu_complete_state;
1129 bool dcu_wait_frdone = false;
1130 unsigned long chk_dcu = 0;
1131 unsigned int i = 0;
1132
1133 dma_dbg_4 = REG_READ(ah, AR_DMADBG_4);
1134 dma_dbg_5 = REG_READ(ah, AR_DMADBG_5);
1135 dma_dbg_6 = REG_READ(ah, AR_DMADBG_6);
1136
1137 dcu_complete_state = dma_dbg_6 & 0x3;
1138 if (dcu_complete_state != 0x1)
1139 goto exit;
1140
1141 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1142 if (i < 6)
1143 chk_dbg = dma_dbg_4;
1144 else
1145 chk_dbg = dma_dbg_5;
1146
1147 dcu_chain_state = (chk_dbg >> (5 * i)) & 0x1f;
1148 if (dcu_chain_state == 0x6) {
1149 dcu_wait_frdone = true;
1150 chk_dcu |= BIT(i);
1151 }
1152 }
1153
1154 if ((dcu_complete_state == 0x1) && dcu_wait_frdone) {
1155 for_each_set_bit(i, &chk_dcu, ATH9K_NUM_TX_QUEUES) {
1156 if (ath9k_hw_verify_hang(ah, i))
1157 return true;
1158 }
1159 }
1160exit:
1161 return false;
1162}
1163
1164/* Sets up the AR9003 hardware familiy callbacks */
1165void ar9003_hw_attach_ops(struct ath_hw *ah)
1166{
1167 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1168 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1169
1170 ar9003_hw_init_mode_regs(ah);
1171
1172 if (AR_SREV_9003_PCOEM(ah)) {
1173 WARN_ON(!ah->iniPcieSerdes.ia_array);
1174 WARN_ON(!ah->iniPcieSerdesLowPower.ia_array);
1175 }
1176
1177 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
1178 priv_ops->init_hang_checks = ar9003_hw_init_hang_checks;
1179 priv_ops->detect_mac_hang = ar9003_hw_detect_mac_hang;
1180
1181 ops->config_pci_powersave = ar9003_hw_configpcipowersave;
1182
1183 ar9003_hw_attach_phy_ops(ah);
1184 ar9003_hw_attach_calib_ops(ah);
1185 ar9003_hw_attach_mac_ops(ah);
1186 ar9003_hw_attach_aic_ops(ah);
1187}