Loading...
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "ar9003_mac.h"
19#include "ar9003_2p2_initvals.h"
20#include "ar9485_initvals.h"
21#include "ar9340_initvals.h"
22#include "ar9330_1p1_initvals.h"
23#include "ar9330_1p2_initvals.h"
24
25/* General hardware code for the AR9003 hadware family */
26
27/*
28 * The AR9003 family uses a new INI format (pre, core, post
29 * arrays per subsystem). This provides support for the
30 * AR9003 2.2 chipsets.
31 */
32static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
33{
34 if (AR_SREV_9330_11(ah)) {
35 /* mac */
36 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
37 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
38 ar9331_1p1_mac_core,
39 ARRAY_SIZE(ar9331_1p1_mac_core), 2);
40 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
41 ar9331_1p1_mac_postamble,
42 ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
43
44 /* bb */
45 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
46 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
47 ar9331_1p1_baseband_core,
48 ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
49 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
50 ar9331_1p1_baseband_postamble,
51 ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
52
53 /* radio */
54 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
55 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
56 ar9331_1p1_radio_core,
57 ARRAY_SIZE(ar9331_1p1_radio_core), 2);
58 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
59
60 /* soc */
61 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
62 ar9331_1p1_soc_preamble,
63 ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
64 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
65 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
66 ar9331_1p1_soc_postamble,
67 ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
68
69 /* rx/tx gain */
70 INIT_INI_ARRAY(&ah->iniModesRxGain,
71 ar9331_common_rx_gain_1p1,
72 ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
73 INIT_INI_ARRAY(&ah->iniModesTxGain,
74 ar9331_modes_lowest_ob_db_tx_gain_1p1,
75 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
76 5);
77
78 /* additional clock settings */
79 if (ah->is_clk_25mhz)
80 INIT_INI_ARRAY(&ah->iniModesAdditional,
81 ar9331_1p1_xtal_25M,
82 ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
83 else
84 INIT_INI_ARRAY(&ah->iniModesAdditional,
85 ar9331_1p1_xtal_40M,
86 ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
87 } else if (AR_SREV_9330_12(ah)) {
88 /* mac */
89 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
90 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
91 ar9331_1p2_mac_core,
92 ARRAY_SIZE(ar9331_1p2_mac_core), 2);
93 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
94 ar9331_1p2_mac_postamble,
95 ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
96
97 /* bb */
98 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
99 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
100 ar9331_1p2_baseband_core,
101 ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
102 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
103 ar9331_1p2_baseband_postamble,
104 ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
105
106 /* radio */
107 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
108 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
109 ar9331_1p2_radio_core,
110 ARRAY_SIZE(ar9331_1p2_radio_core), 2);
111 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
112
113 /* soc */
114 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
115 ar9331_1p2_soc_preamble,
116 ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
117 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
118 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
119 ar9331_1p2_soc_postamble,
120 ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
121
122 /* rx/tx gain */
123 INIT_INI_ARRAY(&ah->iniModesRxGain,
124 ar9331_common_rx_gain_1p2,
125 ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
126 INIT_INI_ARRAY(&ah->iniModesTxGain,
127 ar9331_modes_lowest_ob_db_tx_gain_1p2,
128 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
129 5);
130
131 /* additional clock settings */
132 if (ah->is_clk_25mhz)
133 INIT_INI_ARRAY(&ah->iniModesAdditional,
134 ar9331_1p2_xtal_25M,
135 ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
136 else
137 INIT_INI_ARRAY(&ah->iniModesAdditional,
138 ar9331_1p2_xtal_40M,
139 ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
140 } else if (AR_SREV_9340(ah)) {
141 /* mac */
142 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
143 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
144 ar9340_1p0_mac_core,
145 ARRAY_SIZE(ar9340_1p0_mac_core), 2);
146 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
147 ar9340_1p0_mac_postamble,
148 ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
149
150 /* bb */
151 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
152 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
153 ar9340_1p0_baseband_core,
154 ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
155 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
156 ar9340_1p0_baseband_postamble,
157 ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
158
159 /* radio */
160 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
161 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
162 ar9340_1p0_radio_core,
163 ARRAY_SIZE(ar9340_1p0_radio_core), 2);
164 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
165 ar9340_1p0_radio_postamble,
166 ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
167
168 /* soc */
169 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
170 ar9340_1p0_soc_preamble,
171 ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
172 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
173 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
174 ar9340_1p0_soc_postamble,
175 ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
176
177 /* rx/tx gain */
178 INIT_INI_ARRAY(&ah->iniModesRxGain,
179 ar9340Common_wo_xlna_rx_gain_table_1p0,
180 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
181 5);
182 INIT_INI_ARRAY(&ah->iniModesTxGain,
183 ar9340Modes_high_ob_db_tx_gain_table_1p0,
184 ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
185 5);
186
187 INIT_INI_ARRAY(&ah->iniModesAdditional,
188 ar9340Modes_fast_clock_1p0,
189 ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
190 3);
191
192 INIT_INI_ARRAY(&ah->iniModesAdditional_40M,
193 ar9340_1p0_radio_core_40M,
194 ARRAY_SIZE(ar9340_1p0_radio_core_40M),
195 2);
196 } else if (AR_SREV_9485_11(ah)) {
197 /* mac */
198 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
199 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
200 ar9485_1_1_mac_core,
201 ARRAY_SIZE(ar9485_1_1_mac_core), 2);
202 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
203 ar9485_1_1_mac_postamble,
204 ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
205
206 /* bb */
207 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
208 ARRAY_SIZE(ar9485_1_1), 2);
209 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
210 ar9485_1_1_baseband_core,
211 ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
212 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
213 ar9485_1_1_baseband_postamble,
214 ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
215
216 /* radio */
217 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
218 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
219 ar9485_1_1_radio_core,
220 ARRAY_SIZE(ar9485_1_1_radio_core), 2);
221 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
222 ar9485_1_1_radio_postamble,
223 ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
224
225 /* soc */
226 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
227 ar9485_1_1_soc_preamble,
228 ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
229 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
230 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
231
232 /* rx/tx gain */
233 INIT_INI_ARRAY(&ah->iniModesRxGain,
234 ar9485Common_wo_xlna_rx_gain_1_1,
235 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
236 INIT_INI_ARRAY(&ah->iniModesTxGain,
237 ar9485_modes_lowest_ob_db_tx_gain_1_1,
238 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
239 5);
240
241 /* Load PCIE SERDES settings from INI */
242
243 /* Awake Setting */
244
245 INIT_INI_ARRAY(&ah->iniPcieSerdes,
246 ar9485_1_1_pcie_phy_clkreq_disable_L1,
247 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
248 2);
249
250 /* Sleep Setting */
251
252 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
253 ar9485_1_1_pcie_phy_clkreq_disable_L1,
254 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
255 2);
256 } else {
257 /* mac */
258 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
259 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
260 ar9300_2p2_mac_core,
261 ARRAY_SIZE(ar9300_2p2_mac_core), 2);
262 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
263 ar9300_2p2_mac_postamble,
264 ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
265
266 /* bb */
267 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
268 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
269 ar9300_2p2_baseband_core,
270 ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
271 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
272 ar9300_2p2_baseband_postamble,
273 ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
274
275 /* radio */
276 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
277 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
278 ar9300_2p2_radio_core,
279 ARRAY_SIZE(ar9300_2p2_radio_core), 2);
280 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
281 ar9300_2p2_radio_postamble,
282 ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
283
284 /* soc */
285 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
286 ar9300_2p2_soc_preamble,
287 ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
288 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
289 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
290 ar9300_2p2_soc_postamble,
291 ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
292
293 /* rx/tx gain */
294 INIT_INI_ARRAY(&ah->iniModesRxGain,
295 ar9300Common_rx_gain_table_2p2,
296 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
297 INIT_INI_ARRAY(&ah->iniModesTxGain,
298 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
299 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
300 5);
301
302 /* Load PCIE SERDES settings from INI */
303
304 /* Awake Setting */
305
306 INIT_INI_ARRAY(&ah->iniPcieSerdes,
307 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
308 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
309 2);
310
311 /* Sleep Setting */
312
313 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
314 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
315 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
316 2);
317
318 /* Fast clock modal settings */
319 INIT_INI_ARRAY(&ah->iniModesAdditional,
320 ar9300Modes_fast_clock_2p2,
321 ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
322 3);
323 }
324}
325
326static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
327{
328 switch (ar9003_hw_get_tx_gain_idx(ah)) {
329 case 0:
330 default:
331 if (AR_SREV_9330_12(ah))
332 INIT_INI_ARRAY(&ah->iniModesTxGain,
333 ar9331_modes_lowest_ob_db_tx_gain_1p2,
334 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
335 5);
336 else if (AR_SREV_9330_11(ah))
337 INIT_INI_ARRAY(&ah->iniModesTxGain,
338 ar9331_modes_lowest_ob_db_tx_gain_1p1,
339 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
340 5);
341 else if (AR_SREV_9340(ah))
342 INIT_INI_ARRAY(&ah->iniModesTxGain,
343 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
344 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
345 5);
346 else if (AR_SREV_9485_11(ah))
347 INIT_INI_ARRAY(&ah->iniModesTxGain,
348 ar9485_modes_lowest_ob_db_tx_gain_1_1,
349 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
350 5);
351 else
352 INIT_INI_ARRAY(&ah->iniModesTxGain,
353 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
354 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
355 5);
356 break;
357 case 1:
358 if (AR_SREV_9330_12(ah))
359 INIT_INI_ARRAY(&ah->iniModesTxGain,
360 ar9331_modes_high_ob_db_tx_gain_1p2,
361 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
362 5);
363 else if (AR_SREV_9330_11(ah))
364 INIT_INI_ARRAY(&ah->iniModesTxGain,
365 ar9331_modes_high_ob_db_tx_gain_1p1,
366 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
367 5);
368 else if (AR_SREV_9340(ah))
369 INIT_INI_ARRAY(&ah->iniModesTxGain,
370 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
371 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
372 5);
373 else if (AR_SREV_9485_11(ah))
374 INIT_INI_ARRAY(&ah->iniModesTxGain,
375 ar9485Modes_high_ob_db_tx_gain_1_1,
376 ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
377 5);
378 else
379 INIT_INI_ARRAY(&ah->iniModesTxGain,
380 ar9300Modes_high_ob_db_tx_gain_table_2p2,
381 ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
382 5);
383 break;
384 case 2:
385 if (AR_SREV_9330_12(ah))
386 INIT_INI_ARRAY(&ah->iniModesTxGain,
387 ar9331_modes_low_ob_db_tx_gain_1p2,
388 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
389 5);
390 else if (AR_SREV_9330_11(ah))
391 INIT_INI_ARRAY(&ah->iniModesTxGain,
392 ar9331_modes_low_ob_db_tx_gain_1p1,
393 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
394 5);
395 else if (AR_SREV_9340(ah))
396 INIT_INI_ARRAY(&ah->iniModesTxGain,
397 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
398 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
399 5);
400 else if (AR_SREV_9485_11(ah))
401 INIT_INI_ARRAY(&ah->iniModesTxGain,
402 ar9485Modes_low_ob_db_tx_gain_1_1,
403 ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
404 5);
405 else
406 INIT_INI_ARRAY(&ah->iniModesTxGain,
407 ar9300Modes_low_ob_db_tx_gain_table_2p2,
408 ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
409 5);
410 break;
411 case 3:
412 if (AR_SREV_9330_12(ah))
413 INIT_INI_ARRAY(&ah->iniModesTxGain,
414 ar9331_modes_high_power_tx_gain_1p2,
415 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
416 5);
417 else if (AR_SREV_9330_11(ah))
418 INIT_INI_ARRAY(&ah->iniModesTxGain,
419 ar9331_modes_high_power_tx_gain_1p1,
420 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
421 5);
422 else if (AR_SREV_9340(ah))
423 INIT_INI_ARRAY(&ah->iniModesTxGain,
424 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
425 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
426 5);
427 else if (AR_SREV_9485_11(ah))
428 INIT_INI_ARRAY(&ah->iniModesTxGain,
429 ar9485Modes_high_power_tx_gain_1_1,
430 ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
431 5);
432 else
433 INIT_INI_ARRAY(&ah->iniModesTxGain,
434 ar9300Modes_high_power_tx_gain_table_2p2,
435 ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
436 5);
437 break;
438 }
439}
440
441static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
442{
443 switch (ar9003_hw_get_rx_gain_idx(ah)) {
444 case 0:
445 default:
446 if (AR_SREV_9330_12(ah))
447 INIT_INI_ARRAY(&ah->iniModesRxGain,
448 ar9331_common_rx_gain_1p2,
449 ARRAY_SIZE(ar9331_common_rx_gain_1p2),
450 2);
451 else if (AR_SREV_9330_11(ah))
452 INIT_INI_ARRAY(&ah->iniModesRxGain,
453 ar9331_common_rx_gain_1p1,
454 ARRAY_SIZE(ar9331_common_rx_gain_1p1),
455 2);
456 else if (AR_SREV_9340(ah))
457 INIT_INI_ARRAY(&ah->iniModesRxGain,
458 ar9340Common_rx_gain_table_1p0,
459 ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
460 2);
461 else if (AR_SREV_9485_11(ah))
462 INIT_INI_ARRAY(&ah->iniModesRxGain,
463 ar9485Common_wo_xlna_rx_gain_1_1,
464 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
465 2);
466 else
467 INIT_INI_ARRAY(&ah->iniModesRxGain,
468 ar9300Common_rx_gain_table_2p2,
469 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
470 2);
471 break;
472 case 1:
473 if (AR_SREV_9330_12(ah))
474 INIT_INI_ARRAY(&ah->iniModesRxGain,
475 ar9331_common_wo_xlna_rx_gain_1p2,
476 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
477 2);
478 else if (AR_SREV_9330_11(ah))
479 INIT_INI_ARRAY(&ah->iniModesRxGain,
480 ar9331_common_wo_xlna_rx_gain_1p1,
481 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
482 2);
483 else if (AR_SREV_9340(ah))
484 INIT_INI_ARRAY(&ah->iniModesRxGain,
485 ar9340Common_wo_xlna_rx_gain_table_1p0,
486 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
487 2);
488 else if (AR_SREV_9485_11(ah))
489 INIT_INI_ARRAY(&ah->iniModesRxGain,
490 ar9485Common_wo_xlna_rx_gain_1_1,
491 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
492 2);
493 else
494 INIT_INI_ARRAY(&ah->iniModesRxGain,
495 ar9300Common_wo_xlna_rx_gain_table_2p2,
496 ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
497 2);
498 break;
499 }
500}
501
502/* set gain table pointers according to values read from the eeprom */
503static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
504{
505 ar9003_tx_gain_table_apply(ah);
506 ar9003_rx_gain_table_apply(ah);
507}
508
509/*
510 * Helper for ASPM support.
511 *
512 * Disable PLL when in L0s as well as receiver clock when in L1.
513 * This power saving option must be enabled through the SerDes.
514 *
515 * Programming the SerDes must go through the same 288 bit serial shift
516 * register as the other analog registers. Hence the 9 writes.
517 */
518static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
519 int restore,
520 int power_off)
521{
522 if (ah->is_pciexpress != true || ah->aspm_enabled != true)
523 return;
524
525 /* Nothing to do on restore for 11N */
526 if (!restore) {
527 /* set bit 19 to allow forcing of pcie core into L1 state */
528 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
529
530 /* Several PCIe massages to ensure proper behaviour */
531 if (ah->config.pcie_waen)
532 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
533 else
534 REG_WRITE(ah, AR_WA, ah->WARegVal);
535 }
536
537 /*
538 * Configire PCIE after Ini init. SERDES values now come from ini file
539 * This enables PCIe low power mode.
540 */
541 if (ah->config.pcieSerDesWrite) {
542 unsigned int i;
543 struct ar5416IniArray *array;
544
545 array = power_off ? &ah->iniPcieSerdes :
546 &ah->iniPcieSerdesLowPower;
547
548 for (i = 0; i < array->ia_rows; i++) {
549 REG_WRITE(ah,
550 INI_RA(array, i, 0),
551 INI_RA(array, i, 1));
552 }
553 }
554}
555
556/* Sets up the AR9003 hardware familiy callbacks */
557void ar9003_hw_attach_ops(struct ath_hw *ah)
558{
559 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
560 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
561
562 priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
563 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
564
565 ops->config_pci_powersave = ar9003_hw_configpcipowersave;
566
567 ar9003_hw_attach_phy_ops(ah);
568 ar9003_hw_attach_calib_ops(ah);
569 ar9003_hw_attach_mac_ops(ah);
570}
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "ar9003_mac.h"
19#include "ar9003_2p2_initvals.h"
20#include "ar9485_initvals.h"
21#include "ar9340_initvals.h"
22#include "ar9330_1p1_initvals.h"
23#include "ar9330_1p2_initvals.h"
24#include "ar9580_1p0_initvals.h"
25#include "ar9462_2p0_initvals.h"
26
27/* General hardware code for the AR9003 hadware family */
28
29/*
30 * The AR9003 family uses a new INI format (pre, core, post
31 * arrays per subsystem). This provides support for the
32 * AR9003 2.2 chipsets.
33 */
34static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
35{
36#define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \
37 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0
38
39#define AR9462_BB_CTX_COEFJ(x) \
40 ar9462_##x##_baseband_core_txfir_coeff_japan_2484
41
42#define AR9462_BBC_TXIFR_COEFFJ \
43 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
44 if (AR_SREV_9330_11(ah)) {
45 /* mac */
46 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
48 ar9331_1p1_mac_core,
49 ARRAY_SIZE(ar9331_1p1_mac_core), 2);
50 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
51 ar9331_1p1_mac_postamble,
52 ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
53
54 /* bb */
55 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
56 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
57 ar9331_1p1_baseband_core,
58 ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
59 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
60 ar9331_1p1_baseband_postamble,
61 ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
62
63 /* radio */
64 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
65 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
66 ar9331_1p1_radio_core,
67 ARRAY_SIZE(ar9331_1p1_radio_core), 2);
68 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
69
70 /* soc */
71 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
72 ar9331_1p1_soc_preamble,
73 ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
74 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
75 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
76 ar9331_1p1_soc_postamble,
77 ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
78
79 /* rx/tx gain */
80 INIT_INI_ARRAY(&ah->iniModesRxGain,
81 ar9331_common_rx_gain_1p1,
82 ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
83 INIT_INI_ARRAY(&ah->iniModesTxGain,
84 ar9331_modes_lowest_ob_db_tx_gain_1p1,
85 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
86 5);
87
88 /* additional clock settings */
89 if (ah->is_clk_25mhz)
90 INIT_INI_ARRAY(&ah->iniAdditional,
91 ar9331_1p1_xtal_25M,
92 ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
93 else
94 INIT_INI_ARRAY(&ah->iniAdditional,
95 ar9331_1p1_xtal_40M,
96 ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
97 } else if (AR_SREV_9330_12(ah)) {
98 /* mac */
99 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
100 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
101 ar9331_1p2_mac_core,
102 ARRAY_SIZE(ar9331_1p2_mac_core), 2);
103 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
104 ar9331_1p2_mac_postamble,
105 ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
106
107 /* bb */
108 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
109 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
110 ar9331_1p2_baseband_core,
111 ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
112 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
113 ar9331_1p2_baseband_postamble,
114 ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
115
116 /* radio */
117 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
118 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
119 ar9331_1p2_radio_core,
120 ARRAY_SIZE(ar9331_1p2_radio_core), 2);
121 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
122
123 /* soc */
124 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
125 ar9331_1p2_soc_preamble,
126 ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
127 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
128 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
129 ar9331_1p2_soc_postamble,
130 ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
131
132 /* rx/tx gain */
133 INIT_INI_ARRAY(&ah->iniModesRxGain,
134 ar9331_common_rx_gain_1p2,
135 ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
136 INIT_INI_ARRAY(&ah->iniModesTxGain,
137 ar9331_modes_lowest_ob_db_tx_gain_1p2,
138 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
139 5);
140
141 /* additional clock settings */
142 if (ah->is_clk_25mhz)
143 INIT_INI_ARRAY(&ah->iniAdditional,
144 ar9331_1p2_xtal_25M,
145 ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
146 else
147 INIT_INI_ARRAY(&ah->iniAdditional,
148 ar9331_1p2_xtal_40M,
149 ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
150 } else if (AR_SREV_9340(ah)) {
151 /* mac */
152 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
153 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
154 ar9340_1p0_mac_core,
155 ARRAY_SIZE(ar9340_1p0_mac_core), 2);
156 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
157 ar9340_1p0_mac_postamble,
158 ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
159
160 /* bb */
161 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
162 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
163 ar9340_1p0_baseband_core,
164 ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
165 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
166 ar9340_1p0_baseband_postamble,
167 ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
168
169 /* radio */
170 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
171 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
172 ar9340_1p0_radio_core,
173 ARRAY_SIZE(ar9340_1p0_radio_core), 2);
174 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
175 ar9340_1p0_radio_postamble,
176 ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
177
178 /* soc */
179 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
180 ar9340_1p0_soc_preamble,
181 ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
182 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
183 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
184 ar9340_1p0_soc_postamble,
185 ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
186
187 /* rx/tx gain */
188 INIT_INI_ARRAY(&ah->iniModesRxGain,
189 ar9340Common_wo_xlna_rx_gain_table_1p0,
190 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
191 5);
192 INIT_INI_ARRAY(&ah->iniModesTxGain,
193 ar9340Modes_high_ob_db_tx_gain_table_1p0,
194 ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
195 5);
196
197 INIT_INI_ARRAY(&ah->iniModesFastClock,
198 ar9340Modes_fast_clock_1p0,
199 ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
200 3);
201
202 if (!ah->is_clk_25mhz)
203 INIT_INI_ARRAY(&ah->iniAdditional,
204 ar9340_1p0_radio_core_40M,
205 ARRAY_SIZE(ar9340_1p0_radio_core_40M),
206 2);
207 } else if (AR_SREV_9485_11(ah)) {
208 /* mac */
209 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
210 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
211 ar9485_1_1_mac_core,
212 ARRAY_SIZE(ar9485_1_1_mac_core), 2);
213 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
214 ar9485_1_1_mac_postamble,
215 ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
216
217 /* bb */
218 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
219 ARRAY_SIZE(ar9485_1_1), 2);
220 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
221 ar9485_1_1_baseband_core,
222 ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
223 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
224 ar9485_1_1_baseband_postamble,
225 ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
226
227 /* radio */
228 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
229 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
230 ar9485_1_1_radio_core,
231 ARRAY_SIZE(ar9485_1_1_radio_core), 2);
232 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
233 ar9485_1_1_radio_postamble,
234 ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
235
236 /* soc */
237 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
238 ar9485_1_1_soc_preamble,
239 ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
240 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
241 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
242
243 /* rx/tx gain */
244 INIT_INI_ARRAY(&ah->iniModesRxGain,
245 ar9485Common_wo_xlna_rx_gain_1_1,
246 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
247 INIT_INI_ARRAY(&ah->iniModesTxGain,
248 ar9485_modes_lowest_ob_db_tx_gain_1_1,
249 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
250 5);
251
252 /* Load PCIE SERDES settings from INI */
253
254 /* Awake Setting */
255
256 INIT_INI_ARRAY(&ah->iniPcieSerdes,
257 ar9485_1_1_pcie_phy_clkreq_disable_L1,
258 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
259 2);
260
261 /* Sleep Setting */
262
263 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
264 ar9485_1_1_pcie_phy_clkreq_disable_L1,
265 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
266 2);
267 } else if (AR_SREV_9462_20(ah)) {
268
269 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
270 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,
271 ARRAY_SIZE(ar9462_2p0_mac_core), 2);
272 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
273 ar9462_2p0_mac_postamble,
274 ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);
275
276 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
277 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
278 ar9462_2p0_baseband_core,
279 ARRAY_SIZE(ar9462_2p0_baseband_core), 2);
280 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
281 ar9462_2p0_baseband_postamble,
282 ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);
283
284 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
285 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
286 ar9462_2p0_radio_core,
287 ARRAY_SIZE(ar9462_2p0_radio_core), 2);
288 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
289 ar9462_2p0_radio_postamble,
290 ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);
291 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
292 ar9462_2p0_radio_postamble_sys2ant,
293 ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),
294 5);
295
296 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
297 ar9462_2p0_soc_preamble,
298 ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);
299 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
300 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
301 ar9462_2p0_soc_postamble,
302 ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);
303
304 INIT_INI_ARRAY(&ah->iniModesRxGain,
305 ar9462_common_rx_gain_table_2p0,
306 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
307
308 /* Awake -> Sleep Setting */
309 INIT_INI_ARRAY(&ah->iniPcieSerdes,
310 PCIE_PLL_ON_CREQ_DIS_L1_2P0,
311 ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
312 2);
313 /* Sleep -> Awake Setting */
314 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
315 PCIE_PLL_ON_CREQ_DIS_L1_2P0,
316 ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
317 2);
318
319 /* Fast clock modal settings */
320 INIT_INI_ARRAY(&ah->iniModesFastClock,
321 ar9462_modes_fast_clock_2p0,
322 ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
323
324 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
325 AR9462_BB_CTX_COEFJ(2p0),
326 ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);
327
328 INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
329 ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
330
331 } else if (AR_SREV_9580(ah)) {
332 /* mac */
333 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
334 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
335 ar9580_1p0_mac_core,
336 ARRAY_SIZE(ar9580_1p0_mac_core), 2);
337 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
338 ar9580_1p0_mac_postamble,
339 ARRAY_SIZE(ar9580_1p0_mac_postamble), 5);
340
341 /* bb */
342 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
343 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
344 ar9580_1p0_baseband_core,
345 ARRAY_SIZE(ar9580_1p0_baseband_core), 2);
346 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
347 ar9580_1p0_baseband_postamble,
348 ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5);
349
350 /* radio */
351 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
352 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
353 ar9580_1p0_radio_core,
354 ARRAY_SIZE(ar9580_1p0_radio_core), 2);
355 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
356 ar9580_1p0_radio_postamble,
357 ARRAY_SIZE(ar9580_1p0_radio_postamble), 5);
358
359 /* soc */
360 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
361 ar9580_1p0_soc_preamble,
362 ARRAY_SIZE(ar9580_1p0_soc_preamble), 2);
363 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
364 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
365 ar9580_1p0_soc_postamble,
366 ARRAY_SIZE(ar9580_1p0_soc_postamble), 5);
367
368 /* rx/tx gain */
369 INIT_INI_ARRAY(&ah->iniModesRxGain,
370 ar9580_1p0_rx_gain_table,
371 ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2);
372 INIT_INI_ARRAY(&ah->iniModesTxGain,
373 ar9580_1p0_low_ob_db_tx_gain_table,
374 ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
375 5);
376
377 INIT_INI_ARRAY(&ah->iniModesFastClock,
378 ar9580_1p0_modes_fast_clock,
379 ARRAY_SIZE(ar9580_1p0_modes_fast_clock),
380 3);
381 } else {
382 /* mac */
383 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
384 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
385 ar9300_2p2_mac_core,
386 ARRAY_SIZE(ar9300_2p2_mac_core), 2);
387 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
388 ar9300_2p2_mac_postamble,
389 ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
390
391 /* bb */
392 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
393 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
394 ar9300_2p2_baseband_core,
395 ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
396 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
397 ar9300_2p2_baseband_postamble,
398 ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
399
400 /* radio */
401 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
402 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
403 ar9300_2p2_radio_core,
404 ARRAY_SIZE(ar9300_2p2_radio_core), 2);
405 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
406 ar9300_2p2_radio_postamble,
407 ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
408
409 /* soc */
410 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
411 ar9300_2p2_soc_preamble,
412 ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
413 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
414 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
415 ar9300_2p2_soc_postamble,
416 ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
417
418 /* rx/tx gain */
419 INIT_INI_ARRAY(&ah->iniModesRxGain,
420 ar9300Common_rx_gain_table_2p2,
421 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
422 INIT_INI_ARRAY(&ah->iniModesTxGain,
423 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
424 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
425 5);
426
427 /* Load PCIE SERDES settings from INI */
428
429 /* Awake Setting */
430
431 INIT_INI_ARRAY(&ah->iniPcieSerdes,
432 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
433 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
434 2);
435
436 /* Sleep Setting */
437
438 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
439 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
440 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
441 2);
442
443 /* Fast clock modal settings */
444 INIT_INI_ARRAY(&ah->iniModesFastClock,
445 ar9300Modes_fast_clock_2p2,
446 ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
447 3);
448 }
449}
450
451static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
452{
453 if (AR_SREV_9330_12(ah))
454 INIT_INI_ARRAY(&ah->iniModesTxGain,
455 ar9331_modes_lowest_ob_db_tx_gain_1p2,
456 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
457 5);
458 else if (AR_SREV_9330_11(ah))
459 INIT_INI_ARRAY(&ah->iniModesTxGain,
460 ar9331_modes_lowest_ob_db_tx_gain_1p1,
461 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
462 5);
463 else if (AR_SREV_9340(ah))
464 INIT_INI_ARRAY(&ah->iniModesTxGain,
465 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
466 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
467 5);
468 else if (AR_SREV_9485_11(ah))
469 INIT_INI_ARRAY(&ah->iniModesTxGain,
470 ar9485_modes_lowest_ob_db_tx_gain_1_1,
471 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
472 5);
473 else if (AR_SREV_9580(ah))
474 INIT_INI_ARRAY(&ah->iniModesTxGain,
475 ar9580_1p0_lowest_ob_db_tx_gain_table,
476 ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
477 5);
478 else if (AR_SREV_9462_20(ah))
479 INIT_INI_ARRAY(&ah->iniModesTxGain,
480 ar9462_modes_low_ob_db_tx_gain_table_2p0,
481 ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),
482 5);
483 else
484 INIT_INI_ARRAY(&ah->iniModesTxGain,
485 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
486 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
487 5);
488}
489
490static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
491{
492 if (AR_SREV_9330_12(ah))
493 INIT_INI_ARRAY(&ah->iniModesTxGain,
494 ar9331_modes_high_ob_db_tx_gain_1p2,
495 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
496 5);
497 else if (AR_SREV_9330_11(ah))
498 INIT_INI_ARRAY(&ah->iniModesTxGain,
499 ar9331_modes_high_ob_db_tx_gain_1p1,
500 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
501 5);
502 else if (AR_SREV_9340(ah))
503 INIT_INI_ARRAY(&ah->iniModesTxGain,
504 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
505 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
506 5);
507 else if (AR_SREV_9485_11(ah))
508 INIT_INI_ARRAY(&ah->iniModesTxGain,
509 ar9485Modes_high_ob_db_tx_gain_1_1,
510 ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
511 5);
512 else if (AR_SREV_9580(ah))
513 INIT_INI_ARRAY(&ah->iniModesTxGain,
514 ar9580_1p0_high_ob_db_tx_gain_table,
515 ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
516 5);
517 else if (AR_SREV_9462_20(ah))
518 INIT_INI_ARRAY(&ah->iniModesTxGain,
519 ar9462_modes_high_ob_db_tx_gain_table_2p0,
520 ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),
521 5);
522 else
523 INIT_INI_ARRAY(&ah->iniModesTxGain,
524 ar9300Modes_high_ob_db_tx_gain_table_2p2,
525 ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
526 5);
527}
528
529static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
530{
531 if (AR_SREV_9330_12(ah))
532 INIT_INI_ARRAY(&ah->iniModesTxGain,
533 ar9331_modes_low_ob_db_tx_gain_1p2,
534 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
535 5);
536 else if (AR_SREV_9330_11(ah))
537 INIT_INI_ARRAY(&ah->iniModesTxGain,
538 ar9331_modes_low_ob_db_tx_gain_1p1,
539 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
540 5);
541 else if (AR_SREV_9340(ah))
542 INIT_INI_ARRAY(&ah->iniModesTxGain,
543 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
544 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
545 5);
546 else if (AR_SREV_9485_11(ah))
547 INIT_INI_ARRAY(&ah->iniModesTxGain,
548 ar9485Modes_low_ob_db_tx_gain_1_1,
549 ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
550 5);
551 else if (AR_SREV_9580(ah))
552 INIT_INI_ARRAY(&ah->iniModesTxGain,
553 ar9580_1p0_low_ob_db_tx_gain_table,
554 ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
555 5);
556 else
557 INIT_INI_ARRAY(&ah->iniModesTxGain,
558 ar9300Modes_low_ob_db_tx_gain_table_2p2,
559 ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
560 5);
561}
562
563static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
564{
565 if (AR_SREV_9330_12(ah))
566 INIT_INI_ARRAY(&ah->iniModesTxGain,
567 ar9331_modes_high_power_tx_gain_1p2,
568 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
569 5);
570 else if (AR_SREV_9330_11(ah))
571 INIT_INI_ARRAY(&ah->iniModesTxGain,
572 ar9331_modes_high_power_tx_gain_1p1,
573 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
574 5);
575 else if (AR_SREV_9340(ah))
576 INIT_INI_ARRAY(&ah->iniModesTxGain,
577 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
578 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
579 5);
580 else if (AR_SREV_9485_11(ah))
581 INIT_INI_ARRAY(&ah->iniModesTxGain,
582 ar9485Modes_high_power_tx_gain_1_1,
583 ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
584 5);
585 else if (AR_SREV_9580(ah))
586 INIT_INI_ARRAY(&ah->iniModesTxGain,
587 ar9580_1p0_high_power_tx_gain_table,
588 ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table),
589 5);
590 else
591 INIT_INI_ARRAY(&ah->iniModesTxGain,
592 ar9300Modes_high_power_tx_gain_table_2p2,
593 ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
594 5);
595}
596
597static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
598{
599 switch (ar9003_hw_get_tx_gain_idx(ah)) {
600 case 0:
601 default:
602 ar9003_tx_gain_table_mode0(ah);
603 break;
604 case 1:
605 ar9003_tx_gain_table_mode1(ah);
606 break;
607 case 2:
608 ar9003_tx_gain_table_mode2(ah);
609 break;
610 case 3:
611 ar9003_tx_gain_table_mode3(ah);
612 break;
613 }
614}
615
616static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
617{
618 if (AR_SREV_9330_12(ah))
619 INIT_INI_ARRAY(&ah->iniModesRxGain,
620 ar9331_common_rx_gain_1p2,
621 ARRAY_SIZE(ar9331_common_rx_gain_1p2),
622 2);
623 else if (AR_SREV_9330_11(ah))
624 INIT_INI_ARRAY(&ah->iniModesRxGain,
625 ar9331_common_rx_gain_1p1,
626 ARRAY_SIZE(ar9331_common_rx_gain_1p1),
627 2);
628 else if (AR_SREV_9340(ah))
629 INIT_INI_ARRAY(&ah->iniModesRxGain,
630 ar9340Common_rx_gain_table_1p0,
631 ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
632 2);
633 else if (AR_SREV_9485_11(ah))
634 INIT_INI_ARRAY(&ah->iniModesRxGain,
635 ar9485Common_wo_xlna_rx_gain_1_1,
636 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
637 2);
638 else if (AR_SREV_9580(ah))
639 INIT_INI_ARRAY(&ah->iniModesRxGain,
640 ar9580_1p0_rx_gain_table,
641 ARRAY_SIZE(ar9580_1p0_rx_gain_table),
642 2);
643 else if (AR_SREV_9462_20(ah))
644 INIT_INI_ARRAY(&ah->iniModesRxGain,
645 ar9462_common_rx_gain_table_2p0,
646 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),
647 2);
648 else
649 INIT_INI_ARRAY(&ah->iniModesRxGain,
650 ar9300Common_rx_gain_table_2p2,
651 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
652 2);
653}
654
655static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
656{
657 if (AR_SREV_9330_12(ah))
658 INIT_INI_ARRAY(&ah->iniModesRxGain,
659 ar9331_common_wo_xlna_rx_gain_1p2,
660 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
661 2);
662 else if (AR_SREV_9330_11(ah))
663 INIT_INI_ARRAY(&ah->iniModesRxGain,
664 ar9331_common_wo_xlna_rx_gain_1p1,
665 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
666 2);
667 else if (AR_SREV_9340(ah))
668 INIT_INI_ARRAY(&ah->iniModesRxGain,
669 ar9340Common_wo_xlna_rx_gain_table_1p0,
670 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
671 2);
672 else if (AR_SREV_9485_11(ah))
673 INIT_INI_ARRAY(&ah->iniModesRxGain,
674 ar9485Common_wo_xlna_rx_gain_1_1,
675 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
676 2);
677 else if (AR_SREV_9462_20(ah))
678 INIT_INI_ARRAY(&ah->iniModesRxGain,
679 ar9462_common_wo_xlna_rx_gain_table_2p0,
680 ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
681 2);
682 else if (AR_SREV_9580(ah))
683 INIT_INI_ARRAY(&ah->iniModesRxGain,
684 ar9580_1p0_wo_xlna_rx_gain_table,
685 ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
686 2);
687 else
688 INIT_INI_ARRAY(&ah->iniModesRxGain,
689 ar9300Common_wo_xlna_rx_gain_table_2p2,
690 ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
691 2);
692}
693
694static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
695{
696 if (AR_SREV_9462_20(ah))
697 INIT_INI_ARRAY(&ah->iniModesRxGain,
698 ar9462_common_mixed_rx_gain_table_2p0,
699 ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
700}
701
702static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
703{
704 switch (ar9003_hw_get_rx_gain_idx(ah)) {
705 case 0:
706 default:
707 ar9003_rx_gain_table_mode0(ah);
708 break;
709 case 1:
710 ar9003_rx_gain_table_mode1(ah);
711 break;
712 case 2:
713 ar9003_rx_gain_table_mode2(ah);
714 break;
715 }
716}
717
718/* set gain table pointers according to values read from the eeprom */
719static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
720{
721 ar9003_tx_gain_table_apply(ah);
722 ar9003_rx_gain_table_apply(ah);
723}
724
725/*
726 * Helper for ASPM support.
727 *
728 * Disable PLL when in L0s as well as receiver clock when in L1.
729 * This power saving option must be enabled through the SerDes.
730 *
731 * Programming the SerDes must go through the same 288 bit serial shift
732 * register as the other analog registers. Hence the 9 writes.
733 */
734static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
735 bool power_off)
736{
737 /* Nothing to do on restore for 11N */
738 if (!power_off /* !restore */) {
739 /* set bit 19 to allow forcing of pcie core into L1 state */
740 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
741
742 /* Several PCIe massages to ensure proper behaviour */
743 if (ah->config.pcie_waen)
744 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
745 else
746 REG_WRITE(ah, AR_WA, ah->WARegVal);
747 }
748
749 /*
750 * Configire PCIE after Ini init. SERDES values now come from ini file
751 * This enables PCIe low power mode.
752 */
753 if (ah->config.pcieSerDesWrite) {
754 unsigned int i;
755 struct ar5416IniArray *array;
756
757 array = power_off ? &ah->iniPcieSerdes :
758 &ah->iniPcieSerdesLowPower;
759
760 for (i = 0; i < array->ia_rows; i++) {
761 REG_WRITE(ah,
762 INI_RA(array, i, 0),
763 INI_RA(array, i, 1));
764 }
765 }
766}
767
768/* Sets up the AR9003 hardware familiy callbacks */
769void ar9003_hw_attach_ops(struct ath_hw *ah)
770{
771 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
772 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
773
774 priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
775 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
776
777 ops->config_pci_powersave = ar9003_hw_configpcipowersave;
778
779 ar9003_hw_attach_phy_ops(ah);
780 ar9003_hw_attach_calib_ops(ah);
781 ar9003_hw_attach_mac_ops(ah);
782}