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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 *
6 * Right now, I am very wasteful with the buffers. I allocate memory
7 * pages and then divide them into 2K frame buffers. This way I know I
8 * have buffers large enough to hold one frame within one buffer descriptor.
9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
10 * will be much more memory efficient and will easily handle lots of
11 * small packets.
12 *
13 * Much better multiple PHY support by Magnus Damm.
14 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 *
16 * Support for FEC controller of ColdFire processors.
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 *
19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
21 *
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
23 */
24
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/string.h>
28#include <linux/pm_runtime.h>
29#include <linux/ptrace.h>
30#include <linux/errno.h>
31#include <linux/ioport.h>
32#include <linux/slab.h>
33#include <linux/interrupt.h>
34#include <linux/delay.h>
35#include <linux/netdevice.h>
36#include <linux/etherdevice.h>
37#include <linux/skbuff.h>
38#include <linux/in.h>
39#include <linux/ip.h>
40#include <net/ip.h>
41#include <net/selftests.h>
42#include <net/tso.h>
43#include <linux/tcp.h>
44#include <linux/udp.h>
45#include <linux/icmp.h>
46#include <linux/spinlock.h>
47#include <linux/workqueue.h>
48#include <linux/bitops.h>
49#include <linux/io.h>
50#include <linux/irq.h>
51#include <linux/clk.h>
52#include <linux/crc32.h>
53#include <linux/platform_device.h>
54#include <linux/mdio.h>
55#include <linux/phy.h>
56#include <linux/fec.h>
57#include <linux/of.h>
58#include <linux/of_device.h>
59#include <linux/of_gpio.h>
60#include <linux/of_mdio.h>
61#include <linux/of_net.h>
62#include <linux/regulator/consumer.h>
63#include <linux/if_vlan.h>
64#include <linux/pinctrl/consumer.h>
65#include <linux/prefetch.h>
66#include <linux/mfd/syscon.h>
67#include <linux/regmap.h>
68#include <soc/imx/cpuidle.h>
69
70#include <asm/cacheflush.h>
71
72#include "fec.h"
73
74static void set_multicast_list(struct net_device *ndev);
75static void fec_enet_itr_coal_init(struct net_device *ndev);
76
77#define DRIVER_NAME "fec"
78
79static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2};
80
81/* Pause frame feild and FIFO threshold */
82#define FEC_ENET_FCE (1 << 5)
83#define FEC_ENET_RSEM_V 0x84
84#define FEC_ENET_RSFL_V 16
85#define FEC_ENET_RAEM_V 0x8
86#define FEC_ENET_RAFL_V 0x8
87#define FEC_ENET_OPD_V 0xFFF0
88#define FEC_MDIO_PM_TIMEOUT 100 /* ms */
89
90struct fec_devinfo {
91 u32 quirks;
92};
93
94static const struct fec_devinfo fec_imx25_info = {
95 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR |
96 FEC_QUIRK_HAS_FRREG,
97};
98
99static const struct fec_devinfo fec_imx27_info = {
100 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG,
101};
102
103static const struct fec_devinfo fec_imx28_info = {
104 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
105 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
106 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII |
107 FEC_QUIRK_NO_HARD_RESET,
108};
109
110static const struct fec_devinfo fec_imx6q_info = {
111 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
112 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
113 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
114 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII,
115};
116
117static const struct fec_devinfo fec_mvf600_info = {
118 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
119};
120
121static const struct fec_devinfo fec_imx6x_info = {
122 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
125 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
126 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
127 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES,
128};
129
130static const struct fec_devinfo fec_imx6ul_info = {
131 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
132 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
133 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
134 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
135 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII,
136};
137
138static struct platform_device_id fec_devtype[] = {
139 {
140 /* keep it for coldfire */
141 .name = DRIVER_NAME,
142 .driver_data = 0,
143 }, {
144 .name = "imx25-fec",
145 .driver_data = (kernel_ulong_t)&fec_imx25_info,
146 }, {
147 .name = "imx27-fec",
148 .driver_data = (kernel_ulong_t)&fec_imx27_info,
149 }, {
150 .name = "imx28-fec",
151 .driver_data = (kernel_ulong_t)&fec_imx28_info,
152 }, {
153 .name = "imx6q-fec",
154 .driver_data = (kernel_ulong_t)&fec_imx6q_info,
155 }, {
156 .name = "mvf600-fec",
157 .driver_data = (kernel_ulong_t)&fec_mvf600_info,
158 }, {
159 .name = "imx6sx-fec",
160 .driver_data = (kernel_ulong_t)&fec_imx6x_info,
161 }, {
162 .name = "imx6ul-fec",
163 .driver_data = (kernel_ulong_t)&fec_imx6ul_info,
164 }, {
165 /* sentinel */
166 }
167};
168MODULE_DEVICE_TABLE(platform, fec_devtype);
169
170enum imx_fec_type {
171 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
172 IMX27_FEC, /* runs on i.mx27/35/51 */
173 IMX28_FEC,
174 IMX6Q_FEC,
175 MVF600_FEC,
176 IMX6SX_FEC,
177 IMX6UL_FEC,
178};
179
180static const struct of_device_id fec_dt_ids[] = {
181 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
182 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
183 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
184 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
185 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
186 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
187 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
188 { /* sentinel */ }
189};
190MODULE_DEVICE_TABLE(of, fec_dt_ids);
191
192static unsigned char macaddr[ETH_ALEN];
193module_param_array(macaddr, byte, NULL, 0);
194MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
195
196#if defined(CONFIG_M5272)
197/*
198 * Some hardware gets it MAC address out of local flash memory.
199 * if this is non-zero then assume it is the address to get MAC from.
200 */
201#if defined(CONFIG_NETtel)
202#define FEC_FLASHMAC 0xf0006006
203#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
204#define FEC_FLASHMAC 0xf0006000
205#elif defined(CONFIG_CANCam)
206#define FEC_FLASHMAC 0xf0020000
207#elif defined (CONFIG_M5272C3)
208#define FEC_FLASHMAC (0xffe04000 + 4)
209#elif defined(CONFIG_MOD5272)
210#define FEC_FLASHMAC 0xffc0406b
211#else
212#define FEC_FLASHMAC 0
213#endif
214#endif /* CONFIG_M5272 */
215
216/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
217 *
218 * 2048 byte skbufs are allocated. However, alignment requirements
219 * varies between FEC variants. Worst case is 64, so round down by 64.
220 */
221#define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64))
222#define PKT_MINBUF_SIZE 64
223
224/* FEC receive acceleration */
225#define FEC_RACC_IPDIS (1 << 1)
226#define FEC_RACC_PRODIS (1 << 2)
227#define FEC_RACC_SHIFT16 BIT(7)
228#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
229
230/* MIB Control Register */
231#define FEC_MIB_CTRLSTAT_DISABLE BIT(31)
232
233/*
234 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
235 * size bits. Other FEC hardware does not, so we need to take that into
236 * account when setting it.
237 */
238#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
239 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
240 defined(CONFIG_ARM64)
241#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
242#else
243#define OPT_FRAME_SIZE 0
244#endif
245
246/* FEC MII MMFR bits definition */
247#define FEC_MMFR_ST (1 << 30)
248#define FEC_MMFR_ST_C45 (0)
249#define FEC_MMFR_OP_READ (2 << 28)
250#define FEC_MMFR_OP_READ_C45 (3 << 28)
251#define FEC_MMFR_OP_WRITE (1 << 28)
252#define FEC_MMFR_OP_ADDR_WRITE (0)
253#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
254#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
255#define FEC_MMFR_TA (2 << 16)
256#define FEC_MMFR_DATA(v) (v & 0xffff)
257/* FEC ECR bits definition */
258#define FEC_ECR_MAGICEN (1 << 2)
259#define FEC_ECR_SLEEP (1 << 3)
260
261#define FEC_MII_TIMEOUT 30000 /* us */
262
263/* Transmitter timeout */
264#define TX_TIMEOUT (2 * HZ)
265
266#define FEC_PAUSE_FLAG_AUTONEG 0x1
267#define FEC_PAUSE_FLAG_ENABLE 0x2
268#define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
269#define FEC_WOL_FLAG_ENABLE (0x1 << 1)
270#define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
271
272#define COPYBREAK_DEFAULT 256
273
274/* Max number of allowed TCP segments for software TSO */
275#define FEC_MAX_TSO_SEGS 100
276#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
277
278#define IS_TSO_HEADER(txq, addr) \
279 ((addr >= txq->tso_hdrs_dma) && \
280 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
281
282static int mii_cnt;
283
284static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
285 struct bufdesc_prop *bd)
286{
287 return (bdp >= bd->last) ? bd->base
288 : (struct bufdesc *)(((void *)bdp) + bd->dsize);
289}
290
291static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
292 struct bufdesc_prop *bd)
293{
294 return (bdp <= bd->base) ? bd->last
295 : (struct bufdesc *)(((void *)bdp) - bd->dsize);
296}
297
298static int fec_enet_get_bd_index(struct bufdesc *bdp,
299 struct bufdesc_prop *bd)
300{
301 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
302}
303
304static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
305{
306 int entries;
307
308 entries = (((const char *)txq->dirty_tx -
309 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
310
311 return entries >= 0 ? entries : entries + txq->bd.ring_size;
312}
313
314static void swap_buffer(void *bufaddr, int len)
315{
316 int i;
317 unsigned int *buf = bufaddr;
318
319 for (i = 0; i < len; i += 4, buf++)
320 swab32s(buf);
321}
322
323static void swap_buffer2(void *dst_buf, void *src_buf, int len)
324{
325 int i;
326 unsigned int *src = src_buf;
327 unsigned int *dst = dst_buf;
328
329 for (i = 0; i < len; i += 4, src++, dst++)
330 *dst = swab32p(src);
331}
332
333static void fec_dump(struct net_device *ndev)
334{
335 struct fec_enet_private *fep = netdev_priv(ndev);
336 struct bufdesc *bdp;
337 struct fec_enet_priv_tx_q *txq;
338 int index = 0;
339
340 netdev_info(ndev, "TX ring dump\n");
341 pr_info("Nr SC addr len SKB\n");
342
343 txq = fep->tx_queue[0];
344 bdp = txq->bd.base;
345
346 do {
347 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
348 index,
349 bdp == txq->bd.cur ? 'S' : ' ',
350 bdp == txq->dirty_tx ? 'H' : ' ',
351 fec16_to_cpu(bdp->cbd_sc),
352 fec32_to_cpu(bdp->cbd_bufaddr),
353 fec16_to_cpu(bdp->cbd_datlen),
354 txq->tx_skbuff[index]);
355 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
356 index++;
357 } while (bdp != txq->bd.base);
358}
359
360static inline bool is_ipv4_pkt(struct sk_buff *skb)
361{
362 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
363}
364
365static int
366fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
367{
368 /* Only run for packets requiring a checksum. */
369 if (skb->ip_summed != CHECKSUM_PARTIAL)
370 return 0;
371
372 if (unlikely(skb_cow_head(skb, 0)))
373 return -1;
374
375 if (is_ipv4_pkt(skb))
376 ip_hdr(skb)->check = 0;
377 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
378
379 return 0;
380}
381
382static struct bufdesc *
383fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
384 struct sk_buff *skb,
385 struct net_device *ndev)
386{
387 struct fec_enet_private *fep = netdev_priv(ndev);
388 struct bufdesc *bdp = txq->bd.cur;
389 struct bufdesc_ex *ebdp;
390 int nr_frags = skb_shinfo(skb)->nr_frags;
391 int frag, frag_len;
392 unsigned short status;
393 unsigned int estatus = 0;
394 skb_frag_t *this_frag;
395 unsigned int index;
396 void *bufaddr;
397 dma_addr_t addr;
398 int i;
399
400 for (frag = 0; frag < nr_frags; frag++) {
401 this_frag = &skb_shinfo(skb)->frags[frag];
402 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
403 ebdp = (struct bufdesc_ex *)bdp;
404
405 status = fec16_to_cpu(bdp->cbd_sc);
406 status &= ~BD_ENET_TX_STATS;
407 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
408 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]);
409
410 /* Handle the last BD specially */
411 if (frag == nr_frags - 1) {
412 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
413 if (fep->bufdesc_ex) {
414 estatus |= BD_ENET_TX_INT;
415 if (unlikely(skb_shinfo(skb)->tx_flags &
416 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
417 estatus |= BD_ENET_TX_TS;
418 }
419 }
420
421 if (fep->bufdesc_ex) {
422 if (fep->quirks & FEC_QUIRK_HAS_AVB)
423 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
424 if (skb->ip_summed == CHECKSUM_PARTIAL)
425 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
426
427 ebdp->cbd_bdu = 0;
428 ebdp->cbd_esc = cpu_to_fec32(estatus);
429 }
430
431 bufaddr = skb_frag_address(this_frag);
432
433 index = fec_enet_get_bd_index(bdp, &txq->bd);
434 if (((unsigned long) bufaddr) & fep->tx_align ||
435 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
436 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
437 bufaddr = txq->tx_bounce[index];
438
439 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
440 swap_buffer(bufaddr, frag_len);
441 }
442
443 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
444 DMA_TO_DEVICE);
445 if (dma_mapping_error(&fep->pdev->dev, addr)) {
446 if (net_ratelimit())
447 netdev_err(ndev, "Tx DMA memory map failed\n");
448 goto dma_mapping_error;
449 }
450
451 bdp->cbd_bufaddr = cpu_to_fec32(addr);
452 bdp->cbd_datlen = cpu_to_fec16(frag_len);
453 /* Make sure the updates to rest of the descriptor are
454 * performed before transferring ownership.
455 */
456 wmb();
457 bdp->cbd_sc = cpu_to_fec16(status);
458 }
459
460 return bdp;
461dma_mapping_error:
462 bdp = txq->bd.cur;
463 for (i = 0; i < frag; i++) {
464 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
465 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
466 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
467 }
468 return ERR_PTR(-ENOMEM);
469}
470
471static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
472 struct sk_buff *skb, struct net_device *ndev)
473{
474 struct fec_enet_private *fep = netdev_priv(ndev);
475 int nr_frags = skb_shinfo(skb)->nr_frags;
476 struct bufdesc *bdp, *last_bdp;
477 void *bufaddr;
478 dma_addr_t addr;
479 unsigned short status;
480 unsigned short buflen;
481 unsigned int estatus = 0;
482 unsigned int index;
483 int entries_free;
484
485 entries_free = fec_enet_get_free_txdesc_num(txq);
486 if (entries_free < MAX_SKB_FRAGS + 1) {
487 dev_kfree_skb_any(skb);
488 if (net_ratelimit())
489 netdev_err(ndev, "NOT enough BD for SG!\n");
490 return NETDEV_TX_OK;
491 }
492
493 /* Protocol checksum off-load for TCP and UDP. */
494 if (fec_enet_clear_csum(skb, ndev)) {
495 dev_kfree_skb_any(skb);
496 return NETDEV_TX_OK;
497 }
498
499 /* Fill in a Tx ring entry */
500 bdp = txq->bd.cur;
501 last_bdp = bdp;
502 status = fec16_to_cpu(bdp->cbd_sc);
503 status &= ~BD_ENET_TX_STATS;
504
505 /* Set buffer length and buffer pointer */
506 bufaddr = skb->data;
507 buflen = skb_headlen(skb);
508
509 index = fec_enet_get_bd_index(bdp, &txq->bd);
510 if (((unsigned long) bufaddr) & fep->tx_align ||
511 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
512 memcpy(txq->tx_bounce[index], skb->data, buflen);
513 bufaddr = txq->tx_bounce[index];
514
515 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
516 swap_buffer(bufaddr, buflen);
517 }
518
519 /* Push the data cache so the CPM does not get stale memory data. */
520 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
521 if (dma_mapping_error(&fep->pdev->dev, addr)) {
522 dev_kfree_skb_any(skb);
523 if (net_ratelimit())
524 netdev_err(ndev, "Tx DMA memory map failed\n");
525 return NETDEV_TX_OK;
526 }
527
528 if (nr_frags) {
529 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
530 if (IS_ERR(last_bdp)) {
531 dma_unmap_single(&fep->pdev->dev, addr,
532 buflen, DMA_TO_DEVICE);
533 dev_kfree_skb_any(skb);
534 return NETDEV_TX_OK;
535 }
536 } else {
537 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
538 if (fep->bufdesc_ex) {
539 estatus = BD_ENET_TX_INT;
540 if (unlikely(skb_shinfo(skb)->tx_flags &
541 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
542 estatus |= BD_ENET_TX_TS;
543 }
544 }
545 bdp->cbd_bufaddr = cpu_to_fec32(addr);
546 bdp->cbd_datlen = cpu_to_fec16(buflen);
547
548 if (fep->bufdesc_ex) {
549
550 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
551
552 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
553 fep->hwts_tx_en))
554 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
555
556 if (fep->quirks & FEC_QUIRK_HAS_AVB)
557 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
558
559 if (skb->ip_summed == CHECKSUM_PARTIAL)
560 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
561
562 ebdp->cbd_bdu = 0;
563 ebdp->cbd_esc = cpu_to_fec32(estatus);
564 }
565
566 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
567 /* Save skb pointer */
568 txq->tx_skbuff[index] = skb;
569
570 /* Make sure the updates to rest of the descriptor are performed before
571 * transferring ownership.
572 */
573 wmb();
574
575 /* Send it on its way. Tell FEC it's ready, interrupt when done,
576 * it's the last BD of the frame, and to put the CRC on the end.
577 */
578 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
579 bdp->cbd_sc = cpu_to_fec16(status);
580
581 /* If this was the last BD in the ring, start at the beginning again. */
582 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
583
584 skb_tx_timestamp(skb);
585
586 /* Make sure the update to bdp and tx_skbuff are performed before
587 * txq->bd.cur.
588 */
589 wmb();
590 txq->bd.cur = bdp;
591
592 /* Trigger transmission start */
593 writel(0, txq->bd.reg_desc_active);
594
595 return 0;
596}
597
598static int
599fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
600 struct net_device *ndev,
601 struct bufdesc *bdp, int index, char *data,
602 int size, bool last_tcp, bool is_last)
603{
604 struct fec_enet_private *fep = netdev_priv(ndev);
605 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
606 unsigned short status;
607 unsigned int estatus = 0;
608 dma_addr_t addr;
609
610 status = fec16_to_cpu(bdp->cbd_sc);
611 status &= ~BD_ENET_TX_STATS;
612
613 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
614
615 if (((unsigned long) data) & fep->tx_align ||
616 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
617 memcpy(txq->tx_bounce[index], data, size);
618 data = txq->tx_bounce[index];
619
620 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
621 swap_buffer(data, size);
622 }
623
624 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
625 if (dma_mapping_error(&fep->pdev->dev, addr)) {
626 dev_kfree_skb_any(skb);
627 if (net_ratelimit())
628 netdev_err(ndev, "Tx DMA memory map failed\n");
629 return NETDEV_TX_BUSY;
630 }
631
632 bdp->cbd_datlen = cpu_to_fec16(size);
633 bdp->cbd_bufaddr = cpu_to_fec32(addr);
634
635 if (fep->bufdesc_ex) {
636 if (fep->quirks & FEC_QUIRK_HAS_AVB)
637 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
638 if (skb->ip_summed == CHECKSUM_PARTIAL)
639 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
640 ebdp->cbd_bdu = 0;
641 ebdp->cbd_esc = cpu_to_fec32(estatus);
642 }
643
644 /* Handle the last BD specially */
645 if (last_tcp)
646 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
647 if (is_last) {
648 status |= BD_ENET_TX_INTR;
649 if (fep->bufdesc_ex)
650 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
651 }
652
653 bdp->cbd_sc = cpu_to_fec16(status);
654
655 return 0;
656}
657
658static int
659fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
660 struct sk_buff *skb, struct net_device *ndev,
661 struct bufdesc *bdp, int index)
662{
663 struct fec_enet_private *fep = netdev_priv(ndev);
664 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
665 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
666 void *bufaddr;
667 unsigned long dmabuf;
668 unsigned short status;
669 unsigned int estatus = 0;
670
671 status = fec16_to_cpu(bdp->cbd_sc);
672 status &= ~BD_ENET_TX_STATS;
673 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
674
675 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
676 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
677 if (((unsigned long)bufaddr) & fep->tx_align ||
678 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
679 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
680 bufaddr = txq->tx_bounce[index];
681
682 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
683 swap_buffer(bufaddr, hdr_len);
684
685 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
686 hdr_len, DMA_TO_DEVICE);
687 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
688 dev_kfree_skb_any(skb);
689 if (net_ratelimit())
690 netdev_err(ndev, "Tx DMA memory map failed\n");
691 return NETDEV_TX_BUSY;
692 }
693 }
694
695 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
696 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
697
698 if (fep->bufdesc_ex) {
699 if (fep->quirks & FEC_QUIRK_HAS_AVB)
700 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
701 if (skb->ip_summed == CHECKSUM_PARTIAL)
702 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
703 ebdp->cbd_bdu = 0;
704 ebdp->cbd_esc = cpu_to_fec32(estatus);
705 }
706
707 bdp->cbd_sc = cpu_to_fec16(status);
708
709 return 0;
710}
711
712static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
713 struct sk_buff *skb,
714 struct net_device *ndev)
715{
716 struct fec_enet_private *fep = netdev_priv(ndev);
717 int hdr_len, total_len, data_left;
718 struct bufdesc *bdp = txq->bd.cur;
719 struct tso_t tso;
720 unsigned int index = 0;
721 int ret;
722
723 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
724 dev_kfree_skb_any(skb);
725 if (net_ratelimit())
726 netdev_err(ndev, "NOT enough BD for TSO!\n");
727 return NETDEV_TX_OK;
728 }
729
730 /* Protocol checksum off-load for TCP and UDP. */
731 if (fec_enet_clear_csum(skb, ndev)) {
732 dev_kfree_skb_any(skb);
733 return NETDEV_TX_OK;
734 }
735
736 /* Initialize the TSO handler, and prepare the first payload */
737 hdr_len = tso_start(skb, &tso);
738
739 total_len = skb->len - hdr_len;
740 while (total_len > 0) {
741 char *hdr;
742
743 index = fec_enet_get_bd_index(bdp, &txq->bd);
744 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
745 total_len -= data_left;
746
747 /* prepare packet headers: MAC + IP + TCP */
748 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
749 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
750 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
751 if (ret)
752 goto err_release;
753
754 while (data_left > 0) {
755 int size;
756
757 size = min_t(int, tso.size, data_left);
758 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
759 index = fec_enet_get_bd_index(bdp, &txq->bd);
760 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
761 bdp, index,
762 tso.data, size,
763 size == data_left,
764 total_len == 0);
765 if (ret)
766 goto err_release;
767
768 data_left -= size;
769 tso_build_data(skb, &tso, size);
770 }
771
772 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
773 }
774
775 /* Save skb pointer */
776 txq->tx_skbuff[index] = skb;
777
778 skb_tx_timestamp(skb);
779 txq->bd.cur = bdp;
780
781 /* Trigger transmission start */
782 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
783 !readl(txq->bd.reg_desc_active) ||
784 !readl(txq->bd.reg_desc_active) ||
785 !readl(txq->bd.reg_desc_active) ||
786 !readl(txq->bd.reg_desc_active))
787 writel(0, txq->bd.reg_desc_active);
788
789 return 0;
790
791err_release:
792 /* TODO: Release all used data descriptors for TSO */
793 return ret;
794}
795
796static netdev_tx_t
797fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
798{
799 struct fec_enet_private *fep = netdev_priv(ndev);
800 int entries_free;
801 unsigned short queue;
802 struct fec_enet_priv_tx_q *txq;
803 struct netdev_queue *nq;
804 int ret;
805
806 queue = skb_get_queue_mapping(skb);
807 txq = fep->tx_queue[queue];
808 nq = netdev_get_tx_queue(ndev, queue);
809
810 if (skb_is_gso(skb))
811 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
812 else
813 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
814 if (ret)
815 return ret;
816
817 entries_free = fec_enet_get_free_txdesc_num(txq);
818 if (entries_free <= txq->tx_stop_threshold)
819 netif_tx_stop_queue(nq);
820
821 return NETDEV_TX_OK;
822}
823
824/* Init RX & TX buffer descriptors
825 */
826static void fec_enet_bd_init(struct net_device *dev)
827{
828 struct fec_enet_private *fep = netdev_priv(dev);
829 struct fec_enet_priv_tx_q *txq;
830 struct fec_enet_priv_rx_q *rxq;
831 struct bufdesc *bdp;
832 unsigned int i;
833 unsigned int q;
834
835 for (q = 0; q < fep->num_rx_queues; q++) {
836 /* Initialize the receive buffer descriptors. */
837 rxq = fep->rx_queue[q];
838 bdp = rxq->bd.base;
839
840 for (i = 0; i < rxq->bd.ring_size; i++) {
841
842 /* Initialize the BD for every fragment in the page. */
843 if (bdp->cbd_bufaddr)
844 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
845 else
846 bdp->cbd_sc = cpu_to_fec16(0);
847 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
848 }
849
850 /* Set the last buffer to wrap */
851 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
852 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
853
854 rxq->bd.cur = rxq->bd.base;
855 }
856
857 for (q = 0; q < fep->num_tx_queues; q++) {
858 /* ...and the same for transmit */
859 txq = fep->tx_queue[q];
860 bdp = txq->bd.base;
861 txq->bd.cur = bdp;
862
863 for (i = 0; i < txq->bd.ring_size; i++) {
864 /* Initialize the BD for every fragment in the page. */
865 bdp->cbd_sc = cpu_to_fec16(0);
866 if (bdp->cbd_bufaddr &&
867 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
868 dma_unmap_single(&fep->pdev->dev,
869 fec32_to_cpu(bdp->cbd_bufaddr),
870 fec16_to_cpu(bdp->cbd_datlen),
871 DMA_TO_DEVICE);
872 if (txq->tx_skbuff[i]) {
873 dev_kfree_skb_any(txq->tx_skbuff[i]);
874 txq->tx_skbuff[i] = NULL;
875 }
876 bdp->cbd_bufaddr = cpu_to_fec32(0);
877 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
878 }
879
880 /* Set the last buffer to wrap */
881 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
882 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
883 txq->dirty_tx = bdp;
884 }
885}
886
887static void fec_enet_active_rxring(struct net_device *ndev)
888{
889 struct fec_enet_private *fep = netdev_priv(ndev);
890 int i;
891
892 for (i = 0; i < fep->num_rx_queues; i++)
893 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
894}
895
896static void fec_enet_enable_ring(struct net_device *ndev)
897{
898 struct fec_enet_private *fep = netdev_priv(ndev);
899 struct fec_enet_priv_tx_q *txq;
900 struct fec_enet_priv_rx_q *rxq;
901 int i;
902
903 for (i = 0; i < fep->num_rx_queues; i++) {
904 rxq = fep->rx_queue[i];
905 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
906 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
907
908 /* enable DMA1/2 */
909 if (i)
910 writel(RCMR_MATCHEN | RCMR_CMP(i),
911 fep->hwp + FEC_RCMR(i));
912 }
913
914 for (i = 0; i < fep->num_tx_queues; i++) {
915 txq = fep->tx_queue[i];
916 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
917
918 /* enable DMA1/2 */
919 if (i)
920 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
921 fep->hwp + FEC_DMA_CFG(i));
922 }
923}
924
925static void fec_enet_reset_skb(struct net_device *ndev)
926{
927 struct fec_enet_private *fep = netdev_priv(ndev);
928 struct fec_enet_priv_tx_q *txq;
929 int i, j;
930
931 for (i = 0; i < fep->num_tx_queues; i++) {
932 txq = fep->tx_queue[i];
933
934 for (j = 0; j < txq->bd.ring_size; j++) {
935 if (txq->tx_skbuff[j]) {
936 dev_kfree_skb_any(txq->tx_skbuff[j]);
937 txq->tx_skbuff[j] = NULL;
938 }
939 }
940 }
941}
942
943/*
944 * This function is called to start or restart the FEC during a link
945 * change, transmit timeout, or to reconfigure the FEC. The network
946 * packet processing for this device must be stopped before this call.
947 */
948static void
949fec_restart(struct net_device *ndev)
950{
951 struct fec_enet_private *fep = netdev_priv(ndev);
952 u32 temp_mac[2];
953 u32 rcntl = OPT_FRAME_SIZE | 0x04;
954 u32 ecntl = 0x2; /* ETHEREN */
955
956 /* Whack a reset. We should wait for this.
957 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
958 * instead of reset MAC itself.
959 */
960 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES ||
961 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) {
962 writel(0, fep->hwp + FEC_ECNTRL);
963 } else {
964 writel(1, fep->hwp + FEC_ECNTRL);
965 udelay(10);
966 }
967
968 /*
969 * enet-mac reset will reset mac address registers too,
970 * so need to reconfigure it.
971 */
972 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
973 writel((__force u32)cpu_to_be32(temp_mac[0]),
974 fep->hwp + FEC_ADDR_LOW);
975 writel((__force u32)cpu_to_be32(temp_mac[1]),
976 fep->hwp + FEC_ADDR_HIGH);
977
978 /* Clear any outstanding interrupt, except MDIO. */
979 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT);
980
981 fec_enet_bd_init(ndev);
982
983 fec_enet_enable_ring(ndev);
984
985 /* Reset tx SKB buffers. */
986 fec_enet_reset_skb(ndev);
987
988 /* Enable MII mode */
989 if (fep->full_duplex == DUPLEX_FULL) {
990 /* FD enable */
991 writel(0x04, fep->hwp + FEC_X_CNTRL);
992 } else {
993 /* No Rcv on Xmit */
994 rcntl |= 0x02;
995 writel(0x0, fep->hwp + FEC_X_CNTRL);
996 }
997
998 /* Set MII speed */
999 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1000
1001#if !defined(CONFIG_M5272)
1002 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
1003 u32 val = readl(fep->hwp + FEC_RACC);
1004
1005 /* align IP header */
1006 val |= FEC_RACC_SHIFT16;
1007 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
1008 /* set RX checksum */
1009 val |= FEC_RACC_OPTIONS;
1010 else
1011 val &= ~FEC_RACC_OPTIONS;
1012 writel(val, fep->hwp + FEC_RACC);
1013 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
1014 }
1015#endif
1016
1017 /*
1018 * The phy interface and speed need to get configured
1019 * differently on enet-mac.
1020 */
1021 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1022 /* Enable flow control and length check */
1023 rcntl |= 0x40000000 | 0x00000020;
1024
1025 /* RGMII, RMII or MII */
1026 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
1027 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1028 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1029 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1030 rcntl |= (1 << 6);
1031 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1032 rcntl |= (1 << 8);
1033 else
1034 rcntl &= ~(1 << 8);
1035
1036 /* 1G, 100M or 10M */
1037 if (ndev->phydev) {
1038 if (ndev->phydev->speed == SPEED_1000)
1039 ecntl |= (1 << 5);
1040 else if (ndev->phydev->speed == SPEED_100)
1041 rcntl &= ~(1 << 9);
1042 else
1043 rcntl |= (1 << 9);
1044 }
1045 } else {
1046#ifdef FEC_MIIGSK_ENR
1047 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1048 u32 cfgr;
1049 /* disable the gasket and wait */
1050 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1051 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1052 udelay(1);
1053
1054 /*
1055 * configure the gasket:
1056 * RMII, 50 MHz, no loopback, no echo
1057 * MII, 25 MHz, no loopback, no echo
1058 */
1059 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1060 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1061 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1062 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1063 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1064
1065 /* re-enable the gasket */
1066 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1067 }
1068#endif
1069 }
1070
1071#if !defined(CONFIG_M5272)
1072 /* enable pause frame*/
1073 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1074 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1075 ndev->phydev && ndev->phydev->pause)) {
1076 rcntl |= FEC_ENET_FCE;
1077
1078 /* set FIFO threshold parameter to reduce overrun */
1079 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1080 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1081 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1082 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1083
1084 /* OPD */
1085 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1086 } else {
1087 rcntl &= ~FEC_ENET_FCE;
1088 }
1089#endif /* !defined(CONFIG_M5272) */
1090
1091 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1092
1093 /* Setup multicast filter. */
1094 set_multicast_list(ndev);
1095#ifndef CONFIG_M5272
1096 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1097 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1098#endif
1099
1100 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1101 /* enable ENET endian swap */
1102 ecntl |= (1 << 8);
1103 /* enable ENET store and forward mode */
1104 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1105 }
1106
1107 if (fep->bufdesc_ex)
1108 ecntl |= (1 << 4);
1109
1110#ifndef CONFIG_M5272
1111 /* Enable the MIB statistic event counters */
1112 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1113#endif
1114
1115 /* And last, enable the transmit and receive processing */
1116 writel(ecntl, fep->hwp + FEC_ECNTRL);
1117 fec_enet_active_rxring(ndev);
1118
1119 if (fep->bufdesc_ex)
1120 fec_ptp_start_cyclecounter(ndev);
1121
1122 /* Enable interrupts we wish to service */
1123 if (fep->link)
1124 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1125 else
1126 writel(0, fep->hwp + FEC_IMASK);
1127
1128 /* Init the interrupt coalescing */
1129 fec_enet_itr_coal_init(ndev);
1130
1131}
1132
1133static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled)
1134{
1135 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1136 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr;
1137
1138 if (stop_gpr->gpr) {
1139 if (enabled)
1140 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1141 BIT(stop_gpr->bit),
1142 BIT(stop_gpr->bit));
1143 else
1144 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1145 BIT(stop_gpr->bit), 0);
1146 } else if (pdata && pdata->sleep_mode_enable) {
1147 pdata->sleep_mode_enable(enabled);
1148 }
1149}
1150
1151static void
1152fec_stop(struct net_device *ndev)
1153{
1154 struct fec_enet_private *fep = netdev_priv(ndev);
1155 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1156 u32 val;
1157
1158 /* We cannot expect a graceful transmit stop without link !!! */
1159 if (fep->link) {
1160 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1161 udelay(10);
1162 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1163 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1164 }
1165
1166 /* Whack a reset. We should wait for this.
1167 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1168 * instead of reset MAC itself.
1169 */
1170 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1171 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
1172 writel(0, fep->hwp + FEC_ECNTRL);
1173 } else {
1174 writel(1, fep->hwp + FEC_ECNTRL);
1175 udelay(10);
1176 }
1177 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1178 } else {
1179 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1180 val = readl(fep->hwp + FEC_ECNTRL);
1181 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1182 writel(val, fep->hwp + FEC_ECNTRL);
1183 fec_enet_stop_mode(fep, true);
1184 }
1185 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1186
1187 /* We have to keep ENET enabled to have MII interrupt stay working */
1188 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1189 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1190 writel(2, fep->hwp + FEC_ECNTRL);
1191 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1192 }
1193}
1194
1195
1196static void
1197fec_timeout(struct net_device *ndev, unsigned int txqueue)
1198{
1199 struct fec_enet_private *fep = netdev_priv(ndev);
1200
1201 fec_dump(ndev);
1202
1203 ndev->stats.tx_errors++;
1204
1205 schedule_work(&fep->tx_timeout_work);
1206}
1207
1208static void fec_enet_timeout_work(struct work_struct *work)
1209{
1210 struct fec_enet_private *fep =
1211 container_of(work, struct fec_enet_private, tx_timeout_work);
1212 struct net_device *ndev = fep->netdev;
1213
1214 rtnl_lock();
1215 if (netif_device_present(ndev) || netif_running(ndev)) {
1216 napi_disable(&fep->napi);
1217 netif_tx_lock_bh(ndev);
1218 fec_restart(ndev);
1219 netif_tx_wake_all_queues(ndev);
1220 netif_tx_unlock_bh(ndev);
1221 napi_enable(&fep->napi);
1222 }
1223 rtnl_unlock();
1224}
1225
1226static void
1227fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1228 struct skb_shared_hwtstamps *hwtstamps)
1229{
1230 unsigned long flags;
1231 u64 ns;
1232
1233 spin_lock_irqsave(&fep->tmreg_lock, flags);
1234 ns = timecounter_cyc2time(&fep->tc, ts);
1235 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1236
1237 memset(hwtstamps, 0, sizeof(*hwtstamps));
1238 hwtstamps->hwtstamp = ns_to_ktime(ns);
1239}
1240
1241static void
1242fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1243{
1244 struct fec_enet_private *fep;
1245 struct bufdesc *bdp;
1246 unsigned short status;
1247 struct sk_buff *skb;
1248 struct fec_enet_priv_tx_q *txq;
1249 struct netdev_queue *nq;
1250 int index = 0;
1251 int entries_free;
1252
1253 fep = netdev_priv(ndev);
1254
1255 txq = fep->tx_queue[queue_id];
1256 /* get next bdp of dirty_tx */
1257 nq = netdev_get_tx_queue(ndev, queue_id);
1258 bdp = txq->dirty_tx;
1259
1260 /* get next bdp of dirty_tx */
1261 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1262
1263 while (bdp != READ_ONCE(txq->bd.cur)) {
1264 /* Order the load of bd.cur and cbd_sc */
1265 rmb();
1266 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1267 if (status & BD_ENET_TX_READY)
1268 break;
1269
1270 index = fec_enet_get_bd_index(bdp, &txq->bd);
1271
1272 skb = txq->tx_skbuff[index];
1273 txq->tx_skbuff[index] = NULL;
1274 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1275 dma_unmap_single(&fep->pdev->dev,
1276 fec32_to_cpu(bdp->cbd_bufaddr),
1277 fec16_to_cpu(bdp->cbd_datlen),
1278 DMA_TO_DEVICE);
1279 bdp->cbd_bufaddr = cpu_to_fec32(0);
1280 if (!skb)
1281 goto skb_done;
1282
1283 /* Check for errors. */
1284 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1285 BD_ENET_TX_RL | BD_ENET_TX_UN |
1286 BD_ENET_TX_CSL)) {
1287 ndev->stats.tx_errors++;
1288 if (status & BD_ENET_TX_HB) /* No heartbeat */
1289 ndev->stats.tx_heartbeat_errors++;
1290 if (status & BD_ENET_TX_LC) /* Late collision */
1291 ndev->stats.tx_window_errors++;
1292 if (status & BD_ENET_TX_RL) /* Retrans limit */
1293 ndev->stats.tx_aborted_errors++;
1294 if (status & BD_ENET_TX_UN) /* Underrun */
1295 ndev->stats.tx_fifo_errors++;
1296 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1297 ndev->stats.tx_carrier_errors++;
1298 } else {
1299 ndev->stats.tx_packets++;
1300 ndev->stats.tx_bytes += skb->len;
1301 }
1302
1303 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who
1304 * are to time stamp the packet, so we still need to check time
1305 * stamping enabled flag.
1306 */
1307 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS &&
1308 fep->hwts_tx_en) &&
1309 fep->bufdesc_ex) {
1310 struct skb_shared_hwtstamps shhwtstamps;
1311 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1312
1313 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1314 skb_tstamp_tx(skb, &shhwtstamps);
1315 }
1316
1317 /* Deferred means some collisions occurred during transmit,
1318 * but we eventually sent the packet OK.
1319 */
1320 if (status & BD_ENET_TX_DEF)
1321 ndev->stats.collisions++;
1322
1323 /* Free the sk buffer associated with this last transmit */
1324 dev_kfree_skb_any(skb);
1325skb_done:
1326 /* Make sure the update to bdp and tx_skbuff are performed
1327 * before dirty_tx
1328 */
1329 wmb();
1330 txq->dirty_tx = bdp;
1331
1332 /* Update pointer to next buffer descriptor to be transmitted */
1333 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1334
1335 /* Since we have freed up a buffer, the ring is no longer full
1336 */
1337 if (netif_tx_queue_stopped(nq)) {
1338 entries_free = fec_enet_get_free_txdesc_num(txq);
1339 if (entries_free >= txq->tx_wake_threshold)
1340 netif_tx_wake_queue(nq);
1341 }
1342 }
1343
1344 /* ERR006358: Keep the transmitter going */
1345 if (bdp != txq->bd.cur &&
1346 readl(txq->bd.reg_desc_active) == 0)
1347 writel(0, txq->bd.reg_desc_active);
1348}
1349
1350static void fec_enet_tx(struct net_device *ndev)
1351{
1352 struct fec_enet_private *fep = netdev_priv(ndev);
1353 int i;
1354
1355 /* Make sure that AVB queues are processed first. */
1356 for (i = fep->num_tx_queues - 1; i >= 0; i--)
1357 fec_enet_tx_queue(ndev, i);
1358}
1359
1360static int
1361fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1362{
1363 struct fec_enet_private *fep = netdev_priv(ndev);
1364 int off;
1365
1366 off = ((unsigned long)skb->data) & fep->rx_align;
1367 if (off)
1368 skb_reserve(skb, fep->rx_align + 1 - off);
1369
1370 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1371 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1372 if (net_ratelimit())
1373 netdev_err(ndev, "Rx DMA memory map failed\n");
1374 return -ENOMEM;
1375 }
1376
1377 return 0;
1378}
1379
1380static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1381 struct bufdesc *bdp, u32 length, bool swap)
1382{
1383 struct fec_enet_private *fep = netdev_priv(ndev);
1384 struct sk_buff *new_skb;
1385
1386 if (length > fep->rx_copybreak)
1387 return false;
1388
1389 new_skb = netdev_alloc_skb(ndev, length);
1390 if (!new_skb)
1391 return false;
1392
1393 dma_sync_single_for_cpu(&fep->pdev->dev,
1394 fec32_to_cpu(bdp->cbd_bufaddr),
1395 FEC_ENET_RX_FRSIZE - fep->rx_align,
1396 DMA_FROM_DEVICE);
1397 if (!swap)
1398 memcpy(new_skb->data, (*skb)->data, length);
1399 else
1400 swap_buffer2(new_skb->data, (*skb)->data, length);
1401 *skb = new_skb;
1402
1403 return true;
1404}
1405
1406/* During a receive, the bd_rx.cur points to the current incoming buffer.
1407 * When we update through the ring, if the next incoming buffer has
1408 * not been given to the system, we just set the empty indicator,
1409 * effectively tossing the packet.
1410 */
1411static int
1412fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1413{
1414 struct fec_enet_private *fep = netdev_priv(ndev);
1415 struct fec_enet_priv_rx_q *rxq;
1416 struct bufdesc *bdp;
1417 unsigned short status;
1418 struct sk_buff *skb_new = NULL;
1419 struct sk_buff *skb;
1420 ushort pkt_len;
1421 __u8 *data;
1422 int pkt_received = 0;
1423 struct bufdesc_ex *ebdp = NULL;
1424 bool vlan_packet_rcvd = false;
1425 u16 vlan_tag;
1426 int index = 0;
1427 bool is_copybreak;
1428 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1429
1430#ifdef CONFIG_M532x
1431 flush_cache_all();
1432#endif
1433 rxq = fep->rx_queue[queue_id];
1434
1435 /* First, grab all of the stats for the incoming packet.
1436 * These get messed up if we get called due to a busy condition.
1437 */
1438 bdp = rxq->bd.cur;
1439
1440 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1441
1442 if (pkt_received >= budget)
1443 break;
1444 pkt_received++;
1445
1446 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
1447
1448 /* Check for errors. */
1449 status ^= BD_ENET_RX_LAST;
1450 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1451 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1452 BD_ENET_RX_CL)) {
1453 ndev->stats.rx_errors++;
1454 if (status & BD_ENET_RX_OV) {
1455 /* FIFO overrun */
1456 ndev->stats.rx_fifo_errors++;
1457 goto rx_processing_done;
1458 }
1459 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1460 | BD_ENET_RX_LAST)) {
1461 /* Frame too long or too short. */
1462 ndev->stats.rx_length_errors++;
1463 if (status & BD_ENET_RX_LAST)
1464 netdev_err(ndev, "rcv is not +last\n");
1465 }
1466 if (status & BD_ENET_RX_CR) /* CRC Error */
1467 ndev->stats.rx_crc_errors++;
1468 /* Report late collisions as a frame error. */
1469 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1470 ndev->stats.rx_frame_errors++;
1471 goto rx_processing_done;
1472 }
1473
1474 /* Process the incoming frame. */
1475 ndev->stats.rx_packets++;
1476 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1477 ndev->stats.rx_bytes += pkt_len;
1478
1479 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1480 skb = rxq->rx_skbuff[index];
1481
1482 /* The packet length includes FCS, but we don't want to
1483 * include that when passing upstream as it messes up
1484 * bridging applications.
1485 */
1486 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1487 need_swap);
1488 if (!is_copybreak) {
1489 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1490 if (unlikely(!skb_new)) {
1491 ndev->stats.rx_dropped++;
1492 goto rx_processing_done;
1493 }
1494 dma_unmap_single(&fep->pdev->dev,
1495 fec32_to_cpu(bdp->cbd_bufaddr),
1496 FEC_ENET_RX_FRSIZE - fep->rx_align,
1497 DMA_FROM_DEVICE);
1498 }
1499
1500 prefetch(skb->data - NET_IP_ALIGN);
1501 skb_put(skb, pkt_len - 4);
1502 data = skb->data;
1503
1504 if (!is_copybreak && need_swap)
1505 swap_buffer(data, pkt_len);
1506
1507#if !defined(CONFIG_M5272)
1508 if (fep->quirks & FEC_QUIRK_HAS_RACC)
1509 data = skb_pull_inline(skb, 2);
1510#endif
1511
1512 /* Extract the enhanced buffer descriptor */
1513 ebdp = NULL;
1514 if (fep->bufdesc_ex)
1515 ebdp = (struct bufdesc_ex *)bdp;
1516
1517 /* If this is a VLAN packet remove the VLAN Tag */
1518 vlan_packet_rcvd = false;
1519 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1520 fep->bufdesc_ex &&
1521 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1522 /* Push and remove the vlan tag */
1523 struct vlan_hdr *vlan_header =
1524 (struct vlan_hdr *) (data + ETH_HLEN);
1525 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1526
1527 vlan_packet_rcvd = true;
1528
1529 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1530 skb_pull(skb, VLAN_HLEN);
1531 }
1532
1533 skb->protocol = eth_type_trans(skb, ndev);
1534
1535 /* Get receive timestamp from the skb */
1536 if (fep->hwts_rx_en && fep->bufdesc_ex)
1537 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1538 skb_hwtstamps(skb));
1539
1540 if (fep->bufdesc_ex &&
1541 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1542 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1543 /* don't check it */
1544 skb->ip_summed = CHECKSUM_UNNECESSARY;
1545 } else {
1546 skb_checksum_none_assert(skb);
1547 }
1548 }
1549
1550 /* Handle received VLAN packets */
1551 if (vlan_packet_rcvd)
1552 __vlan_hwaccel_put_tag(skb,
1553 htons(ETH_P_8021Q),
1554 vlan_tag);
1555
1556 skb_record_rx_queue(skb, queue_id);
1557 napi_gro_receive(&fep->napi, skb);
1558
1559 if (is_copybreak) {
1560 dma_sync_single_for_device(&fep->pdev->dev,
1561 fec32_to_cpu(bdp->cbd_bufaddr),
1562 FEC_ENET_RX_FRSIZE - fep->rx_align,
1563 DMA_FROM_DEVICE);
1564 } else {
1565 rxq->rx_skbuff[index] = skb_new;
1566 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1567 }
1568
1569rx_processing_done:
1570 /* Clear the status flags for this buffer */
1571 status &= ~BD_ENET_RX_STATS;
1572
1573 /* Mark the buffer empty */
1574 status |= BD_ENET_RX_EMPTY;
1575
1576 if (fep->bufdesc_ex) {
1577 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1578
1579 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1580 ebdp->cbd_prot = 0;
1581 ebdp->cbd_bdu = 0;
1582 }
1583 /* Make sure the updates to rest of the descriptor are
1584 * performed before transferring ownership.
1585 */
1586 wmb();
1587 bdp->cbd_sc = cpu_to_fec16(status);
1588
1589 /* Update BD pointer to next entry */
1590 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1591
1592 /* Doing this here will keep the FEC running while we process
1593 * incoming frames. On a heavily loaded network, we should be
1594 * able to keep up at the expense of system resources.
1595 */
1596 writel(0, rxq->bd.reg_desc_active);
1597 }
1598 rxq->bd.cur = bdp;
1599 return pkt_received;
1600}
1601
1602static int fec_enet_rx(struct net_device *ndev, int budget)
1603{
1604 struct fec_enet_private *fep = netdev_priv(ndev);
1605 int i, done = 0;
1606
1607 /* Make sure that AVB queues are processed first. */
1608 for (i = fep->num_rx_queues - 1; i >= 0; i--)
1609 done += fec_enet_rx_queue(ndev, budget - done, i);
1610
1611 return done;
1612}
1613
1614static bool fec_enet_collect_events(struct fec_enet_private *fep)
1615{
1616 uint int_events;
1617
1618 int_events = readl(fep->hwp + FEC_IEVENT);
1619
1620 /* Don't clear MDIO events, we poll for those */
1621 int_events &= ~FEC_ENET_MII;
1622
1623 writel(int_events, fep->hwp + FEC_IEVENT);
1624
1625 return int_events != 0;
1626}
1627
1628static irqreturn_t
1629fec_enet_interrupt(int irq, void *dev_id)
1630{
1631 struct net_device *ndev = dev_id;
1632 struct fec_enet_private *fep = netdev_priv(ndev);
1633 irqreturn_t ret = IRQ_NONE;
1634
1635 if (fec_enet_collect_events(fep) && fep->link) {
1636 ret = IRQ_HANDLED;
1637
1638 if (napi_schedule_prep(&fep->napi)) {
1639 /* Disable interrupts */
1640 writel(0, fep->hwp + FEC_IMASK);
1641 __napi_schedule(&fep->napi);
1642 }
1643 }
1644
1645 return ret;
1646}
1647
1648static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1649{
1650 struct net_device *ndev = napi->dev;
1651 struct fec_enet_private *fep = netdev_priv(ndev);
1652 int done = 0;
1653
1654 do {
1655 done += fec_enet_rx(ndev, budget - done);
1656 fec_enet_tx(ndev);
1657 } while ((done < budget) && fec_enet_collect_events(fep));
1658
1659 if (done < budget) {
1660 napi_complete_done(napi, done);
1661 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1662 }
1663
1664 return done;
1665}
1666
1667/* ------------------------------------------------------------------------- */
1668static int fec_get_mac(struct net_device *ndev)
1669{
1670 struct fec_enet_private *fep = netdev_priv(ndev);
1671 unsigned char *iap, tmpaddr[ETH_ALEN];
1672 int ret;
1673
1674 /*
1675 * try to get mac address in following order:
1676 *
1677 * 1) module parameter via kernel command line in form
1678 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1679 */
1680 iap = macaddr;
1681
1682 /*
1683 * 2) from device tree data
1684 */
1685 if (!is_valid_ether_addr(iap)) {
1686 struct device_node *np = fep->pdev->dev.of_node;
1687 if (np) {
1688 ret = of_get_mac_address(np, tmpaddr);
1689 if (!ret)
1690 iap = tmpaddr;
1691 else if (ret == -EPROBE_DEFER)
1692 return ret;
1693 }
1694 }
1695
1696 /*
1697 * 3) from flash or fuse (via platform data)
1698 */
1699 if (!is_valid_ether_addr(iap)) {
1700#ifdef CONFIG_M5272
1701 if (FEC_FLASHMAC)
1702 iap = (unsigned char *)FEC_FLASHMAC;
1703#else
1704 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1705
1706 if (pdata)
1707 iap = (unsigned char *)&pdata->mac;
1708#endif
1709 }
1710
1711 /*
1712 * 4) FEC mac registers set by bootloader
1713 */
1714 if (!is_valid_ether_addr(iap)) {
1715 *((__be32 *) &tmpaddr[0]) =
1716 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1717 *((__be16 *) &tmpaddr[4]) =
1718 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1719 iap = &tmpaddr[0];
1720 }
1721
1722 /*
1723 * 5) random mac address
1724 */
1725 if (!is_valid_ether_addr(iap)) {
1726 /* Report it and use a random ethernet address instead */
1727 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap);
1728 eth_hw_addr_random(ndev);
1729 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n",
1730 ndev->dev_addr);
1731 return 0;
1732 }
1733
1734 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1735
1736 /* Adjust MAC if using macaddr */
1737 if (iap == macaddr)
1738 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1739
1740 return 0;
1741}
1742
1743/* ------------------------------------------------------------------------- */
1744
1745/*
1746 * Phy section
1747 */
1748static void fec_enet_adjust_link(struct net_device *ndev)
1749{
1750 struct fec_enet_private *fep = netdev_priv(ndev);
1751 struct phy_device *phy_dev = ndev->phydev;
1752 int status_change = 0;
1753
1754 /*
1755 * If the netdev is down, or is going down, we're not interested
1756 * in link state events, so just mark our idea of the link as down
1757 * and ignore the event.
1758 */
1759 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1760 fep->link = 0;
1761 } else if (phy_dev->link) {
1762 if (!fep->link) {
1763 fep->link = phy_dev->link;
1764 status_change = 1;
1765 }
1766
1767 if (fep->full_duplex != phy_dev->duplex) {
1768 fep->full_duplex = phy_dev->duplex;
1769 status_change = 1;
1770 }
1771
1772 if (phy_dev->speed != fep->speed) {
1773 fep->speed = phy_dev->speed;
1774 status_change = 1;
1775 }
1776
1777 /* if any of the above changed restart the FEC */
1778 if (status_change) {
1779 napi_disable(&fep->napi);
1780 netif_tx_lock_bh(ndev);
1781 fec_restart(ndev);
1782 netif_tx_wake_all_queues(ndev);
1783 netif_tx_unlock_bh(ndev);
1784 napi_enable(&fep->napi);
1785 }
1786 } else {
1787 if (fep->link) {
1788 napi_disable(&fep->napi);
1789 netif_tx_lock_bh(ndev);
1790 fec_stop(ndev);
1791 netif_tx_unlock_bh(ndev);
1792 napi_enable(&fep->napi);
1793 fep->link = phy_dev->link;
1794 status_change = 1;
1795 }
1796 }
1797
1798 if (status_change)
1799 phy_print_status(phy_dev);
1800}
1801
1802static int fec_enet_mdio_wait(struct fec_enet_private *fep)
1803{
1804 uint ievent;
1805 int ret;
1806
1807 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent,
1808 ievent & FEC_ENET_MII, 2, 30000);
1809
1810 if (!ret)
1811 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
1812
1813 return ret;
1814}
1815
1816static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1817{
1818 struct fec_enet_private *fep = bus->priv;
1819 struct device *dev = &fep->pdev->dev;
1820 int ret = 0, frame_start, frame_addr, frame_op;
1821 bool is_c45 = !!(regnum & MII_ADDR_C45);
1822
1823 ret = pm_runtime_resume_and_get(dev);
1824 if (ret < 0)
1825 return ret;
1826
1827 if (is_c45) {
1828 frame_start = FEC_MMFR_ST_C45;
1829
1830 /* write address */
1831 frame_addr = (regnum >> 16);
1832 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
1833 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1834 FEC_MMFR_TA | (regnum & 0xFFFF),
1835 fep->hwp + FEC_MII_DATA);
1836
1837 /* wait for end of transfer */
1838 ret = fec_enet_mdio_wait(fep);
1839 if (ret) {
1840 netdev_err(fep->netdev, "MDIO address write timeout\n");
1841 goto out;
1842 }
1843
1844 frame_op = FEC_MMFR_OP_READ_C45;
1845
1846 } else {
1847 /* C22 read */
1848 frame_op = FEC_MMFR_OP_READ;
1849 frame_start = FEC_MMFR_ST;
1850 frame_addr = regnum;
1851 }
1852
1853 /* start a read op */
1854 writel(frame_start | frame_op |
1855 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1856 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1857
1858 /* wait for end of transfer */
1859 ret = fec_enet_mdio_wait(fep);
1860 if (ret) {
1861 netdev_err(fep->netdev, "MDIO read timeout\n");
1862 goto out;
1863 }
1864
1865 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1866
1867out:
1868 pm_runtime_mark_last_busy(dev);
1869 pm_runtime_put_autosuspend(dev);
1870
1871 return ret;
1872}
1873
1874static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1875 u16 value)
1876{
1877 struct fec_enet_private *fep = bus->priv;
1878 struct device *dev = &fep->pdev->dev;
1879 int ret, frame_start, frame_addr;
1880 bool is_c45 = !!(regnum & MII_ADDR_C45);
1881
1882 ret = pm_runtime_resume_and_get(dev);
1883 if (ret < 0)
1884 return ret;
1885
1886 if (is_c45) {
1887 frame_start = FEC_MMFR_ST_C45;
1888
1889 /* write address */
1890 frame_addr = (regnum >> 16);
1891 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
1892 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1893 FEC_MMFR_TA | (regnum & 0xFFFF),
1894 fep->hwp + FEC_MII_DATA);
1895
1896 /* wait for end of transfer */
1897 ret = fec_enet_mdio_wait(fep);
1898 if (ret) {
1899 netdev_err(fep->netdev, "MDIO address write timeout\n");
1900 goto out;
1901 }
1902 } else {
1903 /* C22 write */
1904 frame_start = FEC_MMFR_ST;
1905 frame_addr = regnum;
1906 }
1907
1908 /* start a write op */
1909 writel(frame_start | FEC_MMFR_OP_WRITE |
1910 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1911 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1912 fep->hwp + FEC_MII_DATA);
1913
1914 /* wait for end of transfer */
1915 ret = fec_enet_mdio_wait(fep);
1916 if (ret)
1917 netdev_err(fep->netdev, "MDIO write timeout\n");
1918
1919out:
1920 pm_runtime_mark_last_busy(dev);
1921 pm_runtime_put_autosuspend(dev);
1922
1923 return ret;
1924}
1925
1926static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev)
1927{
1928 struct fec_enet_private *fep = netdev_priv(ndev);
1929 struct phy_device *phy_dev = ndev->phydev;
1930
1931 if (phy_dev) {
1932 phy_reset_after_clk_enable(phy_dev);
1933 } else if (fep->phy_node) {
1934 /*
1935 * If the PHY still is not bound to the MAC, but there is
1936 * OF PHY node and a matching PHY device instance already,
1937 * use the OF PHY node to obtain the PHY device instance,
1938 * and then use that PHY device instance when triggering
1939 * the PHY reset.
1940 */
1941 phy_dev = of_phy_find_device(fep->phy_node);
1942 phy_reset_after_clk_enable(phy_dev);
1943 put_device(&phy_dev->mdio.dev);
1944 }
1945}
1946
1947static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1948{
1949 struct fec_enet_private *fep = netdev_priv(ndev);
1950 int ret;
1951
1952 if (enable) {
1953 ret = clk_prepare_enable(fep->clk_enet_out);
1954 if (ret)
1955 return ret;
1956
1957 if (fep->clk_ptp) {
1958 mutex_lock(&fep->ptp_clk_mutex);
1959 ret = clk_prepare_enable(fep->clk_ptp);
1960 if (ret) {
1961 mutex_unlock(&fep->ptp_clk_mutex);
1962 goto failed_clk_ptp;
1963 } else {
1964 fep->ptp_clk_on = true;
1965 }
1966 mutex_unlock(&fep->ptp_clk_mutex);
1967 }
1968
1969 ret = clk_prepare_enable(fep->clk_ref);
1970 if (ret)
1971 goto failed_clk_ref;
1972
1973 fec_enet_phy_reset_after_clk_enable(ndev);
1974 } else {
1975 clk_disable_unprepare(fep->clk_enet_out);
1976 if (fep->clk_ptp) {
1977 mutex_lock(&fep->ptp_clk_mutex);
1978 clk_disable_unprepare(fep->clk_ptp);
1979 fep->ptp_clk_on = false;
1980 mutex_unlock(&fep->ptp_clk_mutex);
1981 }
1982 clk_disable_unprepare(fep->clk_ref);
1983 }
1984
1985 return 0;
1986
1987failed_clk_ref:
1988 if (fep->clk_ptp) {
1989 mutex_lock(&fep->ptp_clk_mutex);
1990 clk_disable_unprepare(fep->clk_ptp);
1991 fep->ptp_clk_on = false;
1992 mutex_unlock(&fep->ptp_clk_mutex);
1993 }
1994failed_clk_ptp:
1995 clk_disable_unprepare(fep->clk_enet_out);
1996
1997 return ret;
1998}
1999
2000static int fec_enet_mii_probe(struct net_device *ndev)
2001{
2002 struct fec_enet_private *fep = netdev_priv(ndev);
2003 struct phy_device *phy_dev = NULL;
2004 char mdio_bus_id[MII_BUS_ID_SIZE];
2005 char phy_name[MII_BUS_ID_SIZE + 3];
2006 int phy_id;
2007 int dev_id = fep->dev_id;
2008
2009 if (fep->phy_node) {
2010 phy_dev = of_phy_connect(ndev, fep->phy_node,
2011 &fec_enet_adjust_link, 0,
2012 fep->phy_interface);
2013 if (!phy_dev) {
2014 netdev_err(ndev, "Unable to connect to phy\n");
2015 return -ENODEV;
2016 }
2017 } else {
2018 /* check for attached phy */
2019 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
2020 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
2021 continue;
2022 if (dev_id--)
2023 continue;
2024 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
2025 break;
2026 }
2027
2028 if (phy_id >= PHY_MAX_ADDR) {
2029 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
2030 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
2031 phy_id = 0;
2032 }
2033
2034 snprintf(phy_name, sizeof(phy_name),
2035 PHY_ID_FMT, mdio_bus_id, phy_id);
2036 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
2037 fep->phy_interface);
2038 }
2039
2040 if (IS_ERR(phy_dev)) {
2041 netdev_err(ndev, "could not attach to PHY\n");
2042 return PTR_ERR(phy_dev);
2043 }
2044
2045 /* mask with MAC supported features */
2046 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
2047 phy_set_max_speed(phy_dev, 1000);
2048 phy_remove_link_mode(phy_dev,
2049 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
2050#if !defined(CONFIG_M5272)
2051 phy_support_sym_pause(phy_dev);
2052#endif
2053 }
2054 else
2055 phy_set_max_speed(phy_dev, 100);
2056
2057 fep->link = 0;
2058 fep->full_duplex = 0;
2059
2060 phy_dev->mac_managed_pm = 1;
2061
2062 phy_attached_info(phy_dev);
2063
2064 return 0;
2065}
2066
2067static int fec_enet_mii_init(struct platform_device *pdev)
2068{
2069 static struct mii_bus *fec0_mii_bus;
2070 struct net_device *ndev = platform_get_drvdata(pdev);
2071 struct fec_enet_private *fep = netdev_priv(ndev);
2072 bool suppress_preamble = false;
2073 struct device_node *node;
2074 int err = -ENXIO;
2075 u32 mii_speed, holdtime;
2076 u32 bus_freq;
2077
2078 /*
2079 * The i.MX28 dual fec interfaces are not equal.
2080 * Here are the differences:
2081 *
2082 * - fec0 supports MII & RMII modes while fec1 only supports RMII
2083 * - fec0 acts as the 1588 time master while fec1 is slave
2084 * - external phys can only be configured by fec0
2085 *
2086 * That is to say fec1 can not work independently. It only works
2087 * when fec0 is working. The reason behind this design is that the
2088 * second interface is added primarily for Switch mode.
2089 *
2090 * Because of the last point above, both phys are attached on fec0
2091 * mdio interface in board design, and need to be configured by
2092 * fec0 mii_bus.
2093 */
2094 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
2095 /* fec1 uses fec0 mii_bus */
2096 if (mii_cnt && fec0_mii_bus) {
2097 fep->mii_bus = fec0_mii_bus;
2098 mii_cnt++;
2099 return 0;
2100 }
2101 return -ENOENT;
2102 }
2103
2104 bus_freq = 2500000; /* 2.5MHz by default */
2105 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2106 if (node) {
2107 of_property_read_u32(node, "clock-frequency", &bus_freq);
2108 suppress_preamble = of_property_read_bool(node,
2109 "suppress-preamble");
2110 }
2111
2112 /*
2113 * Set MII speed (= clk_get_rate() / 2 * phy_speed)
2114 *
2115 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2116 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2117 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2118 * document.
2119 */
2120 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2);
2121 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2122 mii_speed--;
2123 if (mii_speed > 63) {
2124 dev_err(&pdev->dev,
2125 "fec clock (%lu) too fast to get right mii speed\n",
2126 clk_get_rate(fep->clk_ipg));
2127 err = -EINVAL;
2128 goto err_out;
2129 }
2130
2131 /*
2132 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2133 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2134 * versions are RAZ there, so just ignore the difference and write the
2135 * register always.
2136 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2137 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2138 * output.
2139 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2140 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2141 * holdtime cannot result in a value greater than 3.
2142 */
2143 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2144
2145 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2146
2147 if (suppress_preamble)
2148 fep->phy_speed |= BIT(7);
2149
2150 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) {
2151 /* Clear MMFR to avoid to generate MII event by writing MSCR.
2152 * MII event generation condition:
2153 * - writing MSCR:
2154 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero &
2155 * mscr_reg_data_in[7:0] != 0
2156 * - writing MMFR:
2157 * - mscr[7:0]_not_zero
2158 */
2159 writel(0, fep->hwp + FEC_MII_DATA);
2160 }
2161
2162 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2163
2164 /* Clear any pending transaction complete indication */
2165 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
2166
2167 fep->mii_bus = mdiobus_alloc();
2168 if (fep->mii_bus == NULL) {
2169 err = -ENOMEM;
2170 goto err_out;
2171 }
2172
2173 fep->mii_bus->name = "fec_enet_mii_bus";
2174 fep->mii_bus->read = fec_enet_mdio_read;
2175 fep->mii_bus->write = fec_enet_mdio_write;
2176 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2177 pdev->name, fep->dev_id + 1);
2178 fep->mii_bus->priv = fep;
2179 fep->mii_bus->parent = &pdev->dev;
2180
2181 err = of_mdiobus_register(fep->mii_bus, node);
2182 if (err)
2183 goto err_out_free_mdiobus;
2184 of_node_put(node);
2185
2186 mii_cnt++;
2187
2188 /* save fec0 mii_bus */
2189 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2190 fec0_mii_bus = fep->mii_bus;
2191
2192 return 0;
2193
2194err_out_free_mdiobus:
2195 mdiobus_free(fep->mii_bus);
2196err_out:
2197 of_node_put(node);
2198 return err;
2199}
2200
2201static void fec_enet_mii_remove(struct fec_enet_private *fep)
2202{
2203 if (--mii_cnt == 0) {
2204 mdiobus_unregister(fep->mii_bus);
2205 mdiobus_free(fep->mii_bus);
2206 }
2207}
2208
2209static void fec_enet_get_drvinfo(struct net_device *ndev,
2210 struct ethtool_drvinfo *info)
2211{
2212 struct fec_enet_private *fep = netdev_priv(ndev);
2213
2214 strlcpy(info->driver, fep->pdev->dev.driver->name,
2215 sizeof(info->driver));
2216 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2217}
2218
2219static int fec_enet_get_regs_len(struct net_device *ndev)
2220{
2221 struct fec_enet_private *fep = netdev_priv(ndev);
2222 struct resource *r;
2223 int s = 0;
2224
2225 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2226 if (r)
2227 s = resource_size(r);
2228
2229 return s;
2230}
2231
2232/* List of registers that can be safety be read to dump them with ethtool */
2233#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2234 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2235 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2236static __u32 fec_enet_register_version = 2;
2237static u32 fec_enet_register_offset[] = {
2238 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2239 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2240 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2241 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2242 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2243 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2244 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2245 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2246 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2247 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2248 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2249 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2250 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2251 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2252 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2253 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2254 RMON_T_P_GTE2048, RMON_T_OCTETS,
2255 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2256 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2257 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2258 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2259 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2260 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2261 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2262 RMON_R_P_GTE2048, RMON_R_OCTETS,
2263 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2264 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2265};
2266#else
2267static __u32 fec_enet_register_version = 1;
2268static u32 fec_enet_register_offset[] = {
2269 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2270 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2271 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2272 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2273 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2274 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2275 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2276 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2277 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2278};
2279#endif
2280
2281static void fec_enet_get_regs(struct net_device *ndev,
2282 struct ethtool_regs *regs, void *regbuf)
2283{
2284 struct fec_enet_private *fep = netdev_priv(ndev);
2285 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2286 struct device *dev = &fep->pdev->dev;
2287 u32 *buf = (u32 *)regbuf;
2288 u32 i, off;
2289 int ret;
2290
2291 ret = pm_runtime_resume_and_get(dev);
2292 if (ret < 0)
2293 return;
2294
2295 regs->version = fec_enet_register_version;
2296
2297 memset(buf, 0, regs->len);
2298
2299 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2300 off = fec_enet_register_offset[i];
2301
2302 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) &&
2303 !(fep->quirks & FEC_QUIRK_HAS_FRREG))
2304 continue;
2305
2306 off >>= 2;
2307 buf[off] = readl(&theregs[off]);
2308 }
2309
2310 pm_runtime_mark_last_busy(dev);
2311 pm_runtime_put_autosuspend(dev);
2312}
2313
2314static int fec_enet_get_ts_info(struct net_device *ndev,
2315 struct ethtool_ts_info *info)
2316{
2317 struct fec_enet_private *fep = netdev_priv(ndev);
2318
2319 if (fep->bufdesc_ex) {
2320
2321 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2322 SOF_TIMESTAMPING_RX_SOFTWARE |
2323 SOF_TIMESTAMPING_SOFTWARE |
2324 SOF_TIMESTAMPING_TX_HARDWARE |
2325 SOF_TIMESTAMPING_RX_HARDWARE |
2326 SOF_TIMESTAMPING_RAW_HARDWARE;
2327 if (fep->ptp_clock)
2328 info->phc_index = ptp_clock_index(fep->ptp_clock);
2329 else
2330 info->phc_index = -1;
2331
2332 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2333 (1 << HWTSTAMP_TX_ON);
2334
2335 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2336 (1 << HWTSTAMP_FILTER_ALL);
2337 return 0;
2338 } else {
2339 return ethtool_op_get_ts_info(ndev, info);
2340 }
2341}
2342
2343#if !defined(CONFIG_M5272)
2344
2345static void fec_enet_get_pauseparam(struct net_device *ndev,
2346 struct ethtool_pauseparam *pause)
2347{
2348 struct fec_enet_private *fep = netdev_priv(ndev);
2349
2350 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2351 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2352 pause->rx_pause = pause->tx_pause;
2353}
2354
2355static int fec_enet_set_pauseparam(struct net_device *ndev,
2356 struct ethtool_pauseparam *pause)
2357{
2358 struct fec_enet_private *fep = netdev_priv(ndev);
2359
2360 if (!ndev->phydev)
2361 return -ENODEV;
2362
2363 if (pause->tx_pause != pause->rx_pause) {
2364 netdev_info(ndev,
2365 "hardware only support enable/disable both tx and rx");
2366 return -EINVAL;
2367 }
2368
2369 fep->pause_flag = 0;
2370
2371 /* tx pause must be same as rx pause */
2372 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2373 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2374
2375 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause,
2376 pause->autoneg);
2377
2378 if (pause->autoneg) {
2379 if (netif_running(ndev))
2380 fec_stop(ndev);
2381 phy_start_aneg(ndev->phydev);
2382 }
2383 if (netif_running(ndev)) {
2384 napi_disable(&fep->napi);
2385 netif_tx_lock_bh(ndev);
2386 fec_restart(ndev);
2387 netif_tx_wake_all_queues(ndev);
2388 netif_tx_unlock_bh(ndev);
2389 napi_enable(&fep->napi);
2390 }
2391
2392 return 0;
2393}
2394
2395static const struct fec_stat {
2396 char name[ETH_GSTRING_LEN];
2397 u16 offset;
2398} fec_stats[] = {
2399 /* RMON TX */
2400 { "tx_dropped", RMON_T_DROP },
2401 { "tx_packets", RMON_T_PACKETS },
2402 { "tx_broadcast", RMON_T_BC_PKT },
2403 { "tx_multicast", RMON_T_MC_PKT },
2404 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2405 { "tx_undersize", RMON_T_UNDERSIZE },
2406 { "tx_oversize", RMON_T_OVERSIZE },
2407 { "tx_fragment", RMON_T_FRAG },
2408 { "tx_jabber", RMON_T_JAB },
2409 { "tx_collision", RMON_T_COL },
2410 { "tx_64byte", RMON_T_P64 },
2411 { "tx_65to127byte", RMON_T_P65TO127 },
2412 { "tx_128to255byte", RMON_T_P128TO255 },
2413 { "tx_256to511byte", RMON_T_P256TO511 },
2414 { "tx_512to1023byte", RMON_T_P512TO1023 },
2415 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2416 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2417 { "tx_octets", RMON_T_OCTETS },
2418
2419 /* IEEE TX */
2420 { "IEEE_tx_drop", IEEE_T_DROP },
2421 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2422 { "IEEE_tx_1col", IEEE_T_1COL },
2423 { "IEEE_tx_mcol", IEEE_T_MCOL },
2424 { "IEEE_tx_def", IEEE_T_DEF },
2425 { "IEEE_tx_lcol", IEEE_T_LCOL },
2426 { "IEEE_tx_excol", IEEE_T_EXCOL },
2427 { "IEEE_tx_macerr", IEEE_T_MACERR },
2428 { "IEEE_tx_cserr", IEEE_T_CSERR },
2429 { "IEEE_tx_sqe", IEEE_T_SQE },
2430 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2431 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2432
2433 /* RMON RX */
2434 { "rx_packets", RMON_R_PACKETS },
2435 { "rx_broadcast", RMON_R_BC_PKT },
2436 { "rx_multicast", RMON_R_MC_PKT },
2437 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2438 { "rx_undersize", RMON_R_UNDERSIZE },
2439 { "rx_oversize", RMON_R_OVERSIZE },
2440 { "rx_fragment", RMON_R_FRAG },
2441 { "rx_jabber", RMON_R_JAB },
2442 { "rx_64byte", RMON_R_P64 },
2443 { "rx_65to127byte", RMON_R_P65TO127 },
2444 { "rx_128to255byte", RMON_R_P128TO255 },
2445 { "rx_256to511byte", RMON_R_P256TO511 },
2446 { "rx_512to1023byte", RMON_R_P512TO1023 },
2447 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2448 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2449 { "rx_octets", RMON_R_OCTETS },
2450
2451 /* IEEE RX */
2452 { "IEEE_rx_drop", IEEE_R_DROP },
2453 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2454 { "IEEE_rx_crc", IEEE_R_CRC },
2455 { "IEEE_rx_align", IEEE_R_ALIGN },
2456 { "IEEE_rx_macerr", IEEE_R_MACERR },
2457 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2458 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2459};
2460
2461#define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64))
2462
2463static void fec_enet_update_ethtool_stats(struct net_device *dev)
2464{
2465 struct fec_enet_private *fep = netdev_priv(dev);
2466 int i;
2467
2468 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2469 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2470}
2471
2472static void fec_enet_get_ethtool_stats(struct net_device *dev,
2473 struct ethtool_stats *stats, u64 *data)
2474{
2475 struct fec_enet_private *fep = netdev_priv(dev);
2476
2477 if (netif_running(dev))
2478 fec_enet_update_ethtool_stats(dev);
2479
2480 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
2481}
2482
2483static void fec_enet_get_strings(struct net_device *netdev,
2484 u32 stringset, u8 *data)
2485{
2486 int i;
2487 switch (stringset) {
2488 case ETH_SS_STATS:
2489 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2490 memcpy(data + i * ETH_GSTRING_LEN,
2491 fec_stats[i].name, ETH_GSTRING_LEN);
2492 break;
2493 case ETH_SS_TEST:
2494 net_selftest_get_strings(data);
2495 break;
2496 }
2497}
2498
2499static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2500{
2501 switch (sset) {
2502 case ETH_SS_STATS:
2503 return ARRAY_SIZE(fec_stats);
2504 case ETH_SS_TEST:
2505 return net_selftest_get_count();
2506 default:
2507 return -EOPNOTSUPP;
2508 }
2509}
2510
2511static void fec_enet_clear_ethtool_stats(struct net_device *dev)
2512{
2513 struct fec_enet_private *fep = netdev_priv(dev);
2514 int i;
2515
2516 /* Disable MIB statistics counters */
2517 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
2518
2519 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2520 writel(0, fep->hwp + fec_stats[i].offset);
2521
2522 /* Don't disable MIB statistics counters */
2523 writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
2524}
2525
2526#else /* !defined(CONFIG_M5272) */
2527#define FEC_STATS_SIZE 0
2528static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
2529{
2530}
2531
2532static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
2533{
2534}
2535#endif /* !defined(CONFIG_M5272) */
2536
2537/* ITR clock source is enet system clock (clk_ahb).
2538 * TCTT unit is cycle_ns * 64 cycle
2539 * So, the ICTT value = X us / (cycle_ns * 64)
2540 */
2541static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2542{
2543 struct fec_enet_private *fep = netdev_priv(ndev);
2544
2545 return us * (fep->itr_clk_rate / 64000) / 1000;
2546}
2547
2548/* Set threshold for interrupt coalescing */
2549static void fec_enet_itr_coal_set(struct net_device *ndev)
2550{
2551 struct fec_enet_private *fep = netdev_priv(ndev);
2552 int rx_itr, tx_itr;
2553
2554 /* Must be greater than zero to avoid unpredictable behavior */
2555 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2556 !fep->tx_time_itr || !fep->tx_pkts_itr)
2557 return;
2558
2559 /* Select enet system clock as Interrupt Coalescing
2560 * timer Clock Source
2561 */
2562 rx_itr = FEC_ITR_CLK_SEL;
2563 tx_itr = FEC_ITR_CLK_SEL;
2564
2565 /* set ICFT and ICTT */
2566 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2567 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2568 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2569 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2570
2571 rx_itr |= FEC_ITR_EN;
2572 tx_itr |= FEC_ITR_EN;
2573
2574 writel(tx_itr, fep->hwp + FEC_TXIC0);
2575 writel(rx_itr, fep->hwp + FEC_RXIC0);
2576 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
2577 writel(tx_itr, fep->hwp + FEC_TXIC1);
2578 writel(rx_itr, fep->hwp + FEC_RXIC1);
2579 writel(tx_itr, fep->hwp + FEC_TXIC2);
2580 writel(rx_itr, fep->hwp + FEC_RXIC2);
2581 }
2582}
2583
2584static int
2585fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2586{
2587 struct fec_enet_private *fep = netdev_priv(ndev);
2588
2589 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2590 return -EOPNOTSUPP;
2591
2592 ec->rx_coalesce_usecs = fep->rx_time_itr;
2593 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2594
2595 ec->tx_coalesce_usecs = fep->tx_time_itr;
2596 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2597
2598 return 0;
2599}
2600
2601static int
2602fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2603{
2604 struct fec_enet_private *fep = netdev_priv(ndev);
2605 struct device *dev = &fep->pdev->dev;
2606 unsigned int cycle;
2607
2608 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2609 return -EOPNOTSUPP;
2610
2611 if (ec->rx_max_coalesced_frames > 255) {
2612 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n");
2613 return -EINVAL;
2614 }
2615
2616 if (ec->tx_max_coalesced_frames > 255) {
2617 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n");
2618 return -EINVAL;
2619 }
2620
2621 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs);
2622 if (cycle > 0xFFFF) {
2623 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n");
2624 return -EINVAL;
2625 }
2626
2627 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs);
2628 if (cycle > 0xFFFF) {
2629 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n");
2630 return -EINVAL;
2631 }
2632
2633 fep->rx_time_itr = ec->rx_coalesce_usecs;
2634 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2635
2636 fep->tx_time_itr = ec->tx_coalesce_usecs;
2637 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2638
2639 fec_enet_itr_coal_set(ndev);
2640
2641 return 0;
2642}
2643
2644static void fec_enet_itr_coal_init(struct net_device *ndev)
2645{
2646 struct ethtool_coalesce ec;
2647
2648 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2649 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2650
2651 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2652 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2653
2654 fec_enet_set_coalesce(ndev, &ec);
2655}
2656
2657static int fec_enet_get_tunable(struct net_device *netdev,
2658 const struct ethtool_tunable *tuna,
2659 void *data)
2660{
2661 struct fec_enet_private *fep = netdev_priv(netdev);
2662 int ret = 0;
2663
2664 switch (tuna->id) {
2665 case ETHTOOL_RX_COPYBREAK:
2666 *(u32 *)data = fep->rx_copybreak;
2667 break;
2668 default:
2669 ret = -EINVAL;
2670 break;
2671 }
2672
2673 return ret;
2674}
2675
2676static int fec_enet_set_tunable(struct net_device *netdev,
2677 const struct ethtool_tunable *tuna,
2678 const void *data)
2679{
2680 struct fec_enet_private *fep = netdev_priv(netdev);
2681 int ret = 0;
2682
2683 switch (tuna->id) {
2684 case ETHTOOL_RX_COPYBREAK:
2685 fep->rx_copybreak = *(u32 *)data;
2686 break;
2687 default:
2688 ret = -EINVAL;
2689 break;
2690 }
2691
2692 return ret;
2693}
2694
2695static void
2696fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2697{
2698 struct fec_enet_private *fep = netdev_priv(ndev);
2699
2700 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2701 wol->supported = WAKE_MAGIC;
2702 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2703 } else {
2704 wol->supported = wol->wolopts = 0;
2705 }
2706}
2707
2708static int
2709fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2710{
2711 struct fec_enet_private *fep = netdev_priv(ndev);
2712
2713 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2714 return -EINVAL;
2715
2716 if (wol->wolopts & ~WAKE_MAGIC)
2717 return -EINVAL;
2718
2719 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2720 if (device_may_wakeup(&ndev->dev)) {
2721 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2722 if (fep->irq[0] > 0)
2723 enable_irq_wake(fep->irq[0]);
2724 } else {
2725 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2726 if (fep->irq[0] > 0)
2727 disable_irq_wake(fep->irq[0]);
2728 }
2729
2730 return 0;
2731}
2732
2733static const struct ethtool_ops fec_enet_ethtool_ops = {
2734 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2735 ETHTOOL_COALESCE_MAX_FRAMES,
2736 .get_drvinfo = fec_enet_get_drvinfo,
2737 .get_regs_len = fec_enet_get_regs_len,
2738 .get_regs = fec_enet_get_regs,
2739 .nway_reset = phy_ethtool_nway_reset,
2740 .get_link = ethtool_op_get_link,
2741 .get_coalesce = fec_enet_get_coalesce,
2742 .set_coalesce = fec_enet_set_coalesce,
2743#ifndef CONFIG_M5272
2744 .get_pauseparam = fec_enet_get_pauseparam,
2745 .set_pauseparam = fec_enet_set_pauseparam,
2746 .get_strings = fec_enet_get_strings,
2747 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2748 .get_sset_count = fec_enet_get_sset_count,
2749#endif
2750 .get_ts_info = fec_enet_get_ts_info,
2751 .get_tunable = fec_enet_get_tunable,
2752 .set_tunable = fec_enet_set_tunable,
2753 .get_wol = fec_enet_get_wol,
2754 .set_wol = fec_enet_set_wol,
2755 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2756 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2757 .self_test = net_selftest,
2758};
2759
2760static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2761{
2762 struct fec_enet_private *fep = netdev_priv(ndev);
2763 struct phy_device *phydev = ndev->phydev;
2764
2765 if (!netif_running(ndev))
2766 return -EINVAL;
2767
2768 if (!phydev)
2769 return -ENODEV;
2770
2771 if (fep->bufdesc_ex) {
2772 bool use_fec_hwts = !phy_has_hwtstamp(phydev);
2773
2774 if (cmd == SIOCSHWTSTAMP) {
2775 if (use_fec_hwts)
2776 return fec_ptp_set(ndev, rq);
2777 fec_ptp_disable_hwts(ndev);
2778 } else if (cmd == SIOCGHWTSTAMP) {
2779 if (use_fec_hwts)
2780 return fec_ptp_get(ndev, rq);
2781 }
2782 }
2783
2784 return phy_mii_ioctl(phydev, rq, cmd);
2785}
2786
2787static void fec_enet_free_buffers(struct net_device *ndev)
2788{
2789 struct fec_enet_private *fep = netdev_priv(ndev);
2790 unsigned int i;
2791 struct sk_buff *skb;
2792 struct bufdesc *bdp;
2793 struct fec_enet_priv_tx_q *txq;
2794 struct fec_enet_priv_rx_q *rxq;
2795 unsigned int q;
2796
2797 for (q = 0; q < fep->num_rx_queues; q++) {
2798 rxq = fep->rx_queue[q];
2799 bdp = rxq->bd.base;
2800 for (i = 0; i < rxq->bd.ring_size; i++) {
2801 skb = rxq->rx_skbuff[i];
2802 rxq->rx_skbuff[i] = NULL;
2803 if (skb) {
2804 dma_unmap_single(&fep->pdev->dev,
2805 fec32_to_cpu(bdp->cbd_bufaddr),
2806 FEC_ENET_RX_FRSIZE - fep->rx_align,
2807 DMA_FROM_DEVICE);
2808 dev_kfree_skb(skb);
2809 }
2810 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2811 }
2812 }
2813
2814 for (q = 0; q < fep->num_tx_queues; q++) {
2815 txq = fep->tx_queue[q];
2816 for (i = 0; i < txq->bd.ring_size; i++) {
2817 kfree(txq->tx_bounce[i]);
2818 txq->tx_bounce[i] = NULL;
2819 skb = txq->tx_skbuff[i];
2820 txq->tx_skbuff[i] = NULL;
2821 dev_kfree_skb(skb);
2822 }
2823 }
2824}
2825
2826static void fec_enet_free_queue(struct net_device *ndev)
2827{
2828 struct fec_enet_private *fep = netdev_priv(ndev);
2829 int i;
2830 struct fec_enet_priv_tx_q *txq;
2831
2832 for (i = 0; i < fep->num_tx_queues; i++)
2833 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2834 txq = fep->tx_queue[i];
2835 dma_free_coherent(&fep->pdev->dev,
2836 txq->bd.ring_size * TSO_HEADER_SIZE,
2837 txq->tso_hdrs,
2838 txq->tso_hdrs_dma);
2839 }
2840
2841 for (i = 0; i < fep->num_rx_queues; i++)
2842 kfree(fep->rx_queue[i]);
2843 for (i = 0; i < fep->num_tx_queues; i++)
2844 kfree(fep->tx_queue[i]);
2845}
2846
2847static int fec_enet_alloc_queue(struct net_device *ndev)
2848{
2849 struct fec_enet_private *fep = netdev_priv(ndev);
2850 int i;
2851 int ret = 0;
2852 struct fec_enet_priv_tx_q *txq;
2853
2854 for (i = 0; i < fep->num_tx_queues; i++) {
2855 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2856 if (!txq) {
2857 ret = -ENOMEM;
2858 goto alloc_failed;
2859 }
2860
2861 fep->tx_queue[i] = txq;
2862 txq->bd.ring_size = TX_RING_SIZE;
2863 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
2864
2865 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2866 txq->tx_wake_threshold =
2867 (txq->bd.ring_size - txq->tx_stop_threshold) / 2;
2868
2869 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev,
2870 txq->bd.ring_size * TSO_HEADER_SIZE,
2871 &txq->tso_hdrs_dma,
2872 GFP_KERNEL);
2873 if (!txq->tso_hdrs) {
2874 ret = -ENOMEM;
2875 goto alloc_failed;
2876 }
2877 }
2878
2879 for (i = 0; i < fep->num_rx_queues; i++) {
2880 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2881 GFP_KERNEL);
2882 if (!fep->rx_queue[i]) {
2883 ret = -ENOMEM;
2884 goto alloc_failed;
2885 }
2886
2887 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
2888 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
2889 }
2890 return ret;
2891
2892alloc_failed:
2893 fec_enet_free_queue(ndev);
2894 return ret;
2895}
2896
2897static int
2898fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2899{
2900 struct fec_enet_private *fep = netdev_priv(ndev);
2901 unsigned int i;
2902 struct sk_buff *skb;
2903 struct bufdesc *bdp;
2904 struct fec_enet_priv_rx_q *rxq;
2905
2906 rxq = fep->rx_queue[queue];
2907 bdp = rxq->bd.base;
2908 for (i = 0; i < rxq->bd.ring_size; i++) {
2909 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2910 if (!skb)
2911 goto err_alloc;
2912
2913 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2914 dev_kfree_skb(skb);
2915 goto err_alloc;
2916 }
2917
2918 rxq->rx_skbuff[i] = skb;
2919 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
2920
2921 if (fep->bufdesc_ex) {
2922 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2923 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
2924 }
2925
2926 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2927 }
2928
2929 /* Set the last buffer to wrap. */
2930 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
2931 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2932 return 0;
2933
2934 err_alloc:
2935 fec_enet_free_buffers(ndev);
2936 return -ENOMEM;
2937}
2938
2939static int
2940fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2941{
2942 struct fec_enet_private *fep = netdev_priv(ndev);
2943 unsigned int i;
2944 struct bufdesc *bdp;
2945 struct fec_enet_priv_tx_q *txq;
2946
2947 txq = fep->tx_queue[queue];
2948 bdp = txq->bd.base;
2949 for (i = 0; i < txq->bd.ring_size; i++) {
2950 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2951 if (!txq->tx_bounce[i])
2952 goto err_alloc;
2953
2954 bdp->cbd_sc = cpu_to_fec16(0);
2955 bdp->cbd_bufaddr = cpu_to_fec32(0);
2956
2957 if (fep->bufdesc_ex) {
2958 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2959 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
2960 }
2961
2962 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
2963 }
2964
2965 /* Set the last buffer to wrap. */
2966 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
2967 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2968
2969 return 0;
2970
2971 err_alloc:
2972 fec_enet_free_buffers(ndev);
2973 return -ENOMEM;
2974}
2975
2976static int fec_enet_alloc_buffers(struct net_device *ndev)
2977{
2978 struct fec_enet_private *fep = netdev_priv(ndev);
2979 unsigned int i;
2980
2981 for (i = 0; i < fep->num_rx_queues; i++)
2982 if (fec_enet_alloc_rxq_buffers(ndev, i))
2983 return -ENOMEM;
2984
2985 for (i = 0; i < fep->num_tx_queues; i++)
2986 if (fec_enet_alloc_txq_buffers(ndev, i))
2987 return -ENOMEM;
2988 return 0;
2989}
2990
2991static int
2992fec_enet_open(struct net_device *ndev)
2993{
2994 struct fec_enet_private *fep = netdev_priv(ndev);
2995 int ret;
2996 bool reset_again;
2997
2998 ret = pm_runtime_resume_and_get(&fep->pdev->dev);
2999 if (ret < 0)
3000 return ret;
3001
3002 pinctrl_pm_select_default_state(&fep->pdev->dev);
3003 ret = fec_enet_clk_enable(ndev, true);
3004 if (ret)
3005 goto clk_enable;
3006
3007 /* During the first fec_enet_open call the PHY isn't probed at this
3008 * point. Therefore the phy_reset_after_clk_enable() call within
3009 * fec_enet_clk_enable() fails. As we need this reset in order to be
3010 * sure the PHY is working correctly we check if we need to reset again
3011 * later when the PHY is probed
3012 */
3013 if (ndev->phydev && ndev->phydev->drv)
3014 reset_again = false;
3015 else
3016 reset_again = true;
3017
3018 /* I should reset the ring buffers here, but I don't yet know
3019 * a simple way to do that.
3020 */
3021
3022 ret = fec_enet_alloc_buffers(ndev);
3023 if (ret)
3024 goto err_enet_alloc;
3025
3026 /* Init MAC prior to mii bus probe */
3027 fec_restart(ndev);
3028
3029 /* Call phy_reset_after_clk_enable() again if it failed during
3030 * phy_reset_after_clk_enable() before because the PHY wasn't probed.
3031 */
3032 if (reset_again)
3033 fec_enet_phy_reset_after_clk_enable(ndev);
3034
3035 /* Probe and connect to PHY when open the interface */
3036 ret = fec_enet_mii_probe(ndev);
3037 if (ret)
3038 goto err_enet_mii_probe;
3039
3040 if (fep->quirks & FEC_QUIRK_ERR006687)
3041 imx6q_cpuidle_fec_irqs_used();
3042
3043 napi_enable(&fep->napi);
3044 phy_start(ndev->phydev);
3045 netif_tx_start_all_queues(ndev);
3046
3047 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
3048 FEC_WOL_FLAG_ENABLE);
3049
3050 return 0;
3051
3052err_enet_mii_probe:
3053 fec_enet_free_buffers(ndev);
3054err_enet_alloc:
3055 fec_enet_clk_enable(ndev, false);
3056clk_enable:
3057 pm_runtime_mark_last_busy(&fep->pdev->dev);
3058 pm_runtime_put_autosuspend(&fep->pdev->dev);
3059 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3060 return ret;
3061}
3062
3063static int
3064fec_enet_close(struct net_device *ndev)
3065{
3066 struct fec_enet_private *fep = netdev_priv(ndev);
3067
3068 phy_stop(ndev->phydev);
3069
3070 if (netif_device_present(ndev)) {
3071 napi_disable(&fep->napi);
3072 netif_tx_disable(ndev);
3073 fec_stop(ndev);
3074 }
3075
3076 phy_disconnect(ndev->phydev);
3077
3078 if (fep->quirks & FEC_QUIRK_ERR006687)
3079 imx6q_cpuidle_fec_irqs_unused();
3080
3081 fec_enet_update_ethtool_stats(ndev);
3082
3083 fec_enet_clk_enable(ndev, false);
3084 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3085 pm_runtime_mark_last_busy(&fep->pdev->dev);
3086 pm_runtime_put_autosuspend(&fep->pdev->dev);
3087
3088 fec_enet_free_buffers(ndev);
3089
3090 return 0;
3091}
3092
3093/* Set or clear the multicast filter for this adaptor.
3094 * Skeleton taken from sunlance driver.
3095 * The CPM Ethernet implementation allows Multicast as well as individual
3096 * MAC address filtering. Some of the drivers check to make sure it is
3097 * a group multicast address, and discard those that are not. I guess I
3098 * will do the same for now, but just remove the test if you want
3099 * individual filtering as well (do the upper net layers want or support
3100 * this kind of feature?).
3101 */
3102
3103#define FEC_HASH_BITS 6 /* #bits in hash */
3104
3105static void set_multicast_list(struct net_device *ndev)
3106{
3107 struct fec_enet_private *fep = netdev_priv(ndev);
3108 struct netdev_hw_addr *ha;
3109 unsigned int crc, tmp;
3110 unsigned char hash;
3111 unsigned int hash_high = 0, hash_low = 0;
3112
3113 if (ndev->flags & IFF_PROMISC) {
3114 tmp = readl(fep->hwp + FEC_R_CNTRL);
3115 tmp |= 0x8;
3116 writel(tmp, fep->hwp + FEC_R_CNTRL);
3117 return;
3118 }
3119
3120 tmp = readl(fep->hwp + FEC_R_CNTRL);
3121 tmp &= ~0x8;
3122 writel(tmp, fep->hwp + FEC_R_CNTRL);
3123
3124 if (ndev->flags & IFF_ALLMULTI) {
3125 /* Catch all multicast addresses, so set the
3126 * filter to all 1's
3127 */
3128 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3129 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3130
3131 return;
3132 }
3133
3134 /* Add the addresses in hash register */
3135 netdev_for_each_mc_addr(ha, ndev) {
3136 /* calculate crc32 value of mac address */
3137 crc = ether_crc_le(ndev->addr_len, ha->addr);
3138
3139 /* only upper 6 bits (FEC_HASH_BITS) are used
3140 * which point to specific bit in the hash registers
3141 */
3142 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
3143
3144 if (hash > 31)
3145 hash_high |= 1 << (hash - 32);
3146 else
3147 hash_low |= 1 << hash;
3148 }
3149
3150 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3151 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3152}
3153
3154/* Set a MAC change in hardware. */
3155static int
3156fec_set_mac_address(struct net_device *ndev, void *p)
3157{
3158 struct fec_enet_private *fep = netdev_priv(ndev);
3159 struct sockaddr *addr = p;
3160
3161 if (addr) {
3162 if (!is_valid_ether_addr(addr->sa_data))
3163 return -EADDRNOTAVAIL;
3164 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3165 }
3166
3167 /* Add netif status check here to avoid system hang in below case:
3168 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3169 * After ethx down, fec all clocks are gated off and then register
3170 * access causes system hang.
3171 */
3172 if (!netif_running(ndev))
3173 return 0;
3174
3175 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3176 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3177 fep->hwp + FEC_ADDR_LOW);
3178 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3179 fep->hwp + FEC_ADDR_HIGH);
3180 return 0;
3181}
3182
3183#ifdef CONFIG_NET_POLL_CONTROLLER
3184/**
3185 * fec_poll_controller - FEC Poll controller function
3186 * @dev: The FEC network adapter
3187 *
3188 * Polled functionality used by netconsole and others in non interrupt mode
3189 *
3190 */
3191static void fec_poll_controller(struct net_device *dev)
3192{
3193 int i;
3194 struct fec_enet_private *fep = netdev_priv(dev);
3195
3196 for (i = 0; i < FEC_IRQ_NUM; i++) {
3197 if (fep->irq[i] > 0) {
3198 disable_irq(fep->irq[i]);
3199 fec_enet_interrupt(fep->irq[i], dev);
3200 enable_irq(fep->irq[i]);
3201 }
3202 }
3203}
3204#endif
3205
3206static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3207 netdev_features_t features)
3208{
3209 struct fec_enet_private *fep = netdev_priv(netdev);
3210 netdev_features_t changed = features ^ netdev->features;
3211
3212 netdev->features = features;
3213
3214 /* Receive checksum has been changed */
3215 if (changed & NETIF_F_RXCSUM) {
3216 if (features & NETIF_F_RXCSUM)
3217 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3218 else
3219 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3220 }
3221}
3222
3223static int fec_set_features(struct net_device *netdev,
3224 netdev_features_t features)
3225{
3226 struct fec_enet_private *fep = netdev_priv(netdev);
3227 netdev_features_t changed = features ^ netdev->features;
3228
3229 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3230 napi_disable(&fep->napi);
3231 netif_tx_lock_bh(netdev);
3232 fec_stop(netdev);
3233 fec_enet_set_netdev_features(netdev, features);
3234 fec_restart(netdev);
3235 netif_tx_wake_all_queues(netdev);
3236 netif_tx_unlock_bh(netdev);
3237 napi_enable(&fep->napi);
3238 } else {
3239 fec_enet_set_netdev_features(netdev, features);
3240 }
3241
3242 return 0;
3243}
3244
3245static u16 fec_enet_get_raw_vlan_tci(struct sk_buff *skb)
3246{
3247 struct vlan_ethhdr *vhdr;
3248 unsigned short vlan_TCI = 0;
3249
3250 if (skb->protocol == htons(ETH_P_ALL)) {
3251 vhdr = (struct vlan_ethhdr *)(skb->data);
3252 vlan_TCI = ntohs(vhdr->h_vlan_TCI);
3253 }
3254
3255 return vlan_TCI;
3256}
3257
3258static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb,
3259 struct net_device *sb_dev)
3260{
3261 struct fec_enet_private *fep = netdev_priv(ndev);
3262 u16 vlan_tag;
3263
3264 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
3265 return netdev_pick_tx(ndev, skb, NULL);
3266
3267 vlan_tag = fec_enet_get_raw_vlan_tci(skb);
3268 if (!vlan_tag)
3269 return vlan_tag;
3270
3271 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13];
3272}
3273
3274static const struct net_device_ops fec_netdev_ops = {
3275 .ndo_open = fec_enet_open,
3276 .ndo_stop = fec_enet_close,
3277 .ndo_start_xmit = fec_enet_start_xmit,
3278 .ndo_select_queue = fec_enet_select_queue,
3279 .ndo_set_rx_mode = set_multicast_list,
3280 .ndo_validate_addr = eth_validate_addr,
3281 .ndo_tx_timeout = fec_timeout,
3282 .ndo_set_mac_address = fec_set_mac_address,
3283 .ndo_do_ioctl = fec_enet_ioctl,
3284#ifdef CONFIG_NET_POLL_CONTROLLER
3285 .ndo_poll_controller = fec_poll_controller,
3286#endif
3287 .ndo_set_features = fec_set_features,
3288};
3289
3290static const unsigned short offset_des_active_rxq[] = {
3291 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3292};
3293
3294static const unsigned short offset_des_active_txq[] = {
3295 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3296};
3297
3298 /*
3299 * XXX: We need to clean up on failure exits here.
3300 *
3301 */
3302static int fec_enet_init(struct net_device *ndev)
3303{
3304 struct fec_enet_private *fep = netdev_priv(ndev);
3305 struct bufdesc *cbd_base;
3306 dma_addr_t bd_dma;
3307 int bd_size;
3308 unsigned int i;
3309 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3310 sizeof(struct bufdesc);
3311 unsigned dsize_log2 = __fls(dsize);
3312 int ret;
3313
3314 WARN_ON(dsize != (1 << dsize_log2));
3315#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
3316 fep->rx_align = 0xf;
3317 fep->tx_align = 0xf;
3318#else
3319 fep->rx_align = 0x3;
3320 fep->tx_align = 0x3;
3321#endif
3322
3323 /* Check mask of the streaming and coherent API */
3324 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32));
3325 if (ret < 0) {
3326 dev_warn(&fep->pdev->dev, "No suitable DMA available\n");
3327 return ret;
3328 }
3329
3330 ret = fec_enet_alloc_queue(ndev);
3331 if (ret)
3332 return ret;
3333
3334 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
3335
3336 /* Allocate memory for buffer descriptors. */
3337 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3338 GFP_KERNEL);
3339 if (!cbd_base) {
3340 ret = -ENOMEM;
3341 goto free_queue_mem;
3342 }
3343
3344 /* Get the Ethernet address */
3345 ret = fec_get_mac(ndev);
3346 if (ret)
3347 goto free_queue_mem;
3348
3349 /* make sure MAC we just acquired is programmed into the hw */
3350 fec_set_mac_address(ndev, NULL);
3351
3352 /* Set receive and transmit descriptor base. */
3353 for (i = 0; i < fep->num_rx_queues; i++) {
3354 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3355 unsigned size = dsize * rxq->bd.ring_size;
3356
3357 rxq->bd.qid = i;
3358 rxq->bd.base = cbd_base;
3359 rxq->bd.cur = cbd_base;
3360 rxq->bd.dma = bd_dma;
3361 rxq->bd.dsize = dsize;
3362 rxq->bd.dsize_log2 = dsize_log2;
3363 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
3364 bd_dma += size;
3365 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3366 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3367 }
3368
3369 for (i = 0; i < fep->num_tx_queues; i++) {
3370 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3371 unsigned size = dsize * txq->bd.ring_size;
3372
3373 txq->bd.qid = i;
3374 txq->bd.base = cbd_base;
3375 txq->bd.cur = cbd_base;
3376 txq->bd.dma = bd_dma;
3377 txq->bd.dsize = dsize;
3378 txq->bd.dsize_log2 = dsize_log2;
3379 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
3380 bd_dma += size;
3381 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3382 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3383 }
3384
3385
3386 /* The FEC Ethernet specific entries in the device structure */
3387 ndev->watchdog_timeo = TX_TIMEOUT;
3388 ndev->netdev_ops = &fec_netdev_ops;
3389 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3390
3391 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3392 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3393
3394 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3395 /* enable hw VLAN support */
3396 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3397
3398 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3399 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3400
3401 /* enable hw accelerator */
3402 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3403 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3404 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3405 }
3406
3407 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
3408 fep->tx_align = 0;
3409 fep->rx_align = 0x3f;
3410 }
3411
3412 ndev->hw_features = ndev->features;
3413
3414 fec_restart(ndev);
3415
3416 if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
3417 fec_enet_clear_ethtool_stats(ndev);
3418 else
3419 fec_enet_update_ethtool_stats(ndev);
3420
3421 return 0;
3422
3423free_queue_mem:
3424 fec_enet_free_queue(ndev);
3425 return ret;
3426}
3427
3428#ifdef CONFIG_OF
3429static int fec_reset_phy(struct platform_device *pdev)
3430{
3431 int err, phy_reset;
3432 bool active_high = false;
3433 int msec = 1, phy_post_delay = 0;
3434 struct device_node *np = pdev->dev.of_node;
3435
3436 if (!np)
3437 return 0;
3438
3439 err = of_property_read_u32(np, "phy-reset-duration", &msec);
3440 /* A sane reset duration should not be longer than 1s */
3441 if (!err && msec > 1000)
3442 msec = 1;
3443
3444 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3445 if (phy_reset == -EPROBE_DEFER)
3446 return phy_reset;
3447 else if (!gpio_is_valid(phy_reset))
3448 return 0;
3449
3450 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay);
3451 /* valid reset duration should be less than 1s */
3452 if (!err && phy_post_delay > 1000)
3453 return -EINVAL;
3454
3455 active_high = of_property_read_bool(np, "phy-reset-active-high");
3456
3457 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3458 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
3459 "phy-reset");
3460 if (err) {
3461 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3462 return err;
3463 }
3464
3465 if (msec > 20)
3466 msleep(msec);
3467 else
3468 usleep_range(msec * 1000, msec * 1000 + 1000);
3469
3470 gpio_set_value_cansleep(phy_reset, !active_high);
3471
3472 if (!phy_post_delay)
3473 return 0;
3474
3475 if (phy_post_delay > 20)
3476 msleep(phy_post_delay);
3477 else
3478 usleep_range(phy_post_delay * 1000,
3479 phy_post_delay * 1000 + 1000);
3480
3481 return 0;
3482}
3483#else /* CONFIG_OF */
3484static int fec_reset_phy(struct platform_device *pdev)
3485{
3486 /*
3487 * In case of platform probe, the reset has been done
3488 * by machine code.
3489 */
3490 return 0;
3491}
3492#endif /* CONFIG_OF */
3493
3494static void
3495fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3496{
3497 struct device_node *np = pdev->dev.of_node;
3498
3499 *num_tx = *num_rx = 1;
3500
3501 if (!np || !of_device_is_available(np))
3502 return;
3503
3504 /* parse the num of tx and rx queues */
3505 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3506
3507 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3508
3509 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3510 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3511 *num_tx);
3512 *num_tx = 1;
3513 return;
3514 }
3515
3516 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3517 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3518 *num_rx);
3519 *num_rx = 1;
3520 return;
3521 }
3522
3523}
3524
3525static int fec_enet_get_irq_cnt(struct platform_device *pdev)
3526{
3527 int irq_cnt = platform_irq_count(pdev);
3528
3529 if (irq_cnt > FEC_IRQ_NUM)
3530 irq_cnt = FEC_IRQ_NUM; /* last for pps */
3531 else if (irq_cnt == 2)
3532 irq_cnt = 1; /* last for pps */
3533 else if (irq_cnt <= 0)
3534 irq_cnt = 1; /* At least 1 irq is needed */
3535 return irq_cnt;
3536}
3537
3538static int fec_enet_init_stop_mode(struct fec_enet_private *fep,
3539 struct device_node *np)
3540{
3541 struct device_node *gpr_np;
3542 u32 out_val[3];
3543 int ret = 0;
3544
3545 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0);
3546 if (!gpr_np)
3547 return 0;
3548
3549 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
3550 ARRAY_SIZE(out_val));
3551 if (ret) {
3552 dev_dbg(&fep->pdev->dev, "no stop mode property\n");
3553 return ret;
3554 }
3555
3556 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np);
3557 if (IS_ERR(fep->stop_gpr.gpr)) {
3558 dev_err(&fep->pdev->dev, "could not find gpr regmap\n");
3559 ret = PTR_ERR(fep->stop_gpr.gpr);
3560 fep->stop_gpr.gpr = NULL;
3561 goto out;
3562 }
3563
3564 fep->stop_gpr.reg = out_val[1];
3565 fep->stop_gpr.bit = out_val[2];
3566
3567out:
3568 of_node_put(gpr_np);
3569
3570 return ret;
3571}
3572
3573static int
3574fec_probe(struct platform_device *pdev)
3575{
3576 struct fec_enet_private *fep;
3577 struct fec_platform_data *pdata;
3578 phy_interface_t interface;
3579 struct net_device *ndev;
3580 int i, irq, ret = 0;
3581 const struct of_device_id *of_id;
3582 static int dev_id;
3583 struct device_node *np = pdev->dev.of_node, *phy_node;
3584 int num_tx_qs;
3585 int num_rx_qs;
3586 char irq_name[8];
3587 int irq_cnt;
3588 struct fec_devinfo *dev_info;
3589
3590 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3591
3592 /* Init network device */
3593 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
3594 FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
3595 if (!ndev)
3596 return -ENOMEM;
3597
3598 SET_NETDEV_DEV(ndev, &pdev->dev);
3599
3600 /* setup board info structure */
3601 fep = netdev_priv(ndev);
3602
3603 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3604 if (of_id)
3605 pdev->id_entry = of_id->data;
3606 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data;
3607 if (dev_info)
3608 fep->quirks = dev_info->quirks;
3609
3610 fep->netdev = ndev;
3611 fep->num_rx_queues = num_rx_qs;
3612 fep->num_tx_queues = num_tx_qs;
3613
3614#if !defined(CONFIG_M5272)
3615 /* default enable pause frame auto negotiation */
3616 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3617 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3618#endif
3619
3620 /* Select default pin state */
3621 pinctrl_pm_select_default_state(&pdev->dev);
3622
3623 fep->hwp = devm_platform_ioremap_resource(pdev, 0);
3624 if (IS_ERR(fep->hwp)) {
3625 ret = PTR_ERR(fep->hwp);
3626 goto failed_ioremap;
3627 }
3628
3629 fep->pdev = pdev;
3630 fep->dev_id = dev_id++;
3631
3632 platform_set_drvdata(pdev, ndev);
3633
3634 if ((of_machine_is_compatible("fsl,imx6q") ||
3635 of_machine_is_compatible("fsl,imx6dl")) &&
3636 !of_property_read_bool(np, "fsl,err006687-workaround-present"))
3637 fep->quirks |= FEC_QUIRK_ERR006687;
3638
3639 if (of_get_property(np, "fsl,magic-packet", NULL))
3640 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3641
3642 ret = fec_enet_init_stop_mode(fep, np);
3643 if (ret)
3644 goto failed_stop_mode;
3645
3646 phy_node = of_parse_phandle(np, "phy-handle", 0);
3647 if (!phy_node && of_phy_is_fixed_link(np)) {
3648 ret = of_phy_register_fixed_link(np);
3649 if (ret < 0) {
3650 dev_err(&pdev->dev,
3651 "broken fixed-link specification\n");
3652 goto failed_phy;
3653 }
3654 phy_node = of_node_get(np);
3655 }
3656 fep->phy_node = phy_node;
3657
3658 ret = of_get_phy_mode(pdev->dev.of_node, &interface);
3659 if (ret) {
3660 pdata = dev_get_platdata(&pdev->dev);
3661 if (pdata)
3662 fep->phy_interface = pdata->phy;
3663 else
3664 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3665 } else {
3666 fep->phy_interface = interface;
3667 }
3668
3669 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3670 if (IS_ERR(fep->clk_ipg)) {
3671 ret = PTR_ERR(fep->clk_ipg);
3672 goto failed_clk;
3673 }
3674
3675 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3676 if (IS_ERR(fep->clk_ahb)) {
3677 ret = PTR_ERR(fep->clk_ahb);
3678 goto failed_clk;
3679 }
3680
3681 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3682
3683 /* enet_out is optional, depends on board */
3684 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3685 if (IS_ERR(fep->clk_enet_out))
3686 fep->clk_enet_out = NULL;
3687
3688 fep->ptp_clk_on = false;
3689 mutex_init(&fep->ptp_clk_mutex);
3690
3691 /* clk_ref is optional, depends on board */
3692 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3693 if (IS_ERR(fep->clk_ref))
3694 fep->clk_ref = NULL;
3695
3696 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3697 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3698 if (IS_ERR(fep->clk_ptp)) {
3699 fep->clk_ptp = NULL;
3700 fep->bufdesc_ex = false;
3701 }
3702
3703 ret = fec_enet_clk_enable(ndev, true);
3704 if (ret)
3705 goto failed_clk;
3706
3707 ret = clk_prepare_enable(fep->clk_ipg);
3708 if (ret)
3709 goto failed_clk_ipg;
3710 ret = clk_prepare_enable(fep->clk_ahb);
3711 if (ret)
3712 goto failed_clk_ahb;
3713
3714 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy");
3715 if (!IS_ERR(fep->reg_phy)) {
3716 ret = regulator_enable(fep->reg_phy);
3717 if (ret) {
3718 dev_err(&pdev->dev,
3719 "Failed to enable phy regulator: %d\n", ret);
3720 goto failed_regulator;
3721 }
3722 } else {
3723 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) {
3724 ret = -EPROBE_DEFER;
3725 goto failed_regulator;
3726 }
3727 fep->reg_phy = NULL;
3728 }
3729
3730 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3731 pm_runtime_use_autosuspend(&pdev->dev);
3732 pm_runtime_get_noresume(&pdev->dev);
3733 pm_runtime_set_active(&pdev->dev);
3734 pm_runtime_enable(&pdev->dev);
3735
3736 ret = fec_reset_phy(pdev);
3737 if (ret)
3738 goto failed_reset;
3739
3740 irq_cnt = fec_enet_get_irq_cnt(pdev);
3741 if (fep->bufdesc_ex)
3742 fec_ptp_init(pdev, irq_cnt);
3743
3744 ret = fec_enet_init(ndev);
3745 if (ret)
3746 goto failed_init;
3747
3748 for (i = 0; i < irq_cnt; i++) {
3749 snprintf(irq_name, sizeof(irq_name), "int%d", i);
3750 irq = platform_get_irq_byname_optional(pdev, irq_name);
3751 if (irq < 0)
3752 irq = platform_get_irq(pdev, i);
3753 if (irq < 0) {
3754 ret = irq;
3755 goto failed_irq;
3756 }
3757 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3758 0, pdev->name, ndev);
3759 if (ret)
3760 goto failed_irq;
3761
3762 fep->irq[i] = irq;
3763 }
3764
3765 ret = fec_enet_mii_init(pdev);
3766 if (ret)
3767 goto failed_mii_init;
3768
3769 /* Carrier starts down, phylib will bring it up */
3770 netif_carrier_off(ndev);
3771 fec_enet_clk_enable(ndev, false);
3772 pinctrl_pm_select_sleep_state(&pdev->dev);
3773
3774 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN;
3775
3776 ret = register_netdev(ndev);
3777 if (ret)
3778 goto failed_register;
3779
3780 device_init_wakeup(&ndev->dev, fep->wol_flag &
3781 FEC_WOL_HAS_MAGIC_PACKET);
3782
3783 if (fep->bufdesc_ex && fep->ptp_clock)
3784 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3785
3786 fep->rx_copybreak = COPYBREAK_DEFAULT;
3787 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3788
3789 pm_runtime_mark_last_busy(&pdev->dev);
3790 pm_runtime_put_autosuspend(&pdev->dev);
3791
3792 return 0;
3793
3794failed_register:
3795 fec_enet_mii_remove(fep);
3796failed_mii_init:
3797failed_irq:
3798failed_init:
3799 fec_ptp_stop(pdev);
3800failed_reset:
3801 pm_runtime_put_noidle(&pdev->dev);
3802 pm_runtime_disable(&pdev->dev);
3803 if (fep->reg_phy)
3804 regulator_disable(fep->reg_phy);
3805failed_regulator:
3806 clk_disable_unprepare(fep->clk_ahb);
3807failed_clk_ahb:
3808 clk_disable_unprepare(fep->clk_ipg);
3809failed_clk_ipg:
3810 fec_enet_clk_enable(ndev, false);
3811failed_clk:
3812 if (of_phy_is_fixed_link(np))
3813 of_phy_deregister_fixed_link(np);
3814 of_node_put(phy_node);
3815failed_stop_mode:
3816failed_phy:
3817 dev_id--;
3818failed_ioremap:
3819 free_netdev(ndev);
3820
3821 return ret;
3822}
3823
3824static int
3825fec_drv_remove(struct platform_device *pdev)
3826{
3827 struct net_device *ndev = platform_get_drvdata(pdev);
3828 struct fec_enet_private *fep = netdev_priv(ndev);
3829 struct device_node *np = pdev->dev.of_node;
3830 int ret;
3831
3832 ret = pm_runtime_resume_and_get(&pdev->dev);
3833 if (ret < 0)
3834 return ret;
3835
3836 cancel_work_sync(&fep->tx_timeout_work);
3837 fec_ptp_stop(pdev);
3838 unregister_netdev(ndev);
3839 fec_enet_mii_remove(fep);
3840 if (fep->reg_phy)
3841 regulator_disable(fep->reg_phy);
3842
3843 if (of_phy_is_fixed_link(np))
3844 of_phy_deregister_fixed_link(np);
3845 of_node_put(fep->phy_node);
3846
3847 clk_disable_unprepare(fep->clk_ahb);
3848 clk_disable_unprepare(fep->clk_ipg);
3849 pm_runtime_put_noidle(&pdev->dev);
3850 pm_runtime_disable(&pdev->dev);
3851
3852 free_netdev(ndev);
3853 return 0;
3854}
3855
3856static int __maybe_unused fec_suspend(struct device *dev)
3857{
3858 struct net_device *ndev = dev_get_drvdata(dev);
3859 struct fec_enet_private *fep = netdev_priv(ndev);
3860
3861 rtnl_lock();
3862 if (netif_running(ndev)) {
3863 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3864 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3865 phy_stop(ndev->phydev);
3866 napi_disable(&fep->napi);
3867 netif_tx_lock_bh(ndev);
3868 netif_device_detach(ndev);
3869 netif_tx_unlock_bh(ndev);
3870 fec_stop(ndev);
3871 fec_enet_clk_enable(ndev, false);
3872 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3873 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3874 }
3875 rtnl_unlock();
3876
3877 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3878 regulator_disable(fep->reg_phy);
3879
3880 /* SOC supply clock to phy, when clock is disabled, phy link down
3881 * SOC control phy regulator, when regulator is disabled, phy link down
3882 */
3883 if (fep->clk_enet_out || fep->reg_phy)
3884 fep->link = 0;
3885
3886 return 0;
3887}
3888
3889static int __maybe_unused fec_resume(struct device *dev)
3890{
3891 struct net_device *ndev = dev_get_drvdata(dev);
3892 struct fec_enet_private *fep = netdev_priv(ndev);
3893 int ret;
3894 int val;
3895
3896 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3897 ret = regulator_enable(fep->reg_phy);
3898 if (ret)
3899 return ret;
3900 }
3901
3902 rtnl_lock();
3903 if (netif_running(ndev)) {
3904 ret = fec_enet_clk_enable(ndev, true);
3905 if (ret) {
3906 rtnl_unlock();
3907 goto failed_clk;
3908 }
3909 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3910 fec_enet_stop_mode(fep, false);
3911
3912 val = readl(fep->hwp + FEC_ECNTRL);
3913 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3914 writel(val, fep->hwp + FEC_ECNTRL);
3915 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3916 } else {
3917 pinctrl_pm_select_default_state(&fep->pdev->dev);
3918 }
3919 fec_restart(ndev);
3920 netif_tx_lock_bh(ndev);
3921 netif_device_attach(ndev);
3922 netif_tx_unlock_bh(ndev);
3923 napi_enable(&fep->napi);
3924 phy_init_hw(ndev->phydev);
3925 phy_start(ndev->phydev);
3926 }
3927 rtnl_unlock();
3928
3929 return 0;
3930
3931failed_clk:
3932 if (fep->reg_phy)
3933 regulator_disable(fep->reg_phy);
3934 return ret;
3935}
3936
3937static int __maybe_unused fec_runtime_suspend(struct device *dev)
3938{
3939 struct net_device *ndev = dev_get_drvdata(dev);
3940 struct fec_enet_private *fep = netdev_priv(ndev);
3941
3942 clk_disable_unprepare(fep->clk_ahb);
3943 clk_disable_unprepare(fep->clk_ipg);
3944
3945 return 0;
3946}
3947
3948static int __maybe_unused fec_runtime_resume(struct device *dev)
3949{
3950 struct net_device *ndev = dev_get_drvdata(dev);
3951 struct fec_enet_private *fep = netdev_priv(ndev);
3952 int ret;
3953
3954 ret = clk_prepare_enable(fep->clk_ahb);
3955 if (ret)
3956 return ret;
3957 ret = clk_prepare_enable(fep->clk_ipg);
3958 if (ret)
3959 goto failed_clk_ipg;
3960
3961 return 0;
3962
3963failed_clk_ipg:
3964 clk_disable_unprepare(fep->clk_ahb);
3965 return ret;
3966}
3967
3968static const struct dev_pm_ops fec_pm_ops = {
3969 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3970 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3971};
3972
3973static struct platform_driver fec_driver = {
3974 .driver = {
3975 .name = DRIVER_NAME,
3976 .pm = &fec_pm_ops,
3977 .of_match_table = fec_dt_ids,
3978 .suppress_bind_attrs = true,
3979 },
3980 .id_table = fec_devtype,
3981 .probe = fec_probe,
3982 .remove = fec_drv_remove,
3983};
3984
3985module_platform_driver(fec_driver);
3986
3987MODULE_ALIAS("platform:"DRIVER_NAME);
3988MODULE_LICENSE("GPL");