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1/*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/string.h>
27#include <linux/pm_runtime.h>
28#include <linux/ptrace.h>
29#include <linux/errno.h>
30#include <linux/ioport.h>
31#include <linux/slab.h>
32#include <linux/interrupt.h>
33#include <linux/delay.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/skbuff.h>
37#include <linux/in.h>
38#include <linux/ip.h>
39#include <net/ip.h>
40#include <net/tso.h>
41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/icmp.h>
44#include <linux/spinlock.h>
45#include <linux/workqueue.h>
46#include <linux/bitops.h>
47#include <linux/io.h>
48#include <linux/irq.h>
49#include <linux/clk.h>
50#include <linux/platform_device.h>
51#include <linux/mdio.h>
52#include <linux/phy.h>
53#include <linux/fec.h>
54#include <linux/of.h>
55#include <linux/of_device.h>
56#include <linux/of_gpio.h>
57#include <linux/of_mdio.h>
58#include <linux/of_net.h>
59#include <linux/regulator/consumer.h>
60#include <linux/if_vlan.h>
61#include <linux/pinctrl/consumer.h>
62#include <linux/prefetch.h>
63#include <soc/imx/cpuidle.h>
64
65#include <asm/cacheflush.h>
66
67#include "fec.h"
68
69static void set_multicast_list(struct net_device *ndev);
70static void fec_enet_itr_coal_init(struct net_device *ndev);
71
72#define DRIVER_NAME "fec"
73
74#define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
75
76/* Pause frame feild and FIFO threshold */
77#define FEC_ENET_FCE (1 << 5)
78#define FEC_ENET_RSEM_V 0x84
79#define FEC_ENET_RSFL_V 16
80#define FEC_ENET_RAEM_V 0x8
81#define FEC_ENET_RAFL_V 0x8
82#define FEC_ENET_OPD_V 0xFFF0
83#define FEC_MDIO_PM_TIMEOUT 100 /* ms */
84
85static struct platform_device_id fec_devtype[] = {
86 {
87 /* keep it for coldfire */
88 .name = DRIVER_NAME,
89 .driver_data = 0,
90 }, {
91 .name = "imx25-fec",
92 .driver_data = FEC_QUIRK_USE_GASKET,
93 }, {
94 .name = "imx27-fec",
95 .driver_data = 0,
96 }, {
97 .name = "imx28-fec",
98 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
99 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC,
100 }, {
101 .name = "imx6q-fec",
102 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
103 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
104 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
105 FEC_QUIRK_HAS_RACC,
106 }, {
107 .name = "mvf600-fec",
108 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
109 }, {
110 .name = "imx6sx-fec",
111 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
112 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
113 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
114 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
115 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE,
116 }, {
117 .name = "imx6ul-fec",
118 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
119 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
120 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_BUG_CAPTURE |
121 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE,
122 }, {
123 /* sentinel */
124 }
125};
126MODULE_DEVICE_TABLE(platform, fec_devtype);
127
128enum imx_fec_type {
129 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
130 IMX27_FEC, /* runs on i.mx27/35/51 */
131 IMX28_FEC,
132 IMX6Q_FEC,
133 MVF600_FEC,
134 IMX6SX_FEC,
135 IMX6UL_FEC,
136};
137
138static const struct of_device_id fec_dt_ids[] = {
139 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
140 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
141 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
142 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
143 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
144 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
145 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
146 { /* sentinel */ }
147};
148MODULE_DEVICE_TABLE(of, fec_dt_ids);
149
150static unsigned char macaddr[ETH_ALEN];
151module_param_array(macaddr, byte, NULL, 0);
152MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
153
154#if defined(CONFIG_M5272)
155/*
156 * Some hardware gets it MAC address out of local flash memory.
157 * if this is non-zero then assume it is the address to get MAC from.
158 */
159#if defined(CONFIG_NETtel)
160#define FEC_FLASHMAC 0xf0006006
161#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
162#define FEC_FLASHMAC 0xf0006000
163#elif defined(CONFIG_CANCam)
164#define FEC_FLASHMAC 0xf0020000
165#elif defined (CONFIG_M5272C3)
166#define FEC_FLASHMAC (0xffe04000 + 4)
167#elif defined(CONFIG_MOD5272)
168#define FEC_FLASHMAC 0xffc0406b
169#else
170#define FEC_FLASHMAC 0
171#endif
172#endif /* CONFIG_M5272 */
173
174/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
175 */
176#define PKT_MAXBUF_SIZE 1522
177#define PKT_MINBUF_SIZE 64
178#define PKT_MAXBLR_SIZE 1536
179
180/* FEC receive acceleration */
181#define FEC_RACC_IPDIS (1 << 1)
182#define FEC_RACC_PRODIS (1 << 2)
183#define FEC_RACC_SHIFT16 BIT(7)
184#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
185
186/*
187 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
188 * size bits. Other FEC hardware does not, so we need to take that into
189 * account when setting it.
190 */
191#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
192 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
193#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
194#else
195#define OPT_FRAME_SIZE 0
196#endif
197
198/* FEC MII MMFR bits definition */
199#define FEC_MMFR_ST (1 << 30)
200#define FEC_MMFR_OP_READ (2 << 28)
201#define FEC_MMFR_OP_WRITE (1 << 28)
202#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
203#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
204#define FEC_MMFR_TA (2 << 16)
205#define FEC_MMFR_DATA(v) (v & 0xffff)
206/* FEC ECR bits definition */
207#define FEC_ECR_MAGICEN (1 << 2)
208#define FEC_ECR_SLEEP (1 << 3)
209
210#define FEC_MII_TIMEOUT 30000 /* us */
211
212/* Transmitter timeout */
213#define TX_TIMEOUT (2 * HZ)
214
215#define FEC_PAUSE_FLAG_AUTONEG 0x1
216#define FEC_PAUSE_FLAG_ENABLE 0x2
217#define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
218#define FEC_WOL_FLAG_ENABLE (0x1 << 1)
219#define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
220
221#define COPYBREAK_DEFAULT 256
222
223#define TSO_HEADER_SIZE 128
224/* Max number of allowed TCP segments for software TSO */
225#define FEC_MAX_TSO_SEGS 100
226#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
227
228#define IS_TSO_HEADER(txq, addr) \
229 ((addr >= txq->tso_hdrs_dma) && \
230 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
231
232static int mii_cnt;
233
234static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
235 struct bufdesc_prop *bd)
236{
237 return (bdp >= bd->last) ? bd->base
238 : (struct bufdesc *)(((unsigned)bdp) + bd->dsize);
239}
240
241static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
242 struct bufdesc_prop *bd)
243{
244 return (bdp <= bd->base) ? bd->last
245 : (struct bufdesc *)(((unsigned)bdp) - bd->dsize);
246}
247
248static int fec_enet_get_bd_index(struct bufdesc *bdp,
249 struct bufdesc_prop *bd)
250{
251 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
252}
253
254static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
255{
256 int entries;
257
258 entries = (((const char *)txq->dirty_tx -
259 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
260
261 return entries >= 0 ? entries : entries + txq->bd.ring_size;
262}
263
264static void swap_buffer(void *bufaddr, int len)
265{
266 int i;
267 unsigned int *buf = bufaddr;
268
269 for (i = 0; i < len; i += 4, buf++)
270 swab32s(buf);
271}
272
273static void swap_buffer2(void *dst_buf, void *src_buf, int len)
274{
275 int i;
276 unsigned int *src = src_buf;
277 unsigned int *dst = dst_buf;
278
279 for (i = 0; i < len; i += 4, src++, dst++)
280 *dst = swab32p(src);
281}
282
283static void fec_dump(struct net_device *ndev)
284{
285 struct fec_enet_private *fep = netdev_priv(ndev);
286 struct bufdesc *bdp;
287 struct fec_enet_priv_tx_q *txq;
288 int index = 0;
289
290 netdev_info(ndev, "TX ring dump\n");
291 pr_info("Nr SC addr len SKB\n");
292
293 txq = fep->tx_queue[0];
294 bdp = txq->bd.base;
295
296 do {
297 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
298 index,
299 bdp == txq->bd.cur ? 'S' : ' ',
300 bdp == txq->dirty_tx ? 'H' : ' ',
301 fec16_to_cpu(bdp->cbd_sc),
302 fec32_to_cpu(bdp->cbd_bufaddr),
303 fec16_to_cpu(bdp->cbd_datlen),
304 txq->tx_skbuff[index]);
305 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
306 index++;
307 } while (bdp != txq->bd.base);
308}
309
310static inline bool is_ipv4_pkt(struct sk_buff *skb)
311{
312 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
313}
314
315static int
316fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
317{
318 /* Only run for packets requiring a checksum. */
319 if (skb->ip_summed != CHECKSUM_PARTIAL)
320 return 0;
321
322 if (unlikely(skb_cow_head(skb, 0)))
323 return -1;
324
325 if (is_ipv4_pkt(skb))
326 ip_hdr(skb)->check = 0;
327 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
328
329 return 0;
330}
331
332static struct bufdesc *
333fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
334 struct sk_buff *skb,
335 struct net_device *ndev)
336{
337 struct fec_enet_private *fep = netdev_priv(ndev);
338 struct bufdesc *bdp = txq->bd.cur;
339 struct bufdesc_ex *ebdp;
340 int nr_frags = skb_shinfo(skb)->nr_frags;
341 int frag, frag_len;
342 unsigned short status;
343 unsigned int estatus = 0;
344 skb_frag_t *this_frag;
345 unsigned int index;
346 void *bufaddr;
347 dma_addr_t addr;
348 int i;
349
350 for (frag = 0; frag < nr_frags; frag++) {
351 this_frag = &skb_shinfo(skb)->frags[frag];
352 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
353 ebdp = (struct bufdesc_ex *)bdp;
354
355 status = fec16_to_cpu(bdp->cbd_sc);
356 status &= ~BD_ENET_TX_STATS;
357 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
358 frag_len = skb_shinfo(skb)->frags[frag].size;
359
360 /* Handle the last BD specially */
361 if (frag == nr_frags - 1) {
362 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
363 if (fep->bufdesc_ex) {
364 estatus |= BD_ENET_TX_INT;
365 if (unlikely(skb_shinfo(skb)->tx_flags &
366 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
367 estatus |= BD_ENET_TX_TS;
368 }
369 }
370
371 if (fep->bufdesc_ex) {
372 if (fep->quirks & FEC_QUIRK_HAS_AVB)
373 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
374 if (skb->ip_summed == CHECKSUM_PARTIAL)
375 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
376 ebdp->cbd_bdu = 0;
377 ebdp->cbd_esc = cpu_to_fec32(estatus);
378 }
379
380 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
381
382 index = fec_enet_get_bd_index(bdp, &txq->bd);
383 if (((unsigned long) bufaddr) & fep->tx_align ||
384 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
385 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
386 bufaddr = txq->tx_bounce[index];
387
388 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
389 swap_buffer(bufaddr, frag_len);
390 }
391
392 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
393 DMA_TO_DEVICE);
394 if (dma_mapping_error(&fep->pdev->dev, addr)) {
395 if (net_ratelimit())
396 netdev_err(ndev, "Tx DMA memory map failed\n");
397 goto dma_mapping_error;
398 }
399
400 bdp->cbd_bufaddr = cpu_to_fec32(addr);
401 bdp->cbd_datlen = cpu_to_fec16(frag_len);
402 /* Make sure the updates to rest of the descriptor are
403 * performed before transferring ownership.
404 */
405 wmb();
406 bdp->cbd_sc = cpu_to_fec16(status);
407 }
408
409 return bdp;
410dma_mapping_error:
411 bdp = txq->bd.cur;
412 for (i = 0; i < frag; i++) {
413 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
414 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
415 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
416 }
417 return ERR_PTR(-ENOMEM);
418}
419
420static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
421 struct sk_buff *skb, struct net_device *ndev)
422{
423 struct fec_enet_private *fep = netdev_priv(ndev);
424 int nr_frags = skb_shinfo(skb)->nr_frags;
425 struct bufdesc *bdp, *last_bdp;
426 void *bufaddr;
427 dma_addr_t addr;
428 unsigned short status;
429 unsigned short buflen;
430 unsigned int estatus = 0;
431 unsigned int index;
432 int entries_free;
433
434 entries_free = fec_enet_get_free_txdesc_num(txq);
435 if (entries_free < MAX_SKB_FRAGS + 1) {
436 dev_kfree_skb_any(skb);
437 if (net_ratelimit())
438 netdev_err(ndev, "NOT enough BD for SG!\n");
439 return NETDEV_TX_OK;
440 }
441
442 /* Protocol checksum off-load for TCP and UDP. */
443 if (fec_enet_clear_csum(skb, ndev)) {
444 dev_kfree_skb_any(skb);
445 return NETDEV_TX_OK;
446 }
447
448 /* Fill in a Tx ring entry */
449 bdp = txq->bd.cur;
450 last_bdp = bdp;
451 status = fec16_to_cpu(bdp->cbd_sc);
452 status &= ~BD_ENET_TX_STATS;
453
454 /* Set buffer length and buffer pointer */
455 bufaddr = skb->data;
456 buflen = skb_headlen(skb);
457
458 index = fec_enet_get_bd_index(bdp, &txq->bd);
459 if (((unsigned long) bufaddr) & fep->tx_align ||
460 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
461 memcpy(txq->tx_bounce[index], skb->data, buflen);
462 bufaddr = txq->tx_bounce[index];
463
464 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
465 swap_buffer(bufaddr, buflen);
466 }
467
468 /* Push the data cache so the CPM does not get stale memory data. */
469 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
470 if (dma_mapping_error(&fep->pdev->dev, addr)) {
471 dev_kfree_skb_any(skb);
472 if (net_ratelimit())
473 netdev_err(ndev, "Tx DMA memory map failed\n");
474 return NETDEV_TX_OK;
475 }
476
477 if (nr_frags) {
478 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
479 if (IS_ERR(last_bdp)) {
480 dma_unmap_single(&fep->pdev->dev, addr,
481 buflen, DMA_TO_DEVICE);
482 dev_kfree_skb_any(skb);
483 return NETDEV_TX_OK;
484 }
485 } else {
486 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
487 if (fep->bufdesc_ex) {
488 estatus = BD_ENET_TX_INT;
489 if (unlikely(skb_shinfo(skb)->tx_flags &
490 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
491 estatus |= BD_ENET_TX_TS;
492 }
493 }
494 bdp->cbd_bufaddr = cpu_to_fec32(addr);
495 bdp->cbd_datlen = cpu_to_fec16(buflen);
496
497 if (fep->bufdesc_ex) {
498
499 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
500
501 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
502 fep->hwts_tx_en))
503 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
504
505 if (fep->quirks & FEC_QUIRK_HAS_AVB)
506 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
507
508 if (skb->ip_summed == CHECKSUM_PARTIAL)
509 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
510
511 ebdp->cbd_bdu = 0;
512 ebdp->cbd_esc = cpu_to_fec32(estatus);
513 }
514
515 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
516 /* Save skb pointer */
517 txq->tx_skbuff[index] = skb;
518
519 /* Make sure the updates to rest of the descriptor are performed before
520 * transferring ownership.
521 */
522 wmb();
523
524 /* Send it on its way. Tell FEC it's ready, interrupt when done,
525 * it's the last BD of the frame, and to put the CRC on the end.
526 */
527 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
528 bdp->cbd_sc = cpu_to_fec16(status);
529
530 /* If this was the last BD in the ring, start at the beginning again. */
531 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
532
533 skb_tx_timestamp(skb);
534
535 /* Make sure the update to bdp and tx_skbuff are performed before
536 * txq->bd.cur.
537 */
538 wmb();
539 txq->bd.cur = bdp;
540
541 /* Trigger transmission start */
542 writel(0, txq->bd.reg_desc_active);
543
544 return 0;
545}
546
547static int
548fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
549 struct net_device *ndev,
550 struct bufdesc *bdp, int index, char *data,
551 int size, bool last_tcp, bool is_last)
552{
553 struct fec_enet_private *fep = netdev_priv(ndev);
554 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
555 unsigned short status;
556 unsigned int estatus = 0;
557 dma_addr_t addr;
558
559 status = fec16_to_cpu(bdp->cbd_sc);
560 status &= ~BD_ENET_TX_STATS;
561
562 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
563
564 if (((unsigned long) data) & fep->tx_align ||
565 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
566 memcpy(txq->tx_bounce[index], data, size);
567 data = txq->tx_bounce[index];
568
569 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
570 swap_buffer(data, size);
571 }
572
573 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
574 if (dma_mapping_error(&fep->pdev->dev, addr)) {
575 dev_kfree_skb_any(skb);
576 if (net_ratelimit())
577 netdev_err(ndev, "Tx DMA memory map failed\n");
578 return NETDEV_TX_BUSY;
579 }
580
581 bdp->cbd_datlen = cpu_to_fec16(size);
582 bdp->cbd_bufaddr = cpu_to_fec32(addr);
583
584 if (fep->bufdesc_ex) {
585 if (fep->quirks & FEC_QUIRK_HAS_AVB)
586 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
587 if (skb->ip_summed == CHECKSUM_PARTIAL)
588 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
589 ebdp->cbd_bdu = 0;
590 ebdp->cbd_esc = cpu_to_fec32(estatus);
591 }
592
593 /* Handle the last BD specially */
594 if (last_tcp)
595 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
596 if (is_last) {
597 status |= BD_ENET_TX_INTR;
598 if (fep->bufdesc_ex)
599 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
600 }
601
602 bdp->cbd_sc = cpu_to_fec16(status);
603
604 return 0;
605}
606
607static int
608fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
609 struct sk_buff *skb, struct net_device *ndev,
610 struct bufdesc *bdp, int index)
611{
612 struct fec_enet_private *fep = netdev_priv(ndev);
613 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
614 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
615 void *bufaddr;
616 unsigned long dmabuf;
617 unsigned short status;
618 unsigned int estatus = 0;
619
620 status = fec16_to_cpu(bdp->cbd_sc);
621 status &= ~BD_ENET_TX_STATS;
622 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
623
624 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
625 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
626 if (((unsigned long)bufaddr) & fep->tx_align ||
627 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
628 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
629 bufaddr = txq->tx_bounce[index];
630
631 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
632 swap_buffer(bufaddr, hdr_len);
633
634 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
635 hdr_len, DMA_TO_DEVICE);
636 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
637 dev_kfree_skb_any(skb);
638 if (net_ratelimit())
639 netdev_err(ndev, "Tx DMA memory map failed\n");
640 return NETDEV_TX_BUSY;
641 }
642 }
643
644 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
645 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
646
647 if (fep->bufdesc_ex) {
648 if (fep->quirks & FEC_QUIRK_HAS_AVB)
649 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
650 if (skb->ip_summed == CHECKSUM_PARTIAL)
651 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
652 ebdp->cbd_bdu = 0;
653 ebdp->cbd_esc = cpu_to_fec32(estatus);
654 }
655
656 bdp->cbd_sc = cpu_to_fec16(status);
657
658 return 0;
659}
660
661static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
662 struct sk_buff *skb,
663 struct net_device *ndev)
664{
665 struct fec_enet_private *fep = netdev_priv(ndev);
666 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
667 int total_len, data_left;
668 struct bufdesc *bdp = txq->bd.cur;
669 struct tso_t tso;
670 unsigned int index = 0;
671 int ret;
672
673 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
674 dev_kfree_skb_any(skb);
675 if (net_ratelimit())
676 netdev_err(ndev, "NOT enough BD for TSO!\n");
677 return NETDEV_TX_OK;
678 }
679
680 /* Protocol checksum off-load for TCP and UDP. */
681 if (fec_enet_clear_csum(skb, ndev)) {
682 dev_kfree_skb_any(skb);
683 return NETDEV_TX_OK;
684 }
685
686 /* Initialize the TSO handler, and prepare the first payload */
687 tso_start(skb, &tso);
688
689 total_len = skb->len - hdr_len;
690 while (total_len > 0) {
691 char *hdr;
692
693 index = fec_enet_get_bd_index(bdp, &txq->bd);
694 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
695 total_len -= data_left;
696
697 /* prepare packet headers: MAC + IP + TCP */
698 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
699 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
700 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
701 if (ret)
702 goto err_release;
703
704 while (data_left > 0) {
705 int size;
706
707 size = min_t(int, tso.size, data_left);
708 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
709 index = fec_enet_get_bd_index(bdp, &txq->bd);
710 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
711 bdp, index,
712 tso.data, size,
713 size == data_left,
714 total_len == 0);
715 if (ret)
716 goto err_release;
717
718 data_left -= size;
719 tso_build_data(skb, &tso, size);
720 }
721
722 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
723 }
724
725 /* Save skb pointer */
726 txq->tx_skbuff[index] = skb;
727
728 skb_tx_timestamp(skb);
729 txq->bd.cur = bdp;
730
731 /* Trigger transmission start */
732 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
733 !readl(txq->bd.reg_desc_active) ||
734 !readl(txq->bd.reg_desc_active) ||
735 !readl(txq->bd.reg_desc_active) ||
736 !readl(txq->bd.reg_desc_active))
737 writel(0, txq->bd.reg_desc_active);
738
739 return 0;
740
741err_release:
742 /* TODO: Release all used data descriptors for TSO */
743 return ret;
744}
745
746static netdev_tx_t
747fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
748{
749 struct fec_enet_private *fep = netdev_priv(ndev);
750 int entries_free;
751 unsigned short queue;
752 struct fec_enet_priv_tx_q *txq;
753 struct netdev_queue *nq;
754 int ret;
755
756 queue = skb_get_queue_mapping(skb);
757 txq = fep->tx_queue[queue];
758 nq = netdev_get_tx_queue(ndev, queue);
759
760 if (skb_is_gso(skb))
761 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
762 else
763 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
764 if (ret)
765 return ret;
766
767 entries_free = fec_enet_get_free_txdesc_num(txq);
768 if (entries_free <= txq->tx_stop_threshold)
769 netif_tx_stop_queue(nq);
770
771 return NETDEV_TX_OK;
772}
773
774/* Init RX & TX buffer descriptors
775 */
776static void fec_enet_bd_init(struct net_device *dev)
777{
778 struct fec_enet_private *fep = netdev_priv(dev);
779 struct fec_enet_priv_tx_q *txq;
780 struct fec_enet_priv_rx_q *rxq;
781 struct bufdesc *bdp;
782 unsigned int i;
783 unsigned int q;
784
785 for (q = 0; q < fep->num_rx_queues; q++) {
786 /* Initialize the receive buffer descriptors. */
787 rxq = fep->rx_queue[q];
788 bdp = rxq->bd.base;
789
790 for (i = 0; i < rxq->bd.ring_size; i++) {
791
792 /* Initialize the BD for every fragment in the page. */
793 if (bdp->cbd_bufaddr)
794 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
795 else
796 bdp->cbd_sc = cpu_to_fec16(0);
797 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
798 }
799
800 /* Set the last buffer to wrap */
801 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
802 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
803
804 rxq->bd.cur = rxq->bd.base;
805 }
806
807 for (q = 0; q < fep->num_tx_queues; q++) {
808 /* ...and the same for transmit */
809 txq = fep->tx_queue[q];
810 bdp = txq->bd.base;
811 txq->bd.cur = bdp;
812
813 for (i = 0; i < txq->bd.ring_size; i++) {
814 /* Initialize the BD for every fragment in the page. */
815 bdp->cbd_sc = cpu_to_fec16(0);
816 if (txq->tx_skbuff[i]) {
817 dev_kfree_skb_any(txq->tx_skbuff[i]);
818 txq->tx_skbuff[i] = NULL;
819 }
820 bdp->cbd_bufaddr = cpu_to_fec32(0);
821 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
822 }
823
824 /* Set the last buffer to wrap */
825 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
826 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
827 txq->dirty_tx = bdp;
828 }
829}
830
831static void fec_enet_active_rxring(struct net_device *ndev)
832{
833 struct fec_enet_private *fep = netdev_priv(ndev);
834 int i;
835
836 for (i = 0; i < fep->num_rx_queues; i++)
837 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
838}
839
840static void fec_enet_enable_ring(struct net_device *ndev)
841{
842 struct fec_enet_private *fep = netdev_priv(ndev);
843 struct fec_enet_priv_tx_q *txq;
844 struct fec_enet_priv_rx_q *rxq;
845 int i;
846
847 for (i = 0; i < fep->num_rx_queues; i++) {
848 rxq = fep->rx_queue[i];
849 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
850 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
851
852 /* enable DMA1/2 */
853 if (i)
854 writel(RCMR_MATCHEN | RCMR_CMP(i),
855 fep->hwp + FEC_RCMR(i));
856 }
857
858 for (i = 0; i < fep->num_tx_queues; i++) {
859 txq = fep->tx_queue[i];
860 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
861
862 /* enable DMA1/2 */
863 if (i)
864 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
865 fep->hwp + FEC_DMA_CFG(i));
866 }
867}
868
869static void fec_enet_reset_skb(struct net_device *ndev)
870{
871 struct fec_enet_private *fep = netdev_priv(ndev);
872 struct fec_enet_priv_tx_q *txq;
873 int i, j;
874
875 for (i = 0; i < fep->num_tx_queues; i++) {
876 txq = fep->tx_queue[i];
877
878 for (j = 0; j < txq->bd.ring_size; j++) {
879 if (txq->tx_skbuff[j]) {
880 dev_kfree_skb_any(txq->tx_skbuff[j]);
881 txq->tx_skbuff[j] = NULL;
882 }
883 }
884 }
885}
886
887/*
888 * This function is called to start or restart the FEC during a link
889 * change, transmit timeout, or to reconfigure the FEC. The network
890 * packet processing for this device must be stopped before this call.
891 */
892static void
893fec_restart(struct net_device *ndev)
894{
895 struct fec_enet_private *fep = netdev_priv(ndev);
896 u32 val;
897 u32 temp_mac[2];
898 u32 rcntl = OPT_FRAME_SIZE | 0x04;
899 u32 ecntl = 0x2; /* ETHEREN */
900
901 /* Whack a reset. We should wait for this.
902 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
903 * instead of reset MAC itself.
904 */
905 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
906 writel(0, fep->hwp + FEC_ECNTRL);
907 } else {
908 writel(1, fep->hwp + FEC_ECNTRL);
909 udelay(10);
910 }
911
912 /*
913 * enet-mac reset will reset mac address registers too,
914 * so need to reconfigure it.
915 */
916 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
917 writel((__force u32)cpu_to_be32(temp_mac[0]),
918 fep->hwp + FEC_ADDR_LOW);
919 writel((__force u32)cpu_to_be32(temp_mac[1]),
920 fep->hwp + FEC_ADDR_HIGH);
921
922 /* Clear any outstanding interrupt. */
923 writel(0xffffffff, fep->hwp + FEC_IEVENT);
924
925 fec_enet_bd_init(ndev);
926
927 fec_enet_enable_ring(ndev);
928
929 /* Reset tx SKB buffers. */
930 fec_enet_reset_skb(ndev);
931
932 /* Enable MII mode */
933 if (fep->full_duplex == DUPLEX_FULL) {
934 /* FD enable */
935 writel(0x04, fep->hwp + FEC_X_CNTRL);
936 } else {
937 /* No Rcv on Xmit */
938 rcntl |= 0x02;
939 writel(0x0, fep->hwp + FEC_X_CNTRL);
940 }
941
942 /* Set MII speed */
943 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
944
945#if !defined(CONFIG_M5272)
946 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
947 val = readl(fep->hwp + FEC_RACC);
948 /* align IP header */
949 val |= FEC_RACC_SHIFT16;
950 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
951 /* set RX checksum */
952 val |= FEC_RACC_OPTIONS;
953 else
954 val &= ~FEC_RACC_OPTIONS;
955 writel(val, fep->hwp + FEC_RACC);
956 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
957 }
958#endif
959
960 /*
961 * The phy interface and speed need to get configured
962 * differently on enet-mac.
963 */
964 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
965 /* Enable flow control and length check */
966 rcntl |= 0x40000000 | 0x00000020;
967
968 /* RGMII, RMII or MII */
969 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
970 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
971 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
972 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
973 rcntl |= (1 << 6);
974 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
975 rcntl |= (1 << 8);
976 else
977 rcntl &= ~(1 << 8);
978
979 /* 1G, 100M or 10M */
980 if (ndev->phydev) {
981 if (ndev->phydev->speed == SPEED_1000)
982 ecntl |= (1 << 5);
983 else if (ndev->phydev->speed == SPEED_100)
984 rcntl &= ~(1 << 9);
985 else
986 rcntl |= (1 << 9);
987 }
988 } else {
989#ifdef FEC_MIIGSK_ENR
990 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
991 u32 cfgr;
992 /* disable the gasket and wait */
993 writel(0, fep->hwp + FEC_MIIGSK_ENR);
994 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
995 udelay(1);
996
997 /*
998 * configure the gasket:
999 * RMII, 50 MHz, no loopback, no echo
1000 * MII, 25 MHz, no loopback, no echo
1001 */
1002 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1003 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1004 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1005 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1006 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1007
1008 /* re-enable the gasket */
1009 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1010 }
1011#endif
1012 }
1013
1014#if !defined(CONFIG_M5272)
1015 /* enable pause frame*/
1016 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1017 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1018 ndev->phydev && ndev->phydev->pause)) {
1019 rcntl |= FEC_ENET_FCE;
1020
1021 /* set FIFO threshold parameter to reduce overrun */
1022 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1023 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1024 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1025 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1026
1027 /* OPD */
1028 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1029 } else {
1030 rcntl &= ~FEC_ENET_FCE;
1031 }
1032#endif /* !defined(CONFIG_M5272) */
1033
1034 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1035
1036 /* Setup multicast filter. */
1037 set_multicast_list(ndev);
1038#ifndef CONFIG_M5272
1039 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1040 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1041#endif
1042
1043 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1044 /* enable ENET endian swap */
1045 ecntl |= (1 << 8);
1046 /* enable ENET store and forward mode */
1047 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1048 }
1049
1050 if (fep->bufdesc_ex)
1051 ecntl |= (1 << 4);
1052
1053#ifndef CONFIG_M5272
1054 /* Enable the MIB statistic event counters */
1055 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1056#endif
1057
1058 /* And last, enable the transmit and receive processing */
1059 writel(ecntl, fep->hwp + FEC_ECNTRL);
1060 fec_enet_active_rxring(ndev);
1061
1062 if (fep->bufdesc_ex)
1063 fec_ptp_start_cyclecounter(ndev);
1064
1065 /* Enable interrupts we wish to service */
1066 if (fep->link)
1067 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1068 else
1069 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1070
1071 /* Init the interrupt coalescing */
1072 fec_enet_itr_coal_init(ndev);
1073
1074}
1075
1076static void
1077fec_stop(struct net_device *ndev)
1078{
1079 struct fec_enet_private *fep = netdev_priv(ndev);
1080 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1081 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1082 u32 val;
1083
1084 /* We cannot expect a graceful transmit stop without link !!! */
1085 if (fep->link) {
1086 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1087 udelay(10);
1088 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1089 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1090 }
1091
1092 /* Whack a reset. We should wait for this.
1093 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1094 * instead of reset MAC itself.
1095 */
1096 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1097 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1098 writel(0, fep->hwp + FEC_ECNTRL);
1099 } else {
1100 writel(1, fep->hwp + FEC_ECNTRL);
1101 udelay(10);
1102 }
1103 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1104 } else {
1105 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1106 val = readl(fep->hwp + FEC_ECNTRL);
1107 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1108 writel(val, fep->hwp + FEC_ECNTRL);
1109
1110 if (pdata && pdata->sleep_mode_enable)
1111 pdata->sleep_mode_enable(true);
1112 }
1113 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1114
1115 /* We have to keep ENET enabled to have MII interrupt stay working */
1116 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1117 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1118 writel(2, fep->hwp + FEC_ECNTRL);
1119 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1120 }
1121}
1122
1123
1124static void
1125fec_timeout(struct net_device *ndev)
1126{
1127 struct fec_enet_private *fep = netdev_priv(ndev);
1128
1129 fec_dump(ndev);
1130
1131 ndev->stats.tx_errors++;
1132
1133 schedule_work(&fep->tx_timeout_work);
1134}
1135
1136static void fec_enet_timeout_work(struct work_struct *work)
1137{
1138 struct fec_enet_private *fep =
1139 container_of(work, struct fec_enet_private, tx_timeout_work);
1140 struct net_device *ndev = fep->netdev;
1141
1142 rtnl_lock();
1143 if (netif_device_present(ndev) || netif_running(ndev)) {
1144 napi_disable(&fep->napi);
1145 netif_tx_lock_bh(ndev);
1146 fec_restart(ndev);
1147 netif_wake_queue(ndev);
1148 netif_tx_unlock_bh(ndev);
1149 napi_enable(&fep->napi);
1150 }
1151 rtnl_unlock();
1152}
1153
1154static void
1155fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1156 struct skb_shared_hwtstamps *hwtstamps)
1157{
1158 unsigned long flags;
1159 u64 ns;
1160
1161 spin_lock_irqsave(&fep->tmreg_lock, flags);
1162 ns = timecounter_cyc2time(&fep->tc, ts);
1163 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1164
1165 memset(hwtstamps, 0, sizeof(*hwtstamps));
1166 hwtstamps->hwtstamp = ns_to_ktime(ns);
1167}
1168
1169static void
1170fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1171{
1172 struct fec_enet_private *fep;
1173 struct bufdesc *bdp;
1174 unsigned short status;
1175 struct sk_buff *skb;
1176 struct fec_enet_priv_tx_q *txq;
1177 struct netdev_queue *nq;
1178 int index = 0;
1179 int entries_free;
1180
1181 fep = netdev_priv(ndev);
1182
1183 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1184
1185 txq = fep->tx_queue[queue_id];
1186 /* get next bdp of dirty_tx */
1187 nq = netdev_get_tx_queue(ndev, queue_id);
1188 bdp = txq->dirty_tx;
1189
1190 /* get next bdp of dirty_tx */
1191 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1192
1193 while (bdp != READ_ONCE(txq->bd.cur)) {
1194 /* Order the load of bd.cur and cbd_sc */
1195 rmb();
1196 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1197 if (status & BD_ENET_TX_READY)
1198 break;
1199
1200 index = fec_enet_get_bd_index(bdp, &txq->bd);
1201
1202 skb = txq->tx_skbuff[index];
1203 txq->tx_skbuff[index] = NULL;
1204 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1205 dma_unmap_single(&fep->pdev->dev,
1206 fec32_to_cpu(bdp->cbd_bufaddr),
1207 fec16_to_cpu(bdp->cbd_datlen),
1208 DMA_TO_DEVICE);
1209 bdp->cbd_bufaddr = cpu_to_fec32(0);
1210 if (!skb)
1211 goto skb_done;
1212
1213 /* Check for errors. */
1214 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1215 BD_ENET_TX_RL | BD_ENET_TX_UN |
1216 BD_ENET_TX_CSL)) {
1217 ndev->stats.tx_errors++;
1218 if (status & BD_ENET_TX_HB) /* No heartbeat */
1219 ndev->stats.tx_heartbeat_errors++;
1220 if (status & BD_ENET_TX_LC) /* Late collision */
1221 ndev->stats.tx_window_errors++;
1222 if (status & BD_ENET_TX_RL) /* Retrans limit */
1223 ndev->stats.tx_aborted_errors++;
1224 if (status & BD_ENET_TX_UN) /* Underrun */
1225 ndev->stats.tx_fifo_errors++;
1226 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1227 ndev->stats.tx_carrier_errors++;
1228 } else {
1229 ndev->stats.tx_packets++;
1230 ndev->stats.tx_bytes += skb->len;
1231 }
1232
1233 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1234 fep->bufdesc_ex) {
1235 struct skb_shared_hwtstamps shhwtstamps;
1236 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1237
1238 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1239 skb_tstamp_tx(skb, &shhwtstamps);
1240 }
1241
1242 /* Deferred means some collisions occurred during transmit,
1243 * but we eventually sent the packet OK.
1244 */
1245 if (status & BD_ENET_TX_DEF)
1246 ndev->stats.collisions++;
1247
1248 /* Free the sk buffer associated with this last transmit */
1249 dev_kfree_skb_any(skb);
1250skb_done:
1251 /* Make sure the update to bdp and tx_skbuff are performed
1252 * before dirty_tx
1253 */
1254 wmb();
1255 txq->dirty_tx = bdp;
1256
1257 /* Update pointer to next buffer descriptor to be transmitted */
1258 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1259
1260 /* Since we have freed up a buffer, the ring is no longer full
1261 */
1262 if (netif_queue_stopped(ndev)) {
1263 entries_free = fec_enet_get_free_txdesc_num(txq);
1264 if (entries_free >= txq->tx_wake_threshold)
1265 netif_tx_wake_queue(nq);
1266 }
1267 }
1268
1269 /* ERR006538: Keep the transmitter going */
1270 if (bdp != txq->bd.cur &&
1271 readl(txq->bd.reg_desc_active) == 0)
1272 writel(0, txq->bd.reg_desc_active);
1273}
1274
1275static void
1276fec_enet_tx(struct net_device *ndev)
1277{
1278 struct fec_enet_private *fep = netdev_priv(ndev);
1279 u16 queue_id;
1280 /* First process class A queue, then Class B and Best Effort queue */
1281 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1282 clear_bit(queue_id, &fep->work_tx);
1283 fec_enet_tx_queue(ndev, queue_id);
1284 }
1285 return;
1286}
1287
1288static int
1289fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1290{
1291 struct fec_enet_private *fep = netdev_priv(ndev);
1292 int off;
1293
1294 off = ((unsigned long)skb->data) & fep->rx_align;
1295 if (off)
1296 skb_reserve(skb, fep->rx_align + 1 - off);
1297
1298 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1299 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1300 if (net_ratelimit())
1301 netdev_err(ndev, "Rx DMA memory map failed\n");
1302 return -ENOMEM;
1303 }
1304
1305 return 0;
1306}
1307
1308static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1309 struct bufdesc *bdp, u32 length, bool swap)
1310{
1311 struct fec_enet_private *fep = netdev_priv(ndev);
1312 struct sk_buff *new_skb;
1313
1314 if (length > fep->rx_copybreak)
1315 return false;
1316
1317 new_skb = netdev_alloc_skb(ndev, length);
1318 if (!new_skb)
1319 return false;
1320
1321 dma_sync_single_for_cpu(&fep->pdev->dev,
1322 fec32_to_cpu(bdp->cbd_bufaddr),
1323 FEC_ENET_RX_FRSIZE - fep->rx_align,
1324 DMA_FROM_DEVICE);
1325 if (!swap)
1326 memcpy(new_skb->data, (*skb)->data, length);
1327 else
1328 swap_buffer2(new_skb->data, (*skb)->data, length);
1329 *skb = new_skb;
1330
1331 return true;
1332}
1333
1334/* During a receive, the bd_rx.cur points to the current incoming buffer.
1335 * When we update through the ring, if the next incoming buffer has
1336 * not been given to the system, we just set the empty indicator,
1337 * effectively tossing the packet.
1338 */
1339static int
1340fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1341{
1342 struct fec_enet_private *fep = netdev_priv(ndev);
1343 struct fec_enet_priv_rx_q *rxq;
1344 struct bufdesc *bdp;
1345 unsigned short status;
1346 struct sk_buff *skb_new = NULL;
1347 struct sk_buff *skb;
1348 ushort pkt_len;
1349 __u8 *data;
1350 int pkt_received = 0;
1351 struct bufdesc_ex *ebdp = NULL;
1352 bool vlan_packet_rcvd = false;
1353 u16 vlan_tag;
1354 int index = 0;
1355 bool is_copybreak;
1356 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1357
1358#ifdef CONFIG_M532x
1359 flush_cache_all();
1360#endif
1361 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1362 rxq = fep->rx_queue[queue_id];
1363
1364 /* First, grab all of the stats for the incoming packet.
1365 * These get messed up if we get called due to a busy condition.
1366 */
1367 bdp = rxq->bd.cur;
1368
1369 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1370
1371 if (pkt_received >= budget)
1372 break;
1373 pkt_received++;
1374
1375 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
1376
1377 /* Check for errors. */
1378 status ^= BD_ENET_RX_LAST;
1379 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1380 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1381 BD_ENET_RX_CL)) {
1382 ndev->stats.rx_errors++;
1383 if (status & BD_ENET_RX_OV) {
1384 /* FIFO overrun */
1385 ndev->stats.rx_fifo_errors++;
1386 goto rx_processing_done;
1387 }
1388 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1389 | BD_ENET_RX_LAST)) {
1390 /* Frame too long or too short. */
1391 ndev->stats.rx_length_errors++;
1392 if (status & BD_ENET_RX_LAST)
1393 netdev_err(ndev, "rcv is not +last\n");
1394 }
1395 if (status & BD_ENET_RX_CR) /* CRC Error */
1396 ndev->stats.rx_crc_errors++;
1397 /* Report late collisions as a frame error. */
1398 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1399 ndev->stats.rx_frame_errors++;
1400 goto rx_processing_done;
1401 }
1402
1403 /* Process the incoming frame. */
1404 ndev->stats.rx_packets++;
1405 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1406 ndev->stats.rx_bytes += pkt_len;
1407
1408 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1409 skb = rxq->rx_skbuff[index];
1410
1411 /* The packet length includes FCS, but we don't want to
1412 * include that when passing upstream as it messes up
1413 * bridging applications.
1414 */
1415 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1416 need_swap);
1417 if (!is_copybreak) {
1418 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1419 if (unlikely(!skb_new)) {
1420 ndev->stats.rx_dropped++;
1421 goto rx_processing_done;
1422 }
1423 dma_unmap_single(&fep->pdev->dev,
1424 fec32_to_cpu(bdp->cbd_bufaddr),
1425 FEC_ENET_RX_FRSIZE - fep->rx_align,
1426 DMA_FROM_DEVICE);
1427 }
1428
1429 prefetch(skb->data - NET_IP_ALIGN);
1430 skb_put(skb, pkt_len - 4);
1431 data = skb->data;
1432
1433 if (!is_copybreak && need_swap)
1434 swap_buffer(data, pkt_len);
1435
1436#if !defined(CONFIG_M5272)
1437 if (fep->quirks & FEC_QUIRK_HAS_RACC)
1438 data = skb_pull_inline(skb, 2);
1439#endif
1440
1441 /* Extract the enhanced buffer descriptor */
1442 ebdp = NULL;
1443 if (fep->bufdesc_ex)
1444 ebdp = (struct bufdesc_ex *)bdp;
1445
1446 /* If this is a VLAN packet remove the VLAN Tag */
1447 vlan_packet_rcvd = false;
1448 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1449 fep->bufdesc_ex &&
1450 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1451 /* Push and remove the vlan tag */
1452 struct vlan_hdr *vlan_header =
1453 (struct vlan_hdr *) (data + ETH_HLEN);
1454 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1455
1456 vlan_packet_rcvd = true;
1457
1458 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1459 skb_pull(skb, VLAN_HLEN);
1460 }
1461
1462 skb->protocol = eth_type_trans(skb, ndev);
1463
1464 /* Get receive timestamp from the skb */
1465 if (fep->hwts_rx_en && fep->bufdesc_ex)
1466 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1467 skb_hwtstamps(skb));
1468
1469 if (fep->bufdesc_ex &&
1470 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1471 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1472 /* don't check it */
1473 skb->ip_summed = CHECKSUM_UNNECESSARY;
1474 } else {
1475 skb_checksum_none_assert(skb);
1476 }
1477 }
1478
1479 /* Handle received VLAN packets */
1480 if (vlan_packet_rcvd)
1481 __vlan_hwaccel_put_tag(skb,
1482 htons(ETH_P_8021Q),
1483 vlan_tag);
1484
1485 napi_gro_receive(&fep->napi, skb);
1486
1487 if (is_copybreak) {
1488 dma_sync_single_for_device(&fep->pdev->dev,
1489 fec32_to_cpu(bdp->cbd_bufaddr),
1490 FEC_ENET_RX_FRSIZE - fep->rx_align,
1491 DMA_FROM_DEVICE);
1492 } else {
1493 rxq->rx_skbuff[index] = skb_new;
1494 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1495 }
1496
1497rx_processing_done:
1498 /* Clear the status flags for this buffer */
1499 status &= ~BD_ENET_RX_STATS;
1500
1501 /* Mark the buffer empty */
1502 status |= BD_ENET_RX_EMPTY;
1503
1504 if (fep->bufdesc_ex) {
1505 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1506
1507 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1508 ebdp->cbd_prot = 0;
1509 ebdp->cbd_bdu = 0;
1510 }
1511 /* Make sure the updates to rest of the descriptor are
1512 * performed before transferring ownership.
1513 */
1514 wmb();
1515 bdp->cbd_sc = cpu_to_fec16(status);
1516
1517 /* Update BD pointer to next entry */
1518 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1519
1520 /* Doing this here will keep the FEC running while we process
1521 * incoming frames. On a heavily loaded network, we should be
1522 * able to keep up at the expense of system resources.
1523 */
1524 writel(0, rxq->bd.reg_desc_active);
1525 }
1526 rxq->bd.cur = bdp;
1527 return pkt_received;
1528}
1529
1530static int
1531fec_enet_rx(struct net_device *ndev, int budget)
1532{
1533 int pkt_received = 0;
1534 u16 queue_id;
1535 struct fec_enet_private *fep = netdev_priv(ndev);
1536
1537 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1538 int ret;
1539
1540 ret = fec_enet_rx_queue(ndev,
1541 budget - pkt_received, queue_id);
1542
1543 if (ret < budget - pkt_received)
1544 clear_bit(queue_id, &fep->work_rx);
1545
1546 pkt_received += ret;
1547 }
1548 return pkt_received;
1549}
1550
1551static bool
1552fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1553{
1554 if (int_events == 0)
1555 return false;
1556
1557 if (int_events & FEC_ENET_RXF)
1558 fep->work_rx |= (1 << 2);
1559 if (int_events & FEC_ENET_RXF_1)
1560 fep->work_rx |= (1 << 0);
1561 if (int_events & FEC_ENET_RXF_2)
1562 fep->work_rx |= (1 << 1);
1563
1564 if (int_events & FEC_ENET_TXF)
1565 fep->work_tx |= (1 << 2);
1566 if (int_events & FEC_ENET_TXF_1)
1567 fep->work_tx |= (1 << 0);
1568 if (int_events & FEC_ENET_TXF_2)
1569 fep->work_tx |= (1 << 1);
1570
1571 return true;
1572}
1573
1574static irqreturn_t
1575fec_enet_interrupt(int irq, void *dev_id)
1576{
1577 struct net_device *ndev = dev_id;
1578 struct fec_enet_private *fep = netdev_priv(ndev);
1579 uint int_events;
1580 irqreturn_t ret = IRQ_NONE;
1581
1582 int_events = readl(fep->hwp + FEC_IEVENT);
1583 writel(int_events, fep->hwp + FEC_IEVENT);
1584 fec_enet_collect_events(fep, int_events);
1585
1586 if ((fep->work_tx || fep->work_rx) && fep->link) {
1587 ret = IRQ_HANDLED;
1588
1589 if (napi_schedule_prep(&fep->napi)) {
1590 /* Disable the NAPI interrupts */
1591 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK);
1592 __napi_schedule(&fep->napi);
1593 }
1594 }
1595
1596 if (int_events & FEC_ENET_MII) {
1597 ret = IRQ_HANDLED;
1598 complete(&fep->mdio_done);
1599 }
1600
1601 if (fep->ptp_clock)
1602 fec_ptp_check_pps_event(fep);
1603
1604 return ret;
1605}
1606
1607static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1608{
1609 struct net_device *ndev = napi->dev;
1610 struct fec_enet_private *fep = netdev_priv(ndev);
1611 int pkts;
1612
1613 pkts = fec_enet_rx(ndev, budget);
1614
1615 fec_enet_tx(ndev);
1616
1617 if (pkts < budget) {
1618 napi_complete(napi);
1619 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1620 }
1621 return pkts;
1622}
1623
1624/* ------------------------------------------------------------------------- */
1625static void fec_get_mac(struct net_device *ndev)
1626{
1627 struct fec_enet_private *fep = netdev_priv(ndev);
1628 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1629 unsigned char *iap, tmpaddr[ETH_ALEN];
1630
1631 /*
1632 * try to get mac address in following order:
1633 *
1634 * 1) module parameter via kernel command line in form
1635 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1636 */
1637 iap = macaddr;
1638
1639 /*
1640 * 2) from device tree data
1641 */
1642 if (!is_valid_ether_addr(iap)) {
1643 struct device_node *np = fep->pdev->dev.of_node;
1644 if (np) {
1645 const char *mac = of_get_mac_address(np);
1646 if (mac)
1647 iap = (unsigned char *) mac;
1648 }
1649 }
1650
1651 /*
1652 * 3) from flash or fuse (via platform data)
1653 */
1654 if (!is_valid_ether_addr(iap)) {
1655#ifdef CONFIG_M5272
1656 if (FEC_FLASHMAC)
1657 iap = (unsigned char *)FEC_FLASHMAC;
1658#else
1659 if (pdata)
1660 iap = (unsigned char *)&pdata->mac;
1661#endif
1662 }
1663
1664 /*
1665 * 4) FEC mac registers set by bootloader
1666 */
1667 if (!is_valid_ether_addr(iap)) {
1668 *((__be32 *) &tmpaddr[0]) =
1669 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1670 *((__be16 *) &tmpaddr[4]) =
1671 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1672 iap = &tmpaddr[0];
1673 }
1674
1675 /*
1676 * 5) random mac address
1677 */
1678 if (!is_valid_ether_addr(iap)) {
1679 /* Report it and use a random ethernet address instead */
1680 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1681 eth_hw_addr_random(ndev);
1682 netdev_info(ndev, "Using random MAC address: %pM\n",
1683 ndev->dev_addr);
1684 return;
1685 }
1686
1687 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1688
1689 /* Adjust MAC if using macaddr */
1690 if (iap == macaddr)
1691 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1692}
1693
1694/* ------------------------------------------------------------------------- */
1695
1696/*
1697 * Phy section
1698 */
1699static void fec_enet_adjust_link(struct net_device *ndev)
1700{
1701 struct fec_enet_private *fep = netdev_priv(ndev);
1702 struct phy_device *phy_dev = ndev->phydev;
1703 int status_change = 0;
1704
1705 /* Prevent a state halted on mii error */
1706 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1707 phy_dev->state = PHY_RESUMING;
1708 return;
1709 }
1710
1711 /*
1712 * If the netdev is down, or is going down, we're not interested
1713 * in link state events, so just mark our idea of the link as down
1714 * and ignore the event.
1715 */
1716 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1717 fep->link = 0;
1718 } else if (phy_dev->link) {
1719 if (!fep->link) {
1720 fep->link = phy_dev->link;
1721 status_change = 1;
1722 }
1723
1724 if (fep->full_duplex != phy_dev->duplex) {
1725 fep->full_duplex = phy_dev->duplex;
1726 status_change = 1;
1727 }
1728
1729 if (phy_dev->speed != fep->speed) {
1730 fep->speed = phy_dev->speed;
1731 status_change = 1;
1732 }
1733
1734 /* if any of the above changed restart the FEC */
1735 if (status_change) {
1736 napi_disable(&fep->napi);
1737 netif_tx_lock_bh(ndev);
1738 fec_restart(ndev);
1739 netif_wake_queue(ndev);
1740 netif_tx_unlock_bh(ndev);
1741 napi_enable(&fep->napi);
1742 }
1743 } else {
1744 if (fep->link) {
1745 napi_disable(&fep->napi);
1746 netif_tx_lock_bh(ndev);
1747 fec_stop(ndev);
1748 netif_tx_unlock_bh(ndev);
1749 napi_enable(&fep->napi);
1750 fep->link = phy_dev->link;
1751 status_change = 1;
1752 }
1753 }
1754
1755 if (status_change)
1756 phy_print_status(phy_dev);
1757}
1758
1759static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1760{
1761 struct fec_enet_private *fep = bus->priv;
1762 struct device *dev = &fep->pdev->dev;
1763 unsigned long time_left;
1764 int ret = 0;
1765
1766 ret = pm_runtime_get_sync(dev);
1767 if (ret < 0)
1768 return ret;
1769
1770 fep->mii_timeout = 0;
1771 reinit_completion(&fep->mdio_done);
1772
1773 /* start a read op */
1774 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1775 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1776 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1777
1778 /* wait for end of transfer */
1779 time_left = wait_for_completion_timeout(&fep->mdio_done,
1780 usecs_to_jiffies(FEC_MII_TIMEOUT));
1781 if (time_left == 0) {
1782 fep->mii_timeout = 1;
1783 netdev_err(fep->netdev, "MDIO read timeout\n");
1784 ret = -ETIMEDOUT;
1785 goto out;
1786 }
1787
1788 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1789
1790out:
1791 pm_runtime_mark_last_busy(dev);
1792 pm_runtime_put_autosuspend(dev);
1793
1794 return ret;
1795}
1796
1797static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1798 u16 value)
1799{
1800 struct fec_enet_private *fep = bus->priv;
1801 struct device *dev = &fep->pdev->dev;
1802 unsigned long time_left;
1803 int ret;
1804
1805 ret = pm_runtime_get_sync(dev);
1806 if (ret < 0)
1807 return ret;
1808 else
1809 ret = 0;
1810
1811 fep->mii_timeout = 0;
1812 reinit_completion(&fep->mdio_done);
1813
1814 /* start a write op */
1815 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1816 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1817 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1818 fep->hwp + FEC_MII_DATA);
1819
1820 /* wait for end of transfer */
1821 time_left = wait_for_completion_timeout(&fep->mdio_done,
1822 usecs_to_jiffies(FEC_MII_TIMEOUT));
1823 if (time_left == 0) {
1824 fep->mii_timeout = 1;
1825 netdev_err(fep->netdev, "MDIO write timeout\n");
1826 ret = -ETIMEDOUT;
1827 }
1828
1829 pm_runtime_mark_last_busy(dev);
1830 pm_runtime_put_autosuspend(dev);
1831
1832 return ret;
1833}
1834
1835static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1836{
1837 struct fec_enet_private *fep = netdev_priv(ndev);
1838 int ret;
1839
1840 if (enable) {
1841 ret = clk_prepare_enable(fep->clk_ahb);
1842 if (ret)
1843 return ret;
1844
1845 ret = clk_prepare_enable(fep->clk_enet_out);
1846 if (ret)
1847 goto failed_clk_enet_out;
1848
1849 if (fep->clk_ptp) {
1850 mutex_lock(&fep->ptp_clk_mutex);
1851 ret = clk_prepare_enable(fep->clk_ptp);
1852 if (ret) {
1853 mutex_unlock(&fep->ptp_clk_mutex);
1854 goto failed_clk_ptp;
1855 } else {
1856 fep->ptp_clk_on = true;
1857 }
1858 mutex_unlock(&fep->ptp_clk_mutex);
1859 }
1860
1861 ret = clk_prepare_enable(fep->clk_ref);
1862 if (ret)
1863 goto failed_clk_ref;
1864 } else {
1865 clk_disable_unprepare(fep->clk_ahb);
1866 clk_disable_unprepare(fep->clk_enet_out);
1867 if (fep->clk_ptp) {
1868 mutex_lock(&fep->ptp_clk_mutex);
1869 clk_disable_unprepare(fep->clk_ptp);
1870 fep->ptp_clk_on = false;
1871 mutex_unlock(&fep->ptp_clk_mutex);
1872 }
1873 clk_disable_unprepare(fep->clk_ref);
1874 }
1875
1876 return 0;
1877
1878failed_clk_ref:
1879 if (fep->clk_ref)
1880 clk_disable_unprepare(fep->clk_ref);
1881failed_clk_ptp:
1882 if (fep->clk_enet_out)
1883 clk_disable_unprepare(fep->clk_enet_out);
1884failed_clk_enet_out:
1885 clk_disable_unprepare(fep->clk_ahb);
1886
1887 return ret;
1888}
1889
1890static int fec_enet_mii_probe(struct net_device *ndev)
1891{
1892 struct fec_enet_private *fep = netdev_priv(ndev);
1893 struct phy_device *phy_dev = NULL;
1894 char mdio_bus_id[MII_BUS_ID_SIZE];
1895 char phy_name[MII_BUS_ID_SIZE + 3];
1896 int phy_id;
1897 int dev_id = fep->dev_id;
1898
1899 if (fep->phy_node) {
1900 phy_dev = of_phy_connect(ndev, fep->phy_node,
1901 &fec_enet_adjust_link, 0,
1902 fep->phy_interface);
1903 if (!phy_dev)
1904 return -ENODEV;
1905 } else {
1906 /* check for attached phy */
1907 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1908 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
1909 continue;
1910 if (dev_id--)
1911 continue;
1912 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1913 break;
1914 }
1915
1916 if (phy_id >= PHY_MAX_ADDR) {
1917 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1918 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1919 phy_id = 0;
1920 }
1921
1922 snprintf(phy_name, sizeof(phy_name),
1923 PHY_ID_FMT, mdio_bus_id, phy_id);
1924 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1925 fep->phy_interface);
1926 }
1927
1928 if (IS_ERR(phy_dev)) {
1929 netdev_err(ndev, "could not attach to PHY\n");
1930 return PTR_ERR(phy_dev);
1931 }
1932
1933 /* mask with MAC supported features */
1934 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1935 phy_dev->supported &= PHY_GBIT_FEATURES;
1936 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1937#if !defined(CONFIG_M5272)
1938 phy_dev->supported |= SUPPORTED_Pause;
1939#endif
1940 }
1941 else
1942 phy_dev->supported &= PHY_BASIC_FEATURES;
1943
1944 phy_dev->advertising = phy_dev->supported;
1945
1946 fep->link = 0;
1947 fep->full_duplex = 0;
1948
1949 phy_attached_info(phy_dev);
1950
1951 return 0;
1952}
1953
1954static int fec_enet_mii_init(struct platform_device *pdev)
1955{
1956 static struct mii_bus *fec0_mii_bus;
1957 struct net_device *ndev = platform_get_drvdata(pdev);
1958 struct fec_enet_private *fep = netdev_priv(ndev);
1959 struct device_node *node;
1960 int err = -ENXIO;
1961 u32 mii_speed, holdtime;
1962
1963 /*
1964 * The i.MX28 dual fec interfaces are not equal.
1965 * Here are the differences:
1966 *
1967 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1968 * - fec0 acts as the 1588 time master while fec1 is slave
1969 * - external phys can only be configured by fec0
1970 *
1971 * That is to say fec1 can not work independently. It only works
1972 * when fec0 is working. The reason behind this design is that the
1973 * second interface is added primarily for Switch mode.
1974 *
1975 * Because of the last point above, both phys are attached on fec0
1976 * mdio interface in board design, and need to be configured by
1977 * fec0 mii_bus.
1978 */
1979 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
1980 /* fec1 uses fec0 mii_bus */
1981 if (mii_cnt && fec0_mii_bus) {
1982 fep->mii_bus = fec0_mii_bus;
1983 mii_cnt++;
1984 return 0;
1985 }
1986 return -ENOENT;
1987 }
1988
1989 fep->mii_timeout = 0;
1990
1991 /*
1992 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1993 *
1994 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1995 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1996 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1997 * document.
1998 */
1999 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
2000 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2001 mii_speed--;
2002 if (mii_speed > 63) {
2003 dev_err(&pdev->dev,
2004 "fec clock (%lu) to fast to get right mii speed\n",
2005 clk_get_rate(fep->clk_ipg));
2006 err = -EINVAL;
2007 goto err_out;
2008 }
2009
2010 /*
2011 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2012 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2013 * versions are RAZ there, so just ignore the difference and write the
2014 * register always.
2015 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2016 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2017 * output.
2018 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2019 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2020 * holdtime cannot result in a value greater than 3.
2021 */
2022 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2023
2024 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2025
2026 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2027
2028 fep->mii_bus = mdiobus_alloc();
2029 if (fep->mii_bus == NULL) {
2030 err = -ENOMEM;
2031 goto err_out;
2032 }
2033
2034 fep->mii_bus->name = "fec_enet_mii_bus";
2035 fep->mii_bus->read = fec_enet_mdio_read;
2036 fep->mii_bus->write = fec_enet_mdio_write;
2037 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2038 pdev->name, fep->dev_id + 1);
2039 fep->mii_bus->priv = fep;
2040 fep->mii_bus->parent = &pdev->dev;
2041
2042 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2043 if (node) {
2044 err = of_mdiobus_register(fep->mii_bus, node);
2045 of_node_put(node);
2046 } else {
2047 err = mdiobus_register(fep->mii_bus);
2048 }
2049
2050 if (err)
2051 goto err_out_free_mdiobus;
2052
2053 mii_cnt++;
2054
2055 /* save fec0 mii_bus */
2056 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2057 fec0_mii_bus = fep->mii_bus;
2058
2059 return 0;
2060
2061err_out_free_mdiobus:
2062 mdiobus_free(fep->mii_bus);
2063err_out:
2064 return err;
2065}
2066
2067static void fec_enet_mii_remove(struct fec_enet_private *fep)
2068{
2069 if (--mii_cnt == 0) {
2070 mdiobus_unregister(fep->mii_bus);
2071 mdiobus_free(fep->mii_bus);
2072 }
2073}
2074
2075static void fec_enet_get_drvinfo(struct net_device *ndev,
2076 struct ethtool_drvinfo *info)
2077{
2078 struct fec_enet_private *fep = netdev_priv(ndev);
2079
2080 strlcpy(info->driver, fep->pdev->dev.driver->name,
2081 sizeof(info->driver));
2082 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2083 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2084}
2085
2086static int fec_enet_get_regs_len(struct net_device *ndev)
2087{
2088 struct fec_enet_private *fep = netdev_priv(ndev);
2089 struct resource *r;
2090 int s = 0;
2091
2092 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2093 if (r)
2094 s = resource_size(r);
2095
2096 return s;
2097}
2098
2099/* List of registers that can be safety be read to dump them with ethtool */
2100#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2101 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
2102static u32 fec_enet_register_offset[] = {
2103 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2104 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2105 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2106 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2107 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2108 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2109 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2110 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2111 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2112 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2113 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2114 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2115 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2116 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2117 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2118 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2119 RMON_T_P_GTE2048, RMON_T_OCTETS,
2120 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2121 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2122 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2123 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2124 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2125 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2126 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2127 RMON_R_P_GTE2048, RMON_R_OCTETS,
2128 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2129 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2130};
2131#else
2132static u32 fec_enet_register_offset[] = {
2133 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2134 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2135 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2136 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2137 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2138 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2139 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2140 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2141 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2142};
2143#endif
2144
2145static void fec_enet_get_regs(struct net_device *ndev,
2146 struct ethtool_regs *regs, void *regbuf)
2147{
2148 struct fec_enet_private *fep = netdev_priv(ndev);
2149 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2150 u32 *buf = (u32 *)regbuf;
2151 u32 i, off;
2152
2153 memset(buf, 0, regs->len);
2154
2155 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2156 off = fec_enet_register_offset[i] / 4;
2157 buf[off] = readl(&theregs[off]);
2158 }
2159}
2160
2161static int fec_enet_get_ts_info(struct net_device *ndev,
2162 struct ethtool_ts_info *info)
2163{
2164 struct fec_enet_private *fep = netdev_priv(ndev);
2165
2166 if (fep->bufdesc_ex) {
2167
2168 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2169 SOF_TIMESTAMPING_RX_SOFTWARE |
2170 SOF_TIMESTAMPING_SOFTWARE |
2171 SOF_TIMESTAMPING_TX_HARDWARE |
2172 SOF_TIMESTAMPING_RX_HARDWARE |
2173 SOF_TIMESTAMPING_RAW_HARDWARE;
2174 if (fep->ptp_clock)
2175 info->phc_index = ptp_clock_index(fep->ptp_clock);
2176 else
2177 info->phc_index = -1;
2178
2179 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2180 (1 << HWTSTAMP_TX_ON);
2181
2182 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2183 (1 << HWTSTAMP_FILTER_ALL);
2184 return 0;
2185 } else {
2186 return ethtool_op_get_ts_info(ndev, info);
2187 }
2188}
2189
2190#if !defined(CONFIG_M5272)
2191
2192static void fec_enet_get_pauseparam(struct net_device *ndev,
2193 struct ethtool_pauseparam *pause)
2194{
2195 struct fec_enet_private *fep = netdev_priv(ndev);
2196
2197 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2198 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2199 pause->rx_pause = pause->tx_pause;
2200}
2201
2202static int fec_enet_set_pauseparam(struct net_device *ndev,
2203 struct ethtool_pauseparam *pause)
2204{
2205 struct fec_enet_private *fep = netdev_priv(ndev);
2206
2207 if (!ndev->phydev)
2208 return -ENODEV;
2209
2210 if (pause->tx_pause != pause->rx_pause) {
2211 netdev_info(ndev,
2212 "hardware only support enable/disable both tx and rx");
2213 return -EINVAL;
2214 }
2215
2216 fep->pause_flag = 0;
2217
2218 /* tx pause must be same as rx pause */
2219 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2220 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2221
2222 if (pause->rx_pause || pause->autoneg) {
2223 ndev->phydev->supported |= ADVERTISED_Pause;
2224 ndev->phydev->advertising |= ADVERTISED_Pause;
2225 } else {
2226 ndev->phydev->supported &= ~ADVERTISED_Pause;
2227 ndev->phydev->advertising &= ~ADVERTISED_Pause;
2228 }
2229
2230 if (pause->autoneg) {
2231 if (netif_running(ndev))
2232 fec_stop(ndev);
2233 phy_start_aneg(ndev->phydev);
2234 }
2235 if (netif_running(ndev)) {
2236 napi_disable(&fep->napi);
2237 netif_tx_lock_bh(ndev);
2238 fec_restart(ndev);
2239 netif_wake_queue(ndev);
2240 netif_tx_unlock_bh(ndev);
2241 napi_enable(&fep->napi);
2242 }
2243
2244 return 0;
2245}
2246
2247static const struct fec_stat {
2248 char name[ETH_GSTRING_LEN];
2249 u16 offset;
2250} fec_stats[] = {
2251 /* RMON TX */
2252 { "tx_dropped", RMON_T_DROP },
2253 { "tx_packets", RMON_T_PACKETS },
2254 { "tx_broadcast", RMON_T_BC_PKT },
2255 { "tx_multicast", RMON_T_MC_PKT },
2256 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2257 { "tx_undersize", RMON_T_UNDERSIZE },
2258 { "tx_oversize", RMON_T_OVERSIZE },
2259 { "tx_fragment", RMON_T_FRAG },
2260 { "tx_jabber", RMON_T_JAB },
2261 { "tx_collision", RMON_T_COL },
2262 { "tx_64byte", RMON_T_P64 },
2263 { "tx_65to127byte", RMON_T_P65TO127 },
2264 { "tx_128to255byte", RMON_T_P128TO255 },
2265 { "tx_256to511byte", RMON_T_P256TO511 },
2266 { "tx_512to1023byte", RMON_T_P512TO1023 },
2267 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2268 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2269 { "tx_octets", RMON_T_OCTETS },
2270
2271 /* IEEE TX */
2272 { "IEEE_tx_drop", IEEE_T_DROP },
2273 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2274 { "IEEE_tx_1col", IEEE_T_1COL },
2275 { "IEEE_tx_mcol", IEEE_T_MCOL },
2276 { "IEEE_tx_def", IEEE_T_DEF },
2277 { "IEEE_tx_lcol", IEEE_T_LCOL },
2278 { "IEEE_tx_excol", IEEE_T_EXCOL },
2279 { "IEEE_tx_macerr", IEEE_T_MACERR },
2280 { "IEEE_tx_cserr", IEEE_T_CSERR },
2281 { "IEEE_tx_sqe", IEEE_T_SQE },
2282 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2283 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2284
2285 /* RMON RX */
2286 { "rx_packets", RMON_R_PACKETS },
2287 { "rx_broadcast", RMON_R_BC_PKT },
2288 { "rx_multicast", RMON_R_MC_PKT },
2289 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2290 { "rx_undersize", RMON_R_UNDERSIZE },
2291 { "rx_oversize", RMON_R_OVERSIZE },
2292 { "rx_fragment", RMON_R_FRAG },
2293 { "rx_jabber", RMON_R_JAB },
2294 { "rx_64byte", RMON_R_P64 },
2295 { "rx_65to127byte", RMON_R_P65TO127 },
2296 { "rx_128to255byte", RMON_R_P128TO255 },
2297 { "rx_256to511byte", RMON_R_P256TO511 },
2298 { "rx_512to1023byte", RMON_R_P512TO1023 },
2299 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2300 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2301 { "rx_octets", RMON_R_OCTETS },
2302
2303 /* IEEE RX */
2304 { "IEEE_rx_drop", IEEE_R_DROP },
2305 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2306 { "IEEE_rx_crc", IEEE_R_CRC },
2307 { "IEEE_rx_align", IEEE_R_ALIGN },
2308 { "IEEE_rx_macerr", IEEE_R_MACERR },
2309 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2310 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2311};
2312
2313#define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64))
2314
2315static void fec_enet_update_ethtool_stats(struct net_device *dev)
2316{
2317 struct fec_enet_private *fep = netdev_priv(dev);
2318 int i;
2319
2320 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2321 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2322}
2323
2324static void fec_enet_get_ethtool_stats(struct net_device *dev,
2325 struct ethtool_stats *stats, u64 *data)
2326{
2327 struct fec_enet_private *fep = netdev_priv(dev);
2328
2329 if (netif_running(dev))
2330 fec_enet_update_ethtool_stats(dev);
2331
2332 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
2333}
2334
2335static void fec_enet_get_strings(struct net_device *netdev,
2336 u32 stringset, u8 *data)
2337{
2338 int i;
2339 switch (stringset) {
2340 case ETH_SS_STATS:
2341 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2342 memcpy(data + i * ETH_GSTRING_LEN,
2343 fec_stats[i].name, ETH_GSTRING_LEN);
2344 break;
2345 }
2346}
2347
2348static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2349{
2350 switch (sset) {
2351 case ETH_SS_STATS:
2352 return ARRAY_SIZE(fec_stats);
2353 default:
2354 return -EOPNOTSUPP;
2355 }
2356}
2357
2358#else /* !defined(CONFIG_M5272) */
2359#define FEC_STATS_SIZE 0
2360static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
2361{
2362}
2363#endif /* !defined(CONFIG_M5272) */
2364
2365/* ITR clock source is enet system clock (clk_ahb).
2366 * TCTT unit is cycle_ns * 64 cycle
2367 * So, the ICTT value = X us / (cycle_ns * 64)
2368 */
2369static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2370{
2371 struct fec_enet_private *fep = netdev_priv(ndev);
2372
2373 return us * (fep->itr_clk_rate / 64000) / 1000;
2374}
2375
2376/* Set threshold for interrupt coalescing */
2377static void fec_enet_itr_coal_set(struct net_device *ndev)
2378{
2379 struct fec_enet_private *fep = netdev_priv(ndev);
2380 int rx_itr, tx_itr;
2381
2382 /* Must be greater than zero to avoid unpredictable behavior */
2383 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2384 !fep->tx_time_itr || !fep->tx_pkts_itr)
2385 return;
2386
2387 /* Select enet system clock as Interrupt Coalescing
2388 * timer Clock Source
2389 */
2390 rx_itr = FEC_ITR_CLK_SEL;
2391 tx_itr = FEC_ITR_CLK_SEL;
2392
2393 /* set ICFT and ICTT */
2394 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2395 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2396 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2397 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2398
2399 rx_itr |= FEC_ITR_EN;
2400 tx_itr |= FEC_ITR_EN;
2401
2402 writel(tx_itr, fep->hwp + FEC_TXIC0);
2403 writel(rx_itr, fep->hwp + FEC_RXIC0);
2404 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
2405 writel(tx_itr, fep->hwp + FEC_TXIC1);
2406 writel(rx_itr, fep->hwp + FEC_RXIC1);
2407 writel(tx_itr, fep->hwp + FEC_TXIC2);
2408 writel(rx_itr, fep->hwp + FEC_RXIC2);
2409 }
2410}
2411
2412static int
2413fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2414{
2415 struct fec_enet_private *fep = netdev_priv(ndev);
2416
2417 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2418 return -EOPNOTSUPP;
2419
2420 ec->rx_coalesce_usecs = fep->rx_time_itr;
2421 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2422
2423 ec->tx_coalesce_usecs = fep->tx_time_itr;
2424 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2425
2426 return 0;
2427}
2428
2429static int
2430fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2431{
2432 struct fec_enet_private *fep = netdev_priv(ndev);
2433 unsigned int cycle;
2434
2435 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2436 return -EOPNOTSUPP;
2437
2438 if (ec->rx_max_coalesced_frames > 255) {
2439 pr_err("Rx coalesced frames exceed hardware limitation\n");
2440 return -EINVAL;
2441 }
2442
2443 if (ec->tx_max_coalesced_frames > 255) {
2444 pr_err("Tx coalesced frame exceed hardware limitation\n");
2445 return -EINVAL;
2446 }
2447
2448 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2449 if (cycle > 0xFFFF) {
2450 pr_err("Rx coalesced usec exceed hardware limitation\n");
2451 return -EINVAL;
2452 }
2453
2454 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2455 if (cycle > 0xFFFF) {
2456 pr_err("Rx coalesced usec exceed hardware limitation\n");
2457 return -EINVAL;
2458 }
2459
2460 fep->rx_time_itr = ec->rx_coalesce_usecs;
2461 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2462
2463 fep->tx_time_itr = ec->tx_coalesce_usecs;
2464 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2465
2466 fec_enet_itr_coal_set(ndev);
2467
2468 return 0;
2469}
2470
2471static void fec_enet_itr_coal_init(struct net_device *ndev)
2472{
2473 struct ethtool_coalesce ec;
2474
2475 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2476 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2477
2478 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2479 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2480
2481 fec_enet_set_coalesce(ndev, &ec);
2482}
2483
2484static int fec_enet_get_tunable(struct net_device *netdev,
2485 const struct ethtool_tunable *tuna,
2486 void *data)
2487{
2488 struct fec_enet_private *fep = netdev_priv(netdev);
2489 int ret = 0;
2490
2491 switch (tuna->id) {
2492 case ETHTOOL_RX_COPYBREAK:
2493 *(u32 *)data = fep->rx_copybreak;
2494 break;
2495 default:
2496 ret = -EINVAL;
2497 break;
2498 }
2499
2500 return ret;
2501}
2502
2503static int fec_enet_set_tunable(struct net_device *netdev,
2504 const struct ethtool_tunable *tuna,
2505 const void *data)
2506{
2507 struct fec_enet_private *fep = netdev_priv(netdev);
2508 int ret = 0;
2509
2510 switch (tuna->id) {
2511 case ETHTOOL_RX_COPYBREAK:
2512 fep->rx_copybreak = *(u32 *)data;
2513 break;
2514 default:
2515 ret = -EINVAL;
2516 break;
2517 }
2518
2519 return ret;
2520}
2521
2522static void
2523fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2524{
2525 struct fec_enet_private *fep = netdev_priv(ndev);
2526
2527 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2528 wol->supported = WAKE_MAGIC;
2529 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2530 } else {
2531 wol->supported = wol->wolopts = 0;
2532 }
2533}
2534
2535static int
2536fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2537{
2538 struct fec_enet_private *fep = netdev_priv(ndev);
2539
2540 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2541 return -EINVAL;
2542
2543 if (wol->wolopts & ~WAKE_MAGIC)
2544 return -EINVAL;
2545
2546 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2547 if (device_may_wakeup(&ndev->dev)) {
2548 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2549 if (fep->irq[0] > 0)
2550 enable_irq_wake(fep->irq[0]);
2551 } else {
2552 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2553 if (fep->irq[0] > 0)
2554 disable_irq_wake(fep->irq[0]);
2555 }
2556
2557 return 0;
2558}
2559
2560static const struct ethtool_ops fec_enet_ethtool_ops = {
2561 .get_drvinfo = fec_enet_get_drvinfo,
2562 .get_regs_len = fec_enet_get_regs_len,
2563 .get_regs = fec_enet_get_regs,
2564 .nway_reset = phy_ethtool_nway_reset,
2565 .get_link = ethtool_op_get_link,
2566 .get_coalesce = fec_enet_get_coalesce,
2567 .set_coalesce = fec_enet_set_coalesce,
2568#ifndef CONFIG_M5272
2569 .get_pauseparam = fec_enet_get_pauseparam,
2570 .set_pauseparam = fec_enet_set_pauseparam,
2571 .get_strings = fec_enet_get_strings,
2572 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2573 .get_sset_count = fec_enet_get_sset_count,
2574#endif
2575 .get_ts_info = fec_enet_get_ts_info,
2576 .get_tunable = fec_enet_get_tunable,
2577 .set_tunable = fec_enet_set_tunable,
2578 .get_wol = fec_enet_get_wol,
2579 .set_wol = fec_enet_set_wol,
2580 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2581 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2582};
2583
2584static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2585{
2586 struct fec_enet_private *fep = netdev_priv(ndev);
2587 struct phy_device *phydev = ndev->phydev;
2588
2589 if (!netif_running(ndev))
2590 return -EINVAL;
2591
2592 if (!phydev)
2593 return -ENODEV;
2594
2595 if (fep->bufdesc_ex) {
2596 if (cmd == SIOCSHWTSTAMP)
2597 return fec_ptp_set(ndev, rq);
2598 if (cmd == SIOCGHWTSTAMP)
2599 return fec_ptp_get(ndev, rq);
2600 }
2601
2602 return phy_mii_ioctl(phydev, rq, cmd);
2603}
2604
2605static void fec_enet_free_buffers(struct net_device *ndev)
2606{
2607 struct fec_enet_private *fep = netdev_priv(ndev);
2608 unsigned int i;
2609 struct sk_buff *skb;
2610 struct bufdesc *bdp;
2611 struct fec_enet_priv_tx_q *txq;
2612 struct fec_enet_priv_rx_q *rxq;
2613 unsigned int q;
2614
2615 for (q = 0; q < fep->num_rx_queues; q++) {
2616 rxq = fep->rx_queue[q];
2617 bdp = rxq->bd.base;
2618 for (i = 0; i < rxq->bd.ring_size; i++) {
2619 skb = rxq->rx_skbuff[i];
2620 rxq->rx_skbuff[i] = NULL;
2621 if (skb) {
2622 dma_unmap_single(&fep->pdev->dev,
2623 fec32_to_cpu(bdp->cbd_bufaddr),
2624 FEC_ENET_RX_FRSIZE - fep->rx_align,
2625 DMA_FROM_DEVICE);
2626 dev_kfree_skb(skb);
2627 }
2628 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2629 }
2630 }
2631
2632 for (q = 0; q < fep->num_tx_queues; q++) {
2633 txq = fep->tx_queue[q];
2634 bdp = txq->bd.base;
2635 for (i = 0; i < txq->bd.ring_size; i++) {
2636 kfree(txq->tx_bounce[i]);
2637 txq->tx_bounce[i] = NULL;
2638 skb = txq->tx_skbuff[i];
2639 txq->tx_skbuff[i] = NULL;
2640 dev_kfree_skb(skb);
2641 }
2642 }
2643}
2644
2645static void fec_enet_free_queue(struct net_device *ndev)
2646{
2647 struct fec_enet_private *fep = netdev_priv(ndev);
2648 int i;
2649 struct fec_enet_priv_tx_q *txq;
2650
2651 for (i = 0; i < fep->num_tx_queues; i++)
2652 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2653 txq = fep->tx_queue[i];
2654 dma_free_coherent(NULL,
2655 txq->bd.ring_size * TSO_HEADER_SIZE,
2656 txq->tso_hdrs,
2657 txq->tso_hdrs_dma);
2658 }
2659
2660 for (i = 0; i < fep->num_rx_queues; i++)
2661 kfree(fep->rx_queue[i]);
2662 for (i = 0; i < fep->num_tx_queues; i++)
2663 kfree(fep->tx_queue[i]);
2664}
2665
2666static int fec_enet_alloc_queue(struct net_device *ndev)
2667{
2668 struct fec_enet_private *fep = netdev_priv(ndev);
2669 int i;
2670 int ret = 0;
2671 struct fec_enet_priv_tx_q *txq;
2672
2673 for (i = 0; i < fep->num_tx_queues; i++) {
2674 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2675 if (!txq) {
2676 ret = -ENOMEM;
2677 goto alloc_failed;
2678 }
2679
2680 fep->tx_queue[i] = txq;
2681 txq->bd.ring_size = TX_RING_SIZE;
2682 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
2683
2684 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2685 txq->tx_wake_threshold =
2686 (txq->bd.ring_size - txq->tx_stop_threshold) / 2;
2687
2688 txq->tso_hdrs = dma_alloc_coherent(NULL,
2689 txq->bd.ring_size * TSO_HEADER_SIZE,
2690 &txq->tso_hdrs_dma,
2691 GFP_KERNEL);
2692 if (!txq->tso_hdrs) {
2693 ret = -ENOMEM;
2694 goto alloc_failed;
2695 }
2696 }
2697
2698 for (i = 0; i < fep->num_rx_queues; i++) {
2699 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2700 GFP_KERNEL);
2701 if (!fep->rx_queue[i]) {
2702 ret = -ENOMEM;
2703 goto alloc_failed;
2704 }
2705
2706 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
2707 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
2708 }
2709 return ret;
2710
2711alloc_failed:
2712 fec_enet_free_queue(ndev);
2713 return ret;
2714}
2715
2716static int
2717fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2718{
2719 struct fec_enet_private *fep = netdev_priv(ndev);
2720 unsigned int i;
2721 struct sk_buff *skb;
2722 struct bufdesc *bdp;
2723 struct fec_enet_priv_rx_q *rxq;
2724
2725 rxq = fep->rx_queue[queue];
2726 bdp = rxq->bd.base;
2727 for (i = 0; i < rxq->bd.ring_size; i++) {
2728 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2729 if (!skb)
2730 goto err_alloc;
2731
2732 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2733 dev_kfree_skb(skb);
2734 goto err_alloc;
2735 }
2736
2737 rxq->rx_skbuff[i] = skb;
2738 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
2739
2740 if (fep->bufdesc_ex) {
2741 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2742 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
2743 }
2744
2745 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2746 }
2747
2748 /* Set the last buffer to wrap. */
2749 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
2750 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2751 return 0;
2752
2753 err_alloc:
2754 fec_enet_free_buffers(ndev);
2755 return -ENOMEM;
2756}
2757
2758static int
2759fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2760{
2761 struct fec_enet_private *fep = netdev_priv(ndev);
2762 unsigned int i;
2763 struct bufdesc *bdp;
2764 struct fec_enet_priv_tx_q *txq;
2765
2766 txq = fep->tx_queue[queue];
2767 bdp = txq->bd.base;
2768 for (i = 0; i < txq->bd.ring_size; i++) {
2769 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2770 if (!txq->tx_bounce[i])
2771 goto err_alloc;
2772
2773 bdp->cbd_sc = cpu_to_fec16(0);
2774 bdp->cbd_bufaddr = cpu_to_fec32(0);
2775
2776 if (fep->bufdesc_ex) {
2777 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2778 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
2779 }
2780
2781 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
2782 }
2783
2784 /* Set the last buffer to wrap. */
2785 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
2786 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2787
2788 return 0;
2789
2790 err_alloc:
2791 fec_enet_free_buffers(ndev);
2792 return -ENOMEM;
2793}
2794
2795static int fec_enet_alloc_buffers(struct net_device *ndev)
2796{
2797 struct fec_enet_private *fep = netdev_priv(ndev);
2798 unsigned int i;
2799
2800 for (i = 0; i < fep->num_rx_queues; i++)
2801 if (fec_enet_alloc_rxq_buffers(ndev, i))
2802 return -ENOMEM;
2803
2804 for (i = 0; i < fep->num_tx_queues; i++)
2805 if (fec_enet_alloc_txq_buffers(ndev, i))
2806 return -ENOMEM;
2807 return 0;
2808}
2809
2810static int
2811fec_enet_open(struct net_device *ndev)
2812{
2813 struct fec_enet_private *fep = netdev_priv(ndev);
2814 int ret;
2815
2816 ret = pm_runtime_get_sync(&fep->pdev->dev);
2817 if (ret < 0)
2818 return ret;
2819
2820 pinctrl_pm_select_default_state(&fep->pdev->dev);
2821 ret = fec_enet_clk_enable(ndev, true);
2822 if (ret)
2823 goto clk_enable;
2824
2825 /* I should reset the ring buffers here, but I don't yet know
2826 * a simple way to do that.
2827 */
2828
2829 ret = fec_enet_alloc_buffers(ndev);
2830 if (ret)
2831 goto err_enet_alloc;
2832
2833 /* Init MAC prior to mii bus probe */
2834 fec_restart(ndev);
2835
2836 /* Probe and connect to PHY when open the interface */
2837 ret = fec_enet_mii_probe(ndev);
2838 if (ret)
2839 goto err_enet_mii_probe;
2840
2841 if (fep->quirks & FEC_QUIRK_ERR006687)
2842 imx6q_cpuidle_fec_irqs_used();
2843
2844 napi_enable(&fep->napi);
2845 phy_start(ndev->phydev);
2846 netif_tx_start_all_queues(ndev);
2847
2848 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2849 FEC_WOL_FLAG_ENABLE);
2850
2851 return 0;
2852
2853err_enet_mii_probe:
2854 fec_enet_free_buffers(ndev);
2855err_enet_alloc:
2856 fec_enet_clk_enable(ndev, false);
2857clk_enable:
2858 pm_runtime_mark_last_busy(&fep->pdev->dev);
2859 pm_runtime_put_autosuspend(&fep->pdev->dev);
2860 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2861 return ret;
2862}
2863
2864static int
2865fec_enet_close(struct net_device *ndev)
2866{
2867 struct fec_enet_private *fep = netdev_priv(ndev);
2868
2869 phy_stop(ndev->phydev);
2870
2871 if (netif_device_present(ndev)) {
2872 napi_disable(&fep->napi);
2873 netif_tx_disable(ndev);
2874 fec_stop(ndev);
2875 }
2876
2877 phy_disconnect(ndev->phydev);
2878
2879 if (fep->quirks & FEC_QUIRK_ERR006687)
2880 imx6q_cpuidle_fec_irqs_unused();
2881
2882 fec_enet_update_ethtool_stats(ndev);
2883
2884 fec_enet_clk_enable(ndev, false);
2885 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2886 pm_runtime_mark_last_busy(&fep->pdev->dev);
2887 pm_runtime_put_autosuspend(&fep->pdev->dev);
2888
2889 fec_enet_free_buffers(ndev);
2890
2891 return 0;
2892}
2893
2894/* Set or clear the multicast filter for this adaptor.
2895 * Skeleton taken from sunlance driver.
2896 * The CPM Ethernet implementation allows Multicast as well as individual
2897 * MAC address filtering. Some of the drivers check to make sure it is
2898 * a group multicast address, and discard those that are not. I guess I
2899 * will do the same for now, but just remove the test if you want
2900 * individual filtering as well (do the upper net layers want or support
2901 * this kind of feature?).
2902 */
2903
2904#define FEC_HASH_BITS 6 /* #bits in hash */
2905#define CRC32_POLY 0xEDB88320
2906
2907static void set_multicast_list(struct net_device *ndev)
2908{
2909 struct fec_enet_private *fep = netdev_priv(ndev);
2910 struct netdev_hw_addr *ha;
2911 unsigned int i, bit, data, crc, tmp;
2912 unsigned char hash;
2913 unsigned int hash_high = 0, hash_low = 0;
2914
2915 if (ndev->flags & IFF_PROMISC) {
2916 tmp = readl(fep->hwp + FEC_R_CNTRL);
2917 tmp |= 0x8;
2918 writel(tmp, fep->hwp + FEC_R_CNTRL);
2919 return;
2920 }
2921
2922 tmp = readl(fep->hwp + FEC_R_CNTRL);
2923 tmp &= ~0x8;
2924 writel(tmp, fep->hwp + FEC_R_CNTRL);
2925
2926 if (ndev->flags & IFF_ALLMULTI) {
2927 /* Catch all multicast addresses, so set the
2928 * filter to all 1's
2929 */
2930 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2931 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2932
2933 return;
2934 }
2935
2936 /* Add the addresses in hash register */
2937 netdev_for_each_mc_addr(ha, ndev) {
2938 /* calculate crc32 value of mac address */
2939 crc = 0xffffffff;
2940
2941 for (i = 0; i < ndev->addr_len; i++) {
2942 data = ha->addr[i];
2943 for (bit = 0; bit < 8; bit++, data >>= 1) {
2944 crc = (crc >> 1) ^
2945 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2946 }
2947 }
2948
2949 /* only upper 6 bits (FEC_HASH_BITS) are used
2950 * which point to specific bit in he hash registers
2951 */
2952 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
2953
2954 if (hash > 31)
2955 hash_high |= 1 << (hash - 32);
2956 else
2957 hash_low |= 1 << hash;
2958 }
2959
2960 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2961 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2962}
2963
2964/* Set a MAC change in hardware. */
2965static int
2966fec_set_mac_address(struct net_device *ndev, void *p)
2967{
2968 struct fec_enet_private *fep = netdev_priv(ndev);
2969 struct sockaddr *addr = p;
2970
2971 if (addr) {
2972 if (!is_valid_ether_addr(addr->sa_data))
2973 return -EADDRNOTAVAIL;
2974 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2975 }
2976
2977 /* Add netif status check here to avoid system hang in below case:
2978 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
2979 * After ethx down, fec all clocks are gated off and then register
2980 * access causes system hang.
2981 */
2982 if (!netif_running(ndev))
2983 return 0;
2984
2985 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2986 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
2987 fep->hwp + FEC_ADDR_LOW);
2988 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
2989 fep->hwp + FEC_ADDR_HIGH);
2990 return 0;
2991}
2992
2993#ifdef CONFIG_NET_POLL_CONTROLLER
2994/**
2995 * fec_poll_controller - FEC Poll controller function
2996 * @dev: The FEC network adapter
2997 *
2998 * Polled functionality used by netconsole and others in non interrupt mode
2999 *
3000 */
3001static void fec_poll_controller(struct net_device *dev)
3002{
3003 int i;
3004 struct fec_enet_private *fep = netdev_priv(dev);
3005
3006 for (i = 0; i < FEC_IRQ_NUM; i++) {
3007 if (fep->irq[i] > 0) {
3008 disable_irq(fep->irq[i]);
3009 fec_enet_interrupt(fep->irq[i], dev);
3010 enable_irq(fep->irq[i]);
3011 }
3012 }
3013}
3014#endif
3015
3016static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3017 netdev_features_t features)
3018{
3019 struct fec_enet_private *fep = netdev_priv(netdev);
3020 netdev_features_t changed = features ^ netdev->features;
3021
3022 netdev->features = features;
3023
3024 /* Receive checksum has been changed */
3025 if (changed & NETIF_F_RXCSUM) {
3026 if (features & NETIF_F_RXCSUM)
3027 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3028 else
3029 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3030 }
3031}
3032
3033static int fec_set_features(struct net_device *netdev,
3034 netdev_features_t features)
3035{
3036 struct fec_enet_private *fep = netdev_priv(netdev);
3037 netdev_features_t changed = features ^ netdev->features;
3038
3039 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3040 napi_disable(&fep->napi);
3041 netif_tx_lock_bh(netdev);
3042 fec_stop(netdev);
3043 fec_enet_set_netdev_features(netdev, features);
3044 fec_restart(netdev);
3045 netif_tx_wake_all_queues(netdev);
3046 netif_tx_unlock_bh(netdev);
3047 napi_enable(&fep->napi);
3048 } else {
3049 fec_enet_set_netdev_features(netdev, features);
3050 }
3051
3052 return 0;
3053}
3054
3055static const struct net_device_ops fec_netdev_ops = {
3056 .ndo_open = fec_enet_open,
3057 .ndo_stop = fec_enet_close,
3058 .ndo_start_xmit = fec_enet_start_xmit,
3059 .ndo_set_rx_mode = set_multicast_list,
3060 .ndo_validate_addr = eth_validate_addr,
3061 .ndo_tx_timeout = fec_timeout,
3062 .ndo_set_mac_address = fec_set_mac_address,
3063 .ndo_do_ioctl = fec_enet_ioctl,
3064#ifdef CONFIG_NET_POLL_CONTROLLER
3065 .ndo_poll_controller = fec_poll_controller,
3066#endif
3067 .ndo_set_features = fec_set_features,
3068};
3069
3070static const unsigned short offset_des_active_rxq[] = {
3071 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3072};
3073
3074static const unsigned short offset_des_active_txq[] = {
3075 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3076};
3077
3078 /*
3079 * XXX: We need to clean up on failure exits here.
3080 *
3081 */
3082static int fec_enet_init(struct net_device *ndev)
3083{
3084 struct fec_enet_private *fep = netdev_priv(ndev);
3085 struct bufdesc *cbd_base;
3086 dma_addr_t bd_dma;
3087 int bd_size;
3088 unsigned int i;
3089 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3090 sizeof(struct bufdesc);
3091 unsigned dsize_log2 = __fls(dsize);
3092
3093 WARN_ON(dsize != (1 << dsize_log2));
3094#if defined(CONFIG_ARM)
3095 fep->rx_align = 0xf;
3096 fep->tx_align = 0xf;
3097#else
3098 fep->rx_align = 0x3;
3099 fep->tx_align = 0x3;
3100#endif
3101
3102 fec_enet_alloc_queue(ndev);
3103
3104 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
3105
3106 /* Allocate memory for buffer descriptors. */
3107 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3108 GFP_KERNEL);
3109 if (!cbd_base) {
3110 return -ENOMEM;
3111 }
3112
3113 memset(cbd_base, 0, bd_size);
3114
3115 /* Get the Ethernet address */
3116 fec_get_mac(ndev);
3117 /* make sure MAC we just acquired is programmed into the hw */
3118 fec_set_mac_address(ndev, NULL);
3119
3120 /* Set receive and transmit descriptor base. */
3121 for (i = 0; i < fep->num_rx_queues; i++) {
3122 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3123 unsigned size = dsize * rxq->bd.ring_size;
3124
3125 rxq->bd.qid = i;
3126 rxq->bd.base = cbd_base;
3127 rxq->bd.cur = cbd_base;
3128 rxq->bd.dma = bd_dma;
3129 rxq->bd.dsize = dsize;
3130 rxq->bd.dsize_log2 = dsize_log2;
3131 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
3132 bd_dma += size;
3133 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3134 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3135 }
3136
3137 for (i = 0; i < fep->num_tx_queues; i++) {
3138 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3139 unsigned size = dsize * txq->bd.ring_size;
3140
3141 txq->bd.qid = i;
3142 txq->bd.base = cbd_base;
3143 txq->bd.cur = cbd_base;
3144 txq->bd.dma = bd_dma;
3145 txq->bd.dsize = dsize;
3146 txq->bd.dsize_log2 = dsize_log2;
3147 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
3148 bd_dma += size;
3149 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3150 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3151 }
3152
3153
3154 /* The FEC Ethernet specific entries in the device structure */
3155 ndev->watchdog_timeo = TX_TIMEOUT;
3156 ndev->netdev_ops = &fec_netdev_ops;
3157 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3158
3159 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3160 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3161
3162 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3163 /* enable hw VLAN support */
3164 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3165
3166 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3167 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3168
3169 /* enable hw accelerator */
3170 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3171 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3172 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3173 }
3174
3175 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3176 fep->tx_align = 0;
3177 fep->rx_align = 0x3f;
3178 }
3179
3180 ndev->hw_features = ndev->features;
3181
3182 fec_restart(ndev);
3183
3184 fec_enet_update_ethtool_stats(ndev);
3185
3186 return 0;
3187}
3188
3189#ifdef CONFIG_OF
3190static void fec_reset_phy(struct platform_device *pdev)
3191{
3192 int err, phy_reset;
3193 bool active_high = false;
3194 int msec = 1;
3195 struct device_node *np = pdev->dev.of_node;
3196
3197 if (!np)
3198 return;
3199
3200 of_property_read_u32(np, "phy-reset-duration", &msec);
3201 /* A sane reset duration should not be longer than 1s */
3202 if (msec > 1000)
3203 msec = 1;
3204
3205 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3206 if (!gpio_is_valid(phy_reset))
3207 return;
3208
3209 active_high = of_property_read_bool(np, "phy-reset-active-high");
3210
3211 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3212 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
3213 "phy-reset");
3214 if (err) {
3215 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3216 return;
3217 }
3218
3219 if (msec > 20)
3220 msleep(msec);
3221 else
3222 usleep_range(msec * 1000, msec * 1000 + 1000);
3223
3224 gpio_set_value_cansleep(phy_reset, !active_high);
3225}
3226#else /* CONFIG_OF */
3227static void fec_reset_phy(struct platform_device *pdev)
3228{
3229 /*
3230 * In case of platform probe, the reset has been done
3231 * by machine code.
3232 */
3233}
3234#endif /* CONFIG_OF */
3235
3236static void
3237fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3238{
3239 struct device_node *np = pdev->dev.of_node;
3240
3241 *num_tx = *num_rx = 1;
3242
3243 if (!np || !of_device_is_available(np))
3244 return;
3245
3246 /* parse the num of tx and rx queues */
3247 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3248
3249 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3250
3251 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3252 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3253 *num_tx);
3254 *num_tx = 1;
3255 return;
3256 }
3257
3258 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3259 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3260 *num_rx);
3261 *num_rx = 1;
3262 return;
3263 }
3264
3265}
3266
3267static int
3268fec_probe(struct platform_device *pdev)
3269{
3270 struct fec_enet_private *fep;
3271 struct fec_platform_data *pdata;
3272 struct net_device *ndev;
3273 int i, irq, ret = 0;
3274 struct resource *r;
3275 const struct of_device_id *of_id;
3276 static int dev_id;
3277 struct device_node *np = pdev->dev.of_node, *phy_node;
3278 int num_tx_qs;
3279 int num_rx_qs;
3280
3281 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3282
3283 /* Init network device */
3284 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
3285 FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
3286 if (!ndev)
3287 return -ENOMEM;
3288
3289 SET_NETDEV_DEV(ndev, &pdev->dev);
3290
3291 /* setup board info structure */
3292 fep = netdev_priv(ndev);
3293
3294 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3295 if (of_id)
3296 pdev->id_entry = of_id->data;
3297 fep->quirks = pdev->id_entry->driver_data;
3298
3299 fep->netdev = ndev;
3300 fep->num_rx_queues = num_rx_qs;
3301 fep->num_tx_queues = num_tx_qs;
3302
3303#if !defined(CONFIG_M5272)
3304 /* default enable pause frame auto negotiation */
3305 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3306 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3307#endif
3308
3309 /* Select default pin state */
3310 pinctrl_pm_select_default_state(&pdev->dev);
3311
3312 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3313 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3314 if (IS_ERR(fep->hwp)) {
3315 ret = PTR_ERR(fep->hwp);
3316 goto failed_ioremap;
3317 }
3318
3319 fep->pdev = pdev;
3320 fep->dev_id = dev_id++;
3321
3322 platform_set_drvdata(pdev, ndev);
3323
3324 if ((of_machine_is_compatible("fsl,imx6q") ||
3325 of_machine_is_compatible("fsl,imx6dl")) &&
3326 !of_property_read_bool(np, "fsl,err006687-workaround-present"))
3327 fep->quirks |= FEC_QUIRK_ERR006687;
3328
3329 if (of_get_property(np, "fsl,magic-packet", NULL))
3330 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3331
3332 phy_node = of_parse_phandle(np, "phy-handle", 0);
3333 if (!phy_node && of_phy_is_fixed_link(np)) {
3334 ret = of_phy_register_fixed_link(np);
3335 if (ret < 0) {
3336 dev_err(&pdev->dev,
3337 "broken fixed-link specification\n");
3338 goto failed_phy;
3339 }
3340 phy_node = of_node_get(np);
3341 }
3342 fep->phy_node = phy_node;
3343
3344 ret = of_get_phy_mode(pdev->dev.of_node);
3345 if (ret < 0) {
3346 pdata = dev_get_platdata(&pdev->dev);
3347 if (pdata)
3348 fep->phy_interface = pdata->phy;
3349 else
3350 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3351 } else {
3352 fep->phy_interface = ret;
3353 }
3354
3355 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3356 if (IS_ERR(fep->clk_ipg)) {
3357 ret = PTR_ERR(fep->clk_ipg);
3358 goto failed_clk;
3359 }
3360
3361 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3362 if (IS_ERR(fep->clk_ahb)) {
3363 ret = PTR_ERR(fep->clk_ahb);
3364 goto failed_clk;
3365 }
3366
3367 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3368
3369 /* enet_out is optional, depends on board */
3370 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3371 if (IS_ERR(fep->clk_enet_out))
3372 fep->clk_enet_out = NULL;
3373
3374 fep->ptp_clk_on = false;
3375 mutex_init(&fep->ptp_clk_mutex);
3376
3377 /* clk_ref is optional, depends on board */
3378 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3379 if (IS_ERR(fep->clk_ref))
3380 fep->clk_ref = NULL;
3381
3382 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3383 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3384 if (IS_ERR(fep->clk_ptp)) {
3385 fep->clk_ptp = NULL;
3386 fep->bufdesc_ex = false;
3387 }
3388
3389 ret = fec_enet_clk_enable(ndev, true);
3390 if (ret)
3391 goto failed_clk;
3392
3393 ret = clk_prepare_enable(fep->clk_ipg);
3394 if (ret)
3395 goto failed_clk_ipg;
3396
3397 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3398 if (!IS_ERR(fep->reg_phy)) {
3399 ret = regulator_enable(fep->reg_phy);
3400 if (ret) {
3401 dev_err(&pdev->dev,
3402 "Failed to enable phy regulator: %d\n", ret);
3403 goto failed_regulator;
3404 }
3405 } else {
3406 fep->reg_phy = NULL;
3407 }
3408
3409 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3410 pm_runtime_use_autosuspend(&pdev->dev);
3411 pm_runtime_get_noresume(&pdev->dev);
3412 pm_runtime_set_active(&pdev->dev);
3413 pm_runtime_enable(&pdev->dev);
3414
3415 fec_reset_phy(pdev);
3416
3417 if (fep->bufdesc_ex)
3418 fec_ptp_init(pdev);
3419
3420 ret = fec_enet_init(ndev);
3421 if (ret)
3422 goto failed_init;
3423
3424 for (i = 0; i < FEC_IRQ_NUM; i++) {
3425 irq = platform_get_irq(pdev, i);
3426 if (irq < 0) {
3427 if (i)
3428 break;
3429 ret = irq;
3430 goto failed_irq;
3431 }
3432 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3433 0, pdev->name, ndev);
3434 if (ret)
3435 goto failed_irq;
3436
3437 fep->irq[i] = irq;
3438 }
3439
3440 init_completion(&fep->mdio_done);
3441 ret = fec_enet_mii_init(pdev);
3442 if (ret)
3443 goto failed_mii_init;
3444
3445 /* Carrier starts down, phylib will bring it up */
3446 netif_carrier_off(ndev);
3447 fec_enet_clk_enable(ndev, false);
3448 pinctrl_pm_select_sleep_state(&pdev->dev);
3449
3450 ret = register_netdev(ndev);
3451 if (ret)
3452 goto failed_register;
3453
3454 device_init_wakeup(&ndev->dev, fep->wol_flag &
3455 FEC_WOL_HAS_MAGIC_PACKET);
3456
3457 if (fep->bufdesc_ex && fep->ptp_clock)
3458 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3459
3460 fep->rx_copybreak = COPYBREAK_DEFAULT;
3461 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3462
3463 pm_runtime_mark_last_busy(&pdev->dev);
3464 pm_runtime_put_autosuspend(&pdev->dev);
3465
3466 return 0;
3467
3468failed_register:
3469 fec_enet_mii_remove(fep);
3470failed_mii_init:
3471failed_irq:
3472failed_init:
3473 fec_ptp_stop(pdev);
3474 if (fep->reg_phy)
3475 regulator_disable(fep->reg_phy);
3476failed_regulator:
3477 clk_disable_unprepare(fep->clk_ipg);
3478failed_clk_ipg:
3479 fec_enet_clk_enable(ndev, false);
3480failed_clk:
3481 if (of_phy_is_fixed_link(np))
3482 of_phy_deregister_fixed_link(np);
3483failed_phy:
3484 of_node_put(phy_node);
3485failed_ioremap:
3486 free_netdev(ndev);
3487
3488 return ret;
3489}
3490
3491static int
3492fec_drv_remove(struct platform_device *pdev)
3493{
3494 struct net_device *ndev = platform_get_drvdata(pdev);
3495 struct fec_enet_private *fep = netdev_priv(ndev);
3496 struct device_node *np = pdev->dev.of_node;
3497
3498 cancel_work_sync(&fep->tx_timeout_work);
3499 fec_ptp_stop(pdev);
3500 unregister_netdev(ndev);
3501 fec_enet_mii_remove(fep);
3502 if (fep->reg_phy)
3503 regulator_disable(fep->reg_phy);
3504 if (of_phy_is_fixed_link(np))
3505 of_phy_deregister_fixed_link(np);
3506 of_node_put(fep->phy_node);
3507 free_netdev(ndev);
3508
3509 return 0;
3510}
3511
3512static int __maybe_unused fec_suspend(struct device *dev)
3513{
3514 struct net_device *ndev = dev_get_drvdata(dev);
3515 struct fec_enet_private *fep = netdev_priv(ndev);
3516
3517 rtnl_lock();
3518 if (netif_running(ndev)) {
3519 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3520 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3521 phy_stop(ndev->phydev);
3522 napi_disable(&fep->napi);
3523 netif_tx_lock_bh(ndev);
3524 netif_device_detach(ndev);
3525 netif_tx_unlock_bh(ndev);
3526 fec_stop(ndev);
3527 fec_enet_clk_enable(ndev, false);
3528 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3529 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3530 }
3531 rtnl_unlock();
3532
3533 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3534 regulator_disable(fep->reg_phy);
3535
3536 /* SOC supply clock to phy, when clock is disabled, phy link down
3537 * SOC control phy regulator, when regulator is disabled, phy link down
3538 */
3539 if (fep->clk_enet_out || fep->reg_phy)
3540 fep->link = 0;
3541
3542 return 0;
3543}
3544
3545static int __maybe_unused fec_resume(struct device *dev)
3546{
3547 struct net_device *ndev = dev_get_drvdata(dev);
3548 struct fec_enet_private *fep = netdev_priv(ndev);
3549 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3550 int ret;
3551 int val;
3552
3553 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3554 ret = regulator_enable(fep->reg_phy);
3555 if (ret)
3556 return ret;
3557 }
3558
3559 rtnl_lock();
3560 if (netif_running(ndev)) {
3561 ret = fec_enet_clk_enable(ndev, true);
3562 if (ret) {
3563 rtnl_unlock();
3564 goto failed_clk;
3565 }
3566 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3567 if (pdata && pdata->sleep_mode_enable)
3568 pdata->sleep_mode_enable(false);
3569 val = readl(fep->hwp + FEC_ECNTRL);
3570 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3571 writel(val, fep->hwp + FEC_ECNTRL);
3572 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3573 } else {
3574 pinctrl_pm_select_default_state(&fep->pdev->dev);
3575 }
3576 fec_restart(ndev);
3577 netif_tx_lock_bh(ndev);
3578 netif_device_attach(ndev);
3579 netif_tx_unlock_bh(ndev);
3580 napi_enable(&fep->napi);
3581 phy_start(ndev->phydev);
3582 }
3583 rtnl_unlock();
3584
3585 return 0;
3586
3587failed_clk:
3588 if (fep->reg_phy)
3589 regulator_disable(fep->reg_phy);
3590 return ret;
3591}
3592
3593static int __maybe_unused fec_runtime_suspend(struct device *dev)
3594{
3595 struct net_device *ndev = dev_get_drvdata(dev);
3596 struct fec_enet_private *fep = netdev_priv(ndev);
3597
3598 clk_disable_unprepare(fep->clk_ipg);
3599
3600 return 0;
3601}
3602
3603static int __maybe_unused fec_runtime_resume(struct device *dev)
3604{
3605 struct net_device *ndev = dev_get_drvdata(dev);
3606 struct fec_enet_private *fep = netdev_priv(ndev);
3607
3608 return clk_prepare_enable(fep->clk_ipg);
3609}
3610
3611static const struct dev_pm_ops fec_pm_ops = {
3612 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3613 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3614};
3615
3616static struct platform_driver fec_driver = {
3617 .driver = {
3618 .name = DRIVER_NAME,
3619 .pm = &fec_pm_ops,
3620 .of_match_table = fec_dt_ids,
3621 },
3622 .id_table = fec_devtype,
3623 .probe = fec_probe,
3624 .remove = fec_drv_remove,
3625};
3626
3627module_platform_driver(fec_driver);
3628
3629MODULE_ALIAS("platform:"DRIVER_NAME);
3630MODULE_LICENSE("GPL");