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1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * License Terms: GNU General Public License v2
6 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
7 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
8 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
9 *
10 * U8500 PRCM Unit interface driver
11 *
12 */
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/delay.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/spinlock.h>
19#include <linux/io.h>
20#include <linux/slab.h>
21#include <linux/mutex.h>
22#include <linux/completion.h>
23#include <linux/irq.h>
24#include <linux/jiffies.h>
25#include <linux/bitops.h>
26#include <linux/fs.h>
27#include <linux/platform_device.h>
28#include <linux/uaccess.h>
29#include <linux/mfd/core.h>
30#include <linux/mfd/db8500-prcmu.h>
31#include <linux/regulator/db8500-prcmu.h>
32#include <linux/regulator/machine.h>
33#include <mach/hardware.h>
34#include <mach/irqs.h>
35#include <mach/db8500-regs.h>
36#include <mach/id.h>
37#include "db8500-prcmu-regs.h"
38
39/* Offset for the firmware version within the TCPM */
40#define PRCMU_FW_VERSION_OFFSET 0xA4
41
42/* PRCMU project numbers, defined by PRCMU FW */
43#define PRCMU_PROJECT_ID_8500V1_0 1
44#define PRCMU_PROJECT_ID_8500V2_0 2
45#define PRCMU_PROJECT_ID_8400V2_0 3
46
47/* Index of different voltages to be used when accessing AVSData */
48#define PRCM_AVS_BASE 0x2FC
49#define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0)
50#define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1)
51#define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2)
52#define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3)
53#define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4)
54#define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5)
55#define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6)
56#define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7)
57#define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8)
58#define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9)
59#define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA)
60#define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB)
61#define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC)
62
63#define PRCM_AVS_VOLTAGE 0
64#define PRCM_AVS_VOLTAGE_MASK 0x3f
65#define PRCM_AVS_ISSLOWSTARTUP 6
66#define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP)
67#define PRCM_AVS_ISMODEENABLE 7
68#define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
69
70#define PRCM_BOOT_STATUS 0xFFF
71#define PRCM_ROMCODE_A2P 0xFFE
72#define PRCM_ROMCODE_P2A 0xFFD
73#define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */
74
75#define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
76
77#define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */
78#define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0)
79#define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1)
80#define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2)
81#define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3)
82#define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4)
83#define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5)
84#define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8)
85
86/* Req Mailboxes */
87#define PRCM_REQ_MB0 0xFDC /* 12 bytes */
88#define PRCM_REQ_MB1 0xFD0 /* 12 bytes */
89#define PRCM_REQ_MB2 0xFC0 /* 16 bytes */
90#define PRCM_REQ_MB3 0xE4C /* 372 bytes */
91#define PRCM_REQ_MB4 0xE48 /* 4 bytes */
92#define PRCM_REQ_MB5 0xE44 /* 4 bytes */
93
94/* Ack Mailboxes */
95#define PRCM_ACK_MB0 0xE08 /* 52 bytes */
96#define PRCM_ACK_MB1 0xE04 /* 4 bytes */
97#define PRCM_ACK_MB2 0xE00 /* 4 bytes */
98#define PRCM_ACK_MB3 0xDFC /* 4 bytes */
99#define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
100#define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
101
102/* Mailbox 0 headers */
103#define MB0H_POWER_STATE_TRANS 0
104#define MB0H_CONFIG_WAKEUPS_EXE 1
105#define MB0H_READ_WAKEUP_ACK 3
106#define MB0H_CONFIG_WAKEUPS_SLEEP 4
107
108#define MB0H_WAKEUP_EXE 2
109#define MB0H_WAKEUP_SLEEP 5
110
111/* Mailbox 0 REQs */
112#define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0)
113#define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1)
114#define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2)
115#define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3)
116#define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4)
117#define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8)
118
119/* Mailbox 0 ACKs */
120#define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0)
121#define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1)
122#define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4)
123#define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8)
124#define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C)
125#define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20)
126#define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
127
128/* Mailbox 1 headers */
129#define MB1H_ARM_APE_OPP 0x0
130#define MB1H_RESET_MODEM 0x2
131#define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
132#define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
133#define MB1H_RELEASE_USB_WAKEUP 0x5
134
135/* Mailbox 1 Requests */
136#define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0)
137#define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1)
138#define PRCM_REQ_MB1_APE_OPP_100_RESTORE (PRCM_REQ_MB1 + 0x4)
139#define PRCM_REQ_MB1_ARM_OPP_100_RESTORE (PRCM_REQ_MB1 + 0x8)
140
141/* Mailbox 1 ACKs */
142#define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0)
143#define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1)
144#define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
145#define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3)
146
147/* Mailbox 2 headers */
148#define MB2H_DPS 0x0
149#define MB2H_AUTO_PWR 0x1
150
151/* Mailbox 2 REQs */
152#define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0)
153#define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1)
154#define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2)
155#define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3)
156#define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4)
157#define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5)
158#define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6)
159#define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7)
160#define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8)
161#define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC)
162
163/* Mailbox 2 ACKs */
164#define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
165#define HWACC_PWR_ST_OK 0xFE
166
167/* Mailbox 3 headers */
168#define MB3H_ANC 0x0
169#define MB3H_SIDETONE 0x1
170#define MB3H_SYSCLK 0xE
171
172/* Mailbox 3 Requests */
173#define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0)
174#define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20)
175#define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60)
176#define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64)
177#define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68)
178#define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
179#define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C)
180
181/* Mailbox 4 headers */
182#define MB4H_DDR_INIT 0x0
183#define MB4H_MEM_ST 0x1
184#define MB4H_HOTDOG 0x12
185#define MB4H_HOTMON 0x13
186#define MB4H_HOT_PERIOD 0x14
187
188/* Mailbox 4 Requests */
189#define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0)
190#define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1)
191#define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3)
192#define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0)
193#define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0)
194#define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1)
195#define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2)
196#define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0)
197#define HOTMON_CONFIG_LOW BIT(0)
198#define HOTMON_CONFIG_HIGH BIT(1)
199
200/* Mailbox 5 Requests */
201#define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0)
202#define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
203#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
204#define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
205#define PRCMU_I2C_WRITE(slave) \
206 (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
207#define PRCMU_I2C_READ(slave) \
208 (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0))
209#define PRCMU_I2C_STOP_EN BIT(3)
210
211/* Mailbox 5 ACKs */
212#define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
213#define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3)
214#define I2C_WR_OK 0x1
215#define I2C_RD_OK 0x2
216
217#define NUM_MB 8
218#define MBOX_BIT BIT
219#define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
220
221/*
222 * Wakeups/IRQs
223 */
224
225#define WAKEUP_BIT_RTC BIT(0)
226#define WAKEUP_BIT_RTT0 BIT(1)
227#define WAKEUP_BIT_RTT1 BIT(2)
228#define WAKEUP_BIT_HSI0 BIT(3)
229#define WAKEUP_BIT_HSI1 BIT(4)
230#define WAKEUP_BIT_CA_WAKE BIT(5)
231#define WAKEUP_BIT_USB BIT(6)
232#define WAKEUP_BIT_ABB BIT(7)
233#define WAKEUP_BIT_ABB_FIFO BIT(8)
234#define WAKEUP_BIT_SYSCLK_OK BIT(9)
235#define WAKEUP_BIT_CA_SLEEP BIT(10)
236#define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
237#define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
238#define WAKEUP_BIT_ANC_OK BIT(13)
239#define WAKEUP_BIT_SW_ERROR BIT(14)
240#define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
241#define WAKEUP_BIT_ARM BIT(17)
242#define WAKEUP_BIT_HOTMON_LOW BIT(18)
243#define WAKEUP_BIT_HOTMON_HIGH BIT(19)
244#define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
245#define WAKEUP_BIT_GPIO0 BIT(23)
246#define WAKEUP_BIT_GPIO1 BIT(24)
247#define WAKEUP_BIT_GPIO2 BIT(25)
248#define WAKEUP_BIT_GPIO3 BIT(26)
249#define WAKEUP_BIT_GPIO4 BIT(27)
250#define WAKEUP_BIT_GPIO5 BIT(28)
251#define WAKEUP_BIT_GPIO6 BIT(29)
252#define WAKEUP_BIT_GPIO7 BIT(30)
253#define WAKEUP_BIT_GPIO8 BIT(31)
254
255/*
256 * This vector maps irq numbers to the bits in the bit field used in
257 * communication with the PRCMU firmware.
258 *
259 * The reason for having this is to keep the irq numbers contiguous even though
260 * the bits in the bit field are not. (The bits also have a tendency to move
261 * around, to further complicate matters.)
262 */
263#define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE)
264#define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
265static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
266 IRQ_ENTRY(RTC),
267 IRQ_ENTRY(RTT0),
268 IRQ_ENTRY(RTT1),
269 IRQ_ENTRY(HSI0),
270 IRQ_ENTRY(HSI1),
271 IRQ_ENTRY(CA_WAKE),
272 IRQ_ENTRY(USB),
273 IRQ_ENTRY(ABB),
274 IRQ_ENTRY(ABB_FIFO),
275 IRQ_ENTRY(CA_SLEEP),
276 IRQ_ENTRY(ARM),
277 IRQ_ENTRY(HOTMON_LOW),
278 IRQ_ENTRY(HOTMON_HIGH),
279 IRQ_ENTRY(MODEM_SW_RESET_REQ),
280 IRQ_ENTRY(GPIO0),
281 IRQ_ENTRY(GPIO1),
282 IRQ_ENTRY(GPIO2),
283 IRQ_ENTRY(GPIO3),
284 IRQ_ENTRY(GPIO4),
285 IRQ_ENTRY(GPIO5),
286 IRQ_ENTRY(GPIO6),
287 IRQ_ENTRY(GPIO7),
288 IRQ_ENTRY(GPIO8)
289};
290
291#define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
292#define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
293static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
294 WAKEUP_ENTRY(RTC),
295 WAKEUP_ENTRY(RTT0),
296 WAKEUP_ENTRY(RTT1),
297 WAKEUP_ENTRY(HSI0),
298 WAKEUP_ENTRY(HSI1),
299 WAKEUP_ENTRY(USB),
300 WAKEUP_ENTRY(ABB),
301 WAKEUP_ENTRY(ABB_FIFO),
302 WAKEUP_ENTRY(ARM)
303};
304
305/*
306 * mb0_transfer - state needed for mailbox 0 communication.
307 * @lock: The transaction lock.
308 * @dbb_events_lock: A lock used to handle concurrent access to (parts of)
309 * the request data.
310 * @mask_work: Work structure used for (un)masking wakeup interrupts.
311 * @req: Request data that need to persist between requests.
312 */
313static struct {
314 spinlock_t lock;
315 spinlock_t dbb_irqs_lock;
316 struct work_struct mask_work;
317 struct mutex ac_wake_lock;
318 struct completion ac_wake_work;
319 struct {
320 u32 dbb_irqs;
321 u32 dbb_wakeups;
322 u32 abb_events;
323 } req;
324} mb0_transfer;
325
326/*
327 * mb1_transfer - state needed for mailbox 1 communication.
328 * @lock: The transaction lock.
329 * @work: The transaction completion structure.
330 * @ack: Reply ("acknowledge") data.
331 */
332static struct {
333 struct mutex lock;
334 struct completion work;
335 struct {
336 u8 header;
337 u8 arm_opp;
338 u8 ape_opp;
339 u8 ape_voltage_status;
340 } ack;
341} mb1_transfer;
342
343/*
344 * mb2_transfer - state needed for mailbox 2 communication.
345 * @lock: The transaction lock.
346 * @work: The transaction completion structure.
347 * @auto_pm_lock: The autonomous power management configuration lock.
348 * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
349 * @req: Request data that need to persist between requests.
350 * @ack: Reply ("acknowledge") data.
351 */
352static struct {
353 struct mutex lock;
354 struct completion work;
355 spinlock_t auto_pm_lock;
356 bool auto_pm_enabled;
357 struct {
358 u8 status;
359 } ack;
360} mb2_transfer;
361
362/*
363 * mb3_transfer - state needed for mailbox 3 communication.
364 * @lock: The request lock.
365 * @sysclk_lock: A lock used to handle concurrent sysclk requests.
366 * @sysclk_work: Work structure used for sysclk requests.
367 */
368static struct {
369 spinlock_t lock;
370 struct mutex sysclk_lock;
371 struct completion sysclk_work;
372} mb3_transfer;
373
374/*
375 * mb4_transfer - state needed for mailbox 4 communication.
376 * @lock: The transaction lock.
377 * @work: The transaction completion structure.
378 */
379static struct {
380 struct mutex lock;
381 struct completion work;
382} mb4_transfer;
383
384/*
385 * mb5_transfer - state needed for mailbox 5 communication.
386 * @lock: The transaction lock.
387 * @work: The transaction completion structure.
388 * @ack: Reply ("acknowledge") data.
389 */
390static struct {
391 struct mutex lock;
392 struct completion work;
393 struct {
394 u8 status;
395 u8 value;
396 } ack;
397} mb5_transfer;
398
399static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
400
401/* Spinlocks */
402static DEFINE_SPINLOCK(clkout_lock);
403static DEFINE_SPINLOCK(gpiocr_lock);
404
405/* Global var to runtime determine TCDM base for v2 or v1 */
406static __iomem void *tcdm_base;
407
408struct clk_mgt {
409 unsigned int offset;
410 u32 pllsw;
411};
412
413static DEFINE_SPINLOCK(clk_mgt_lock);
414
415#define CLK_MGT_ENTRY(_name)[PRCMU_##_name] = { (PRCM_##_name##_MGT), 0 }
416struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
417 CLK_MGT_ENTRY(SGACLK),
418 CLK_MGT_ENTRY(UARTCLK),
419 CLK_MGT_ENTRY(MSP02CLK),
420 CLK_MGT_ENTRY(MSP1CLK),
421 CLK_MGT_ENTRY(I2CCLK),
422 CLK_MGT_ENTRY(SDMMCCLK),
423 CLK_MGT_ENTRY(SLIMCLK),
424 CLK_MGT_ENTRY(PER1CLK),
425 CLK_MGT_ENTRY(PER2CLK),
426 CLK_MGT_ENTRY(PER3CLK),
427 CLK_MGT_ENTRY(PER5CLK),
428 CLK_MGT_ENTRY(PER6CLK),
429 CLK_MGT_ENTRY(PER7CLK),
430 CLK_MGT_ENTRY(LCDCLK),
431 CLK_MGT_ENTRY(BMLCLK),
432 CLK_MGT_ENTRY(HSITXCLK),
433 CLK_MGT_ENTRY(HSIRXCLK),
434 CLK_MGT_ENTRY(HDMICLK),
435 CLK_MGT_ENTRY(APEATCLK),
436 CLK_MGT_ENTRY(APETRACECLK),
437 CLK_MGT_ENTRY(MCDECLK),
438 CLK_MGT_ENTRY(IPI2CCLK),
439 CLK_MGT_ENTRY(DSIALTCLK),
440 CLK_MGT_ENTRY(DMACLK),
441 CLK_MGT_ENTRY(B2R2CLK),
442 CLK_MGT_ENTRY(TVCLK),
443 CLK_MGT_ENTRY(SSPCLK),
444 CLK_MGT_ENTRY(RNGCLK),
445 CLK_MGT_ENTRY(UICCCLK),
446};
447
448/*
449* Used by MCDE to setup all necessary PRCMU registers
450*/
451#define PRCMU_RESET_DSIPLL 0x00004000
452#define PRCMU_UNCLAMP_DSIPLL 0x00400800
453
454#define PRCMU_CLK_PLL_DIV_SHIFT 0
455#define PRCMU_CLK_PLL_SW_SHIFT 5
456#define PRCMU_CLK_38 (1 << 9)
457#define PRCMU_CLK_38_SRC (1 << 10)
458#define PRCMU_CLK_38_DIV (1 << 11)
459
460/* PLLDIV=12, PLLSW=4 (PLLDDR) */
461#define PRCMU_DSI_CLOCK_SETTING 0x0000008C
462
463/* PLLDIV=8, PLLSW=4 (PLLDDR) */
464#define PRCMU_DSI_CLOCK_SETTING_U8400 0x00000088
465
466/* DPI 50000000 Hz */
467#define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
468 (16 << PRCMU_CLK_PLL_DIV_SHIFT))
469#define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00
470
471/* D=101, N=1, R=4, SELDIV2=0 */
472#define PRCMU_PLLDSI_FREQ_SETTING 0x00040165
473
474/* D=70, N=1, R=3, SELDIV2=0 */
475#define PRCMU_PLLDSI_FREQ_SETTING_U8400 0x00030146
476
477#define PRCMU_ENABLE_PLLDSI 0x00000001
478#define PRCMU_DISABLE_PLLDSI 0x00000000
479#define PRCMU_RELEASE_RESET_DSS 0x0000400C
480#define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202
481/* ESC clk, div0=1, div1=1, div2=3 */
482#define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101
483#define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101
484#define PRCMU_DSI_RESET_SW 0x00000007
485
486#define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
487
488static struct {
489 u8 project_number;
490 u8 api_version;
491 u8 func_version;
492 u8 errata;
493} prcmu_version;
494
495
496int prcmu_enable_dsipll(void)
497{
498 int i;
499 unsigned int plldsifreq;
500
501 /* Clear DSIPLL_RESETN */
502 writel(PRCMU_RESET_DSIPLL, (_PRCMU_BASE + PRCM_APE_RESETN_CLR));
503 /* Unclamp DSIPLL in/out */
504 writel(PRCMU_UNCLAMP_DSIPLL, (_PRCMU_BASE + PRCM_MMIP_LS_CLAMP_CLR));
505
506 if (prcmu_is_u8400())
507 plldsifreq = PRCMU_PLLDSI_FREQ_SETTING_U8400;
508 else
509 plldsifreq = PRCMU_PLLDSI_FREQ_SETTING;
510 /* Set DSI PLL FREQ */
511 writel(plldsifreq, (_PRCMU_BASE + PRCM_PLLDSI_FREQ));
512 writel(PRCMU_DSI_PLLOUT_SEL_SETTING,
513 (_PRCMU_BASE + PRCM_DSI_PLLOUT_SEL));
514 /* Enable Escape clocks */
515 writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV,
516 (_PRCMU_BASE + PRCM_DSITVCLK_DIV));
517
518 /* Start DSI PLL */
519 writel(PRCMU_ENABLE_PLLDSI, (_PRCMU_BASE + PRCM_PLLDSI_ENABLE));
520 /* Reset DSI PLL */
521 writel(PRCMU_DSI_RESET_SW, (_PRCMU_BASE + PRCM_DSI_SW_RESET));
522 for (i = 0; i < 10; i++) {
523 if ((readl(_PRCMU_BASE + PRCM_PLLDSI_LOCKP) &
524 PRCMU_PLLDSI_LOCKP_LOCKED)
525 == PRCMU_PLLDSI_LOCKP_LOCKED)
526 break;
527 udelay(100);
528 }
529 /* Set DSIPLL_RESETN */
530 writel(PRCMU_RESET_DSIPLL, (_PRCMU_BASE + PRCM_APE_RESETN_SET));
531 return 0;
532}
533
534int prcmu_disable_dsipll(void)
535{
536 /* Disable dsi pll */
537 writel(PRCMU_DISABLE_PLLDSI, (_PRCMU_BASE + PRCM_PLLDSI_ENABLE));
538 /* Disable escapeclock */
539 writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV,
540 (_PRCMU_BASE + PRCM_DSITVCLK_DIV));
541 return 0;
542}
543
544int prcmu_set_display_clocks(void)
545{
546 unsigned long flags;
547 unsigned int dsiclk;
548
549 if (prcmu_is_u8400())
550 dsiclk = PRCMU_DSI_CLOCK_SETTING_U8400;
551 else
552 dsiclk = PRCMU_DSI_CLOCK_SETTING;
553
554 spin_lock_irqsave(&clk_mgt_lock, flags);
555
556 /* Grab the HW semaphore. */
557 while ((readl(_PRCMU_BASE + PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
558 cpu_relax();
559
560 writel(dsiclk, (_PRCMU_BASE + PRCM_HDMICLK_MGT));
561 writel(PRCMU_DSI_LP_CLOCK_SETTING, (_PRCMU_BASE + PRCM_TVCLK_MGT));
562 writel(PRCMU_DPI_CLOCK_SETTING, (_PRCMU_BASE + PRCM_LCDCLK_MGT));
563
564 /* Release the HW semaphore. */
565 writel(0, (_PRCMU_BASE + PRCM_SEM));
566
567 spin_unlock_irqrestore(&clk_mgt_lock, flags);
568
569 return 0;
570}
571
572/**
573 * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
574 */
575void prcmu_enable_spi2(void)
576{
577 u32 reg;
578 unsigned long flags;
579
580 spin_lock_irqsave(&gpiocr_lock, flags);
581 reg = readl(_PRCMU_BASE + PRCM_GPIOCR);
582 writel(reg | PRCM_GPIOCR_SPI2_SELECT, _PRCMU_BASE + PRCM_GPIOCR);
583 spin_unlock_irqrestore(&gpiocr_lock, flags);
584}
585
586/**
587 * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1.
588 */
589void prcmu_disable_spi2(void)
590{
591 u32 reg;
592 unsigned long flags;
593
594 spin_lock_irqsave(&gpiocr_lock, flags);
595 reg = readl(_PRCMU_BASE + PRCM_GPIOCR);
596 writel(reg & ~PRCM_GPIOCR_SPI2_SELECT, _PRCMU_BASE + PRCM_GPIOCR);
597 spin_unlock_irqrestore(&gpiocr_lock, flags);
598}
599
600bool prcmu_has_arm_maxopp(void)
601{
602 return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
603 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
604}
605
606bool prcmu_is_u8400(void)
607{
608 return prcmu_version.project_number == PRCMU_PROJECT_ID_8400V2_0;
609}
610
611/**
612 * prcmu_get_boot_status - PRCMU boot status checking
613 * Returns: the current PRCMU boot status
614 */
615int prcmu_get_boot_status(void)
616{
617 return readb(tcdm_base + PRCM_BOOT_STATUS);
618}
619
620/**
621 * prcmu_set_rc_a2p - This function is used to run few power state sequences
622 * @val: Value to be set, i.e. transition requested
623 * Returns: 0 on success, -EINVAL on invalid argument
624 *
625 * This function is used to run the following power state sequences -
626 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
627 */
628int prcmu_set_rc_a2p(enum romcode_write val)
629{
630 if (val < RDY_2_DS || val > RDY_2_XP70_RST)
631 return -EINVAL;
632 writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
633 return 0;
634}
635
636/**
637 * prcmu_get_rc_p2a - This function is used to get power state sequences
638 * Returns: the power transition that has last happened
639 *
640 * This function can return the following transitions-
641 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
642 */
643enum romcode_read prcmu_get_rc_p2a(void)
644{
645 return readb(tcdm_base + PRCM_ROMCODE_P2A);
646}
647
648/**
649 * prcmu_get_current_mode - Return the current XP70 power mode
650 * Returns: Returns the current AP(ARM) power mode: init,
651 * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
652 */
653enum ap_pwrst prcmu_get_xp70_current_state(void)
654{
655 return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
656}
657
658/**
659 * prcmu_config_clkout - Configure one of the programmable clock outputs.
660 * @clkout: The CLKOUT number (0 or 1).
661 * @source: The clock to be used (one of the PRCMU_CLKSRC_*).
662 * @div: The divider to be applied.
663 *
664 * Configures one of the programmable clock outputs (CLKOUTs).
665 * @div should be in the range [1,63] to request a configuration, or 0 to
666 * inform that the configuration is no longer requested.
667 */
668int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
669{
670 static int requests[2];
671 int r = 0;
672 unsigned long flags;
673 u32 val;
674 u32 bits;
675 u32 mask;
676 u32 div_mask;
677
678 BUG_ON(clkout > 1);
679 BUG_ON(div > 63);
680 BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
681
682 if (!div && !requests[clkout])
683 return -EINVAL;
684
685 switch (clkout) {
686 case 0:
687 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
688 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
689 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
690 (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
691 break;
692 case 1:
693 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
694 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
695 PRCM_CLKOCR_CLK1TYPE);
696 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
697 (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
698 break;
699 }
700 bits &= mask;
701
702 spin_lock_irqsave(&clkout_lock, flags);
703
704 val = readl(_PRCMU_BASE + PRCM_CLKOCR);
705 if (val & div_mask) {
706 if (div) {
707 if ((val & mask) != bits) {
708 r = -EBUSY;
709 goto unlock_and_return;
710 }
711 } else {
712 if ((val & mask & ~div_mask) != bits) {
713 r = -EINVAL;
714 goto unlock_and_return;
715 }
716 }
717 }
718 writel((bits | (val & ~mask)), (_PRCMU_BASE + PRCM_CLKOCR));
719 requests[clkout] += (div ? 1 : -1);
720
721unlock_and_return:
722 spin_unlock_irqrestore(&clkout_lock, flags);
723
724 return r;
725}
726
727int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
728{
729 unsigned long flags;
730
731 BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
732
733 spin_lock_irqsave(&mb0_transfer.lock, flags);
734
735 while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
736 cpu_relax();
737
738 writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
739 writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
740 writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
741 writeb((keep_ulp_clk ? 1 : 0),
742 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
743 writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
744 writel(MBOX_BIT(0), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
745
746 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
747
748 return 0;
749}
750
751/* This function should only be called while mb0_transfer.lock is held. */
752static void config_wakeups(void)
753{
754 const u8 header[2] = {
755 MB0H_CONFIG_WAKEUPS_EXE,
756 MB0H_CONFIG_WAKEUPS_SLEEP
757 };
758 static u32 last_dbb_events;
759 static u32 last_abb_events;
760 u32 dbb_events;
761 u32 abb_events;
762 unsigned int i;
763
764 dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
765 dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
766
767 abb_events = mb0_transfer.req.abb_events;
768
769 if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
770 return;
771
772 for (i = 0; i < 2; i++) {
773 while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
774 cpu_relax();
775 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
776 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
777 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
778 writel(MBOX_BIT(0), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
779 }
780 last_dbb_events = dbb_events;
781 last_abb_events = abb_events;
782}
783
784void prcmu_enable_wakeups(u32 wakeups)
785{
786 unsigned long flags;
787 u32 bits;
788 int i;
789
790 BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
791
792 for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
793 if (wakeups & BIT(i))
794 bits |= prcmu_wakeup_bit[i];
795 }
796
797 spin_lock_irqsave(&mb0_transfer.lock, flags);
798
799 mb0_transfer.req.dbb_wakeups = bits;
800 config_wakeups();
801
802 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
803}
804
805void prcmu_config_abb_event_readout(u32 abb_events)
806{
807 unsigned long flags;
808
809 spin_lock_irqsave(&mb0_transfer.lock, flags);
810
811 mb0_transfer.req.abb_events = abb_events;
812 config_wakeups();
813
814 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
815}
816
817void prcmu_get_abb_event_buffer(void __iomem **buf)
818{
819 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
820 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
821 else
822 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
823}
824
825/**
826 * prcmu_set_arm_opp - set the appropriate ARM OPP
827 * @opp: The new ARM operating point to which transition is to be made
828 * Returns: 0 on success, non-zero on failure
829 *
830 * This function sets the the operating point of the ARM.
831 */
832int prcmu_set_arm_opp(u8 opp)
833{
834 int r;
835
836 if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
837 return -EINVAL;
838
839 r = 0;
840
841 mutex_lock(&mb1_transfer.lock);
842
843 while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
844 cpu_relax();
845
846 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
847 writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
848 writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
849
850 writel(MBOX_BIT(1), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
851 wait_for_completion(&mb1_transfer.work);
852
853 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
854 (mb1_transfer.ack.arm_opp != opp))
855 r = -EIO;
856
857 mutex_unlock(&mb1_transfer.lock);
858
859 return r;
860}
861
862/**
863 * prcmu_get_arm_opp - get the current ARM OPP
864 *
865 * Returns: the current ARM OPP
866 */
867int prcmu_get_arm_opp(void)
868{
869 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
870}
871
872/**
873 * prcmu_get_ddr_opp - get the current DDR OPP
874 *
875 * Returns: the current DDR OPP
876 */
877int prcmu_get_ddr_opp(void)
878{
879 return readb(_PRCMU_BASE + PRCM_DDR_SUBSYS_APE_MINBW);
880}
881
882/**
883 * set_ddr_opp - set the appropriate DDR OPP
884 * @opp: The new DDR operating point to which transition is to be made
885 * Returns: 0 on success, non-zero on failure
886 *
887 * This function sets the operating point of the DDR.
888 */
889int prcmu_set_ddr_opp(u8 opp)
890{
891 if (opp < DDR_100_OPP || opp > DDR_25_OPP)
892 return -EINVAL;
893 /* Changing the DDR OPP can hang the hardware pre-v21 */
894 if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20())
895 writeb(opp, (_PRCMU_BASE + PRCM_DDR_SUBSYS_APE_MINBW));
896
897 return 0;
898}
899/**
900 * set_ape_opp - set the appropriate APE OPP
901 * @opp: The new APE operating point to which transition is to be made
902 * Returns: 0 on success, non-zero on failure
903 *
904 * This function sets the operating point of the APE.
905 */
906int prcmu_set_ape_opp(u8 opp)
907{
908 int r = 0;
909
910 mutex_lock(&mb1_transfer.lock);
911
912 while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
913 cpu_relax();
914
915 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
916 writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
917 writeb(opp, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
918
919 writel(MBOX_BIT(1), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
920 wait_for_completion(&mb1_transfer.work);
921
922 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
923 (mb1_transfer.ack.ape_opp != opp))
924 r = -EIO;
925
926 mutex_unlock(&mb1_transfer.lock);
927
928 return r;
929}
930
931/**
932 * prcmu_get_ape_opp - get the current APE OPP
933 *
934 * Returns: the current APE OPP
935 */
936int prcmu_get_ape_opp(void)
937{
938 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
939}
940
941/**
942 * prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
943 * @enable: true to request the higher voltage, false to drop a request.
944 *
945 * Calls to this function to enable and disable requests must be balanced.
946 */
947int prcmu_request_ape_opp_100_voltage(bool enable)
948{
949 int r = 0;
950 u8 header;
951 static unsigned int requests;
952
953 mutex_lock(&mb1_transfer.lock);
954
955 if (enable) {
956 if (0 != requests++)
957 goto unlock_and_return;
958 header = MB1H_REQUEST_APE_OPP_100_VOLT;
959 } else {
960 if (requests == 0) {
961 r = -EIO;
962 goto unlock_and_return;
963 } else if (1 != requests--) {
964 goto unlock_and_return;
965 }
966 header = MB1H_RELEASE_APE_OPP_100_VOLT;
967 }
968
969 while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
970 cpu_relax();
971
972 writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
973
974 writel(MBOX_BIT(1), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
975 wait_for_completion(&mb1_transfer.work);
976
977 if ((mb1_transfer.ack.header != header) ||
978 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
979 r = -EIO;
980
981unlock_and_return:
982 mutex_unlock(&mb1_transfer.lock);
983
984 return r;
985}
986
987/**
988 * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
989 *
990 * This function releases the power state requirements of a USB wakeup.
991 */
992int prcmu_release_usb_wakeup_state(void)
993{
994 int r = 0;
995
996 mutex_lock(&mb1_transfer.lock);
997
998 while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
999 cpu_relax();
1000
1001 writeb(MB1H_RELEASE_USB_WAKEUP,
1002 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1003
1004 writel(MBOX_BIT(1), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
1005 wait_for_completion(&mb1_transfer.work);
1006
1007 if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1008 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1009 r = -EIO;
1010
1011 mutex_unlock(&mb1_transfer.lock);
1012
1013 return r;
1014}
1015
1016/**
1017 * prcmu_set_epod - set the state of a EPOD (power domain)
1018 * @epod_id: The EPOD to set
1019 * @epod_state: The new EPOD state
1020 *
1021 * This function sets the state of a EPOD (power domain). It may not be called
1022 * from interrupt context.
1023 */
1024int prcmu_set_epod(u16 epod_id, u8 epod_state)
1025{
1026 int r = 0;
1027 bool ram_retention = false;
1028 int i;
1029
1030 /* check argument */
1031 BUG_ON(epod_id >= NUM_EPOD_ID);
1032
1033 /* set flag if retention is possible */
1034 switch (epod_id) {
1035 case EPOD_ID_SVAMMDSP:
1036 case EPOD_ID_SIAMMDSP:
1037 case EPOD_ID_ESRAM12:
1038 case EPOD_ID_ESRAM34:
1039 ram_retention = true;
1040 break;
1041 }
1042
1043 /* check argument */
1044 BUG_ON(epod_state > EPOD_STATE_ON);
1045 BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1046
1047 /* get lock */
1048 mutex_lock(&mb2_transfer.lock);
1049
1050 /* wait for mailbox */
1051 while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
1052 cpu_relax();
1053
1054 /* fill in mailbox */
1055 for (i = 0; i < NUM_EPOD_ID; i++)
1056 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1057 writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1058
1059 writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1060
1061 writel(MBOX_BIT(2), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
1062
1063 /*
1064 * The current firmware version does not handle errors correctly,
1065 * and we cannot recover if there is an error.
1066 * This is expected to change when the firmware is updated.
1067 */
1068 if (!wait_for_completion_timeout(&mb2_transfer.work,
1069 msecs_to_jiffies(20000))) {
1070 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1071 __func__);
1072 r = -EIO;
1073 goto unlock_and_return;
1074 }
1075
1076 if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1077 r = -EIO;
1078
1079unlock_and_return:
1080 mutex_unlock(&mb2_transfer.lock);
1081 return r;
1082}
1083
1084/**
1085 * prcmu_configure_auto_pm - Configure autonomous power management.
1086 * @sleep: Configuration for ApSleep.
1087 * @idle: Configuration for ApIdle.
1088 */
1089void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1090 struct prcmu_auto_pm_config *idle)
1091{
1092 u32 sleep_cfg;
1093 u32 idle_cfg;
1094 unsigned long flags;
1095
1096 BUG_ON((sleep == NULL) || (idle == NULL));
1097
1098 sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1099 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1100 sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1101 sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1102 sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1103 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1104
1105 idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1106 idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1107 idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1108 idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1109 idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1110 idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1111
1112 spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1113
1114 /*
1115 * The autonomous power management configuration is done through
1116 * fields in mailbox 2, but these fields are only used as shared
1117 * variables - i.e. there is no need to send a message.
1118 */
1119 writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1120 writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1121
1122 mb2_transfer.auto_pm_enabled =
1123 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1124 (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1125 (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1126 (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1127
1128 spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1129}
1130EXPORT_SYMBOL(prcmu_configure_auto_pm);
1131
1132bool prcmu_is_auto_pm_enabled(void)
1133{
1134 return mb2_transfer.auto_pm_enabled;
1135}
1136
1137static int request_sysclk(bool enable)
1138{
1139 int r;
1140 unsigned long flags;
1141
1142 r = 0;
1143
1144 mutex_lock(&mb3_transfer.sysclk_lock);
1145
1146 spin_lock_irqsave(&mb3_transfer.lock, flags);
1147
1148 while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
1149 cpu_relax();
1150
1151 writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1152
1153 writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1154 writel(MBOX_BIT(3), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
1155
1156 spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1157
1158 /*
1159 * The firmware only sends an ACK if we want to enable the
1160 * SysClk, and it succeeds.
1161 */
1162 if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1163 msecs_to_jiffies(20000))) {
1164 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1165 __func__);
1166 r = -EIO;
1167 }
1168
1169 mutex_unlock(&mb3_transfer.sysclk_lock);
1170
1171 return r;
1172}
1173
1174static int request_timclk(bool enable)
1175{
1176 u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1177
1178 if (!enable)
1179 val |= PRCM_TCR_STOP_TIMERS;
1180 writel(val, (_PRCMU_BASE + PRCM_TCR));
1181
1182 return 0;
1183}
1184
1185static int request_reg_clock(u8 clock, bool enable)
1186{
1187 u32 val;
1188 unsigned long flags;
1189
1190 spin_lock_irqsave(&clk_mgt_lock, flags);
1191
1192 /* Grab the HW semaphore. */
1193 while ((readl(_PRCMU_BASE + PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1194 cpu_relax();
1195
1196 val = readl(_PRCMU_BASE + clk_mgt[clock].offset);
1197 if (enable) {
1198 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1199 } else {
1200 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1201 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1202 }
1203 writel(val, (_PRCMU_BASE + clk_mgt[clock].offset));
1204
1205 /* Release the HW semaphore. */
1206 writel(0, (_PRCMU_BASE + PRCM_SEM));
1207
1208 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1209
1210 return 0;
1211}
1212
1213/**
1214 * prcmu_request_clock() - Request for a clock to be enabled or disabled.
1215 * @clock: The clock for which the request is made.
1216 * @enable: Whether the clock should be enabled (true) or disabled (false).
1217 *
1218 * This function should only be used by the clock implementation.
1219 * Do not use it from any other place!
1220 */
1221int prcmu_request_clock(u8 clock, bool enable)
1222{
1223 if (clock < PRCMU_NUM_REG_CLOCKS)
1224 return request_reg_clock(clock, enable);
1225 else if (clock == PRCMU_TIMCLK)
1226 return request_timclk(enable);
1227 else if (clock == PRCMU_SYSCLK)
1228 return request_sysclk(enable);
1229 else
1230 return -EINVAL;
1231}
1232
1233int prcmu_config_esram0_deep_sleep(u8 state)
1234{
1235 if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
1236 (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
1237 return -EINVAL;
1238
1239 mutex_lock(&mb4_transfer.lock);
1240
1241 while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
1242 cpu_relax();
1243
1244 writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1245 writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
1246 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
1247 writeb(DDR_PWR_STATE_ON,
1248 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
1249 writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
1250
1251 writel(MBOX_BIT(4), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
1252 wait_for_completion(&mb4_transfer.work);
1253
1254 mutex_unlock(&mb4_transfer.lock);
1255
1256 return 0;
1257}
1258
1259int prcmu_config_hotdog(u8 threshold)
1260{
1261 mutex_lock(&mb4_transfer.lock);
1262
1263 while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
1264 cpu_relax();
1265
1266 writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
1267 writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1268
1269 writel(MBOX_BIT(4), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
1270 wait_for_completion(&mb4_transfer.work);
1271
1272 mutex_unlock(&mb4_transfer.lock);
1273
1274 return 0;
1275}
1276
1277int prcmu_config_hotmon(u8 low, u8 high)
1278{
1279 mutex_lock(&mb4_transfer.lock);
1280
1281 while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
1282 cpu_relax();
1283
1284 writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
1285 writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
1286 writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
1287 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
1288 writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1289
1290 writel(MBOX_BIT(4), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
1291 wait_for_completion(&mb4_transfer.work);
1292
1293 mutex_unlock(&mb4_transfer.lock);
1294
1295 return 0;
1296}
1297
1298static int config_hot_period(u16 val)
1299{
1300 mutex_lock(&mb4_transfer.lock);
1301
1302 while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
1303 cpu_relax();
1304
1305 writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
1306 writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1307
1308 writel(MBOX_BIT(4), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
1309 wait_for_completion(&mb4_transfer.work);
1310
1311 mutex_unlock(&mb4_transfer.lock);
1312
1313 return 0;
1314}
1315
1316int prcmu_start_temp_sense(u16 cycles32k)
1317{
1318 if (cycles32k == 0xFFFF)
1319 return -EINVAL;
1320
1321 return config_hot_period(cycles32k);
1322}
1323
1324int prcmu_stop_temp_sense(void)
1325{
1326 return config_hot_period(0xFFFF);
1327}
1328
1329/**
1330 * prcmu_set_clock_divider() - Configure the clock divider.
1331 * @clock: The clock for which the request is made.
1332 * @divider: The clock divider. (< 32)
1333 *
1334 * This function should only be used by the clock implementation.
1335 * Do not use it from any other place!
1336 */
1337int prcmu_set_clock_divider(u8 clock, u8 divider)
1338{
1339 u32 val;
1340 unsigned long flags;
1341
1342 if ((clock >= PRCMU_NUM_REG_CLOCKS) || (divider < 1) || (31 < divider))
1343 return -EINVAL;
1344
1345 spin_lock_irqsave(&clk_mgt_lock, flags);
1346
1347 /* Grab the HW semaphore. */
1348 while ((readl(_PRCMU_BASE + PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1349 cpu_relax();
1350
1351 val = readl(_PRCMU_BASE + clk_mgt[clock].offset);
1352 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK);
1353 val |= (u32)divider;
1354 writel(val, (_PRCMU_BASE + clk_mgt[clock].offset));
1355
1356 /* Release the HW semaphore. */
1357 writel(0, (_PRCMU_BASE + PRCM_SEM));
1358
1359 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1360
1361 return 0;
1362}
1363
1364/**
1365 * prcmu_abb_read() - Read register value(s) from the ABB.
1366 * @slave: The I2C slave address.
1367 * @reg: The (start) register address.
1368 * @value: The read out value(s).
1369 * @size: The number of registers to read.
1370 *
1371 * Reads register value(s) from the ABB.
1372 * @size has to be 1 for the current firmware version.
1373 */
1374int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
1375{
1376 int r;
1377
1378 if (size != 1)
1379 return -EINVAL;
1380
1381 mutex_lock(&mb5_transfer.lock);
1382
1383 while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
1384 cpu_relax();
1385
1386 writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
1387 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
1388 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
1389 writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
1390
1391 writel(MBOX_BIT(5), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
1392
1393 if (!wait_for_completion_timeout(&mb5_transfer.work,
1394 msecs_to_jiffies(20000))) {
1395 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1396 __func__);
1397 r = -EIO;
1398 } else {
1399 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
1400 }
1401
1402 if (!r)
1403 *value = mb5_transfer.ack.value;
1404
1405 mutex_unlock(&mb5_transfer.lock);
1406
1407 return r;
1408}
1409
1410/**
1411 * prcmu_abb_write() - Write register value(s) to the ABB.
1412 * @slave: The I2C slave address.
1413 * @reg: The (start) register address.
1414 * @value: The value(s) to write.
1415 * @size: The number of registers to write.
1416 *
1417 * Reads register value(s) from the ABB.
1418 * @size has to be 1 for the current firmware version.
1419 */
1420int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
1421{
1422 int r;
1423
1424 if (size != 1)
1425 return -EINVAL;
1426
1427 mutex_lock(&mb5_transfer.lock);
1428
1429 while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
1430 cpu_relax();
1431
1432 writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
1433 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
1434 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
1435 writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
1436
1437 writel(MBOX_BIT(5), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
1438
1439 if (!wait_for_completion_timeout(&mb5_transfer.work,
1440 msecs_to_jiffies(20000))) {
1441 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1442 __func__);
1443 r = -EIO;
1444 } else {
1445 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
1446 }
1447
1448 mutex_unlock(&mb5_transfer.lock);
1449
1450 return r;
1451}
1452
1453/**
1454 * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
1455 */
1456void prcmu_ac_wake_req(void)
1457{
1458 u32 val;
1459
1460 mutex_lock(&mb0_transfer.ac_wake_lock);
1461
1462 val = readl(_PRCMU_BASE + PRCM_HOSTACCESS_REQ);
1463 if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
1464 goto unlock_and_return;
1465
1466 atomic_set(&ac_wake_req_state, 1);
1467
1468 writel((val | PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
1469 (_PRCMU_BASE + PRCM_HOSTACCESS_REQ));
1470
1471 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
1472 msecs_to_jiffies(20000))) {
1473 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1474 __func__);
1475 }
1476
1477unlock_and_return:
1478 mutex_unlock(&mb0_transfer.ac_wake_lock);
1479}
1480
1481/**
1482 * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
1483 */
1484void prcmu_ac_sleep_req()
1485{
1486 u32 val;
1487
1488 mutex_lock(&mb0_transfer.ac_wake_lock);
1489
1490 val = readl(_PRCMU_BASE + PRCM_HOSTACCESS_REQ);
1491 if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
1492 goto unlock_and_return;
1493
1494 writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
1495 (_PRCMU_BASE + PRCM_HOSTACCESS_REQ));
1496
1497 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
1498 msecs_to_jiffies(20000))) {
1499 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1500 __func__);
1501 }
1502
1503 atomic_set(&ac_wake_req_state, 0);
1504
1505unlock_and_return:
1506 mutex_unlock(&mb0_transfer.ac_wake_lock);
1507}
1508
1509bool prcmu_is_ac_wake_requested(void)
1510{
1511 return (atomic_read(&ac_wake_req_state) != 0);
1512}
1513
1514/**
1515 * prcmu_system_reset - System reset
1516 *
1517 * Saves the reset reason code and then sets the APE_SOFRST register which
1518 * fires interrupt to fw
1519 */
1520void prcmu_system_reset(u16 reset_code)
1521{
1522 writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
1523 writel(1, (_PRCMU_BASE + PRCM_APE_SOFTRST));
1524}
1525
1526/**
1527 * prcmu_reset_modem - ask the PRCMU to reset modem
1528 */
1529void prcmu_modem_reset(void)
1530{
1531 mutex_lock(&mb1_transfer.lock);
1532
1533 while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1534 cpu_relax();
1535
1536 writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1537 writel(MBOX_BIT(1), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
1538 wait_for_completion(&mb1_transfer.work);
1539
1540 /*
1541 * No need to check return from PRCMU as modem should go in reset state
1542 * This state is already managed by upper layer
1543 */
1544
1545 mutex_unlock(&mb1_transfer.lock);
1546}
1547
1548static void ack_dbb_wakeup(void)
1549{
1550 unsigned long flags;
1551
1552 spin_lock_irqsave(&mb0_transfer.lock, flags);
1553
1554 while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
1555 cpu_relax();
1556
1557 writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
1558 writel(MBOX_BIT(0), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
1559
1560 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
1561}
1562
1563static inline void print_unknown_header_warning(u8 n, u8 header)
1564{
1565 pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
1566 header, n);
1567}
1568
1569static bool read_mailbox_0(void)
1570{
1571 bool r;
1572 u32 ev;
1573 unsigned int n;
1574 u8 header;
1575
1576 header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
1577 switch (header) {
1578 case MB0H_WAKEUP_EXE:
1579 case MB0H_WAKEUP_SLEEP:
1580 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
1581 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
1582 else
1583 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
1584
1585 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
1586 complete(&mb0_transfer.ac_wake_work);
1587 if (ev & WAKEUP_BIT_SYSCLK_OK)
1588 complete(&mb3_transfer.sysclk_work);
1589
1590 ev &= mb0_transfer.req.dbb_irqs;
1591
1592 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
1593 if (ev & prcmu_irq_bit[n])
1594 generic_handle_irq(IRQ_PRCMU_BASE + n);
1595 }
1596 r = true;
1597 break;
1598 default:
1599 print_unknown_header_warning(0, header);
1600 r = false;
1601 break;
1602 }
1603 writel(MBOX_BIT(0), (_PRCMU_BASE + PRCM_ARM_IT1_CLR));
1604 return r;
1605}
1606
1607static bool read_mailbox_1(void)
1608{
1609 mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
1610 mb1_transfer.ack.arm_opp = readb(tcdm_base +
1611 PRCM_ACK_MB1_CURRENT_ARM_OPP);
1612 mb1_transfer.ack.ape_opp = readb(tcdm_base +
1613 PRCM_ACK_MB1_CURRENT_APE_OPP);
1614 mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
1615 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
1616 writel(MBOX_BIT(1), (_PRCMU_BASE + PRCM_ARM_IT1_CLR));
1617 complete(&mb1_transfer.work);
1618 return false;
1619}
1620
1621static bool read_mailbox_2(void)
1622{
1623 mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
1624 writel(MBOX_BIT(2), (_PRCMU_BASE + PRCM_ARM_IT1_CLR));
1625 complete(&mb2_transfer.work);
1626 return false;
1627}
1628
1629static bool read_mailbox_3(void)
1630{
1631 writel(MBOX_BIT(3), (_PRCMU_BASE + PRCM_ARM_IT1_CLR));
1632 return false;
1633}
1634
1635static bool read_mailbox_4(void)
1636{
1637 u8 header;
1638 bool do_complete = true;
1639
1640 header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
1641 switch (header) {
1642 case MB4H_MEM_ST:
1643 case MB4H_HOTDOG:
1644 case MB4H_HOTMON:
1645 case MB4H_HOT_PERIOD:
1646 break;
1647 default:
1648 print_unknown_header_warning(4, header);
1649 do_complete = false;
1650 break;
1651 }
1652
1653 writel(MBOX_BIT(4), (_PRCMU_BASE + PRCM_ARM_IT1_CLR));
1654
1655 if (do_complete)
1656 complete(&mb4_transfer.work);
1657
1658 return false;
1659}
1660
1661static bool read_mailbox_5(void)
1662{
1663 mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
1664 mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
1665 writel(MBOX_BIT(5), (_PRCMU_BASE + PRCM_ARM_IT1_CLR));
1666 complete(&mb5_transfer.work);
1667 return false;
1668}
1669
1670static bool read_mailbox_6(void)
1671{
1672 writel(MBOX_BIT(6), (_PRCMU_BASE + PRCM_ARM_IT1_CLR));
1673 return false;
1674}
1675
1676static bool read_mailbox_7(void)
1677{
1678 writel(MBOX_BIT(7), (_PRCMU_BASE + PRCM_ARM_IT1_CLR));
1679 return false;
1680}
1681
1682static bool (* const read_mailbox[NUM_MB])(void) = {
1683 read_mailbox_0,
1684 read_mailbox_1,
1685 read_mailbox_2,
1686 read_mailbox_3,
1687 read_mailbox_4,
1688 read_mailbox_5,
1689 read_mailbox_6,
1690 read_mailbox_7
1691};
1692
1693static irqreturn_t prcmu_irq_handler(int irq, void *data)
1694{
1695 u32 bits;
1696 u8 n;
1697 irqreturn_t r;
1698
1699 bits = (readl(_PRCMU_BASE + PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
1700 if (unlikely(!bits))
1701 return IRQ_NONE;
1702
1703 r = IRQ_HANDLED;
1704 for (n = 0; bits; n++) {
1705 if (bits & MBOX_BIT(n)) {
1706 bits -= MBOX_BIT(n);
1707 if (read_mailbox[n]())
1708 r = IRQ_WAKE_THREAD;
1709 }
1710 }
1711 return r;
1712}
1713
1714static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
1715{
1716 ack_dbb_wakeup();
1717 return IRQ_HANDLED;
1718}
1719
1720static void prcmu_mask_work(struct work_struct *work)
1721{
1722 unsigned long flags;
1723
1724 spin_lock_irqsave(&mb0_transfer.lock, flags);
1725
1726 config_wakeups();
1727
1728 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
1729}
1730
1731static void prcmu_irq_mask(struct irq_data *d)
1732{
1733 unsigned long flags;
1734
1735 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
1736
1737 mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
1738
1739 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
1740
1741 if (d->irq != IRQ_PRCMU_CA_SLEEP)
1742 schedule_work(&mb0_transfer.mask_work);
1743}
1744
1745static void prcmu_irq_unmask(struct irq_data *d)
1746{
1747 unsigned long flags;
1748
1749 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
1750
1751 mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
1752
1753 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
1754
1755 if (d->irq != IRQ_PRCMU_CA_SLEEP)
1756 schedule_work(&mb0_transfer.mask_work);
1757}
1758
1759static void noop(struct irq_data *d)
1760{
1761}
1762
1763static struct irq_chip prcmu_irq_chip = {
1764 .name = "prcmu",
1765 .irq_disable = prcmu_irq_mask,
1766 .irq_ack = noop,
1767 .irq_mask = prcmu_irq_mask,
1768 .irq_unmask = prcmu_irq_unmask,
1769};
1770
1771void __init prcmu_early_init(void)
1772{
1773 unsigned int i;
1774
1775 if (cpu_is_u8500v1()) {
1776 tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE_V1);
1777 } else if (cpu_is_u8500v2()) {
1778 void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K);
1779
1780 if (tcpm_base != NULL) {
1781 int version;
1782 version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET);
1783 prcmu_version.project_number = version & 0xFF;
1784 prcmu_version.api_version = (version >> 8) & 0xFF;
1785 prcmu_version.func_version = (version >> 16) & 0xFF;
1786 prcmu_version.errata = (version >> 24) & 0xFF;
1787 pr_info("PRCMU firmware version %d.%d.%d\n",
1788 (version >> 8) & 0xFF, (version >> 16) & 0xFF,
1789 (version >> 24) & 0xFF);
1790 iounmap(tcpm_base);
1791 }
1792
1793 tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
1794 } else {
1795 pr_err("prcmu: Unsupported chip version\n");
1796 BUG();
1797 }
1798
1799 spin_lock_init(&mb0_transfer.lock);
1800 spin_lock_init(&mb0_transfer.dbb_irqs_lock);
1801 mutex_init(&mb0_transfer.ac_wake_lock);
1802 init_completion(&mb0_transfer.ac_wake_work);
1803 mutex_init(&mb1_transfer.lock);
1804 init_completion(&mb1_transfer.work);
1805 mutex_init(&mb2_transfer.lock);
1806 init_completion(&mb2_transfer.work);
1807 spin_lock_init(&mb2_transfer.auto_pm_lock);
1808 spin_lock_init(&mb3_transfer.lock);
1809 mutex_init(&mb3_transfer.sysclk_lock);
1810 init_completion(&mb3_transfer.sysclk_work);
1811 mutex_init(&mb4_transfer.lock);
1812 init_completion(&mb4_transfer.work);
1813 mutex_init(&mb5_transfer.lock);
1814 init_completion(&mb5_transfer.work);
1815
1816 INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
1817
1818 /* Initalize irqs. */
1819 for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) {
1820 unsigned int irq;
1821
1822 irq = IRQ_PRCMU_BASE + i;
1823 irq_set_chip_and_handler(irq, &prcmu_irq_chip,
1824 handle_simple_irq);
1825 set_irq_flags(irq, IRQF_VALID);
1826 }
1827}
1828
1829/*
1830 * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
1831 */
1832static struct regulator_consumer_supply db8500_vape_consumers[] = {
1833 REGULATOR_SUPPLY("v-ape", NULL),
1834 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
1835 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
1836 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
1837 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
1838 /* "v-mmc" changed to "vcore" in the mainline kernel */
1839 REGULATOR_SUPPLY("vcore", "sdi0"),
1840 REGULATOR_SUPPLY("vcore", "sdi1"),
1841 REGULATOR_SUPPLY("vcore", "sdi2"),
1842 REGULATOR_SUPPLY("vcore", "sdi3"),
1843 REGULATOR_SUPPLY("vcore", "sdi4"),
1844 REGULATOR_SUPPLY("v-dma", "dma40.0"),
1845 REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
1846 /* "v-uart" changed to "vcore" in the mainline kernel */
1847 REGULATOR_SUPPLY("vcore", "uart0"),
1848 REGULATOR_SUPPLY("vcore", "uart1"),
1849 REGULATOR_SUPPLY("vcore", "uart2"),
1850 REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
1851};
1852
1853static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
1854 /* CG2900 and CW1200 power to off-chip peripherals */
1855 REGULATOR_SUPPLY("gbf_1v8", "cg2900-uart.0"),
1856 REGULATOR_SUPPLY("wlan_1v8", "cw1200.0"),
1857 REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
1858 /* AV8100 regulator */
1859 REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
1860};
1861
1862static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
1863 REGULATOR_SUPPLY("vsupply", "b2r2.0"),
1864 REGULATOR_SUPPLY("vsupply", "mcde.0"),
1865};
1866
1867static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
1868 [DB8500_REGULATOR_VAPE] = {
1869 .constraints = {
1870 .name = "db8500-vape",
1871 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1872 },
1873 .consumer_supplies = db8500_vape_consumers,
1874 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
1875 },
1876 [DB8500_REGULATOR_VARM] = {
1877 .constraints = {
1878 .name = "db8500-varm",
1879 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1880 },
1881 },
1882 [DB8500_REGULATOR_VMODEM] = {
1883 .constraints = {
1884 .name = "db8500-vmodem",
1885 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1886 },
1887 },
1888 [DB8500_REGULATOR_VPLL] = {
1889 .constraints = {
1890 .name = "db8500-vpll",
1891 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1892 },
1893 },
1894 [DB8500_REGULATOR_VSMPS1] = {
1895 .constraints = {
1896 .name = "db8500-vsmps1",
1897 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1898 },
1899 },
1900 [DB8500_REGULATOR_VSMPS2] = {
1901 .constraints = {
1902 .name = "db8500-vsmps2",
1903 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1904 },
1905 .consumer_supplies = db8500_vsmps2_consumers,
1906 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
1907 },
1908 [DB8500_REGULATOR_VSMPS3] = {
1909 .constraints = {
1910 .name = "db8500-vsmps3",
1911 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1912 },
1913 },
1914 [DB8500_REGULATOR_VRF1] = {
1915 .constraints = {
1916 .name = "db8500-vrf1",
1917 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1918 },
1919 },
1920 [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
1921 .supply_regulator = "db8500-vape",
1922 .constraints = {
1923 .name = "db8500-sva-mmdsp",
1924 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1925 },
1926 },
1927 [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
1928 .constraints = {
1929 /* "ret" means "retention" */
1930 .name = "db8500-sva-mmdsp-ret",
1931 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1932 },
1933 },
1934 [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
1935 .supply_regulator = "db8500-vape",
1936 .constraints = {
1937 .name = "db8500-sva-pipe",
1938 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1939 },
1940 },
1941 [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
1942 .supply_regulator = "db8500-vape",
1943 .constraints = {
1944 .name = "db8500-sia-mmdsp",
1945 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1946 },
1947 },
1948 [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
1949 .constraints = {
1950 .name = "db8500-sia-mmdsp-ret",
1951 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1952 },
1953 },
1954 [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
1955 .supply_regulator = "db8500-vape",
1956 .constraints = {
1957 .name = "db8500-sia-pipe",
1958 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1959 },
1960 },
1961 [DB8500_REGULATOR_SWITCH_SGA] = {
1962 .supply_regulator = "db8500-vape",
1963 .constraints = {
1964 .name = "db8500-sga",
1965 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1966 },
1967 },
1968 [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
1969 .supply_regulator = "db8500-vape",
1970 .constraints = {
1971 .name = "db8500-b2r2-mcde",
1972 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1973 },
1974 .consumer_supplies = db8500_b2r2_mcde_consumers,
1975 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
1976 },
1977 [DB8500_REGULATOR_SWITCH_ESRAM12] = {
1978 .supply_regulator = "db8500-vape",
1979 .constraints = {
1980 .name = "db8500-esram12",
1981 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1982 },
1983 },
1984 [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
1985 .constraints = {
1986 .name = "db8500-esram12-ret",
1987 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1988 },
1989 },
1990 [DB8500_REGULATOR_SWITCH_ESRAM34] = {
1991 .supply_regulator = "db8500-vape",
1992 .constraints = {
1993 .name = "db8500-esram34",
1994 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1995 },
1996 },
1997 [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
1998 .constraints = {
1999 .name = "db8500-esram34-ret",
2000 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2001 },
2002 },
2003};
2004
2005static struct mfd_cell db8500_prcmu_devs[] = {
2006 {
2007 .name = "db8500-prcmu-regulators",
2008 .platform_data = &db8500_regulators,
2009 .pdata_size = sizeof(db8500_regulators),
2010 },
2011 {
2012 .name = "cpufreq-u8500",
2013 },
2014};
2015
2016/**
2017 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
2018 *
2019 */
2020static int __init db8500_prcmu_probe(struct platform_device *pdev)
2021{
2022 int err = 0;
2023
2024 if (ux500_is_svp())
2025 return -ENODEV;
2026
2027 /* Clean up the mailbox interrupts after pre-kernel code. */
2028 writel(ALL_MBOX_BITS, (_PRCMU_BASE + PRCM_ARM_IT1_CLR));
2029
2030 err = request_threaded_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler,
2031 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
2032 if (err < 0) {
2033 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
2034 err = -EBUSY;
2035 goto no_irq_return;
2036 }
2037
2038 if (cpu_is_u8500v20_or_later())
2039 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
2040
2041 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
2042 ARRAY_SIZE(db8500_prcmu_devs), NULL,
2043 0);
2044
2045 if (err)
2046 pr_err("prcmu: Failed to add subdevices\n");
2047 else
2048 pr_info("DB8500 PRCMU initialized\n");
2049
2050no_irq_return:
2051 return err;
2052}
2053
2054static struct platform_driver db8500_prcmu_driver = {
2055 .driver = {
2056 .name = "db8500-prcmu",
2057 .owner = THIS_MODULE,
2058 },
2059};
2060
2061static int __init db8500_prcmu_init(void)
2062{
2063 return platform_driver_probe(&db8500_prcmu_driver, db8500_prcmu_probe);
2064}
2065
2066arch_initcall(db8500_prcmu_init);
2067
2068MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
2069MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
2070MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * DB8500 PRCM Unit driver
4 *
5 * Copyright (C) STMicroelectronics 2009
6 * Copyright (C) ST-Ericsson SA 2010
7 *
8 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
9 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
10 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
11 *
12 * U8500 PRCM Unit interface driver
13 */
14#include <linux/init.h>
15#include <linux/export.h>
16#include <linux/kernel.h>
17#include <linux/delay.h>
18#include <linux/errno.h>
19#include <linux/err.h>
20#include <linux/spinlock.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23#include <linux/mutex.h>
24#include <linux/completion.h>
25#include <linux/irq.h>
26#include <linux/jiffies.h>
27#include <linux/bitops.h>
28#include <linux/fs.h>
29#include <linux/of.h>
30#include <linux/of_address.h>
31#include <linux/of_irq.h>
32#include <linux/platform_device.h>
33#include <linux/uaccess.h>
34#include <linux/mfd/core.h>
35#include <linux/mfd/dbx500-prcmu.h>
36#include <linux/mfd/abx500/ab8500.h>
37#include <linux/regulator/db8500-prcmu.h>
38#include <linux/regulator/machine.h>
39#include <linux/platform_data/ux500_wdt.h>
40#include "dbx500-prcmu-regs.h"
41
42/* Index of different voltages to be used when accessing AVSData */
43#define PRCM_AVS_BASE 0x2FC
44#define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0)
45#define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1)
46#define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2)
47#define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3)
48#define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4)
49#define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5)
50#define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6)
51#define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7)
52#define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8)
53#define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9)
54#define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA)
55#define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB)
56#define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC)
57
58#define PRCM_AVS_VOLTAGE 0
59#define PRCM_AVS_VOLTAGE_MASK 0x3f
60#define PRCM_AVS_ISSLOWSTARTUP 6
61#define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP)
62#define PRCM_AVS_ISMODEENABLE 7
63#define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
64
65#define PRCM_BOOT_STATUS 0xFFF
66#define PRCM_ROMCODE_A2P 0xFFE
67#define PRCM_ROMCODE_P2A 0xFFD
68#define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */
69
70#define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
71
72#define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */
73#define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0)
74#define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1)
75#define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2)
76#define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3)
77#define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4)
78#define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5)
79#define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8)
80
81/* Req Mailboxes */
82#define PRCM_REQ_MB0 0xFDC /* 12 bytes */
83#define PRCM_REQ_MB1 0xFD0 /* 12 bytes */
84#define PRCM_REQ_MB2 0xFC0 /* 16 bytes */
85#define PRCM_REQ_MB3 0xE4C /* 372 bytes */
86#define PRCM_REQ_MB4 0xE48 /* 4 bytes */
87#define PRCM_REQ_MB5 0xE44 /* 4 bytes */
88
89/* Ack Mailboxes */
90#define PRCM_ACK_MB0 0xE08 /* 52 bytes */
91#define PRCM_ACK_MB1 0xE04 /* 4 bytes */
92#define PRCM_ACK_MB2 0xE00 /* 4 bytes */
93#define PRCM_ACK_MB3 0xDFC /* 4 bytes */
94#define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
95#define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
96
97/* Mailbox 0 headers */
98#define MB0H_POWER_STATE_TRANS 0
99#define MB0H_CONFIG_WAKEUPS_EXE 1
100#define MB0H_READ_WAKEUP_ACK 3
101#define MB0H_CONFIG_WAKEUPS_SLEEP 4
102
103#define MB0H_WAKEUP_EXE 2
104#define MB0H_WAKEUP_SLEEP 5
105
106/* Mailbox 0 REQs */
107#define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0)
108#define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1)
109#define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2)
110#define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3)
111#define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4)
112#define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8)
113
114/* Mailbox 0 ACKs */
115#define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0)
116#define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1)
117#define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4)
118#define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8)
119#define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C)
120#define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20)
121#define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
122
123/* Mailbox 1 headers */
124#define MB1H_ARM_APE_OPP 0x0
125#define MB1H_RESET_MODEM 0x2
126#define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
127#define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
128#define MB1H_RELEASE_USB_WAKEUP 0x5
129#define MB1H_PLL_ON_OFF 0x6
130
131/* Mailbox 1 Requests */
132#define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0)
133#define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1)
134#define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4)
135#define PLL_SOC0_OFF 0x1
136#define PLL_SOC0_ON 0x2
137#define PLL_SOC1_OFF 0x4
138#define PLL_SOC1_ON 0x8
139
140/* Mailbox 1 ACKs */
141#define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0)
142#define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1)
143#define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
144#define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3)
145
146/* Mailbox 2 headers */
147#define MB2H_DPS 0x0
148#define MB2H_AUTO_PWR 0x1
149
150/* Mailbox 2 REQs */
151#define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0)
152#define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1)
153#define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2)
154#define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3)
155#define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4)
156#define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5)
157#define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6)
158#define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7)
159#define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8)
160#define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC)
161
162/* Mailbox 2 ACKs */
163#define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
164#define HWACC_PWR_ST_OK 0xFE
165
166/* Mailbox 3 headers */
167#define MB3H_ANC 0x0
168#define MB3H_SIDETONE 0x1
169#define MB3H_SYSCLK 0xE
170
171/* Mailbox 3 Requests */
172#define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0)
173#define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20)
174#define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60)
175#define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64)
176#define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68)
177#define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
178#define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C)
179
180/* Mailbox 4 headers */
181#define MB4H_DDR_INIT 0x0
182#define MB4H_MEM_ST 0x1
183#define MB4H_HOTDOG 0x12
184#define MB4H_HOTMON 0x13
185#define MB4H_HOT_PERIOD 0x14
186#define MB4H_A9WDOG_CONF 0x16
187#define MB4H_A9WDOG_EN 0x17
188#define MB4H_A9WDOG_DIS 0x18
189#define MB4H_A9WDOG_LOAD 0x19
190#define MB4H_A9WDOG_KICK 0x20
191
192/* Mailbox 4 Requests */
193#define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0)
194#define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1)
195#define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3)
196#define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0)
197#define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0)
198#define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1)
199#define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2)
200#define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0)
201#define HOTMON_CONFIG_LOW BIT(0)
202#define HOTMON_CONFIG_HIGH BIT(1)
203#define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0)
204#define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1)
205#define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2)
206#define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3)
207#define A9WDOG_AUTO_OFF_EN BIT(7)
208#define A9WDOG_AUTO_OFF_DIS 0
209#define A9WDOG_ID_MASK 0xf
210
211/* Mailbox 5 Requests */
212#define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0)
213#define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
214#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
215#define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
216#define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
217#define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
218#define PRCMU_I2C_STOP_EN BIT(3)
219
220/* Mailbox 5 ACKs */
221#define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
222#define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3)
223#define I2C_WR_OK 0x1
224#define I2C_RD_OK 0x2
225
226#define NUM_MB 8
227#define MBOX_BIT BIT
228#define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
229
230/*
231 * Wakeups/IRQs
232 */
233
234#define WAKEUP_BIT_RTC BIT(0)
235#define WAKEUP_BIT_RTT0 BIT(1)
236#define WAKEUP_BIT_RTT1 BIT(2)
237#define WAKEUP_BIT_HSI0 BIT(3)
238#define WAKEUP_BIT_HSI1 BIT(4)
239#define WAKEUP_BIT_CA_WAKE BIT(5)
240#define WAKEUP_BIT_USB BIT(6)
241#define WAKEUP_BIT_ABB BIT(7)
242#define WAKEUP_BIT_ABB_FIFO BIT(8)
243#define WAKEUP_BIT_SYSCLK_OK BIT(9)
244#define WAKEUP_BIT_CA_SLEEP BIT(10)
245#define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
246#define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
247#define WAKEUP_BIT_ANC_OK BIT(13)
248#define WAKEUP_BIT_SW_ERROR BIT(14)
249#define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
250#define WAKEUP_BIT_ARM BIT(17)
251#define WAKEUP_BIT_HOTMON_LOW BIT(18)
252#define WAKEUP_BIT_HOTMON_HIGH BIT(19)
253#define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
254#define WAKEUP_BIT_GPIO0 BIT(23)
255#define WAKEUP_BIT_GPIO1 BIT(24)
256#define WAKEUP_BIT_GPIO2 BIT(25)
257#define WAKEUP_BIT_GPIO3 BIT(26)
258#define WAKEUP_BIT_GPIO4 BIT(27)
259#define WAKEUP_BIT_GPIO5 BIT(28)
260#define WAKEUP_BIT_GPIO6 BIT(29)
261#define WAKEUP_BIT_GPIO7 BIT(30)
262#define WAKEUP_BIT_GPIO8 BIT(31)
263
264static struct {
265 bool valid;
266 struct prcmu_fw_version version;
267} fw_info;
268
269static struct irq_domain *db8500_irq_domain;
270
271/*
272 * This vector maps irq numbers to the bits in the bit field used in
273 * communication with the PRCMU firmware.
274 *
275 * The reason for having this is to keep the irq numbers contiguous even though
276 * the bits in the bit field are not. (The bits also have a tendency to move
277 * around, to further complicate matters.)
278 */
279#define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name))
280#define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
281
282#define IRQ_PRCMU_RTC 0
283#define IRQ_PRCMU_RTT0 1
284#define IRQ_PRCMU_RTT1 2
285#define IRQ_PRCMU_HSI0 3
286#define IRQ_PRCMU_HSI1 4
287#define IRQ_PRCMU_CA_WAKE 5
288#define IRQ_PRCMU_USB 6
289#define IRQ_PRCMU_ABB 7
290#define IRQ_PRCMU_ABB_FIFO 8
291#define IRQ_PRCMU_ARM 9
292#define IRQ_PRCMU_MODEM_SW_RESET_REQ 10
293#define IRQ_PRCMU_GPIO0 11
294#define IRQ_PRCMU_GPIO1 12
295#define IRQ_PRCMU_GPIO2 13
296#define IRQ_PRCMU_GPIO3 14
297#define IRQ_PRCMU_GPIO4 15
298#define IRQ_PRCMU_GPIO5 16
299#define IRQ_PRCMU_GPIO6 17
300#define IRQ_PRCMU_GPIO7 18
301#define IRQ_PRCMU_GPIO8 19
302#define IRQ_PRCMU_CA_SLEEP 20
303#define IRQ_PRCMU_HOTMON_LOW 21
304#define IRQ_PRCMU_HOTMON_HIGH 22
305#define NUM_PRCMU_WAKEUPS 23
306
307static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
308 IRQ_ENTRY(RTC),
309 IRQ_ENTRY(RTT0),
310 IRQ_ENTRY(RTT1),
311 IRQ_ENTRY(HSI0),
312 IRQ_ENTRY(HSI1),
313 IRQ_ENTRY(CA_WAKE),
314 IRQ_ENTRY(USB),
315 IRQ_ENTRY(ABB),
316 IRQ_ENTRY(ABB_FIFO),
317 IRQ_ENTRY(CA_SLEEP),
318 IRQ_ENTRY(ARM),
319 IRQ_ENTRY(HOTMON_LOW),
320 IRQ_ENTRY(HOTMON_HIGH),
321 IRQ_ENTRY(MODEM_SW_RESET_REQ),
322 IRQ_ENTRY(GPIO0),
323 IRQ_ENTRY(GPIO1),
324 IRQ_ENTRY(GPIO2),
325 IRQ_ENTRY(GPIO3),
326 IRQ_ENTRY(GPIO4),
327 IRQ_ENTRY(GPIO5),
328 IRQ_ENTRY(GPIO6),
329 IRQ_ENTRY(GPIO7),
330 IRQ_ENTRY(GPIO8)
331};
332
333#define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
334#define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
335static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
336 WAKEUP_ENTRY(RTC),
337 WAKEUP_ENTRY(RTT0),
338 WAKEUP_ENTRY(RTT1),
339 WAKEUP_ENTRY(HSI0),
340 WAKEUP_ENTRY(HSI1),
341 WAKEUP_ENTRY(USB),
342 WAKEUP_ENTRY(ABB),
343 WAKEUP_ENTRY(ABB_FIFO),
344 WAKEUP_ENTRY(ARM)
345};
346
347/*
348 * mb0_transfer - state needed for mailbox 0 communication.
349 * @lock: The transaction lock.
350 * @dbb_events_lock: A lock used to handle concurrent access to (parts of)
351 * the request data.
352 * @mask_work: Work structure used for (un)masking wakeup interrupts.
353 * @req: Request data that need to persist between requests.
354 */
355static struct {
356 spinlock_t lock;
357 spinlock_t dbb_irqs_lock;
358 struct work_struct mask_work;
359 struct mutex ac_wake_lock;
360 struct completion ac_wake_work;
361 struct {
362 u32 dbb_irqs;
363 u32 dbb_wakeups;
364 u32 abb_events;
365 } req;
366} mb0_transfer;
367
368/*
369 * mb1_transfer - state needed for mailbox 1 communication.
370 * @lock: The transaction lock.
371 * @work: The transaction completion structure.
372 * @ape_opp: The current APE OPP.
373 * @ack: Reply ("acknowledge") data.
374 */
375static struct {
376 struct mutex lock;
377 struct completion work;
378 u8 ape_opp;
379 struct {
380 u8 header;
381 u8 arm_opp;
382 u8 ape_opp;
383 u8 ape_voltage_status;
384 } ack;
385} mb1_transfer;
386
387/*
388 * mb2_transfer - state needed for mailbox 2 communication.
389 * @lock: The transaction lock.
390 * @work: The transaction completion structure.
391 * @auto_pm_lock: The autonomous power management configuration lock.
392 * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
393 * @req: Request data that need to persist between requests.
394 * @ack: Reply ("acknowledge") data.
395 */
396static struct {
397 struct mutex lock;
398 struct completion work;
399 spinlock_t auto_pm_lock;
400 bool auto_pm_enabled;
401 struct {
402 u8 status;
403 } ack;
404} mb2_transfer;
405
406/*
407 * mb3_transfer - state needed for mailbox 3 communication.
408 * @lock: The request lock.
409 * @sysclk_lock: A lock used to handle concurrent sysclk requests.
410 * @sysclk_work: Work structure used for sysclk requests.
411 */
412static struct {
413 spinlock_t lock;
414 struct mutex sysclk_lock;
415 struct completion sysclk_work;
416} mb3_transfer;
417
418/*
419 * mb4_transfer - state needed for mailbox 4 communication.
420 * @lock: The transaction lock.
421 * @work: The transaction completion structure.
422 */
423static struct {
424 struct mutex lock;
425 struct completion work;
426} mb4_transfer;
427
428/*
429 * mb5_transfer - state needed for mailbox 5 communication.
430 * @lock: The transaction lock.
431 * @work: The transaction completion structure.
432 * @ack: Reply ("acknowledge") data.
433 */
434static struct {
435 struct mutex lock;
436 struct completion work;
437 struct {
438 u8 status;
439 u8 value;
440 } ack;
441} mb5_transfer;
442
443static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
444
445/* Spinlocks */
446static DEFINE_SPINLOCK(prcmu_lock);
447static DEFINE_SPINLOCK(clkout_lock);
448
449/* Global var to runtime determine TCDM base for v2 or v1 */
450static __iomem void *tcdm_base;
451static __iomem void *prcmu_base;
452
453struct clk_mgt {
454 u32 offset;
455 u32 pllsw;
456 int branch;
457 bool clk38div;
458};
459
460enum {
461 PLL_RAW,
462 PLL_FIX,
463 PLL_DIV
464};
465
466static DEFINE_SPINLOCK(clk_mgt_lock);
467
468#define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
469 { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
470static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
471 CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
472 CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
473 CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
474 CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
475 CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
476 CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
477 CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
478 CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
479 CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
480 CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
481 CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
482 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
483 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
484 CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
485 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
486 CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
487 CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
488 CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
489 CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
490 CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
491 CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
492 CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
493 CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
494 CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
495 CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
496 CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
497 CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
498 CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
499 CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
500};
501
502struct dsiclk {
503 u32 divsel_mask;
504 u32 divsel_shift;
505 u32 divsel;
506};
507
508static struct dsiclk dsiclk[2] = {
509 {
510 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
511 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
512 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
513 },
514 {
515 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
516 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
517 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
518 }
519};
520
521struct dsiescclk {
522 u32 en;
523 u32 div_mask;
524 u32 div_shift;
525};
526
527static struct dsiescclk dsiescclk[3] = {
528 {
529 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
530 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
531 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
532 },
533 {
534 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
535 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
536 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
537 },
538 {
539 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
540 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
541 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
542 }
543};
544
545u32 db8500_prcmu_read(unsigned int reg)
546{
547 return readl(prcmu_base + reg);
548}
549
550void db8500_prcmu_write(unsigned int reg, u32 value)
551{
552 unsigned long flags;
553
554 spin_lock_irqsave(&prcmu_lock, flags);
555 writel(value, (prcmu_base + reg));
556 spin_unlock_irqrestore(&prcmu_lock, flags);
557}
558
559void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
560{
561 u32 val;
562 unsigned long flags;
563
564 spin_lock_irqsave(&prcmu_lock, flags);
565 val = readl(prcmu_base + reg);
566 val = ((val & ~mask) | (value & mask));
567 writel(val, (prcmu_base + reg));
568 spin_unlock_irqrestore(&prcmu_lock, flags);
569}
570
571struct prcmu_fw_version *prcmu_get_fw_version(void)
572{
573 return fw_info.valid ? &fw_info.version : NULL;
574}
575
576static bool prcmu_is_ulppll_disabled(void)
577{
578 struct prcmu_fw_version *ver;
579
580 ver = prcmu_get_fw_version();
581 return ver && ver->project == PRCMU_FW_PROJECT_U8420_SYSCLK;
582}
583
584bool prcmu_has_arm_maxopp(void)
585{
586 return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
587 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
588}
589
590/**
591 * prcmu_set_rc_a2p - This function is used to run few power state sequences
592 * @val: Value to be set, i.e. transition requested
593 * Returns: 0 on success, -EINVAL on invalid argument
594 *
595 * This function is used to run the following power state sequences -
596 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
597 */
598int prcmu_set_rc_a2p(enum romcode_write val)
599{
600 if (val < RDY_2_DS || val > RDY_2_XP70_RST)
601 return -EINVAL;
602 writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
603 return 0;
604}
605
606/**
607 * prcmu_get_rc_p2a - This function is used to get power state sequences
608 * Returns: the power transition that has last happened
609 *
610 * This function can return the following transitions-
611 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
612 */
613enum romcode_read prcmu_get_rc_p2a(void)
614{
615 return readb(tcdm_base + PRCM_ROMCODE_P2A);
616}
617
618/**
619 * prcmu_get_xp70_current_state - Return the current XP70 power mode
620 * Returns: Returns the current AP(ARM) power mode: init,
621 * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
622 */
623enum ap_pwrst prcmu_get_xp70_current_state(void)
624{
625 return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
626}
627
628/**
629 * prcmu_config_clkout - Configure one of the programmable clock outputs.
630 * @clkout: The CLKOUT number (0 or 1).
631 * @source: The clock to be used (one of the PRCMU_CLKSRC_*).
632 * @div: The divider to be applied.
633 *
634 * Configures one of the programmable clock outputs (CLKOUTs).
635 * @div should be in the range [1,63] to request a configuration, or 0 to
636 * inform that the configuration is no longer requested.
637 */
638int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
639{
640 static int requests[2];
641 int r = 0;
642 unsigned long flags;
643 u32 val;
644 u32 bits;
645 u32 mask;
646 u32 div_mask;
647
648 BUG_ON(clkout > 1);
649 BUG_ON(div > 63);
650 BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
651
652 if (!div && !requests[clkout])
653 return -EINVAL;
654
655 if (clkout == 0) {
656 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
657 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
658 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
659 (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
660 } else {
661 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
662 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
663 PRCM_CLKOCR_CLK1TYPE);
664 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
665 (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
666 }
667 bits &= mask;
668
669 spin_lock_irqsave(&clkout_lock, flags);
670
671 val = readl(PRCM_CLKOCR);
672 if (val & div_mask) {
673 if (div) {
674 if ((val & mask) != bits) {
675 r = -EBUSY;
676 goto unlock_and_return;
677 }
678 } else {
679 if ((val & mask & ~div_mask) != bits) {
680 r = -EINVAL;
681 goto unlock_and_return;
682 }
683 }
684 }
685 writel((bits | (val & ~mask)), PRCM_CLKOCR);
686 requests[clkout] += (div ? 1 : -1);
687
688unlock_and_return:
689 spin_unlock_irqrestore(&clkout_lock, flags);
690
691 return r;
692}
693
694int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
695{
696 unsigned long flags;
697
698 BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
699
700 spin_lock_irqsave(&mb0_transfer.lock, flags);
701
702 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
703 cpu_relax();
704
705 writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
706 writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
707 writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
708 writeb((keep_ulp_clk ? 1 : 0),
709 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
710 writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
711 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
712
713 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
714
715 return 0;
716}
717
718u8 db8500_prcmu_get_power_state_result(void)
719{
720 return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
721}
722
723/* This function should only be called while mb0_transfer.lock is held. */
724static void config_wakeups(void)
725{
726 const u8 header[2] = {
727 MB0H_CONFIG_WAKEUPS_EXE,
728 MB0H_CONFIG_WAKEUPS_SLEEP
729 };
730 static u32 last_dbb_events;
731 static u32 last_abb_events;
732 u32 dbb_events;
733 u32 abb_events;
734 unsigned int i;
735
736 dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
737 dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
738
739 abb_events = mb0_transfer.req.abb_events;
740
741 if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
742 return;
743
744 for (i = 0; i < 2; i++) {
745 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
746 cpu_relax();
747 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
748 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
749 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
750 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
751 }
752 last_dbb_events = dbb_events;
753 last_abb_events = abb_events;
754}
755
756void db8500_prcmu_enable_wakeups(u32 wakeups)
757{
758 unsigned long flags;
759 u32 bits;
760 int i;
761
762 BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
763
764 for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
765 if (wakeups & BIT(i))
766 bits |= prcmu_wakeup_bit[i];
767 }
768
769 spin_lock_irqsave(&mb0_transfer.lock, flags);
770
771 mb0_transfer.req.dbb_wakeups = bits;
772 config_wakeups();
773
774 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
775}
776
777void db8500_prcmu_config_abb_event_readout(u32 abb_events)
778{
779 unsigned long flags;
780
781 spin_lock_irqsave(&mb0_transfer.lock, flags);
782
783 mb0_transfer.req.abb_events = abb_events;
784 config_wakeups();
785
786 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
787}
788
789void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
790{
791 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
792 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
793 else
794 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
795}
796
797/**
798 * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
799 * @opp: The new ARM operating point to which transition is to be made
800 * Returns: 0 on success, non-zero on failure
801 *
802 * This function sets the the operating point of the ARM.
803 */
804int db8500_prcmu_set_arm_opp(u8 opp)
805{
806 int r;
807
808 if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
809 return -EINVAL;
810
811 r = 0;
812
813 mutex_lock(&mb1_transfer.lock);
814
815 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
816 cpu_relax();
817
818 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
819 writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
820 writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
821
822 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
823 wait_for_completion(&mb1_transfer.work);
824
825 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
826 (mb1_transfer.ack.arm_opp != opp))
827 r = -EIO;
828
829 mutex_unlock(&mb1_transfer.lock);
830
831 return r;
832}
833
834/**
835 * db8500_prcmu_get_arm_opp - get the current ARM OPP
836 *
837 * Returns: the current ARM OPP
838 */
839int db8500_prcmu_get_arm_opp(void)
840{
841 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
842}
843
844/**
845 * db8500_prcmu_get_ddr_opp - get the current DDR OPP
846 *
847 * Returns: the current DDR OPP
848 */
849int db8500_prcmu_get_ddr_opp(void)
850{
851 return readb(PRCM_DDR_SUBSYS_APE_MINBW);
852}
853
854/* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
855static void request_even_slower_clocks(bool enable)
856{
857 u32 clock_reg[] = {
858 PRCM_ACLK_MGT,
859 PRCM_DMACLK_MGT
860 };
861 unsigned long flags;
862 unsigned int i;
863
864 spin_lock_irqsave(&clk_mgt_lock, flags);
865
866 /* Grab the HW semaphore. */
867 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
868 cpu_relax();
869
870 for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
871 u32 val;
872 u32 div;
873
874 val = readl(prcmu_base + clock_reg[i]);
875 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
876 if (enable) {
877 if ((div <= 1) || (div > 15)) {
878 pr_err("prcmu: Bad clock divider %d in %s\n",
879 div, __func__);
880 goto unlock_and_return;
881 }
882 div <<= 1;
883 } else {
884 if (div <= 2)
885 goto unlock_and_return;
886 div >>= 1;
887 }
888 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
889 (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
890 writel(val, prcmu_base + clock_reg[i]);
891 }
892
893unlock_and_return:
894 /* Release the HW semaphore. */
895 writel(0, PRCM_SEM);
896
897 spin_unlock_irqrestore(&clk_mgt_lock, flags);
898}
899
900/**
901 * db8500_prcmu_set_ape_opp - set the appropriate APE OPP
902 * @opp: The new APE operating point to which transition is to be made
903 * Returns: 0 on success, non-zero on failure
904 *
905 * This function sets the operating point of the APE.
906 */
907int db8500_prcmu_set_ape_opp(u8 opp)
908{
909 int r = 0;
910
911 if (opp == mb1_transfer.ape_opp)
912 return 0;
913
914 mutex_lock(&mb1_transfer.lock);
915
916 if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
917 request_even_slower_clocks(false);
918
919 if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
920 goto skip_message;
921
922 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
923 cpu_relax();
924
925 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
926 writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
927 writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
928 (tcdm_base + PRCM_REQ_MB1_APE_OPP));
929
930 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
931 wait_for_completion(&mb1_transfer.work);
932
933 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
934 (mb1_transfer.ack.ape_opp != opp))
935 r = -EIO;
936
937skip_message:
938 if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
939 (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
940 request_even_slower_clocks(true);
941 if (!r)
942 mb1_transfer.ape_opp = opp;
943
944 mutex_unlock(&mb1_transfer.lock);
945
946 return r;
947}
948
949/**
950 * db8500_prcmu_get_ape_opp - get the current APE OPP
951 *
952 * Returns: the current APE OPP
953 */
954int db8500_prcmu_get_ape_opp(void)
955{
956 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
957}
958
959/**
960 * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
961 * @enable: true to request the higher voltage, false to drop a request.
962 *
963 * Calls to this function to enable and disable requests must be balanced.
964 */
965int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
966{
967 int r = 0;
968 u8 header;
969 static unsigned int requests;
970
971 mutex_lock(&mb1_transfer.lock);
972
973 if (enable) {
974 if (0 != requests++)
975 goto unlock_and_return;
976 header = MB1H_REQUEST_APE_OPP_100_VOLT;
977 } else {
978 if (requests == 0) {
979 r = -EIO;
980 goto unlock_and_return;
981 } else if (1 != requests--) {
982 goto unlock_and_return;
983 }
984 header = MB1H_RELEASE_APE_OPP_100_VOLT;
985 }
986
987 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
988 cpu_relax();
989
990 writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
991
992 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
993 wait_for_completion(&mb1_transfer.work);
994
995 if ((mb1_transfer.ack.header != header) ||
996 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
997 r = -EIO;
998
999unlock_and_return:
1000 mutex_unlock(&mb1_transfer.lock);
1001
1002 return r;
1003}
1004
1005/**
1006 * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1007 *
1008 * This function releases the power state requirements of a USB wakeup.
1009 */
1010int prcmu_release_usb_wakeup_state(void)
1011{
1012 int r = 0;
1013
1014 mutex_lock(&mb1_transfer.lock);
1015
1016 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1017 cpu_relax();
1018
1019 writeb(MB1H_RELEASE_USB_WAKEUP,
1020 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1021
1022 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1023 wait_for_completion(&mb1_transfer.work);
1024
1025 if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1026 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1027 r = -EIO;
1028
1029 mutex_unlock(&mb1_transfer.lock);
1030
1031 return r;
1032}
1033
1034static int request_pll(u8 clock, bool enable)
1035{
1036 int r = 0;
1037
1038 if (clock == PRCMU_PLLSOC0)
1039 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1040 else if (clock == PRCMU_PLLSOC1)
1041 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1042 else
1043 return -EINVAL;
1044
1045 mutex_lock(&mb1_transfer.lock);
1046
1047 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1048 cpu_relax();
1049
1050 writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1051 writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1052
1053 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1054 wait_for_completion(&mb1_transfer.work);
1055
1056 if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1057 r = -EIO;
1058
1059 mutex_unlock(&mb1_transfer.lock);
1060
1061 return r;
1062}
1063
1064/**
1065 * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1066 * @epod_id: The EPOD to set
1067 * @epod_state: The new EPOD state
1068 *
1069 * This function sets the state of a EPOD (power domain). It may not be called
1070 * from interrupt context.
1071 */
1072int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
1073{
1074 int r = 0;
1075 bool ram_retention = false;
1076 int i;
1077
1078 /* check argument */
1079 BUG_ON(epod_id >= NUM_EPOD_ID);
1080
1081 /* set flag if retention is possible */
1082 switch (epod_id) {
1083 case EPOD_ID_SVAMMDSP:
1084 case EPOD_ID_SIAMMDSP:
1085 case EPOD_ID_ESRAM12:
1086 case EPOD_ID_ESRAM34:
1087 ram_retention = true;
1088 break;
1089 }
1090
1091 /* check argument */
1092 BUG_ON(epod_state > EPOD_STATE_ON);
1093 BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1094
1095 /* get lock */
1096 mutex_lock(&mb2_transfer.lock);
1097
1098 /* wait for mailbox */
1099 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
1100 cpu_relax();
1101
1102 /* fill in mailbox */
1103 for (i = 0; i < NUM_EPOD_ID; i++)
1104 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1105 writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1106
1107 writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1108
1109 writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
1110
1111 /*
1112 * The current firmware version does not handle errors correctly,
1113 * and we cannot recover if there is an error.
1114 * This is expected to change when the firmware is updated.
1115 */
1116 if (!wait_for_completion_timeout(&mb2_transfer.work,
1117 msecs_to_jiffies(20000))) {
1118 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1119 __func__);
1120 r = -EIO;
1121 goto unlock_and_return;
1122 }
1123
1124 if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1125 r = -EIO;
1126
1127unlock_and_return:
1128 mutex_unlock(&mb2_transfer.lock);
1129 return r;
1130}
1131
1132/**
1133 * prcmu_configure_auto_pm - Configure autonomous power management.
1134 * @sleep: Configuration for ApSleep.
1135 * @idle: Configuration for ApIdle.
1136 */
1137void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1138 struct prcmu_auto_pm_config *idle)
1139{
1140 u32 sleep_cfg;
1141 u32 idle_cfg;
1142 unsigned long flags;
1143
1144 BUG_ON((sleep == NULL) || (idle == NULL));
1145
1146 sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1147 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1148 sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1149 sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1150 sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1151 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1152
1153 idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1154 idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1155 idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1156 idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1157 idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1158 idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1159
1160 spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1161
1162 /*
1163 * The autonomous power management configuration is done through
1164 * fields in mailbox 2, but these fields are only used as shared
1165 * variables - i.e. there is no need to send a message.
1166 */
1167 writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1168 writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1169
1170 mb2_transfer.auto_pm_enabled =
1171 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1172 (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1173 (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1174 (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1175
1176 spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1177}
1178EXPORT_SYMBOL(prcmu_configure_auto_pm);
1179
1180bool prcmu_is_auto_pm_enabled(void)
1181{
1182 return mb2_transfer.auto_pm_enabled;
1183}
1184
1185static int request_sysclk(bool enable)
1186{
1187 int r;
1188 unsigned long flags;
1189
1190 r = 0;
1191
1192 mutex_lock(&mb3_transfer.sysclk_lock);
1193
1194 spin_lock_irqsave(&mb3_transfer.lock, flags);
1195
1196 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
1197 cpu_relax();
1198
1199 writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1200
1201 writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1202 writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
1203
1204 spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1205
1206 /*
1207 * The firmware only sends an ACK if we want to enable the
1208 * SysClk, and it succeeds.
1209 */
1210 if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1211 msecs_to_jiffies(20000))) {
1212 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1213 __func__);
1214 r = -EIO;
1215 }
1216
1217 mutex_unlock(&mb3_transfer.sysclk_lock);
1218
1219 return r;
1220}
1221
1222static int request_timclk(bool enable)
1223{
1224 u32 val;
1225
1226 /*
1227 * On the U8420_CLKSEL firmware, the ULP (Ultra Low Power)
1228 * PLL is disabled so we cannot use doze mode, this will
1229 * stop the clock on this firmware.
1230 */
1231 if (prcmu_is_ulppll_disabled())
1232 val = 0;
1233 else
1234 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1235
1236 if (!enable)
1237 val |= PRCM_TCR_STOP_TIMERS |
1238 PRCM_TCR_DOZE_MODE |
1239 PRCM_TCR_TENSEL_MASK;
1240
1241 writel(val, PRCM_TCR);
1242
1243 return 0;
1244}
1245
1246static int request_clock(u8 clock, bool enable)
1247{
1248 u32 val;
1249 unsigned long flags;
1250
1251 spin_lock_irqsave(&clk_mgt_lock, flags);
1252
1253 /* Grab the HW semaphore. */
1254 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1255 cpu_relax();
1256
1257 val = readl(prcmu_base + clk_mgt[clock].offset);
1258 if (enable) {
1259 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1260 } else {
1261 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1262 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1263 }
1264 writel(val, prcmu_base + clk_mgt[clock].offset);
1265
1266 /* Release the HW semaphore. */
1267 writel(0, PRCM_SEM);
1268
1269 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1270
1271 return 0;
1272}
1273
1274static int request_sga_clock(u8 clock, bool enable)
1275{
1276 u32 val;
1277 int ret;
1278
1279 if (enable) {
1280 val = readl(PRCM_CGATING_BYPASS);
1281 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1282 }
1283
1284 ret = request_clock(clock, enable);
1285
1286 if (!ret && !enable) {
1287 val = readl(PRCM_CGATING_BYPASS);
1288 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1289 }
1290
1291 return ret;
1292}
1293
1294static inline bool plldsi_locked(void)
1295{
1296 return (readl(PRCM_PLLDSI_LOCKP) &
1297 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1298 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1299 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1300 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1301}
1302
1303static int request_plldsi(bool enable)
1304{
1305 int r = 0;
1306 u32 val;
1307
1308 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1309 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1310 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1311
1312 val = readl(PRCM_PLLDSI_ENABLE);
1313 if (enable)
1314 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1315 else
1316 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1317 writel(val, PRCM_PLLDSI_ENABLE);
1318
1319 if (enable) {
1320 unsigned int i;
1321 bool locked = plldsi_locked();
1322
1323 for (i = 10; !locked && (i > 0); --i) {
1324 udelay(100);
1325 locked = plldsi_locked();
1326 }
1327 if (locked) {
1328 writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1329 PRCM_APE_RESETN_SET);
1330 } else {
1331 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1332 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1333 PRCM_MMIP_LS_CLAMP_SET);
1334 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1335 writel(val, PRCM_PLLDSI_ENABLE);
1336 r = -EAGAIN;
1337 }
1338 } else {
1339 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1340 }
1341 return r;
1342}
1343
1344static int request_dsiclk(u8 n, bool enable)
1345{
1346 u32 val;
1347
1348 val = readl(PRCM_DSI_PLLOUT_SEL);
1349 val &= ~dsiclk[n].divsel_mask;
1350 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1351 dsiclk[n].divsel_shift);
1352 writel(val, PRCM_DSI_PLLOUT_SEL);
1353 return 0;
1354}
1355
1356static int request_dsiescclk(u8 n, bool enable)
1357{
1358 u32 val;
1359
1360 val = readl(PRCM_DSITVCLK_DIV);
1361 enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1362 writel(val, PRCM_DSITVCLK_DIV);
1363 return 0;
1364}
1365
1366/**
1367 * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1368 * @clock: The clock for which the request is made.
1369 * @enable: Whether the clock should be enabled (true) or disabled (false).
1370 *
1371 * This function should only be used by the clock implementation.
1372 * Do not use it from any other place!
1373 */
1374int db8500_prcmu_request_clock(u8 clock, bool enable)
1375{
1376 if (clock == PRCMU_SGACLK)
1377 return request_sga_clock(clock, enable);
1378 else if (clock < PRCMU_NUM_REG_CLOCKS)
1379 return request_clock(clock, enable);
1380 else if (clock == PRCMU_TIMCLK)
1381 return request_timclk(enable);
1382 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1383 return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1384 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1385 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1386 else if (clock == PRCMU_PLLDSI)
1387 return request_plldsi(enable);
1388 else if (clock == PRCMU_SYSCLK)
1389 return request_sysclk(enable);
1390 else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
1391 return request_pll(clock, enable);
1392 else
1393 return -EINVAL;
1394}
1395
1396static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1397 int branch)
1398{
1399 u64 rate;
1400 u32 val;
1401 u32 d;
1402 u32 div = 1;
1403
1404 val = readl(reg);
1405
1406 rate = src_rate;
1407 rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1408
1409 d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1410 if (d > 1)
1411 div *= d;
1412
1413 d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1414 if (d > 1)
1415 div *= d;
1416
1417 if (val & PRCM_PLL_FREQ_SELDIV2)
1418 div *= 2;
1419
1420 if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1421 (val & PRCM_PLL_FREQ_DIV2EN) &&
1422 ((reg == PRCM_PLLSOC0_FREQ) ||
1423 (reg == PRCM_PLLARM_FREQ) ||
1424 (reg == PRCM_PLLDDR_FREQ))))
1425 div *= 2;
1426
1427 (void)do_div(rate, div);
1428
1429 return (unsigned long)rate;
1430}
1431
1432#define ROOT_CLOCK_RATE 38400000
1433
1434static unsigned long clock_rate(u8 clock)
1435{
1436 u32 val;
1437 u32 pllsw;
1438 unsigned long rate = ROOT_CLOCK_RATE;
1439
1440 val = readl(prcmu_base + clk_mgt[clock].offset);
1441
1442 if (val & PRCM_CLK_MGT_CLK38) {
1443 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1444 rate /= 2;
1445 return rate;
1446 }
1447
1448 val |= clk_mgt[clock].pllsw;
1449 pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1450
1451 if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1452 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1453 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1454 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1455 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1456 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1457 else
1458 return 0;
1459
1460 if ((clock == PRCMU_SGACLK) &&
1461 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1462 u64 r = (rate * 10);
1463
1464 (void)do_div(r, 25);
1465 return (unsigned long)r;
1466 }
1467 val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1468 if (val)
1469 return rate / val;
1470 else
1471 return 0;
1472}
1473
1474static unsigned long armss_rate(void)
1475{
1476 u32 r;
1477 unsigned long rate;
1478
1479 r = readl(PRCM_ARM_CHGCLKREQ);
1480
1481 if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
1482 /* External ARMCLKFIX clock */
1483
1484 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
1485
1486 /* Check PRCM_ARM_CHGCLKREQ divider */
1487 if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
1488 rate /= 2;
1489
1490 /* Check PRCM_ARMCLKFIX_MGT divider */
1491 r = readl(PRCM_ARMCLKFIX_MGT);
1492 r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1493 rate /= r;
1494
1495 } else {/* ARM PLL */
1496 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1497 }
1498
1499 return rate;
1500}
1501
1502static unsigned long dsiclk_rate(u8 n)
1503{
1504 u32 divsel;
1505 u32 div = 1;
1506
1507 divsel = readl(PRCM_DSI_PLLOUT_SEL);
1508 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1509
1510 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1511 divsel = dsiclk[n].divsel;
1512 else
1513 dsiclk[n].divsel = divsel;
1514
1515 switch (divsel) {
1516 case PRCM_DSI_PLLOUT_SEL_PHI_4:
1517 div *= 2;
1518 fallthrough;
1519 case PRCM_DSI_PLLOUT_SEL_PHI_2:
1520 div *= 2;
1521 fallthrough;
1522 case PRCM_DSI_PLLOUT_SEL_PHI:
1523 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1524 PLL_RAW) / div;
1525 default:
1526 return 0;
1527 }
1528}
1529
1530static unsigned long dsiescclk_rate(u8 n)
1531{
1532 u32 div;
1533
1534 div = readl(PRCM_DSITVCLK_DIV);
1535 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1536 return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1537}
1538
1539unsigned long prcmu_clock_rate(u8 clock)
1540{
1541 if (clock < PRCMU_NUM_REG_CLOCKS)
1542 return clock_rate(clock);
1543 else if (clock == PRCMU_TIMCLK)
1544 return prcmu_is_ulppll_disabled() ?
1545 32768 : ROOT_CLOCK_RATE / 16;
1546 else if (clock == PRCMU_SYSCLK)
1547 return ROOT_CLOCK_RATE;
1548 else if (clock == PRCMU_PLLSOC0)
1549 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1550 else if (clock == PRCMU_PLLSOC1)
1551 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1552 else if (clock == PRCMU_ARMSS)
1553 return armss_rate();
1554 else if (clock == PRCMU_PLLDDR)
1555 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1556 else if (clock == PRCMU_PLLDSI)
1557 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1558 PLL_RAW);
1559 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1560 return dsiclk_rate(clock - PRCMU_DSI0CLK);
1561 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1562 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1563 else
1564 return 0;
1565}
1566
1567static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1568{
1569 if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1570 return ROOT_CLOCK_RATE;
1571 clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1572 if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1573 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1574 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1575 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1576 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1577 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1578 else
1579 return 0;
1580}
1581
1582static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1583{
1584 u32 div;
1585
1586 div = (src_rate / rate);
1587 if (div == 0)
1588 return 1;
1589 if (rate < (src_rate / div))
1590 div++;
1591 return div;
1592}
1593
1594static long round_clock_rate(u8 clock, unsigned long rate)
1595{
1596 u32 val;
1597 u32 div;
1598 unsigned long src_rate;
1599 long rounded_rate;
1600
1601 val = readl(prcmu_base + clk_mgt[clock].offset);
1602 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1603 clk_mgt[clock].branch);
1604 div = clock_divider(src_rate, rate);
1605 if (val & PRCM_CLK_MGT_CLK38) {
1606 if (clk_mgt[clock].clk38div) {
1607 if (div > 2)
1608 div = 2;
1609 } else {
1610 div = 1;
1611 }
1612 } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1613 u64 r = (src_rate * 10);
1614
1615 (void)do_div(r, 25);
1616 if (r <= rate)
1617 return (unsigned long)r;
1618 }
1619 rounded_rate = (src_rate / min(div, (u32)31));
1620
1621 return rounded_rate;
1622}
1623
1624static const unsigned long db8500_armss_freqs[] = {
1625 199680000,
1626 399360000,
1627 798720000,
1628 998400000
1629};
1630
1631/* The DB8520 has slightly higher ARMSS max frequency */
1632static const unsigned long db8520_armss_freqs[] = {
1633 199680000,
1634 399360000,
1635 798720000,
1636 1152000000
1637};
1638
1639static long round_armss_rate(unsigned long rate)
1640{
1641 unsigned long freq = 0;
1642 const unsigned long *freqs;
1643 int nfreqs;
1644 int i;
1645
1646 if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) {
1647 freqs = db8520_armss_freqs;
1648 nfreqs = ARRAY_SIZE(db8520_armss_freqs);
1649 } else {
1650 freqs = db8500_armss_freqs;
1651 nfreqs = ARRAY_SIZE(db8500_armss_freqs);
1652 }
1653
1654 /* Find the corresponding arm opp from the cpufreq table. */
1655 for (i = 0; i < nfreqs; i++) {
1656 freq = freqs[i];
1657 if (rate <= freq)
1658 break;
1659 }
1660
1661 /* Return the last valid value, even if a match was not found. */
1662 return freq;
1663}
1664
1665#define MIN_PLL_VCO_RATE 600000000ULL
1666#define MAX_PLL_VCO_RATE 1680640000ULL
1667
1668static long round_plldsi_rate(unsigned long rate)
1669{
1670 long rounded_rate = 0;
1671 unsigned long src_rate;
1672 unsigned long rem;
1673 u32 r;
1674
1675 src_rate = clock_rate(PRCMU_HDMICLK);
1676 rem = rate;
1677
1678 for (r = 7; (rem > 0) && (r > 0); r--) {
1679 u64 d;
1680
1681 d = (r * rate);
1682 (void)do_div(d, src_rate);
1683 if (d < 6)
1684 d = 6;
1685 else if (d > 255)
1686 d = 255;
1687 d *= src_rate;
1688 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1689 ((r * MAX_PLL_VCO_RATE) < (2 * d)))
1690 continue;
1691 (void)do_div(d, r);
1692 if (rate < d) {
1693 if (rounded_rate == 0)
1694 rounded_rate = (long)d;
1695 break;
1696 }
1697 if ((rate - d) < rem) {
1698 rem = (rate - d);
1699 rounded_rate = (long)d;
1700 }
1701 }
1702 return rounded_rate;
1703}
1704
1705static long round_dsiclk_rate(unsigned long rate)
1706{
1707 u32 div;
1708 unsigned long src_rate;
1709 long rounded_rate;
1710
1711 src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1712 PLL_RAW);
1713 div = clock_divider(src_rate, rate);
1714 rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1715
1716 return rounded_rate;
1717}
1718
1719static long round_dsiescclk_rate(unsigned long rate)
1720{
1721 u32 div;
1722 unsigned long src_rate;
1723 long rounded_rate;
1724
1725 src_rate = clock_rate(PRCMU_TVCLK);
1726 div = clock_divider(src_rate, rate);
1727 rounded_rate = (src_rate / min(div, (u32)255));
1728
1729 return rounded_rate;
1730}
1731
1732long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1733{
1734 if (clock < PRCMU_NUM_REG_CLOCKS)
1735 return round_clock_rate(clock, rate);
1736 else if (clock == PRCMU_ARMSS)
1737 return round_armss_rate(rate);
1738 else if (clock == PRCMU_PLLDSI)
1739 return round_plldsi_rate(rate);
1740 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1741 return round_dsiclk_rate(rate);
1742 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1743 return round_dsiescclk_rate(rate);
1744 else
1745 return (long)prcmu_clock_rate(clock);
1746}
1747
1748static void set_clock_rate(u8 clock, unsigned long rate)
1749{
1750 u32 val;
1751 u32 div;
1752 unsigned long src_rate;
1753 unsigned long flags;
1754
1755 spin_lock_irqsave(&clk_mgt_lock, flags);
1756
1757 /* Grab the HW semaphore. */
1758 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1759 cpu_relax();
1760
1761 val = readl(prcmu_base + clk_mgt[clock].offset);
1762 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1763 clk_mgt[clock].branch);
1764 div = clock_divider(src_rate, rate);
1765 if (val & PRCM_CLK_MGT_CLK38) {
1766 if (clk_mgt[clock].clk38div) {
1767 if (div > 1)
1768 val |= PRCM_CLK_MGT_CLK38DIV;
1769 else
1770 val &= ~PRCM_CLK_MGT_CLK38DIV;
1771 }
1772 } else if (clock == PRCMU_SGACLK) {
1773 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1774 PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
1775 if (div == 3) {
1776 u64 r = (src_rate * 10);
1777
1778 (void)do_div(r, 25);
1779 if (r <= rate) {
1780 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1781 div = 0;
1782 }
1783 }
1784 val |= min(div, (u32)31);
1785 } else {
1786 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1787 val |= min(div, (u32)31);
1788 }
1789 writel(val, prcmu_base + clk_mgt[clock].offset);
1790
1791 /* Release the HW semaphore. */
1792 writel(0, PRCM_SEM);
1793
1794 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1795}
1796
1797static int set_armss_rate(unsigned long rate)
1798{
1799 unsigned long freq;
1800 u8 opps[] = { ARM_EXTCLK, ARM_50_OPP, ARM_100_OPP, ARM_MAX_OPP };
1801 const unsigned long *freqs;
1802 int nfreqs;
1803 int i;
1804
1805 if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) {
1806 freqs = db8520_armss_freqs;
1807 nfreqs = ARRAY_SIZE(db8520_armss_freqs);
1808 } else {
1809 freqs = db8500_armss_freqs;
1810 nfreqs = ARRAY_SIZE(db8500_armss_freqs);
1811 }
1812
1813 /* Find the corresponding arm opp from the cpufreq table. */
1814 for (i = 0; i < nfreqs; i++) {
1815 freq = freqs[i];
1816 if (rate == freq)
1817 break;
1818 }
1819
1820 if (rate != freq)
1821 return -EINVAL;
1822
1823 /* Set the new arm opp. */
1824 pr_debug("SET ARM OPP 0x%02x\n", opps[i]);
1825 return db8500_prcmu_set_arm_opp(opps[i]);
1826}
1827
1828static int set_plldsi_rate(unsigned long rate)
1829{
1830 unsigned long src_rate;
1831 unsigned long rem;
1832 u32 pll_freq = 0;
1833 u32 r;
1834
1835 src_rate = clock_rate(PRCMU_HDMICLK);
1836 rem = rate;
1837
1838 for (r = 7; (rem > 0) && (r > 0); r--) {
1839 u64 d;
1840 u64 hwrate;
1841
1842 d = (r * rate);
1843 (void)do_div(d, src_rate);
1844 if (d < 6)
1845 d = 6;
1846 else if (d > 255)
1847 d = 255;
1848 hwrate = (d * src_rate);
1849 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
1850 ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
1851 continue;
1852 (void)do_div(hwrate, r);
1853 if (rate < hwrate) {
1854 if (pll_freq == 0)
1855 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1856 (r << PRCM_PLL_FREQ_R_SHIFT));
1857 break;
1858 }
1859 if ((rate - hwrate) < rem) {
1860 rem = (rate - hwrate);
1861 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1862 (r << PRCM_PLL_FREQ_R_SHIFT));
1863 }
1864 }
1865 if (pll_freq == 0)
1866 return -EINVAL;
1867
1868 pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
1869 writel(pll_freq, PRCM_PLLDSI_FREQ);
1870
1871 return 0;
1872}
1873
1874static void set_dsiclk_rate(u8 n, unsigned long rate)
1875{
1876 u32 val;
1877 u32 div;
1878
1879 div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
1880 clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
1881
1882 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
1883 (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
1884 /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4;
1885
1886 val = readl(PRCM_DSI_PLLOUT_SEL);
1887 val &= ~dsiclk[n].divsel_mask;
1888 val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
1889 writel(val, PRCM_DSI_PLLOUT_SEL);
1890}
1891
1892static void set_dsiescclk_rate(u8 n, unsigned long rate)
1893{
1894 u32 val;
1895 u32 div;
1896
1897 div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
1898 val = readl(PRCM_DSITVCLK_DIV);
1899 val &= ~dsiescclk[n].div_mask;
1900 val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
1901 writel(val, PRCM_DSITVCLK_DIV);
1902}
1903
1904int prcmu_set_clock_rate(u8 clock, unsigned long rate)
1905{
1906 if (clock < PRCMU_NUM_REG_CLOCKS)
1907 set_clock_rate(clock, rate);
1908 else if (clock == PRCMU_ARMSS)
1909 return set_armss_rate(rate);
1910 else if (clock == PRCMU_PLLDSI)
1911 return set_plldsi_rate(rate);
1912 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1913 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
1914 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1915 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
1916 return 0;
1917}
1918
1919int db8500_prcmu_config_esram0_deep_sleep(u8 state)
1920{
1921 if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
1922 (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
1923 return -EINVAL;
1924
1925 mutex_lock(&mb4_transfer.lock);
1926
1927 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
1928 cpu_relax();
1929
1930 writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1931 writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
1932 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
1933 writeb(DDR_PWR_STATE_ON,
1934 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
1935 writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
1936
1937 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
1938 wait_for_completion(&mb4_transfer.work);
1939
1940 mutex_unlock(&mb4_transfer.lock);
1941
1942 return 0;
1943}
1944
1945int db8500_prcmu_config_hotdog(u8 threshold)
1946{
1947 mutex_lock(&mb4_transfer.lock);
1948
1949 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
1950 cpu_relax();
1951
1952 writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
1953 writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1954
1955 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
1956 wait_for_completion(&mb4_transfer.work);
1957
1958 mutex_unlock(&mb4_transfer.lock);
1959
1960 return 0;
1961}
1962
1963int db8500_prcmu_config_hotmon(u8 low, u8 high)
1964{
1965 mutex_lock(&mb4_transfer.lock);
1966
1967 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
1968 cpu_relax();
1969
1970 writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
1971 writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
1972 writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
1973 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
1974 writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1975
1976 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
1977 wait_for_completion(&mb4_transfer.work);
1978
1979 mutex_unlock(&mb4_transfer.lock);
1980
1981 return 0;
1982}
1983EXPORT_SYMBOL_GPL(db8500_prcmu_config_hotmon);
1984
1985static int config_hot_period(u16 val)
1986{
1987 mutex_lock(&mb4_transfer.lock);
1988
1989 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
1990 cpu_relax();
1991
1992 writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
1993 writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1994
1995 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
1996 wait_for_completion(&mb4_transfer.work);
1997
1998 mutex_unlock(&mb4_transfer.lock);
1999
2000 return 0;
2001}
2002
2003int db8500_prcmu_start_temp_sense(u16 cycles32k)
2004{
2005 if (cycles32k == 0xFFFF)
2006 return -EINVAL;
2007
2008 return config_hot_period(cycles32k);
2009}
2010EXPORT_SYMBOL_GPL(db8500_prcmu_start_temp_sense);
2011
2012int db8500_prcmu_stop_temp_sense(void)
2013{
2014 return config_hot_period(0xFFFF);
2015}
2016EXPORT_SYMBOL_GPL(db8500_prcmu_stop_temp_sense);
2017
2018static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2019{
2020
2021 mutex_lock(&mb4_transfer.lock);
2022
2023 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2024 cpu_relax();
2025
2026 writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2027 writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2028 writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2029 writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2030
2031 writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2032
2033 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2034 wait_for_completion(&mb4_transfer.work);
2035
2036 mutex_unlock(&mb4_transfer.lock);
2037
2038 return 0;
2039
2040}
2041
2042int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
2043{
2044 BUG_ON(num == 0 || num > 0xf);
2045 return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2046 sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2047 A9WDOG_AUTO_OFF_DIS);
2048}
2049EXPORT_SYMBOL(db8500_prcmu_config_a9wdog);
2050
2051int db8500_prcmu_enable_a9wdog(u8 id)
2052{
2053 return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2054}
2055EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog);
2056
2057int db8500_prcmu_disable_a9wdog(u8 id)
2058{
2059 return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2060}
2061EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog);
2062
2063int db8500_prcmu_kick_a9wdog(u8 id)
2064{
2065 return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2066}
2067EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog);
2068
2069/*
2070 * timeout is 28 bit, in ms.
2071 */
2072int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
2073{
2074 return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2075 (id & A9WDOG_ID_MASK) |
2076 /*
2077 * Put the lowest 28 bits of timeout at
2078 * offset 4. Four first bits are used for id.
2079 */
2080 (u8)((timeout << 4) & 0xf0),
2081 (u8)((timeout >> 4) & 0xff),
2082 (u8)((timeout >> 12) & 0xff),
2083 (u8)((timeout >> 20) & 0xff));
2084}
2085EXPORT_SYMBOL(db8500_prcmu_load_a9wdog);
2086
2087/**
2088 * prcmu_abb_read() - Read register value(s) from the ABB.
2089 * @slave: The I2C slave address.
2090 * @reg: The (start) register address.
2091 * @value: The read out value(s).
2092 * @size: The number of registers to read.
2093 *
2094 * Reads register value(s) from the ABB.
2095 * @size has to be 1 for the current firmware version.
2096 */
2097int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2098{
2099 int r;
2100
2101 if (size != 1)
2102 return -EINVAL;
2103
2104 mutex_lock(&mb5_transfer.lock);
2105
2106 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2107 cpu_relax();
2108
2109 writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2110 writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2111 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2112 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2113 writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2114
2115 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2116
2117 if (!wait_for_completion_timeout(&mb5_transfer.work,
2118 msecs_to_jiffies(20000))) {
2119 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2120 __func__);
2121 r = -EIO;
2122 } else {
2123 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
2124 }
2125
2126 if (!r)
2127 *value = mb5_transfer.ack.value;
2128
2129 mutex_unlock(&mb5_transfer.lock);
2130
2131 return r;
2132}
2133
2134/**
2135 * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2136 * @slave: The I2C slave address.
2137 * @reg: The (start) register address.
2138 * @value: The value(s) to write.
2139 * @mask: The mask(s) to use.
2140 * @size: The number of registers to write.
2141 *
2142 * Writes masked register value(s) to the ABB.
2143 * For each @value, only the bits set to 1 in the corresponding @mask
2144 * will be written. The other bits are not changed.
2145 * @size has to be 1 for the current firmware version.
2146 */
2147int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
2148{
2149 int r;
2150
2151 if (size != 1)
2152 return -EINVAL;
2153
2154 mutex_lock(&mb5_transfer.lock);
2155
2156 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2157 cpu_relax();
2158
2159 writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2160 writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2161 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2162 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2163 writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2164
2165 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2166
2167 if (!wait_for_completion_timeout(&mb5_transfer.work,
2168 msecs_to_jiffies(20000))) {
2169 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2170 __func__);
2171 r = -EIO;
2172 } else {
2173 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
2174 }
2175
2176 mutex_unlock(&mb5_transfer.lock);
2177
2178 return r;
2179}
2180
2181/**
2182 * prcmu_abb_write() - Write register value(s) to the ABB.
2183 * @slave: The I2C slave address.
2184 * @reg: The (start) register address.
2185 * @value: The value(s) to write.
2186 * @size: The number of registers to write.
2187 *
2188 * Writes register value(s) to the ABB.
2189 * @size has to be 1 for the current firmware version.
2190 */
2191int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2192{
2193 u8 mask = ~0;
2194
2195 return prcmu_abb_write_masked(slave, reg, value, &mask, size);
2196}
2197
2198/**
2199 * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2200 */
2201int prcmu_ac_wake_req(void)
2202{
2203 u32 val;
2204 int ret = 0;
2205
2206 mutex_lock(&mb0_transfer.ac_wake_lock);
2207
2208 val = readl(PRCM_HOSTACCESS_REQ);
2209 if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2210 goto unlock_and_return;
2211
2212 atomic_set(&ac_wake_req_state, 1);
2213
2214 /*
2215 * Force Modem Wake-up before hostaccess_req ping-pong.
2216 * It prevents Modem to enter in Sleep while acking the hostaccess
2217 * request. The 31us delay has been calculated by HWI.
2218 */
2219 val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
2220 writel(val, PRCM_HOSTACCESS_REQ);
2221
2222 udelay(31);
2223
2224 val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
2225 writel(val, PRCM_HOSTACCESS_REQ);
2226
2227 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2228 msecs_to_jiffies(5000))) {
2229 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2230 __func__);
2231 ret = -EFAULT;
2232 }
2233
2234unlock_and_return:
2235 mutex_unlock(&mb0_transfer.ac_wake_lock);
2236 return ret;
2237}
2238
2239/**
2240 * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2241 */
2242void prcmu_ac_sleep_req(void)
2243{
2244 u32 val;
2245
2246 mutex_lock(&mb0_transfer.ac_wake_lock);
2247
2248 val = readl(PRCM_HOSTACCESS_REQ);
2249 if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2250 goto unlock_and_return;
2251
2252 writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2253 PRCM_HOSTACCESS_REQ);
2254
2255 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2256 msecs_to_jiffies(5000))) {
2257 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2258 __func__);
2259 }
2260
2261 atomic_set(&ac_wake_req_state, 0);
2262
2263unlock_and_return:
2264 mutex_unlock(&mb0_transfer.ac_wake_lock);
2265}
2266
2267bool db8500_prcmu_is_ac_wake_requested(void)
2268{
2269 return (atomic_read(&ac_wake_req_state) != 0);
2270}
2271
2272/**
2273 * db8500_prcmu_system_reset - System reset
2274 *
2275 * Saves the reset reason code and then sets the APE_SOFTRST register which
2276 * fires interrupt to fw
2277 *
2278 * @reset_code: The reason for system reset
2279 */
2280void db8500_prcmu_system_reset(u16 reset_code)
2281{
2282 writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
2283 writel(1, PRCM_APE_SOFTRST);
2284}
2285
2286/**
2287 * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2288 *
2289 * Retrieves the reset reason code stored by prcmu_system_reset() before
2290 * last restart.
2291 */
2292u16 db8500_prcmu_get_reset_code(void)
2293{
2294 return readw(tcdm_base + PRCM_SW_RST_REASON);
2295}
2296
2297/**
2298 * db8500_prcmu_modem_reset - ask the PRCMU to reset modem
2299 */
2300void db8500_prcmu_modem_reset(void)
2301{
2302 mutex_lock(&mb1_transfer.lock);
2303
2304 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
2305 cpu_relax();
2306
2307 writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
2308 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
2309 wait_for_completion(&mb1_transfer.work);
2310
2311 /*
2312 * No need to check return from PRCMU as modem should go in reset state
2313 * This state is already managed by upper layer
2314 */
2315
2316 mutex_unlock(&mb1_transfer.lock);
2317}
2318
2319static void ack_dbb_wakeup(void)
2320{
2321 unsigned long flags;
2322
2323 spin_lock_irqsave(&mb0_transfer.lock, flags);
2324
2325 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
2326 cpu_relax();
2327
2328 writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
2329 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
2330
2331 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2332}
2333
2334static inline void print_unknown_header_warning(u8 n, u8 header)
2335{
2336 pr_warn("prcmu: Unknown message header (%d) in mailbox %d\n",
2337 header, n);
2338}
2339
2340static bool read_mailbox_0(void)
2341{
2342 bool r;
2343 u32 ev;
2344 unsigned int n;
2345 u8 header;
2346
2347 header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2348 switch (header) {
2349 case MB0H_WAKEUP_EXE:
2350 case MB0H_WAKEUP_SLEEP:
2351 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2352 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2353 else
2354 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2355
2356 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2357 complete(&mb0_transfer.ac_wake_work);
2358 if (ev & WAKEUP_BIT_SYSCLK_OK)
2359 complete(&mb3_transfer.sysclk_work);
2360
2361 ev &= mb0_transfer.req.dbb_irqs;
2362
2363 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2364 if (ev & prcmu_irq_bit[n])
2365 generic_handle_irq(irq_find_mapping(db8500_irq_domain, n));
2366 }
2367 r = true;
2368 break;
2369 default:
2370 print_unknown_header_warning(0, header);
2371 r = false;
2372 break;
2373 }
2374 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
2375 return r;
2376}
2377
2378static bool read_mailbox_1(void)
2379{
2380 mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2381 mb1_transfer.ack.arm_opp = readb(tcdm_base +
2382 PRCM_ACK_MB1_CURRENT_ARM_OPP);
2383 mb1_transfer.ack.ape_opp = readb(tcdm_base +
2384 PRCM_ACK_MB1_CURRENT_APE_OPP);
2385 mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2386 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
2387 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
2388 complete(&mb1_transfer.work);
2389 return false;
2390}
2391
2392static bool read_mailbox_2(void)
2393{
2394 mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
2395 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
2396 complete(&mb2_transfer.work);
2397 return false;
2398}
2399
2400static bool read_mailbox_3(void)
2401{
2402 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
2403 return false;
2404}
2405
2406static bool read_mailbox_4(void)
2407{
2408 u8 header;
2409 bool do_complete = true;
2410
2411 header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2412 switch (header) {
2413 case MB4H_MEM_ST:
2414 case MB4H_HOTDOG:
2415 case MB4H_HOTMON:
2416 case MB4H_HOT_PERIOD:
2417 case MB4H_A9WDOG_CONF:
2418 case MB4H_A9WDOG_EN:
2419 case MB4H_A9WDOG_DIS:
2420 case MB4H_A9WDOG_LOAD:
2421 case MB4H_A9WDOG_KICK:
2422 break;
2423 default:
2424 print_unknown_header_warning(4, header);
2425 do_complete = false;
2426 break;
2427 }
2428
2429 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
2430
2431 if (do_complete)
2432 complete(&mb4_transfer.work);
2433
2434 return false;
2435}
2436
2437static bool read_mailbox_5(void)
2438{
2439 mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2440 mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
2441 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
2442 complete(&mb5_transfer.work);
2443 return false;
2444}
2445
2446static bool read_mailbox_6(void)
2447{
2448 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
2449 return false;
2450}
2451
2452static bool read_mailbox_7(void)
2453{
2454 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
2455 return false;
2456}
2457
2458static bool (* const read_mailbox[NUM_MB])(void) = {
2459 read_mailbox_0,
2460 read_mailbox_1,
2461 read_mailbox_2,
2462 read_mailbox_3,
2463 read_mailbox_4,
2464 read_mailbox_5,
2465 read_mailbox_6,
2466 read_mailbox_7
2467};
2468
2469static irqreturn_t prcmu_irq_handler(int irq, void *data)
2470{
2471 u32 bits;
2472 u8 n;
2473 irqreturn_t r;
2474
2475 bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
2476 if (unlikely(!bits))
2477 return IRQ_NONE;
2478
2479 r = IRQ_HANDLED;
2480 for (n = 0; bits; n++) {
2481 if (bits & MBOX_BIT(n)) {
2482 bits -= MBOX_BIT(n);
2483 if (read_mailbox[n]())
2484 r = IRQ_WAKE_THREAD;
2485 }
2486 }
2487 return r;
2488}
2489
2490static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2491{
2492 ack_dbb_wakeup();
2493 return IRQ_HANDLED;
2494}
2495
2496static void prcmu_mask_work(struct work_struct *work)
2497{
2498 unsigned long flags;
2499
2500 spin_lock_irqsave(&mb0_transfer.lock, flags);
2501
2502 config_wakeups();
2503
2504 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2505}
2506
2507static void prcmu_irq_mask(struct irq_data *d)
2508{
2509 unsigned long flags;
2510
2511 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2512
2513 mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
2514
2515 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2516
2517 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2518 schedule_work(&mb0_transfer.mask_work);
2519}
2520
2521static void prcmu_irq_unmask(struct irq_data *d)
2522{
2523 unsigned long flags;
2524
2525 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2526
2527 mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
2528
2529 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2530
2531 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2532 schedule_work(&mb0_transfer.mask_work);
2533}
2534
2535static void noop(struct irq_data *d)
2536{
2537}
2538
2539static struct irq_chip prcmu_irq_chip = {
2540 .name = "prcmu",
2541 .irq_disable = prcmu_irq_mask,
2542 .irq_ack = noop,
2543 .irq_mask = prcmu_irq_mask,
2544 .irq_unmask = prcmu_irq_unmask,
2545};
2546
2547static char *fw_project_name(u32 project)
2548{
2549 switch (project) {
2550 case PRCMU_FW_PROJECT_U8500:
2551 return "U8500";
2552 case PRCMU_FW_PROJECT_U8400:
2553 return "U8400";
2554 case PRCMU_FW_PROJECT_U9500:
2555 return "U9500";
2556 case PRCMU_FW_PROJECT_U8500_MBB:
2557 return "U8500 MBB";
2558 case PRCMU_FW_PROJECT_U8500_C1:
2559 return "U8500 C1";
2560 case PRCMU_FW_PROJECT_U8500_C2:
2561 return "U8500 C2";
2562 case PRCMU_FW_PROJECT_U8500_C3:
2563 return "U8500 C3";
2564 case PRCMU_FW_PROJECT_U8500_C4:
2565 return "U8500 C4";
2566 case PRCMU_FW_PROJECT_U9500_MBL:
2567 return "U9500 MBL";
2568 case PRCMU_FW_PROJECT_U8500_MBL:
2569 return "U8500 MBL";
2570 case PRCMU_FW_PROJECT_U8500_MBL2:
2571 return "U8500 MBL2";
2572 case PRCMU_FW_PROJECT_U8520:
2573 return "U8520 MBL";
2574 case PRCMU_FW_PROJECT_U8420:
2575 return "U8420";
2576 case PRCMU_FW_PROJECT_U8420_SYSCLK:
2577 return "U8420-sysclk";
2578 case PRCMU_FW_PROJECT_U9540:
2579 return "U9540";
2580 case PRCMU_FW_PROJECT_A9420:
2581 return "A9420";
2582 case PRCMU_FW_PROJECT_L8540:
2583 return "L8540";
2584 case PRCMU_FW_PROJECT_L8580:
2585 return "L8580";
2586 default:
2587 return "Unknown";
2588 }
2589}
2590
2591static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
2592 irq_hw_number_t hwirq)
2593{
2594 irq_set_chip_and_handler(virq, &prcmu_irq_chip,
2595 handle_simple_irq);
2596
2597 return 0;
2598}
2599
2600static const struct irq_domain_ops db8500_irq_ops = {
2601 .map = db8500_irq_map,
2602 .xlate = irq_domain_xlate_twocell,
2603};
2604
2605static int db8500_irq_init(struct device_node *np)
2606{
2607 int i;
2608
2609 db8500_irq_domain = irq_domain_add_simple(
2610 np, NUM_PRCMU_WAKEUPS, 0,
2611 &db8500_irq_ops, NULL);
2612
2613 if (!db8500_irq_domain) {
2614 pr_err("Failed to create irqdomain\n");
2615 return -ENOSYS;
2616 }
2617
2618 /* All wakeups will be used, so create mappings for all */
2619 for (i = 0; i < NUM_PRCMU_WAKEUPS; i++)
2620 irq_create_mapping(db8500_irq_domain, i);
2621
2622 return 0;
2623}
2624
2625static void dbx500_fw_version_init(struct device_node *np)
2626{
2627 void __iomem *tcpm_base;
2628 u32 version;
2629
2630 tcpm_base = of_iomap(np, 1);
2631 if (!tcpm_base) {
2632 pr_err("no prcmu tcpm mem region provided\n");
2633 return;
2634 }
2635
2636 version = readl(tcpm_base + DB8500_PRCMU_FW_VERSION_OFFSET);
2637 fw_info.version.project = (version & 0xFF);
2638 fw_info.version.api_version = (version >> 8) & 0xFF;
2639 fw_info.version.func_version = (version >> 16) & 0xFF;
2640 fw_info.version.errata = (version >> 24) & 0xFF;
2641 strncpy(fw_info.version.project_name,
2642 fw_project_name(fw_info.version.project),
2643 PRCMU_FW_PROJECT_NAME_LEN);
2644 fw_info.valid = true;
2645 pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n",
2646 fw_info.version.project_name,
2647 fw_info.version.project,
2648 fw_info.version.api_version,
2649 fw_info.version.func_version,
2650 fw_info.version.errata);
2651 iounmap(tcpm_base);
2652}
2653
2654void __init db8500_prcmu_early_init(void)
2655{
2656 /*
2657 * This is a temporary remap to bring up the clocks. It is
2658 * subsequently replaces with a real remap. After the merge of
2659 * the mailbox subsystem all of this early code goes away, and the
2660 * clock driver can probe independently. An early initcall will
2661 * still be needed, but it can be diverted into drivers/clk/ux500.
2662 */
2663 struct device_node *np;
2664
2665 np = of_find_compatible_node(NULL, NULL, "stericsson,db8500-prcmu");
2666 prcmu_base = of_iomap(np, 0);
2667 if (!prcmu_base) {
2668 of_node_put(np);
2669 pr_err("%s: ioremap() of prcmu registers failed!\n", __func__);
2670 return;
2671 }
2672 dbx500_fw_version_init(np);
2673 of_node_put(np);
2674
2675 spin_lock_init(&mb0_transfer.lock);
2676 spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2677 mutex_init(&mb0_transfer.ac_wake_lock);
2678 init_completion(&mb0_transfer.ac_wake_work);
2679 mutex_init(&mb1_transfer.lock);
2680 init_completion(&mb1_transfer.work);
2681 mb1_transfer.ape_opp = APE_NO_CHANGE;
2682 mutex_init(&mb2_transfer.lock);
2683 init_completion(&mb2_transfer.work);
2684 spin_lock_init(&mb2_transfer.auto_pm_lock);
2685 spin_lock_init(&mb3_transfer.lock);
2686 mutex_init(&mb3_transfer.sysclk_lock);
2687 init_completion(&mb3_transfer.sysclk_work);
2688 mutex_init(&mb4_transfer.lock);
2689 init_completion(&mb4_transfer.work);
2690 mutex_init(&mb5_transfer.lock);
2691 init_completion(&mb5_transfer.work);
2692
2693 INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
2694}
2695
2696static void init_prcm_registers(void)
2697{
2698 u32 val;
2699
2700 val = readl(PRCM_A9PL_FORCE_CLKEN);
2701 val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2702 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2703 writel(val, (PRCM_A9PL_FORCE_CLKEN));
2704}
2705
2706/*
2707 * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2708 */
2709static struct regulator_consumer_supply db8500_vape_consumers[] = {
2710 REGULATOR_SUPPLY("v-ape", NULL),
2711 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2712 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2713 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2714 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2715 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
2716 /* "v-mmc" changed to "vcore" in the mainline kernel */
2717 REGULATOR_SUPPLY("vcore", "sdi0"),
2718 REGULATOR_SUPPLY("vcore", "sdi1"),
2719 REGULATOR_SUPPLY("vcore", "sdi2"),
2720 REGULATOR_SUPPLY("vcore", "sdi3"),
2721 REGULATOR_SUPPLY("vcore", "sdi4"),
2722 REGULATOR_SUPPLY("v-dma", "dma40.0"),
2723 REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2724 /* "v-uart" changed to "vcore" in the mainline kernel */
2725 REGULATOR_SUPPLY("vcore", "uart0"),
2726 REGULATOR_SUPPLY("vcore", "uart1"),
2727 REGULATOR_SUPPLY("vcore", "uart2"),
2728 REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2729 REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2730 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
2731};
2732
2733static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
2734 REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2735 /* AV8100 regulator */
2736 REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2737};
2738
2739static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
2740 REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2741 REGULATOR_SUPPLY("vsupply", "mcde"),
2742};
2743
2744/* SVA MMDSP regulator switch */
2745static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2746 REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2747};
2748
2749/* SVA pipe regulator switch */
2750static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2751 REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2752};
2753
2754/* SIA MMDSP regulator switch */
2755static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2756 REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2757};
2758
2759/* SIA pipe regulator switch */
2760static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2761 REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2762};
2763
2764static struct regulator_consumer_supply db8500_sga_consumers[] = {
2765 REGULATOR_SUPPLY("v-mali", NULL),
2766};
2767
2768/* ESRAM1 and 2 regulator switch */
2769static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2770 REGULATOR_SUPPLY("esram12", "cm_control"),
2771};
2772
2773/* ESRAM3 and 4 regulator switch */
2774static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2775 REGULATOR_SUPPLY("v-esram34", "mcde"),
2776 REGULATOR_SUPPLY("esram34", "cm_control"),
2777 REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
2778};
2779
2780static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2781 [DB8500_REGULATOR_VAPE] = {
2782 .constraints = {
2783 .name = "db8500-vape",
2784 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2785 .always_on = true,
2786 },
2787 .consumer_supplies = db8500_vape_consumers,
2788 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2789 },
2790 [DB8500_REGULATOR_VARM] = {
2791 .constraints = {
2792 .name = "db8500-varm",
2793 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2794 },
2795 },
2796 [DB8500_REGULATOR_VMODEM] = {
2797 .constraints = {
2798 .name = "db8500-vmodem",
2799 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2800 },
2801 },
2802 [DB8500_REGULATOR_VPLL] = {
2803 .constraints = {
2804 .name = "db8500-vpll",
2805 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2806 },
2807 },
2808 [DB8500_REGULATOR_VSMPS1] = {
2809 .constraints = {
2810 .name = "db8500-vsmps1",
2811 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2812 },
2813 },
2814 [DB8500_REGULATOR_VSMPS2] = {
2815 .constraints = {
2816 .name = "db8500-vsmps2",
2817 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2818 },
2819 .consumer_supplies = db8500_vsmps2_consumers,
2820 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2821 },
2822 [DB8500_REGULATOR_VSMPS3] = {
2823 .constraints = {
2824 .name = "db8500-vsmps3",
2825 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2826 },
2827 },
2828 [DB8500_REGULATOR_VRF1] = {
2829 .constraints = {
2830 .name = "db8500-vrf1",
2831 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2832 },
2833 },
2834 [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
2835 /* dependency to u8500-vape is handled outside regulator framework */
2836 .constraints = {
2837 .name = "db8500-sva-mmdsp",
2838 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2839 },
2840 .consumer_supplies = db8500_svammdsp_consumers,
2841 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
2842 },
2843 [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2844 .constraints = {
2845 /* "ret" means "retention" */
2846 .name = "db8500-sva-mmdsp-ret",
2847 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2848 },
2849 },
2850 [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
2851 /* dependency to u8500-vape is handled outside regulator framework */
2852 .constraints = {
2853 .name = "db8500-sva-pipe",
2854 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2855 },
2856 .consumer_supplies = db8500_svapipe_consumers,
2857 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
2858 },
2859 [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
2860 /* dependency to u8500-vape is handled outside regulator framework */
2861 .constraints = {
2862 .name = "db8500-sia-mmdsp",
2863 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2864 },
2865 .consumer_supplies = db8500_siammdsp_consumers,
2866 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
2867 },
2868 [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
2869 .constraints = {
2870 .name = "db8500-sia-mmdsp-ret",
2871 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2872 },
2873 },
2874 [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
2875 /* dependency to u8500-vape is handled outside regulator framework */
2876 .constraints = {
2877 .name = "db8500-sia-pipe",
2878 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2879 },
2880 .consumer_supplies = db8500_siapipe_consumers,
2881 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
2882 },
2883 [DB8500_REGULATOR_SWITCH_SGA] = {
2884 .supply_regulator = "db8500-vape",
2885 .constraints = {
2886 .name = "db8500-sga",
2887 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2888 },
2889 .consumer_supplies = db8500_sga_consumers,
2890 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
2891
2892 },
2893 [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
2894 .supply_regulator = "db8500-vape",
2895 .constraints = {
2896 .name = "db8500-b2r2-mcde",
2897 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2898 },
2899 .consumer_supplies = db8500_b2r2_mcde_consumers,
2900 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
2901 },
2902 [DB8500_REGULATOR_SWITCH_ESRAM12] = {
2903 /*
2904 * esram12 is set in retention and supplied by Vsafe when Vape is off,
2905 * no need to hold Vape
2906 */
2907 .constraints = {
2908 .name = "db8500-esram12",
2909 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2910 },
2911 .consumer_supplies = db8500_esram12_consumers,
2912 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
2913 },
2914 [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
2915 .constraints = {
2916 .name = "db8500-esram12-ret",
2917 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2918 },
2919 },
2920 [DB8500_REGULATOR_SWITCH_ESRAM34] = {
2921 /*
2922 * esram34 is set in retention and supplied by Vsafe when Vape is off,
2923 * no need to hold Vape
2924 */
2925 .constraints = {
2926 .name = "db8500-esram34",
2927 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2928 },
2929 .consumer_supplies = db8500_esram34_consumers,
2930 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
2931 },
2932 [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
2933 .constraints = {
2934 .name = "db8500-esram34-ret",
2935 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2936 },
2937 },
2938};
2939
2940static struct ux500_wdt_data db8500_wdt_pdata = {
2941 .timeout = 600, /* 10 minutes */
2942 .has_28_bits_resolution = true,
2943};
2944
2945static const struct mfd_cell common_prcmu_devs[] = {
2946 {
2947 .name = "ux500_wdt",
2948 .platform_data = &db8500_wdt_pdata,
2949 .pdata_size = sizeof(db8500_wdt_pdata),
2950 .id = -1,
2951 },
2952};
2953
2954static const struct mfd_cell db8500_prcmu_devs[] = {
2955 MFD_CELL_OF("db8500-prcmu-regulators", NULL,
2956 &db8500_regulators, sizeof(db8500_regulators), 0,
2957 "stericsson,db8500-prcmu-regulator"),
2958 MFD_CELL_OF("cpuidle-dbx500",
2959 NULL, NULL, 0, 0, "stericsson,cpuidle-dbx500"),
2960 MFD_CELL_OF("db8500-thermal",
2961 NULL, NULL, 0, 0, "stericsson,db8500-thermal"),
2962};
2963
2964static int db8500_prcmu_register_ab8500(struct device *parent)
2965{
2966 struct device_node *np;
2967 struct resource ab850x_resource;
2968 const struct mfd_cell ab8500_cell = {
2969 .name = "ab8500-core",
2970 .of_compatible = "stericsson,ab8500",
2971 .id = AB8500_VERSION_AB8500,
2972 .resources = &ab850x_resource,
2973 .num_resources = 1,
2974 };
2975 const struct mfd_cell ab8505_cell = {
2976 .name = "ab8505-core",
2977 .of_compatible = "stericsson,ab8505",
2978 .id = AB8500_VERSION_AB8505,
2979 .resources = &ab850x_resource,
2980 .num_resources = 1,
2981 };
2982 const struct mfd_cell *ab850x_cell;
2983
2984 if (!parent->of_node)
2985 return -ENODEV;
2986
2987 /* Look up the device node, sneak the IRQ out of it */
2988 for_each_child_of_node(parent->of_node, np) {
2989 if (of_device_is_compatible(np, ab8500_cell.of_compatible)) {
2990 ab850x_cell = &ab8500_cell;
2991 break;
2992 }
2993 if (of_device_is_compatible(np, ab8505_cell.of_compatible)) {
2994 ab850x_cell = &ab8505_cell;
2995 break;
2996 }
2997 }
2998 if (!np) {
2999 dev_info(parent, "could not find AB850X node in the device tree\n");
3000 return -ENODEV;
3001 }
3002 of_irq_to_resource_table(np, &ab850x_resource, 1);
3003
3004 return mfd_add_devices(parent, 0, ab850x_cell, 1, NULL, 0, NULL);
3005}
3006
3007static int db8500_prcmu_probe(struct platform_device *pdev)
3008{
3009 struct device_node *np = pdev->dev.of_node;
3010 int irq = 0, err = 0;
3011 struct resource *res;
3012
3013 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu");
3014 if (!res) {
3015 dev_err(&pdev->dev, "no prcmu memory region provided\n");
3016 return -EINVAL;
3017 }
3018 prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3019 if (!prcmu_base) {
3020 dev_err(&pdev->dev,
3021 "failed to ioremap prcmu register memory\n");
3022 return -ENOMEM;
3023 }
3024 init_prcm_registers();
3025 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm");
3026 if (!res) {
3027 dev_err(&pdev->dev, "no prcmu tcdm region provided\n");
3028 return -EINVAL;
3029 }
3030 tcdm_base = devm_ioremap(&pdev->dev, res->start,
3031 resource_size(res));
3032 if (!tcdm_base) {
3033 dev_err(&pdev->dev,
3034 "failed to ioremap prcmu-tcdm register memory\n");
3035 return -ENOMEM;
3036 }
3037
3038 /* Clean up the mailbox interrupts after pre-kernel code. */
3039 writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
3040
3041 irq = platform_get_irq(pdev, 0);
3042 if (irq <= 0)
3043 return irq;
3044
3045 err = request_threaded_irq(irq, prcmu_irq_handler,
3046 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
3047 if (err < 0) {
3048 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
3049 return err;
3050 }
3051
3052 db8500_irq_init(np);
3053
3054 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3055
3056 err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs,
3057 ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain);
3058 if (err) {
3059 pr_err("prcmu: Failed to add subdevices\n");
3060 return err;
3061 }
3062
3063 /* TODO: Remove restriction when clk definitions are available. */
3064 if (!of_machine_is_compatible("st-ericsson,u8540")) {
3065 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3066 ARRAY_SIZE(db8500_prcmu_devs), NULL, 0,
3067 db8500_irq_domain);
3068 if (err) {
3069 mfd_remove_devices(&pdev->dev);
3070 pr_err("prcmu: Failed to add subdevices\n");
3071 return err;
3072 }
3073 }
3074
3075 err = db8500_prcmu_register_ab8500(&pdev->dev);
3076 if (err) {
3077 mfd_remove_devices(&pdev->dev);
3078 pr_err("prcmu: Failed to add ab8500 subdevice\n");
3079 return err;
3080 }
3081
3082 pr_info("DB8500 PRCMU initialized\n");
3083 return err;
3084}
3085static const struct of_device_id db8500_prcmu_match[] = {
3086 { .compatible = "stericsson,db8500-prcmu"},
3087 { },
3088};
3089
3090static struct platform_driver db8500_prcmu_driver = {
3091 .driver = {
3092 .name = "db8500-prcmu",
3093 .of_match_table = db8500_prcmu_match,
3094 },
3095 .probe = db8500_prcmu_probe,
3096};
3097
3098static int __init db8500_prcmu_init(void)
3099{
3100 return platform_driver_register(&db8500_prcmu_driver);
3101}
3102core_initcall(db8500_prcmu_init);