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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
7 */
8
9/**
10 * DOC: VC4 Falcon HDMI module
11 *
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
15 *
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
18 *
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
23 * blank regions.
24 *
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
29 *
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
32 */
33
34#include <drm/drm_atomic_helper.h>
35#include <drm/drm_edid.h>
36#include <drm/drm_probe_helper.h>
37#include <drm/drm_simple_kms_helper.h>
38#include <drm/drm_scdc_helper.h>
39#include <linux/clk.h>
40#include <linux/component.h>
41#include <linux/i2c.h>
42#include <linux/of_address.h>
43#include <linux/of_gpio.h>
44#include <linux/of_platform.h>
45#include <linux/pm_runtime.h>
46#include <linux/rational.h>
47#include <linux/reset.h>
48#include <sound/dmaengine_pcm.h>
49#include <sound/pcm_drm_eld.h>
50#include <sound/pcm_params.h>
51#include <sound/soc.h>
52#include "media/cec.h"
53#include "vc4_drv.h"
54#include "vc4_hdmi.h"
55#include "vc4_hdmi_regs.h"
56#include "vc4_regs.h"
57
58#define VC5_HDMI_HORZA_HFP_SHIFT 16
59#define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
60#define VC5_HDMI_HORZA_VPOS BIT(15)
61#define VC5_HDMI_HORZA_HPOS BIT(14)
62#define VC5_HDMI_HORZA_HAP_SHIFT 0
63#define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
64
65#define VC5_HDMI_HORZB_HBP_SHIFT 16
66#define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
67#define VC5_HDMI_HORZB_HSP_SHIFT 0
68#define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
69
70#define VC5_HDMI_VERTA_VSP_SHIFT 24
71#define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
72#define VC5_HDMI_VERTA_VFP_SHIFT 16
73#define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
74#define VC5_HDMI_VERTA_VAL_SHIFT 0
75#define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
76
77#define VC5_HDMI_VERTB_VSPO_SHIFT 16
78#define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
79
80#define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
81
82#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
83#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
84
85#define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
86#define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
87
88#define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
89
90#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
91#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
92
93# define VC4_HD_M_SW_RST BIT(2)
94# define VC4_HD_M_ENABLE BIT(0)
95
96#define CEC_CLOCK_FREQ 40000
97
98#define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
99
100static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)
101{
102 return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;
103}
104
105static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
106{
107 struct drm_info_node *node = (struct drm_info_node *)m->private;
108 struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
109 struct drm_printer p = drm_seq_file_printer(m);
110
111 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
112 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
113
114 return 0;
115}
116
117static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
118{
119 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
120 udelay(1);
121 HDMI_WRITE(HDMI_M_CTL, 0);
122
123 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
124
125 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
126 VC4_HDMI_SW_RESET_HDMI |
127 VC4_HDMI_SW_RESET_FORMAT_DETECT);
128
129 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
130}
131
132static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
133{
134 reset_control_reset(vc4_hdmi->reset);
135
136 HDMI_WRITE(HDMI_DVP_CTL, 0);
137
138 HDMI_WRITE(HDMI_CLOCK_STOP,
139 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
140}
141
142#ifdef CONFIG_DRM_VC4_HDMI_CEC
143static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
144{
145 u16 clk_cnt;
146 u32 value;
147
148 value = HDMI_READ(HDMI_CEC_CNTRL_1);
149 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
150
151 /*
152 * Set the clock divider: the hsm_clock rate and this divider
153 * setting will give a 40 kHz CEC clock.
154 */
155 clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ;
156 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
157 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
158}
159#else
160static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
161#endif
162
163static enum drm_connector_status
164vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
165{
166 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
167 bool connected = false;
168
169 if (vc4_hdmi->hpd_gpio &&
170 gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) {
171 connected = true;
172 } else if (drm_probe_ddc(vc4_hdmi->ddc)) {
173 connected = true;
174 } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) {
175 connected = true;
176 }
177
178 if (connected) {
179 if (connector->status != connector_status_connected) {
180 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
181
182 if (edid) {
183 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
184 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
185 kfree(edid);
186 }
187 }
188
189 return connector_status_connected;
190 }
191
192 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
193 return connector_status_disconnected;
194}
195
196static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
197{
198 drm_connector_unregister(connector);
199 drm_connector_cleanup(connector);
200}
201
202static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
203{
204 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
205 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
206 int ret = 0;
207 struct edid *edid;
208
209 edid = drm_get_edid(connector, vc4_hdmi->ddc);
210 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
211 if (!edid)
212 return -ENODEV;
213
214 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
215
216 drm_connector_update_edid_property(connector, edid);
217 ret = drm_add_edid_modes(connector, edid);
218 kfree(edid);
219
220 if (vc4_hdmi->disable_4kp60) {
221 struct drm_device *drm = connector->dev;
222 struct drm_display_mode *mode;
223
224 list_for_each_entry(mode, &connector->probed_modes, head) {
225 if (vc4_hdmi_mode_needs_scrambling(mode)) {
226 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
227 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
228 }
229 }
230 }
231
232 return ret;
233}
234
235static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
236 struct drm_atomic_state *state)
237{
238 struct drm_connector_state *old_state =
239 drm_atomic_get_old_connector_state(state, connector);
240 struct drm_connector_state *new_state =
241 drm_atomic_get_new_connector_state(state, connector);
242 struct drm_crtc *crtc = new_state->crtc;
243
244 if (!crtc)
245 return 0;
246
247 if (old_state->colorspace != new_state->colorspace ||
248 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
249 struct drm_crtc_state *crtc_state;
250
251 crtc_state = drm_atomic_get_crtc_state(state, crtc);
252 if (IS_ERR(crtc_state))
253 return PTR_ERR(crtc_state);
254
255 crtc_state->mode_changed = true;
256 }
257
258 return 0;
259}
260
261static void vc4_hdmi_connector_reset(struct drm_connector *connector)
262{
263 struct vc4_hdmi_connector_state *old_state =
264 conn_state_to_vc4_hdmi_conn_state(connector->state);
265 struct vc4_hdmi_connector_state *new_state =
266 kzalloc(sizeof(*new_state), GFP_KERNEL);
267
268 if (connector->state)
269 __drm_atomic_helper_connector_destroy_state(connector->state);
270
271 kfree(old_state);
272 __drm_atomic_helper_connector_reset(connector, &new_state->base);
273
274 if (!new_state)
275 return;
276
277 new_state->base.max_bpc = 8;
278 new_state->base.max_requested_bpc = 8;
279 drm_atomic_helper_connector_tv_reset(connector);
280}
281
282static struct drm_connector_state *
283vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
284{
285 struct drm_connector_state *conn_state = connector->state;
286 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
287 struct vc4_hdmi_connector_state *new_state;
288
289 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
290 if (!new_state)
291 return NULL;
292
293 new_state->pixel_rate = vc4_state->pixel_rate;
294 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
295
296 return &new_state->base;
297}
298
299static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
300 .detect = vc4_hdmi_connector_detect,
301 .fill_modes = drm_helper_probe_single_connector_modes,
302 .destroy = vc4_hdmi_connector_destroy,
303 .reset = vc4_hdmi_connector_reset,
304 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
305 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
306};
307
308static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
309 .get_modes = vc4_hdmi_connector_get_modes,
310 .atomic_check = vc4_hdmi_connector_atomic_check,
311};
312
313static int vc4_hdmi_connector_init(struct drm_device *dev,
314 struct vc4_hdmi *vc4_hdmi)
315{
316 struct drm_connector *connector = &vc4_hdmi->connector;
317 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
318 int ret;
319
320 drm_connector_init_with_ddc(dev, connector,
321 &vc4_hdmi_connector_funcs,
322 DRM_MODE_CONNECTOR_HDMIA,
323 vc4_hdmi->ddc);
324 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
325
326 /*
327 * Some of the properties below require access to state, like bpc.
328 * Allocate some default initial connector state with our reset helper.
329 */
330 if (connector->funcs->reset)
331 connector->funcs->reset(connector);
332
333 /* Create and attach TV margin props to this connector. */
334 ret = drm_mode_create_tv_margin_properties(dev);
335 if (ret)
336 return ret;
337
338 ret = drm_mode_create_hdmi_colorspace_property(connector);
339 if (ret)
340 return ret;
341
342 drm_connector_attach_colorspace_property(connector);
343 drm_connector_attach_tv_margin_properties(connector);
344 drm_connector_attach_max_bpc_property(connector, 8, 12);
345
346 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
347 DRM_CONNECTOR_POLL_DISCONNECT);
348
349 connector->interlace_allowed = 1;
350 connector->doublescan_allowed = 0;
351
352 if (vc4_hdmi->variant->supports_hdr)
353 drm_connector_attach_hdr_output_metadata_property(connector);
354
355 drm_connector_attach_encoder(connector, encoder);
356
357 return 0;
358}
359
360static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
361 enum hdmi_infoframe_type type,
362 bool poll)
363{
364 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
365 u32 packet_id = type - 0x80;
366
367 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
368 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
369
370 if (!poll)
371 return 0;
372
373 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
374 BIT(packet_id)), 100);
375}
376
377static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
378 union hdmi_infoframe *frame)
379{
380 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
381 u32 packet_id = frame->any.type - 0x80;
382 const struct vc4_hdmi_register *ram_packet_start =
383 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
384 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
385 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
386 ram_packet_start->reg);
387 uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
388 ssize_t len, i;
389 int ret;
390
391 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
392 VC4_HDMI_RAM_PACKET_ENABLE),
393 "Packet RAM has to be on to store the packet.");
394
395 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
396 if (len < 0)
397 return;
398
399 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
400 if (ret) {
401 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
402 return;
403 }
404
405 for (i = 0; i < len; i += 7) {
406 writel(buffer[i + 0] << 0 |
407 buffer[i + 1] << 8 |
408 buffer[i + 2] << 16,
409 base + packet_reg);
410 packet_reg += 4;
411
412 writel(buffer[i + 3] << 0 |
413 buffer[i + 4] << 8 |
414 buffer[i + 5] << 16 |
415 buffer[i + 6] << 24,
416 base + packet_reg);
417 packet_reg += 4;
418 }
419
420 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
421 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
422 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
423 BIT(packet_id)), 100);
424 if (ret)
425 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
426}
427
428static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
429{
430 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
431 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
432 struct drm_connector *connector = &vc4_hdmi->connector;
433 struct drm_connector_state *cstate = connector->state;
434 struct drm_crtc *crtc = encoder->crtc;
435 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
436 union hdmi_infoframe frame;
437 int ret;
438
439 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
440 connector, mode);
441 if (ret < 0) {
442 DRM_ERROR("couldn't fill AVI infoframe\n");
443 return;
444 }
445
446 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
447 connector, mode,
448 vc4_encoder->limited_rgb_range ?
449 HDMI_QUANTIZATION_RANGE_LIMITED :
450 HDMI_QUANTIZATION_RANGE_FULL);
451 drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate);
452 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
453
454 vc4_hdmi_write_infoframe(encoder, &frame);
455}
456
457static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
458{
459 union hdmi_infoframe frame;
460 int ret;
461
462 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
463 if (ret < 0) {
464 DRM_ERROR("couldn't fill SPD infoframe\n");
465 return;
466 }
467
468 frame.spd.sdi = HDMI_SPD_SDI_PC;
469
470 vc4_hdmi_write_infoframe(encoder, &frame);
471}
472
473static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
474{
475 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
476 union hdmi_infoframe frame;
477
478 hdmi_audio_infoframe_init(&frame.audio);
479
480 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
481 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
482 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
483 frame.audio.channels = vc4_hdmi->audio.channels;
484
485 vc4_hdmi_write_infoframe(encoder, &frame);
486}
487
488static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
489{
490 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
491 struct drm_connector *connector = &vc4_hdmi->connector;
492 struct drm_connector_state *conn_state = connector->state;
493 union hdmi_infoframe frame;
494
495 if (!vc4_hdmi->variant->supports_hdr)
496 return;
497
498 if (!conn_state->hdr_output_metadata)
499 return;
500
501 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
502 return;
503
504 vc4_hdmi_write_infoframe(encoder, &frame);
505}
506
507static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
508{
509 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
510
511 vc4_hdmi_set_avi_infoframe(encoder);
512 vc4_hdmi_set_spd_infoframe(encoder);
513 /*
514 * If audio was streaming, then we need to reenabled the audio
515 * infoframe here during encoder_enable.
516 */
517 if (vc4_hdmi->audio.streaming)
518 vc4_hdmi_set_audio_infoframe(encoder);
519
520 vc4_hdmi_set_hdr_infoframe(encoder);
521}
522
523static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
524 struct drm_display_mode *mode)
525{
526 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
527 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
528 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
529
530 if (!vc4_encoder->hdmi_monitor)
531 return false;
532
533 if (!display->hdmi.scdc.supported ||
534 !display->hdmi.scdc.scrambling.supported)
535 return false;
536
537 return true;
538}
539
540#define SCRAMBLING_POLLING_DELAY_MS 1000
541
542static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
543{
544 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
545 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
546
547 if (!vc4_hdmi_supports_scrambling(encoder, mode))
548 return;
549
550 if (!vc4_hdmi_mode_needs_scrambling(mode))
551 return;
552
553 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
554 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
555
556 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
557 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
558
559 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
560 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
561}
562
563static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
564{
565 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
566 struct drm_crtc *crtc = encoder->crtc;
567
568 /*
569 * At boot, encoder->crtc will be NULL. Since we don't know the
570 * state of the scrambler and in order to avoid any
571 * inconsistency, let's disable it all the time.
572 */
573 if (crtc && !vc4_hdmi_supports_scrambling(encoder, &crtc->mode))
574 return;
575
576 if (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode))
577 return;
578
579 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
580 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
581
582 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
583 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
584
585 drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
586 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
587}
588
589static void vc4_hdmi_scrambling_wq(struct work_struct *work)
590{
591 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
592 struct vc4_hdmi,
593 scrambling_work);
594
595 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
596 return;
597
598 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
599 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
600
601 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
602 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
603}
604
605static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
606 struct drm_atomic_state *state)
607{
608 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
609
610 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
611
612 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
613
614 mdelay(1);
615
616 HDMI_WRITE(HDMI_VID_CTL,
617 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
618 vc4_hdmi_disable_scrambling(encoder);
619}
620
621static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
622 struct drm_atomic_state *state)
623{
624 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
625 int ret;
626
627 HDMI_WRITE(HDMI_VID_CTL,
628 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
629
630 if (vc4_hdmi->variant->phy_disable)
631 vc4_hdmi->variant->phy_disable(vc4_hdmi);
632
633 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
634 clk_disable_unprepare(vc4_hdmi->hsm_clock);
635 clk_disable_unprepare(vc4_hdmi->pixel_clock);
636
637 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
638 if (ret < 0)
639 DRM_ERROR("Failed to release power domain: %d\n", ret);
640}
641
642static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
643{
644}
645
646static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
647{
648 u32 csc_ctl;
649
650 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
651 VC4_HD_CSC_CTL_ORDER);
652
653 if (enable) {
654 /* CEA VICs other than #1 requre limited range RGB
655 * output unless overridden by an AVI infoframe.
656 * Apply a colorspace conversion to squash 0-255 down
657 * to 16-235. The matrix here is:
658 *
659 * [ 0 0 0.8594 16]
660 * [ 0 0.8594 0 16]
661 * [ 0.8594 0 0 16]
662 * [ 0 0 0 1]
663 */
664 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
665 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
666 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
667 VC4_HD_CSC_CTL_MODE);
668
669 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
670 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
671 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
672 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
673 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
674 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
675 }
676
677 /* The RGB order applies even when CSC is disabled. */
678 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
679}
680
681static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
682{
683 u32 csc_ctl;
684
685 csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
686
687 if (enable) {
688 /* CEA VICs other than #1 requre limited range RGB
689 * output unless overridden by an AVI infoframe.
690 * Apply a colorspace conversion to squash 0-255 down
691 * to 16-235. The matrix here is:
692 *
693 * [ 0.8594 0 0 16]
694 * [ 0 0.8594 0 16]
695 * [ 0 0 0.8594 16]
696 * [ 0 0 0 1]
697 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
698 */
699 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
700 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
701 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
702 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
703 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
704 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
705 } else {
706 /* Still use the matrix for full range, but make it unity.
707 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
708 */
709 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
710 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
711 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
712 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
713 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
714 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
715 }
716
717 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
718}
719
720static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
721 struct drm_connector_state *state,
722 struct drm_display_mode *mode)
723{
724 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
725 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
726 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
727 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
728 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
729 VC4_HDMI_VERTA_VSP) |
730 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
731 VC4_HDMI_VERTA_VFP) |
732 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
733 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
734 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
735 VC4_HDMI_VERTB_VBP));
736 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
737 VC4_SET_FIELD(mode->crtc_vtotal -
738 mode->crtc_vsync_end -
739 interlaced,
740 VC4_HDMI_VERTB_VBP));
741
742 HDMI_WRITE(HDMI_HORZA,
743 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
744 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
745 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
746 VC4_HDMI_HORZA_HAP));
747
748 HDMI_WRITE(HDMI_HORZB,
749 VC4_SET_FIELD((mode->htotal -
750 mode->hsync_end) * pixel_rep,
751 VC4_HDMI_HORZB_HBP) |
752 VC4_SET_FIELD((mode->hsync_end -
753 mode->hsync_start) * pixel_rep,
754 VC4_HDMI_HORZB_HSP) |
755 VC4_SET_FIELD((mode->hsync_start -
756 mode->hdisplay) * pixel_rep,
757 VC4_HDMI_HORZB_HFP));
758
759 HDMI_WRITE(HDMI_VERTA0, verta);
760 HDMI_WRITE(HDMI_VERTA1, verta);
761
762 HDMI_WRITE(HDMI_VERTB0, vertb_even);
763 HDMI_WRITE(HDMI_VERTB1, vertb);
764}
765
766static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
767 struct drm_connector_state *state,
768 struct drm_display_mode *mode)
769{
770 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
771 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
772 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
773 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
774 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
775 VC5_HDMI_VERTA_VSP) |
776 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
777 VC5_HDMI_VERTA_VFP) |
778 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
779 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
780 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
781 VC4_HDMI_VERTB_VBP));
782 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
783 VC4_SET_FIELD(mode->crtc_vtotal -
784 mode->crtc_vsync_end -
785 interlaced,
786 VC4_HDMI_VERTB_VBP));
787 unsigned char gcp;
788 bool gcp_en;
789 u32 reg;
790
791 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
792 HDMI_WRITE(HDMI_HORZA,
793 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
794 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
795 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
796 VC5_HDMI_HORZA_HAP) |
797 VC4_SET_FIELD((mode->hsync_start -
798 mode->hdisplay) * pixel_rep,
799 VC5_HDMI_HORZA_HFP));
800
801 HDMI_WRITE(HDMI_HORZB,
802 VC4_SET_FIELD((mode->htotal -
803 mode->hsync_end) * pixel_rep,
804 VC5_HDMI_HORZB_HBP) |
805 VC4_SET_FIELD((mode->hsync_end -
806 mode->hsync_start) * pixel_rep,
807 VC5_HDMI_HORZB_HSP));
808
809 HDMI_WRITE(HDMI_VERTA0, verta);
810 HDMI_WRITE(HDMI_VERTA1, verta);
811
812 HDMI_WRITE(HDMI_VERTB0, vertb_even);
813 HDMI_WRITE(HDMI_VERTB1, vertb);
814
815 switch (state->max_bpc) {
816 case 12:
817 gcp = 6;
818 gcp_en = true;
819 break;
820 case 10:
821 gcp = 5;
822 gcp_en = true;
823 break;
824 case 8:
825 default:
826 gcp = 4;
827 gcp_en = false;
828 break;
829 }
830
831 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
832 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
833 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
834 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
835 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
836 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
837
838 reg = HDMI_READ(HDMI_GCP_WORD_1);
839 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
840 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
841 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
842
843 reg = HDMI_READ(HDMI_GCP_CONFIG);
844 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
845 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
846 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
847
848 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
849}
850
851static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
852{
853 u32 drift;
854 int ret;
855
856 drift = HDMI_READ(HDMI_FIFO_CTL);
857 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
858
859 HDMI_WRITE(HDMI_FIFO_CTL,
860 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
861 HDMI_WRITE(HDMI_FIFO_CTL,
862 drift | VC4_HDMI_FIFO_CTL_RECENTER);
863 usleep_range(1000, 1100);
864 HDMI_WRITE(HDMI_FIFO_CTL,
865 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
866 HDMI_WRITE(HDMI_FIFO_CTL,
867 drift | VC4_HDMI_FIFO_CTL_RECENTER);
868
869 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
870 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
871 WARN_ONCE(ret, "Timeout waiting for "
872 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
873}
874
875static struct drm_connector_state *
876vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,
877 struct drm_atomic_state *state)
878{
879 struct drm_connector_state *conn_state;
880 struct drm_connector *connector;
881 unsigned int i;
882
883 for_each_new_connector_in_state(state, connector, conn_state, i) {
884 if (conn_state->best_encoder == encoder)
885 return conn_state;
886 }
887
888 return NULL;
889}
890
891static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
892 struct drm_atomic_state *state)
893{
894 struct drm_connector_state *conn_state =
895 vc4_hdmi_encoder_get_connector_state(encoder, state);
896 struct vc4_hdmi_connector_state *vc4_conn_state =
897 conn_state_to_vc4_hdmi_conn_state(conn_state);
898 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
899 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
900 unsigned long bvb_rate, pixel_rate, hsm_rate;
901 int ret;
902
903 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
904 if (ret < 0) {
905 DRM_ERROR("Failed to retain power domain: %d\n", ret);
906 return;
907 }
908
909 pixel_rate = vc4_conn_state->pixel_rate;
910 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
911 if (ret) {
912 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
913 return;
914 }
915
916 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
917 if (ret) {
918 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
919 return;
920 }
921
922 /*
923 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
924 * be faster than pixel clock, infinitesimally faster, tested in
925 * simulation. Otherwise, exact value is unimportant for HDMI
926 * operation." This conflicts with bcm2835's vc4 documentation, which
927 * states HSM's clock has to be at least 108% of the pixel clock.
928 *
929 * Real life tests reveal that vc4's firmware statement holds up, and
930 * users are able to use pixel clocks closer to HSM's, namely for
931 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
932 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
933 * 162MHz.
934 *
935 * Additionally, the AXI clock needs to be at least 25% of
936 * pixel clock, but HSM ends up being the limiting factor.
937 */
938 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
939 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
940 if (ret) {
941 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
942 return;
943 }
944
945 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
946 if (ret) {
947 DRM_ERROR("Failed to turn on HSM clock: %d\n", ret);
948 clk_disable_unprepare(vc4_hdmi->pixel_clock);
949 return;
950 }
951
952 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
953
954 if (pixel_rate > 297000000)
955 bvb_rate = 300000000;
956 else if (pixel_rate > 148500000)
957 bvb_rate = 150000000;
958 else
959 bvb_rate = 75000000;
960
961 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
962 if (ret) {
963 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
964 clk_disable_unprepare(vc4_hdmi->hsm_clock);
965 clk_disable_unprepare(vc4_hdmi->pixel_clock);
966 return;
967 }
968
969 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
970 if (ret) {
971 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
972 clk_disable_unprepare(vc4_hdmi->hsm_clock);
973 clk_disable_unprepare(vc4_hdmi->pixel_clock);
974 return;
975 }
976
977 if (vc4_hdmi->variant->phy_init)
978 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
979
980 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
981 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
982 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
983 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
984
985 if (vc4_hdmi->variant->set_timings)
986 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
987}
988
989static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
990 struct drm_atomic_state *state)
991{
992 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
993 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
994 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
995
996 if (vc4_encoder->hdmi_monitor &&
997 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
998 if (vc4_hdmi->variant->csc_setup)
999 vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
1000
1001 vc4_encoder->limited_rgb_range = true;
1002 } else {
1003 if (vc4_hdmi->variant->csc_setup)
1004 vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
1005
1006 vc4_encoder->limited_rgb_range = false;
1007 }
1008
1009 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1010}
1011
1012static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1013 struct drm_atomic_state *state)
1014{
1015 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1016 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1017 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1018 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1019 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1020 int ret;
1021
1022 HDMI_WRITE(HDMI_VID_CTL,
1023 VC4_HD_VID_CTL_ENABLE |
1024 VC4_HD_VID_CTL_CLRRGB |
1025 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1026 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1027 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1028 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1029
1030 HDMI_WRITE(HDMI_VID_CTL,
1031 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1032
1033 if (vc4_encoder->hdmi_monitor) {
1034 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1035 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1036 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1037
1038 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1039 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1040 WARN_ONCE(ret, "Timeout waiting for "
1041 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1042 } else {
1043 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1044 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1045 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1046 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1047 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1048 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1049
1050 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1051 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1052 WARN_ONCE(ret, "Timeout waiting for "
1053 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1054 }
1055
1056 if (vc4_encoder->hdmi_monitor) {
1057 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1058 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1059 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1060 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1061 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1062
1063 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1064 VC4_HDMI_RAM_PACKET_ENABLE);
1065
1066 vc4_hdmi_set_infoframes(encoder);
1067 }
1068
1069 vc4_hdmi_recenter_fifo(vc4_hdmi);
1070 vc4_hdmi_enable_scrambling(encoder);
1071}
1072
1073static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
1074{
1075}
1076
1077#define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
1078#define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
1079
1080static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1081 struct drm_crtc_state *crtc_state,
1082 struct drm_connector_state *conn_state)
1083{
1084 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1085 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1086 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1087 unsigned long long pixel_rate = mode->clock * 1000;
1088 unsigned long long tmds_rate;
1089
1090 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1091 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1092 (mode->hsync_end % 2) || (mode->htotal % 2)))
1093 return -EINVAL;
1094
1095 /*
1096 * The 1440p@60 pixel rate is in the same range than the first
1097 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1098 * bandwidth). Slightly lower the frequency to bring it out of
1099 * the WiFi range.
1100 */
1101 tmds_rate = pixel_rate * 10;
1102 if (vc4_hdmi->disable_wifi_frequencies &&
1103 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1104 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1105 mode->clock = 238560;
1106 pixel_rate = mode->clock * 1000;
1107 }
1108
1109 if (conn_state->max_bpc == 12) {
1110 pixel_rate = pixel_rate * 150;
1111 do_div(pixel_rate, 100);
1112 } else if (conn_state->max_bpc == 10) {
1113 pixel_rate = pixel_rate * 125;
1114 do_div(pixel_rate, 100);
1115 }
1116
1117 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1118 pixel_rate = pixel_rate * 2;
1119
1120 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1121 return -EINVAL;
1122
1123 if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK))
1124 return -EINVAL;
1125
1126 vc4_state->pixel_rate = pixel_rate;
1127
1128 return 0;
1129}
1130
1131static enum drm_mode_status
1132vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1133 const struct drm_display_mode *mode)
1134{
1135 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1136
1137 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1138 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1139 (mode->hsync_end % 2) || (mode->htotal % 2)))
1140 return MODE_H_ILLEGAL;
1141
1142 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1143 return MODE_CLOCK_HIGH;
1144
1145 if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode))
1146 return MODE_CLOCK_HIGH;
1147
1148 return MODE_OK;
1149}
1150
1151static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1152 .atomic_check = vc4_hdmi_encoder_atomic_check,
1153 .mode_valid = vc4_hdmi_encoder_mode_valid,
1154 .disable = vc4_hdmi_encoder_disable,
1155 .enable = vc4_hdmi_encoder_enable,
1156};
1157
1158static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1159{
1160 int i;
1161 u32 channel_map = 0;
1162
1163 for (i = 0; i < 8; i++) {
1164 if (channel_mask & BIT(i))
1165 channel_map |= i << (3 * i);
1166 }
1167 return channel_map;
1168}
1169
1170static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1171{
1172 int i;
1173 u32 channel_map = 0;
1174
1175 for (i = 0; i < 8; i++) {
1176 if (channel_mask & BIT(i))
1177 channel_map |= i << (4 * i);
1178 }
1179 return channel_map;
1180}
1181
1182/* HDMI audio codec callbacks */
1183static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi)
1184{
1185 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1186 unsigned long n, m;
1187
1188 rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate,
1189 VC4_HD_MAI_SMP_N_MASK >>
1190 VC4_HD_MAI_SMP_N_SHIFT,
1191 (VC4_HD_MAI_SMP_M_MASK >>
1192 VC4_HD_MAI_SMP_M_SHIFT) + 1,
1193 &n, &m);
1194
1195 HDMI_WRITE(HDMI_MAI_SMP,
1196 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1197 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1198}
1199
1200static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi)
1201{
1202 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1203 struct drm_crtc *crtc = encoder->crtc;
1204 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1205 u32 samplerate = vc4_hdmi->audio.samplerate;
1206 u32 n, cts;
1207 u64 tmp;
1208
1209 n = 128 * samplerate / 1000;
1210 tmp = (u64)(mode->clock * 1000) * n;
1211 do_div(tmp, 128 * samplerate);
1212 cts = tmp;
1213
1214 HDMI_WRITE(HDMI_CRP_CFG,
1215 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1216 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1217
1218 /*
1219 * We could get slightly more accurate clocks in some cases by
1220 * providing a CTS_1 value. The two CTS values are alternated
1221 * between based on the period fields
1222 */
1223 HDMI_WRITE(HDMI_CTS_0, cts);
1224 HDMI_WRITE(HDMI_CTS_1, cts);
1225}
1226
1227static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1228{
1229 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1230
1231 return snd_soc_card_get_drvdata(card);
1232}
1233
1234static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
1235 struct snd_soc_dai *dai)
1236{
1237 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1238 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1239 struct drm_connector *connector = &vc4_hdmi->connector;
1240 int ret;
1241
1242 if (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream)
1243 return -EINVAL;
1244
1245 vc4_hdmi->audio.substream = substream;
1246
1247 /*
1248 * If the HDMI encoder hasn't probed, or the encoder is
1249 * currently in DVI mode, treat the codec dai as missing.
1250 */
1251 if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1252 VC4_HDMI_RAM_PACKET_ENABLE))
1253 return -ENODEV;
1254
1255 ret = snd_pcm_hw_constraint_eld(substream->runtime, connector->eld);
1256 if (ret)
1257 return ret;
1258
1259 return 0;
1260}
1261
1262static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1263{
1264 return 0;
1265}
1266
1267static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1268{
1269 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1270 struct device *dev = &vc4_hdmi->pdev->dev;
1271 int ret;
1272
1273 vc4_hdmi->audio.streaming = false;
1274 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1275 if (ret)
1276 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1277
1278 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1279 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1280 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1281}
1282
1283static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
1284 struct snd_soc_dai *dai)
1285{
1286 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1287
1288 if (substream != vc4_hdmi->audio.substream)
1289 return;
1290
1291 vc4_hdmi_audio_reset(vc4_hdmi);
1292
1293 vc4_hdmi->audio.substream = NULL;
1294}
1295
1296/* HDMI audio codec callbacks */
1297static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
1298 struct snd_pcm_hw_params *params,
1299 struct snd_soc_dai *dai)
1300{
1301 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1302 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1303 struct device *dev = &vc4_hdmi->pdev->dev;
1304 u32 audio_packet_config, channel_mask;
1305 u32 channel_map;
1306
1307 if (substream != vc4_hdmi->audio.substream)
1308 return -EINVAL;
1309
1310 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1311 params_rate(params), params_width(params),
1312 params_channels(params));
1313
1314 vc4_hdmi->audio.channels = params_channels(params);
1315 vc4_hdmi->audio.samplerate = params_rate(params);
1316
1317 HDMI_WRITE(HDMI_MAI_CTL,
1318 VC4_HD_MAI_CTL_RESET |
1319 VC4_HD_MAI_CTL_FLUSH |
1320 VC4_HD_MAI_CTL_DLATE |
1321 VC4_HD_MAI_CTL_ERRORE |
1322 VC4_HD_MAI_CTL_ERRORF);
1323
1324 vc4_hdmi_audio_set_mai_clock(vc4_hdmi);
1325
1326 /* The B frame identifier should match the value used by alsa-lib (8) */
1327 audio_packet_config =
1328 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1329 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1330 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1331
1332 channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0);
1333 audio_packet_config |= VC4_SET_FIELD(channel_mask,
1334 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1335
1336 /* Set the MAI threshold. This logic mimics the firmware's. */
1337 if (vc4_hdmi->audio.samplerate > 96000) {
1338 HDMI_WRITE(HDMI_MAI_THR,
1339 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
1340 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
1341 } else if (vc4_hdmi->audio.samplerate > 48000) {
1342 HDMI_WRITE(HDMI_MAI_THR,
1343 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
1344 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
1345 } else {
1346 HDMI_WRITE(HDMI_MAI_THR,
1347 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1348 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1349 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1350 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1351 }
1352
1353 HDMI_WRITE(HDMI_MAI_CONFIG,
1354 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1355 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1356
1357 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1358 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1359 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1360 vc4_hdmi_set_n_cts(vc4_hdmi);
1361
1362 vc4_hdmi_set_audio_infoframe(encoder);
1363
1364 return 0;
1365}
1366
1367static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
1368 struct snd_soc_dai *dai)
1369{
1370 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1371
1372 switch (cmd) {
1373 case SNDRV_PCM_TRIGGER_START:
1374 vc4_hdmi->audio.streaming = true;
1375
1376 if (vc4_hdmi->variant->phy_rng_enable)
1377 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1378
1379 HDMI_WRITE(HDMI_MAI_CTL,
1380 VC4_SET_FIELD(vc4_hdmi->audio.channels,
1381 VC4_HD_MAI_CTL_CHNUM) |
1382 VC4_HD_MAI_CTL_WHOLSMP |
1383 VC4_HD_MAI_CTL_CHALIGN |
1384 VC4_HD_MAI_CTL_ENABLE);
1385 break;
1386 case SNDRV_PCM_TRIGGER_STOP:
1387 HDMI_WRITE(HDMI_MAI_CTL,
1388 VC4_HD_MAI_CTL_DLATE |
1389 VC4_HD_MAI_CTL_ERRORE |
1390 VC4_HD_MAI_CTL_ERRORF);
1391
1392 if (vc4_hdmi->variant->phy_rng_disable)
1393 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1394
1395 vc4_hdmi->audio.streaming = false;
1396
1397 break;
1398 default:
1399 break;
1400 }
1401
1402 return 0;
1403}
1404
1405static inline struct vc4_hdmi *
1406snd_component_to_hdmi(struct snd_soc_component *component)
1407{
1408 struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
1409
1410 return snd_soc_card_get_drvdata(card);
1411}
1412
1413static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
1414 struct snd_ctl_elem_info *uinfo)
1415{
1416 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1417 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1418 struct drm_connector *connector = &vc4_hdmi->connector;
1419
1420 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1421 uinfo->count = sizeof(connector->eld);
1422
1423 return 0;
1424}
1425
1426static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
1427 struct snd_ctl_elem_value *ucontrol)
1428{
1429 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1430 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1431 struct drm_connector *connector = &vc4_hdmi->connector;
1432
1433 memcpy(ucontrol->value.bytes.data, connector->eld,
1434 sizeof(connector->eld));
1435
1436 return 0;
1437}
1438
1439static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
1440 {
1441 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1442 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1443 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1444 .name = "ELD",
1445 .info = vc4_hdmi_audio_eld_ctl_info,
1446 .get = vc4_hdmi_audio_eld_ctl_get,
1447 },
1448};
1449
1450static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
1451 SND_SOC_DAPM_OUTPUT("TX"),
1452};
1453
1454static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
1455 { "TX", NULL, "Playback" },
1456};
1457
1458static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
1459 .name = "vc4-hdmi-codec-dai-component",
1460 .controls = vc4_hdmi_audio_controls,
1461 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls),
1462 .dapm_widgets = vc4_hdmi_audio_widgets,
1463 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets),
1464 .dapm_routes = vc4_hdmi_audio_routes,
1465 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes),
1466 .idle_bias_on = 1,
1467 .use_pmdown_time = 1,
1468 .endianness = 1,
1469 .non_legacy_dai_naming = 1,
1470};
1471
1472static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
1473 .startup = vc4_hdmi_audio_startup,
1474 .shutdown = vc4_hdmi_audio_shutdown,
1475 .hw_params = vc4_hdmi_audio_hw_params,
1476 .set_fmt = vc4_hdmi_audio_set_fmt,
1477 .trigger = vc4_hdmi_audio_trigger,
1478};
1479
1480static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1481 .name = "vc4-hdmi-hifi",
1482 .playback = {
1483 .stream_name = "Playback",
1484 .channels_min = 2,
1485 .channels_max = 8,
1486 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1487 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1488 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1489 SNDRV_PCM_RATE_192000,
1490 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1491 },
1492};
1493
1494static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1495 .name = "vc4-hdmi-cpu-dai-component",
1496};
1497
1498static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1499{
1500 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1501
1502 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1503
1504 return 0;
1505}
1506
1507static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1508 .name = "vc4-hdmi-cpu-dai",
1509 .probe = vc4_hdmi_audio_cpu_dai_probe,
1510 .playback = {
1511 .stream_name = "Playback",
1512 .channels_min = 1,
1513 .channels_max = 8,
1514 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1515 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1516 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1517 SNDRV_PCM_RATE_192000,
1518 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1519 },
1520 .ops = &vc4_hdmi_audio_dai_ops,
1521};
1522
1523static const struct snd_dmaengine_pcm_config pcm_conf = {
1524 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1525 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1526};
1527
1528static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1529{
1530 const struct vc4_hdmi_register *mai_data =
1531 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1532 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1533 struct snd_soc_card *card = &vc4_hdmi->audio.card;
1534 struct device *dev = &vc4_hdmi->pdev->dev;
1535 const __be32 *addr;
1536 int index;
1537 int ret;
1538
1539 if (!of_find_property(dev->of_node, "dmas", NULL)) {
1540 dev_warn(dev,
1541 "'dmas' DT property is missing, no HDMI audio\n");
1542 return 0;
1543 }
1544
1545 if (mai_data->reg != VC4_HD) {
1546 WARN_ONCE(true, "MAI isn't in the HD block\n");
1547 return -EINVAL;
1548 }
1549
1550 /*
1551 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1552 * the bus address specified in the DT, because the physical address
1553 * (the one returned by platform_get_resource()) is not appropriate
1554 * for DMA transfers.
1555 * This VC/MMU should probably be exposed to avoid this kind of hacks.
1556 */
1557 index = of_property_match_string(dev->of_node, "reg-names", "hd");
1558 /* Before BCM2711, we don't have a named register range */
1559 if (index < 0)
1560 index = 1;
1561
1562 addr = of_get_address(dev->of_node, index, NULL, NULL);
1563
1564 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1565 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1566 vc4_hdmi->audio.dma_data.maxburst = 2;
1567
1568 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1569 if (ret) {
1570 dev_err(dev, "Could not register PCM component: %d\n", ret);
1571 return ret;
1572 }
1573
1574 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1575 &vc4_hdmi_audio_cpu_dai_drv, 1);
1576 if (ret) {
1577 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1578 return ret;
1579 }
1580
1581 /* register component and codec dai */
1582 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv,
1583 &vc4_hdmi_audio_codec_dai_drv, 1);
1584 if (ret) {
1585 dev_err(dev, "Could not register component: %d\n", ret);
1586 return ret;
1587 }
1588
1589 dai_link->cpus = &vc4_hdmi->audio.cpu;
1590 dai_link->codecs = &vc4_hdmi->audio.codec;
1591 dai_link->platforms = &vc4_hdmi->audio.platform;
1592
1593 dai_link->num_cpus = 1;
1594 dai_link->num_codecs = 1;
1595 dai_link->num_platforms = 1;
1596
1597 dai_link->name = "MAI";
1598 dai_link->stream_name = "MAI PCM";
1599 dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1600 dai_link->cpus->dai_name = dev_name(dev);
1601 dai_link->codecs->name = dev_name(dev);
1602 dai_link->platforms->name = dev_name(dev);
1603
1604 card->dai_link = dai_link;
1605 card->num_links = 1;
1606 card->name = vc4_hdmi->variant->card_name;
1607 card->driver_name = "vc4-hdmi";
1608 card->dev = dev;
1609 card->owner = THIS_MODULE;
1610
1611 /*
1612 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1613 * stores a pointer to the snd card object in dev->driver_data. This
1614 * means we cannot use it for something else. The hdmi back-pointer is
1615 * now stored in card->drvdata and should be retrieved with
1616 * snd_soc_card_get_drvdata() if needed.
1617 */
1618 snd_soc_card_set_drvdata(card, vc4_hdmi);
1619 ret = devm_snd_soc_register_card(dev, card);
1620 if (ret)
1621 dev_err(dev, "Could not register sound card: %d\n", ret);
1622
1623 return ret;
1624
1625}
1626
1627#ifdef CONFIG_DRM_VC4_HDMI_CEC
1628static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1629{
1630 struct vc4_hdmi *vc4_hdmi = priv;
1631
1632 if (vc4_hdmi->cec_rx_msg.len)
1633 cec_received_msg(vc4_hdmi->cec_adap,
1634 &vc4_hdmi->cec_rx_msg);
1635
1636 return IRQ_HANDLED;
1637}
1638
1639static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1640{
1641 struct vc4_hdmi *vc4_hdmi = priv;
1642
1643 if (vc4_hdmi->cec_tx_ok) {
1644 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1645 0, 0, 0, 0);
1646 } else {
1647 /*
1648 * This CEC implementation makes 1 retry, so if we
1649 * get a NACK, then that means it made 2 attempts.
1650 */
1651 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1652 0, 2, 0, 0);
1653 }
1654 return IRQ_HANDLED;
1655}
1656
1657static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1658{
1659 struct vc4_hdmi *vc4_hdmi = priv;
1660 irqreturn_t ret;
1661
1662 if (vc4_hdmi->cec_irq_was_rx)
1663 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1664 else
1665 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1666
1667 return ret;
1668}
1669
1670static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1671{
1672 struct drm_device *dev = vc4_hdmi->connector.dev;
1673 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1674 unsigned int i;
1675
1676 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1677 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1678
1679 if (msg->len > 16) {
1680 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1681 return;
1682 }
1683
1684 for (i = 0; i < msg->len; i += 4) {
1685 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1686
1687 msg->msg[i] = val & 0xff;
1688 msg->msg[i + 1] = (val >> 8) & 0xff;
1689 msg->msg[i + 2] = (val >> 16) & 0xff;
1690 msg->msg[i + 3] = (val >> 24) & 0xff;
1691 }
1692}
1693
1694static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1695{
1696 struct vc4_hdmi *vc4_hdmi = priv;
1697 u32 cntrl1;
1698
1699 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1700 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1701 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1702 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1703
1704 return IRQ_WAKE_THREAD;
1705}
1706
1707static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1708{
1709 struct vc4_hdmi *vc4_hdmi = priv;
1710 u32 cntrl1;
1711
1712 vc4_hdmi->cec_rx_msg.len = 0;
1713 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1714 vc4_cec_read_msg(vc4_hdmi, cntrl1);
1715 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1716 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1717 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1718
1719 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1720
1721 return IRQ_WAKE_THREAD;
1722}
1723
1724static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1725{
1726 struct vc4_hdmi *vc4_hdmi = priv;
1727 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1728 irqreturn_t ret;
1729 u32 cntrl5;
1730
1731 if (!(stat & VC4_HDMI_CPU_CEC))
1732 return IRQ_NONE;
1733
1734 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1735 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1736 if (vc4_hdmi->cec_irq_was_rx)
1737 ret = vc4_cec_irq_handler_rx_bare(irq, priv);
1738 else
1739 ret = vc4_cec_irq_handler_tx_bare(irq, priv);
1740
1741 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1742 return ret;
1743}
1744
1745static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1746{
1747 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1748 /* clock period in microseconds */
1749 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1750 u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1751
1752 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1753 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1754 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1755 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1756 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1757
1758 if (enable) {
1759 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1760 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1761 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1762 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1763 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1764 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1765 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1766 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1767 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1768 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1769 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1770 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1771 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1772 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1773 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1774 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1775 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1776 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1777 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1778
1779 if (!vc4_hdmi->variant->external_irq_controller)
1780 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1781 } else {
1782 if (!vc4_hdmi->variant->external_irq_controller)
1783 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1784 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1785 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1786 }
1787 return 0;
1788}
1789
1790static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1791{
1792 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1793
1794 HDMI_WRITE(HDMI_CEC_CNTRL_1,
1795 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1796 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1797 return 0;
1798}
1799
1800static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1801 u32 signal_free_time, struct cec_msg *msg)
1802{
1803 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1804 struct drm_device *dev = vc4_hdmi->connector.dev;
1805 u32 val;
1806 unsigned int i;
1807
1808 if (msg->len > 16) {
1809 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
1810 return -ENOMEM;
1811 }
1812
1813 for (i = 0; i < msg->len; i += 4)
1814 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
1815 (msg->msg[i]) |
1816 (msg->msg[i + 1] << 8) |
1817 (msg->msg[i + 2] << 16) |
1818 (msg->msg[i + 3] << 24));
1819
1820 val = HDMI_READ(HDMI_CEC_CNTRL_1);
1821 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1822 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1823 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1824 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1825 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1826
1827 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1828 return 0;
1829}
1830
1831static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1832 .adap_enable = vc4_hdmi_cec_adap_enable,
1833 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1834 .adap_transmit = vc4_hdmi_cec_adap_transmit,
1835};
1836
1837static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1838{
1839 struct cec_connector_info conn_info;
1840 struct platform_device *pdev = vc4_hdmi->pdev;
1841 struct device *dev = &pdev->dev;
1842 u32 value;
1843 int ret;
1844
1845 if (!of_find_property(dev->of_node, "interrupts", NULL)) {
1846 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
1847 return 0;
1848 }
1849
1850 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1851 vc4_hdmi, "vc4",
1852 CEC_CAP_DEFAULTS |
1853 CEC_CAP_CONNECTOR_INFO, 1);
1854 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1855 if (ret < 0)
1856 return ret;
1857
1858 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1859 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1860
1861 value = HDMI_READ(HDMI_CEC_CNTRL_1);
1862 /* Set the logical address to Unregistered */
1863 value |= VC4_HDMI_CEC_ADDR_MASK;
1864 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1865
1866 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1867
1868 if (vc4_hdmi->variant->external_irq_controller) {
1869 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
1870 vc4_cec_irq_handler_rx_bare,
1871 vc4_cec_irq_handler_rx_thread, 0,
1872 "vc4 hdmi cec rx", vc4_hdmi);
1873 if (ret)
1874 goto err_delete_cec_adap;
1875
1876 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
1877 vc4_cec_irq_handler_tx_bare,
1878 vc4_cec_irq_handler_tx_thread, 0,
1879 "vc4 hdmi cec tx", vc4_hdmi);
1880 if (ret)
1881 goto err_remove_cec_rx_handler;
1882 } else {
1883 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1884
1885 ret = request_threaded_irq(platform_get_irq(pdev, 0),
1886 vc4_cec_irq_handler,
1887 vc4_cec_irq_handler_thread, 0,
1888 "vc4 hdmi cec", vc4_hdmi);
1889 if (ret)
1890 goto err_delete_cec_adap;
1891 }
1892
1893 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1894 if (ret < 0)
1895 goto err_remove_handlers;
1896
1897 return 0;
1898
1899err_remove_handlers:
1900 if (vc4_hdmi->variant->external_irq_controller)
1901 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1902 else
1903 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1904
1905err_remove_cec_rx_handler:
1906 if (vc4_hdmi->variant->external_irq_controller)
1907 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1908
1909err_delete_cec_adap:
1910 cec_delete_adapter(vc4_hdmi->cec_adap);
1911
1912 return ret;
1913}
1914
1915static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1916{
1917 struct platform_device *pdev = vc4_hdmi->pdev;
1918
1919 if (vc4_hdmi->variant->external_irq_controller) {
1920 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1921 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1922 } else {
1923 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1924 }
1925
1926 cec_unregister_adapter(vc4_hdmi->cec_adap);
1927}
1928#else
1929static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1930{
1931 return 0;
1932}
1933
1934static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1935
1936#endif
1937
1938static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1939 struct debugfs_regset32 *regset,
1940 enum vc4_hdmi_regs reg)
1941{
1942 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1943 struct debugfs_reg32 *regs, *new_regs;
1944 unsigned int count = 0;
1945 unsigned int i;
1946
1947 regs = kcalloc(variant->num_registers, sizeof(*regs),
1948 GFP_KERNEL);
1949 if (!regs)
1950 return -ENOMEM;
1951
1952 for (i = 0; i < variant->num_registers; i++) {
1953 const struct vc4_hdmi_register *field = &variant->registers[i];
1954
1955 if (field->reg != reg)
1956 continue;
1957
1958 regs[count].name = field->name;
1959 regs[count].offset = field->offset;
1960 count++;
1961 }
1962
1963 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1964 if (!new_regs)
1965 return -ENOMEM;
1966
1967 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1968 regset->regs = new_regs;
1969 regset->nregs = count;
1970
1971 return 0;
1972}
1973
1974static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1975{
1976 struct platform_device *pdev = vc4_hdmi->pdev;
1977 struct device *dev = &pdev->dev;
1978 int ret;
1979
1980 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1981 if (IS_ERR(vc4_hdmi->hdmicore_regs))
1982 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1983
1984 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1985 if (IS_ERR(vc4_hdmi->hd_regs))
1986 return PTR_ERR(vc4_hdmi->hd_regs);
1987
1988 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1989 if (ret)
1990 return ret;
1991
1992 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
1993 if (ret)
1994 return ret;
1995
1996 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1997 if (IS_ERR(vc4_hdmi->pixel_clock)) {
1998 ret = PTR_ERR(vc4_hdmi->pixel_clock);
1999 if (ret != -EPROBE_DEFER)
2000 DRM_ERROR("Failed to get pixel clock\n");
2001 return ret;
2002 }
2003
2004 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2005 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2006 DRM_ERROR("Failed to get HDMI state machine clock\n");
2007 return PTR_ERR(vc4_hdmi->hsm_clock);
2008 }
2009 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2010 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2011
2012 return 0;
2013}
2014
2015static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2016{
2017 struct platform_device *pdev = vc4_hdmi->pdev;
2018 struct device *dev = &pdev->dev;
2019 struct resource *res;
2020
2021 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2022 if (!res)
2023 return -ENODEV;
2024
2025 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2026 resource_size(res));
2027 if (!vc4_hdmi->hdmicore_regs)
2028 return -ENOMEM;
2029
2030 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2031 if (!res)
2032 return -ENODEV;
2033
2034 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2035 if (!vc4_hdmi->hd_regs)
2036 return -ENOMEM;
2037
2038 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2039 if (!res)
2040 return -ENODEV;
2041
2042 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2043 if (!vc4_hdmi->cec_regs)
2044 return -ENOMEM;
2045
2046 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2047 if (!res)
2048 return -ENODEV;
2049
2050 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2051 if (!vc4_hdmi->csc_regs)
2052 return -ENOMEM;
2053
2054 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2055 if (!res)
2056 return -ENODEV;
2057
2058 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2059 if (!vc4_hdmi->dvp_regs)
2060 return -ENOMEM;
2061
2062 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2063 if (!res)
2064 return -ENODEV;
2065
2066 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2067 if (!vc4_hdmi->phy_regs)
2068 return -ENOMEM;
2069
2070 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2071 if (!res)
2072 return -ENODEV;
2073
2074 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2075 if (!vc4_hdmi->ram_regs)
2076 return -ENOMEM;
2077
2078 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2079 if (!res)
2080 return -ENODEV;
2081
2082 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2083 if (!vc4_hdmi->rm_regs)
2084 return -ENOMEM;
2085
2086 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2087 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2088 DRM_ERROR("Failed to get HDMI state machine clock\n");
2089 return PTR_ERR(vc4_hdmi->hsm_clock);
2090 }
2091
2092 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2093 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2094 DRM_ERROR("Failed to get pixel bvb clock\n");
2095 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2096 }
2097
2098 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2099 if (IS_ERR(vc4_hdmi->audio_clock)) {
2100 DRM_ERROR("Failed to get audio clock\n");
2101 return PTR_ERR(vc4_hdmi->audio_clock);
2102 }
2103
2104 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2105 if (IS_ERR(vc4_hdmi->cec_clock)) {
2106 DRM_ERROR("Failed to get CEC clock\n");
2107 return PTR_ERR(vc4_hdmi->cec_clock);
2108 }
2109
2110 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2111 if (IS_ERR(vc4_hdmi->reset)) {
2112 DRM_ERROR("Failed to get HDMI reset line\n");
2113 return PTR_ERR(vc4_hdmi->reset);
2114 }
2115
2116 return 0;
2117}
2118
2119static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2120{
2121 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2122 struct platform_device *pdev = to_platform_device(dev);
2123 struct drm_device *drm = dev_get_drvdata(master);
2124 struct vc4_hdmi *vc4_hdmi;
2125 struct drm_encoder *encoder;
2126 struct device_node *ddc_node;
2127 int ret;
2128
2129 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2130 if (!vc4_hdmi)
2131 return -ENOMEM;
2132 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2133
2134 dev_set_drvdata(dev, vc4_hdmi);
2135 encoder = &vc4_hdmi->encoder.base.base;
2136 vc4_hdmi->encoder.base.type = variant->encoder_type;
2137 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2138 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2139 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2140 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2141 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2142 vc4_hdmi->pdev = pdev;
2143 vc4_hdmi->variant = variant;
2144
2145 ret = variant->init_resources(vc4_hdmi);
2146 if (ret)
2147 return ret;
2148
2149 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2150 if (!ddc_node) {
2151 DRM_ERROR("Failed to find ddc node in device tree\n");
2152 return -ENODEV;
2153 }
2154
2155 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2156 of_node_put(ddc_node);
2157 if (!vc4_hdmi->ddc) {
2158 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2159 return -EPROBE_DEFER;
2160 }
2161
2162 /* Only use the GPIO HPD pin if present in the DT, otherwise
2163 * we'll use the HDMI core's register.
2164 */
2165 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2166 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2167 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2168 goto err_put_ddc;
2169 }
2170
2171 vc4_hdmi->disable_wifi_frequencies =
2172 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2173
2174 if (variant->max_pixel_clock == 600000000) {
2175 struct vc4_dev *vc4 = to_vc4_dev(drm);
2176 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2177
2178 if (max_rate < 550000000)
2179 vc4_hdmi->disable_4kp60 = true;
2180 }
2181
2182 if (vc4_hdmi->variant->reset)
2183 vc4_hdmi->variant->reset(vc4_hdmi);
2184
2185 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2186 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2187 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2188 clk_prepare_enable(vc4_hdmi->pixel_clock);
2189 clk_prepare_enable(vc4_hdmi->hsm_clock);
2190 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2191 }
2192
2193 pm_runtime_enable(dev);
2194
2195 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2196 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2197
2198 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2199 if (ret)
2200 goto err_destroy_encoder;
2201
2202 ret = vc4_hdmi_cec_init(vc4_hdmi);
2203 if (ret)
2204 goto err_destroy_conn;
2205
2206 ret = vc4_hdmi_audio_init(vc4_hdmi);
2207 if (ret)
2208 goto err_free_cec;
2209
2210 vc4_debugfs_add_file(drm, variant->debugfs_name,
2211 vc4_hdmi_debugfs_regs,
2212 vc4_hdmi);
2213
2214 return 0;
2215
2216err_free_cec:
2217 vc4_hdmi_cec_exit(vc4_hdmi);
2218err_destroy_conn:
2219 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2220err_destroy_encoder:
2221 drm_encoder_cleanup(encoder);
2222 pm_runtime_disable(dev);
2223err_put_ddc:
2224 put_device(&vc4_hdmi->ddc->dev);
2225
2226 return ret;
2227}
2228
2229static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2230 void *data)
2231{
2232 struct vc4_hdmi *vc4_hdmi;
2233
2234 /*
2235 * ASoC makes it a bit hard to retrieve a pointer to the
2236 * vc4_hdmi structure. Registering the card will overwrite our
2237 * device drvdata with a pointer to the snd_soc_card structure,
2238 * which can then be used to retrieve whatever drvdata we want
2239 * to associate.
2240 *
2241 * However, that doesn't fly in the case where we wouldn't
2242 * register an ASoC card (because of an old DT that is missing
2243 * the dmas properties for example), then the card isn't
2244 * registered and the device drvdata wouldn't be set.
2245 *
2246 * We can deal with both cases by making sure a snd_soc_card
2247 * pointer and a vc4_hdmi structure are pointing to the same
2248 * memory address, so we can treat them indistinctly without any
2249 * issue.
2250 */
2251 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2252 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2253 vc4_hdmi = dev_get_drvdata(dev);
2254
2255 kfree(vc4_hdmi->hdmi_regset.regs);
2256 kfree(vc4_hdmi->hd_regset.regs);
2257
2258 vc4_hdmi_cec_exit(vc4_hdmi);
2259 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2260 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2261
2262 pm_runtime_disable(dev);
2263
2264 put_device(&vc4_hdmi->ddc->dev);
2265}
2266
2267static const struct component_ops vc4_hdmi_ops = {
2268 .bind = vc4_hdmi_bind,
2269 .unbind = vc4_hdmi_unbind,
2270};
2271
2272static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2273{
2274 return component_add(&pdev->dev, &vc4_hdmi_ops);
2275}
2276
2277static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2278{
2279 component_del(&pdev->dev, &vc4_hdmi_ops);
2280 return 0;
2281}
2282
2283static const struct vc4_hdmi_variant bcm2835_variant = {
2284 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
2285 .debugfs_name = "hdmi_regs",
2286 .card_name = "vc4-hdmi",
2287 .max_pixel_clock = 162000000,
2288 .registers = vc4_hdmi_fields,
2289 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
2290
2291 .init_resources = vc4_hdmi_init_resources,
2292 .csc_setup = vc4_hdmi_csc_setup,
2293 .reset = vc4_hdmi_reset,
2294 .set_timings = vc4_hdmi_set_timings,
2295 .phy_init = vc4_hdmi_phy_init,
2296 .phy_disable = vc4_hdmi_phy_disable,
2297 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
2298 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
2299 .channel_map = vc4_hdmi_channel_map,
2300 .supports_hdr = false,
2301};
2302
2303static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2304 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
2305 .debugfs_name = "hdmi0_regs",
2306 .card_name = "vc4-hdmi-0",
2307 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
2308 .registers = vc5_hdmi_hdmi0_fields,
2309 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2310 .phy_lane_mapping = {
2311 PHY_LANE_0,
2312 PHY_LANE_1,
2313 PHY_LANE_2,
2314 PHY_LANE_CK,
2315 },
2316 .unsupported_odd_h_timings = true,
2317 .external_irq_controller = true,
2318
2319 .init_resources = vc5_hdmi_init_resources,
2320 .csc_setup = vc5_hdmi_csc_setup,
2321 .reset = vc5_hdmi_reset,
2322 .set_timings = vc5_hdmi_set_timings,
2323 .phy_init = vc5_hdmi_phy_init,
2324 .phy_disable = vc5_hdmi_phy_disable,
2325 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
2326 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
2327 .channel_map = vc5_hdmi_channel_map,
2328 .supports_hdr = true,
2329};
2330
2331static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2332 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
2333 .debugfs_name = "hdmi1_regs",
2334 .card_name = "vc4-hdmi-1",
2335 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
2336 .registers = vc5_hdmi_hdmi1_fields,
2337 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2338 .phy_lane_mapping = {
2339 PHY_LANE_1,
2340 PHY_LANE_0,
2341 PHY_LANE_CK,
2342 PHY_LANE_2,
2343 },
2344 .unsupported_odd_h_timings = true,
2345 .external_irq_controller = true,
2346
2347 .init_resources = vc5_hdmi_init_resources,
2348 .csc_setup = vc5_hdmi_csc_setup,
2349 .reset = vc5_hdmi_reset,
2350 .set_timings = vc5_hdmi_set_timings,
2351 .phy_init = vc5_hdmi_phy_init,
2352 .phy_disable = vc5_hdmi_phy_disable,
2353 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
2354 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
2355 .channel_map = vc5_hdmi_channel_map,
2356 .supports_hdr = true,
2357};
2358
2359static const struct of_device_id vc4_hdmi_dt_match[] = {
2360 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2361 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2362 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2363 {}
2364};
2365
2366struct platform_driver vc4_hdmi_driver = {
2367 .probe = vc4_hdmi_dev_probe,
2368 .remove = vc4_hdmi_dev_remove,
2369 .driver = {
2370 .name = "vc4_hdmi",
2371 .of_match_table = vc4_hdmi_dt_match,
2372 },
2373};