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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 */
6
7#include <linux/clk.h>
8
9#include <drm/drm_atomic_helper.h>
10#include <drm/drm_bridge_connector.h>
11#include <drm/drm_simple_kms_helper.h>
12
13#include "drm.h"
14#include "dc.h"
15
16struct tegra_rgb {
17 struct tegra_output output;
18 struct tegra_dc *dc;
19
20 struct clk *clk_parent;
21 struct clk *clk;
22};
23
24static inline struct tegra_rgb *to_rgb(struct tegra_output *output)
25{
26 return container_of(output, struct tegra_rgb, output);
27}
28
29struct reg_entry {
30 unsigned long offset;
31 unsigned long value;
32};
33
34static const struct reg_entry rgb_enable[] = {
35 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 },
36 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 },
37 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 },
38 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 },
39 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
40 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 },
41 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
42 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
43 { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 },
44 { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 },
45 { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 },
46 { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 },
47 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
48 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
49 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
50 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
51 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 },
52 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 },
53 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 },
54};
55
56static const struct reg_entry rgb_disable[] = {
57 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 },
58 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 },
59 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 },
60 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
61 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
62 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
63 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
64 { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa },
65 { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa },
66 { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa },
67 { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa },
68 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
69 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
70 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 },
71 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
72 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 },
73 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 },
74 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 },
75 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 },
76};
77
78static void tegra_dc_write_regs(struct tegra_dc *dc,
79 const struct reg_entry *table,
80 unsigned int num)
81{
82 unsigned int i;
83
84 for (i = 0; i < num; i++)
85 tegra_dc_writel(dc, table[i].value, table[i].offset);
86}
87
88static void tegra_rgb_encoder_disable(struct drm_encoder *encoder)
89{
90 struct tegra_output *output = encoder_to_output(encoder);
91 struct tegra_rgb *rgb = to_rgb(output);
92
93 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
94 tegra_dc_commit(rgb->dc);
95}
96
97static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
98{
99 struct tegra_output *output = encoder_to_output(encoder);
100 struct tegra_rgb *rgb = to_rgb(output);
101 u32 value;
102
103 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
104
105 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
106 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
107
108 /* XXX: parameterize? */
109 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));
110 value &= ~LVS_OUTPUT_POLARITY_LOW;
111 value &= ~LHS_OUTPUT_POLARITY_LOW;
112 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
113
114 /* XXX: parameterize? */
115 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
116 DISP_ORDER_RED_BLUE;
117 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
118
119 /* XXX: parameterize? */
120 value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
121 tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
122
123 tegra_dc_commit(rgb->dc);
124}
125
126static int
127tegra_rgb_encoder_atomic_check(struct drm_encoder *encoder,
128 struct drm_crtc_state *crtc_state,
129 struct drm_connector_state *conn_state)
130{
131 struct tegra_output *output = encoder_to_output(encoder);
132 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
133 unsigned long pclk = crtc_state->mode.clock * 1000;
134 struct tegra_rgb *rgb = to_rgb(output);
135 unsigned int div;
136 int err;
137
138 /*
139 * We may not want to change the frequency of the parent clock, since
140 * it may be a parent for other peripherals. This is due to the fact
141 * that on Tegra20 there's only a single clock dedicated to display
142 * (pll_d_out0), whereas later generations have a second one that can
143 * be used to independently drive a second output (pll_d2_out0).
144 *
145 * As a way to support multiple outputs on Tegra20 as well, pll_p is
146 * typically used as the parent clock for the display controllers.
147 * But this comes at a cost: pll_p is the parent of several other
148 * peripherals, so its frequency shouldn't change out of the blue.
149 *
150 * The best we can do at this point is to use the shift clock divider
151 * and hope that the desired frequency can be matched (or at least
152 * matched sufficiently close that the panel will still work).
153 */
154 div = ((clk_get_rate(rgb->clk) * 2) / pclk) - 2;
155 pclk = 0;
156
157 err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent,
158 pclk, div);
159 if (err < 0) {
160 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
161 return err;
162 }
163
164 return err;
165}
166
167static const struct drm_encoder_helper_funcs tegra_rgb_encoder_helper_funcs = {
168 .disable = tegra_rgb_encoder_disable,
169 .enable = tegra_rgb_encoder_enable,
170 .atomic_check = tegra_rgb_encoder_atomic_check,
171};
172
173int tegra_dc_rgb_probe(struct tegra_dc *dc)
174{
175 struct device_node *np;
176 struct tegra_rgb *rgb;
177 int err;
178
179 np = of_get_child_by_name(dc->dev->of_node, "rgb");
180 if (!np || !of_device_is_available(np))
181 return -ENODEV;
182
183 rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);
184 if (!rgb)
185 return -ENOMEM;
186
187 rgb->output.dev = dc->dev;
188 rgb->output.of_node = np;
189 rgb->dc = dc;
190
191 err = tegra_output_probe(&rgb->output);
192 if (err < 0)
193 return err;
194
195 rgb->clk = devm_clk_get(dc->dev, NULL);
196 if (IS_ERR(rgb->clk)) {
197 dev_err(dc->dev, "failed to get clock\n");
198 return PTR_ERR(rgb->clk);
199 }
200
201 rgb->clk_parent = devm_clk_get(dc->dev, "parent");
202 if (IS_ERR(rgb->clk_parent)) {
203 dev_err(dc->dev, "failed to get parent clock\n");
204 return PTR_ERR(rgb->clk_parent);
205 }
206
207 err = clk_set_parent(rgb->clk, rgb->clk_parent);
208 if (err < 0) {
209 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
210 return err;
211 }
212
213 dc->rgb = &rgb->output;
214
215 return 0;
216}
217
218int tegra_dc_rgb_remove(struct tegra_dc *dc)
219{
220 if (!dc->rgb)
221 return 0;
222
223 tegra_output_remove(dc->rgb);
224 dc->rgb = NULL;
225
226 return 0;
227}
228
229int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
230{
231 struct tegra_output *output = dc->rgb;
232 struct drm_connector *connector;
233 int err;
234
235 if (!dc->rgb)
236 return -ENODEV;
237
238 drm_simple_encoder_init(drm, &output->encoder, DRM_MODE_ENCODER_LVDS);
239 drm_encoder_helper_add(&output->encoder,
240 &tegra_rgb_encoder_helper_funcs);
241
242 /*
243 * Wrap directly-connected panel into DRM bridge in order to let
244 * DRM core to handle panel for us.
245 */
246 if (output->panel) {
247 output->bridge = devm_drm_panel_bridge_add(output->dev,
248 output->panel);
249 if (IS_ERR(output->bridge)) {
250 dev_err(output->dev,
251 "failed to wrap panel into bridge: %pe\n",
252 output->bridge);
253 return PTR_ERR(output->bridge);
254 }
255
256 output->panel = NULL;
257 }
258
259 /*
260 * Tegra devices that have LVDS panel utilize LVDS encoder bridge
261 * for converting up to 28 LCD LVTTL lanes into 5/4 LVDS lanes that
262 * go to display panel's receiver.
263 *
264 * Encoder usually have a power-down control which needs to be enabled
265 * in order to transmit data to the panel. Historically devices that
266 * use an older device-tree version didn't model the bridge, assuming
267 * that encoder is turned ON by default, while today's DRM allows us
268 * to model LVDS encoder properly.
269 *
270 * Newer device-trees utilize LVDS encoder bridge, which provides
271 * us with a connector and handles the display panel.
272 *
273 * For older device-trees we wrapped panel into the panel-bridge.
274 */
275 if (output->bridge) {
276 err = drm_bridge_attach(&output->encoder, output->bridge,
277 NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
278 if (err) {
279 dev_err(output->dev, "failed to attach bridge: %d\n",
280 err);
281 return err;
282 }
283
284 connector = drm_bridge_connector_init(drm, &output->encoder);
285 if (IS_ERR(connector)) {
286 dev_err(output->dev,
287 "failed to initialize bridge connector: %pe\n",
288 connector);
289 return PTR_ERR(connector);
290 }
291
292 drm_connector_attach_encoder(connector, &output->encoder);
293 }
294
295 err = tegra_output_init(drm, output);
296 if (err < 0) {
297 dev_err(output->dev, "failed to initialize output: %d\n", err);
298 return err;
299 }
300
301 /*
302 * Other outputs can be attached to either display controller. The RGB
303 * outputs are an exception and work only with their parent display
304 * controller.
305 */
306 output->encoder.possible_crtcs = drm_crtc_mask(&dc->base);
307
308 return 0;
309}
310
311int tegra_dc_rgb_exit(struct tegra_dc *dc)
312{
313 if (dc->rgb)
314 tegra_output_exit(dc->rgb);
315
316 return 0;
317}