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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * mtu3.h - MediaTek USB3 DRD header
4 *
5 * Copyright (C) 2016 MediaTek Inc.
6 *
7 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
8 */
9
10#ifndef __MTU3_H__
11#define __MTU3_H__
12
13#include <linux/clk.h>
14#include <linux/device.h>
15#include <linux/dmapool.h>
16#include <linux/extcon.h>
17#include <linux/interrupt.h>
18#include <linux/list.h>
19#include <linux/phy/phy.h>
20#include <linux/regulator/consumer.h>
21#include <linux/usb.h>
22#include <linux/usb/ch9.h>
23#include <linux/usb/gadget.h>
24#include <linux/usb/otg.h>
25#include <linux/usb/role.h>
26
27struct mtu3;
28struct mtu3_ep;
29struct mtu3_request;
30
31#include "mtu3_hw_regs.h"
32#include "mtu3_qmu.h"
33
34#define MU3D_EP_TXCR0(epnum) (U3D_TX1CSR0 + (((epnum) - 1) * 0x10))
35#define MU3D_EP_TXCR1(epnum) (U3D_TX1CSR1 + (((epnum) - 1) * 0x10))
36#define MU3D_EP_TXCR2(epnum) (U3D_TX1CSR2 + (((epnum) - 1) * 0x10))
37
38#define MU3D_EP_RXCR0(epnum) (U3D_RX1CSR0 + (((epnum) - 1) * 0x10))
39#define MU3D_EP_RXCR1(epnum) (U3D_RX1CSR1 + (((epnum) - 1) * 0x10))
40#define MU3D_EP_RXCR2(epnum) (U3D_RX1CSR2 + (((epnum) - 1) * 0x10))
41
42#define USB_QMU_TQHIAR(epnum) (U3D_TXQHIAR1 + (((epnum) - 1) * 0x4))
43#define USB_QMU_RQHIAR(epnum) (U3D_RXQHIAR1 + (((epnum) - 1) * 0x4))
44
45#define USB_QMU_RQCSR(epnum) (U3D_RXQCSR1 + (((epnum) - 1) * 0x10))
46#define USB_QMU_RQSAR(epnum) (U3D_RXQSAR1 + (((epnum) - 1) * 0x10))
47#define USB_QMU_RQCPR(epnum) (U3D_RXQCPR1 + (((epnum) - 1) * 0x10))
48
49#define USB_QMU_TQCSR(epnum) (U3D_TXQCSR1 + (((epnum) - 1) * 0x10))
50#define USB_QMU_TQSAR(epnum) (U3D_TXQSAR1 + (((epnum) - 1) * 0x10))
51#define USB_QMU_TQCPR(epnum) (U3D_TXQCPR1 + (((epnum) - 1) * 0x10))
52
53#define SSUSB_U3_CTRL(p) (U3D_SSUSB_U3_CTRL_0P + ((p) * 0x08))
54#define SSUSB_U2_CTRL(p) (U3D_SSUSB_U2_CTRL_0P + ((p) * 0x08))
55
56#define MTU3_DRIVER_NAME "mtu3"
57#define DMA_ADDR_INVALID (~(dma_addr_t)0)
58
59#define MTU3_EP_ENABLED BIT(0)
60#define MTU3_EP_STALL BIT(1)
61#define MTU3_EP_WEDGE BIT(2)
62#define MTU3_EP_BUSY BIT(3)
63
64#define MTU3_U3_IP_SLOT_DEFAULT 2
65#define MTU3_U2_IP_SLOT_DEFAULT 1
66
67/**
68 * IP TRUNK version
69 * from 0x1003 version, USB3 Gen2 is supported, two changes affect driver:
70 * 1. MAXPKT and MULTI bits layout of TXCSR1 and RXCSR1 are adjusted,
71 * but not backward compatible
72 * 2. QMU extend buffer length supported
73 */
74#define MTU3_TRUNK_VERS_1003 0x1003
75
76/**
77 * Normally the device works on HS or SS, to simplify fifo management,
78 * devide fifo into some 512B parts, use bitmap to manage it; And
79 * 128 bits size of bitmap is large enough, that means it can manage
80 * up to 64KB fifo size.
81 * NOTE: MTU3_EP_FIFO_UNIT should be power of two
82 */
83#define MTU3_EP_FIFO_UNIT (1 << 9)
84#define MTU3_FIFO_BIT_SIZE 128
85#define MTU3_U2_IP_EP0_FIFO_SIZE 64
86
87/**
88 * Maximum size of ep0 response buffer for ch9 requests,
89 * the SET_SEL request uses 6 so far, and GET_STATUS is 2
90 */
91#define EP0_RESPONSE_BUF 6
92
93#define BULK_CLKS_CNT 4
94
95/* device operated link and speed got from DEVICE_CONF register */
96enum mtu3_speed {
97 MTU3_SPEED_INACTIVE = 0,
98 MTU3_SPEED_FULL = 1,
99 MTU3_SPEED_HIGH = 3,
100 MTU3_SPEED_SUPER = 4,
101 MTU3_SPEED_SUPER_PLUS = 5,
102};
103
104/**
105 * @MU3D_EP0_STATE_SETUP: waits for SETUP or received a SETUP
106 * without data stage.
107 * @MU3D_EP0_STATE_TX: IN data stage
108 * @MU3D_EP0_STATE_RX: OUT data stage
109 * @MU3D_EP0_STATE_TX_END: the last IN data is transferred, and
110 * waits for its completion interrupt
111 * @MU3D_EP0_STATE_STALL: ep0 is in stall status, will be auto-cleared
112 * after receives a SETUP.
113 */
114enum mtu3_g_ep0_state {
115 MU3D_EP0_STATE_SETUP = 1,
116 MU3D_EP0_STATE_TX,
117 MU3D_EP0_STATE_RX,
118 MU3D_EP0_STATE_TX_END,
119 MU3D_EP0_STATE_STALL,
120};
121
122/**
123 * MTU3_DR_FORCE_NONE: automatically switch host and periperal mode
124 * by IDPIN signal.
125 * MTU3_DR_FORCE_HOST: force to enter host mode and override OTG
126 * IDPIN signal.
127 * MTU3_DR_FORCE_DEVICE: force to enter peripheral mode.
128 */
129enum mtu3_dr_force_mode {
130 MTU3_DR_FORCE_NONE = 0,
131 MTU3_DR_FORCE_HOST,
132 MTU3_DR_FORCE_DEVICE,
133};
134
135/**
136 * @base: the base address of fifo
137 * @limit: the bitmap size in bits
138 * @bitmap: fifo bitmap in unit of @MTU3_EP_FIFO_UNIT
139 */
140struct mtu3_fifo_info {
141 u32 base;
142 u32 limit;
143 DECLARE_BITMAP(bitmap, MTU3_FIFO_BIT_SIZE);
144};
145
146/**
147 * General Purpose Descriptor (GPD):
148 * The format of TX GPD is a little different from RX one.
149 * And the size of GPD is 16 bytes.
150 *
151 * @dw0_info:
152 * bit0: Hardware Own (HWO)
153 * bit1: Buffer Descriptor Present (BDP), always 0, BD is not supported
154 * bit2: Bypass (BPS), 1: HW skips this GPD if HWO = 1
155 * bit6: [EL] Zero Length Packet (ZLP), moved from @dw3_info[29]
156 * bit7: Interrupt On Completion (IOC)
157 * bit[31:16]: ([EL] bit[31:12]) allow data buffer length (RX ONLY),
158 * the buffer length of the data to receive
159 * bit[23:16]: ([EL] bit[31:24]) extension address (TX ONLY),
160 * lower 4 bits are extension bits of @buffer,
161 * upper 4 bits are extension bits of @next_gpd
162 * @next_gpd: Physical address of the next GPD
163 * @buffer: Physical address of the data buffer
164 * @dw3_info:
165 * bit[15:0]: ([EL] bit[19:0]) data buffer length,
166 * (TX): the buffer length of the data to transmit
167 * (RX): The total length of data received
168 * bit[23:16]: ([EL] bit[31:24]) extension address (RX ONLY),
169 * lower 4 bits are extension bits of @buffer,
170 * upper 4 bits are extension bits of @next_gpd
171 * bit29: ([EL] abandoned) Zero Length Packet (ZLP) (TX ONLY)
172 */
173struct qmu_gpd {
174 __le32 dw0_info;
175 __le32 next_gpd;
176 __le32 buffer;
177 __le32 dw3_info;
178} __packed;
179
180/**
181* dma: physical base address of GPD segment
182* start: virtual base address of GPD segment
183* end: the last GPD element
184* enqueue: the first empty GPD to use
185* dequeue: the first completed GPD serviced by ISR
186* NOTE: the size of GPD ring should be >= 2
187*/
188struct mtu3_gpd_ring {
189 dma_addr_t dma;
190 struct qmu_gpd *start;
191 struct qmu_gpd *end;
192 struct qmu_gpd *enqueue;
193 struct qmu_gpd *dequeue;
194};
195
196/**
197* @vbus: vbus 5V used by host mode
198* @edev: external connector used to detect vbus and iddig changes
199* @id_nb : notifier for iddig(idpin) detection
200* @dr_work : work for drd mode switch, used to avoid sleep in atomic context
201* @desired_role : role desired to switch
202* @role_sw : use USB Role Switch to support dual-role switch, can't use
203* extcon at the same time, and extcon is deprecated.
204* @role_sw_used : true when the USB Role Switch is used.
205* @is_u3_drd: whether port0 supports usb3.0 dual-role device or not
206* @manual_drd_enabled: it's true when supports dual-role device by debugfs
207* to switch host/device modes depending on user input.
208*/
209struct otg_switch_mtk {
210 struct regulator *vbus;
211 struct extcon_dev *edev;
212 struct notifier_block id_nb;
213 struct work_struct dr_work;
214 enum usb_role desired_role;
215 struct usb_role_switch *role_sw;
216 bool role_sw_used;
217 bool is_u3_drd;
218 bool manual_drd_enabled;
219};
220
221/**
222 * @mac_base: register base address of device MAC, exclude xHCI's
223 * @ippc_base: register base address of IP Power and Clock interface (IPPC)
224 * @vusb33: usb3.3V shared by device/host IP
225 * @dr_mode: works in which mode:
226 * host only, device only or dual-role mode
227 * @u2_ports: number of usb2.0 host ports
228 * @u3_ports: number of usb3.0 host ports
229 * @u3p_dis_msk: mask of disabling usb3 ports, for example, bit0==1 to
230 * disable u3port0, bit1==1 to disable u3port1,... etc
231 * @dbgfs_root: only used when supports manual dual-role switch via debugfs
232 * @uwk_en: it's true when supports remote wakeup in host mode
233 * @uwk: syscon including usb wakeup glue layer between SSUSB IP and SPM
234 * @uwk_reg_base: the base address of the wakeup glue layer in @uwk
235 * @uwk_vers: the version of the wakeup glue layer
236 */
237struct ssusb_mtk {
238 struct device *dev;
239 struct mtu3 *u3d;
240 void __iomem *mac_base;
241 void __iomem *ippc_base;
242 struct phy **phys;
243 int num_phys;
244 /* common power & clock */
245 struct regulator *vusb33;
246 struct clk_bulk_data clks[BULK_CLKS_CNT];
247 /* otg */
248 struct otg_switch_mtk otg_switch;
249 enum usb_dr_mode dr_mode;
250 bool is_host;
251 int u2_ports;
252 int u3_ports;
253 int u3p_dis_msk;
254 struct dentry *dbgfs_root;
255 /* usb wakeup for host mode */
256 bool uwk_en;
257 struct regmap *uwk;
258 u32 uwk_reg_base;
259 u32 uwk_vers;
260};
261
262/**
263 * @fifo_size: it is (@slot + 1) * @fifo_seg_size
264 * @fifo_seg_size: it is roundup_pow_of_two(@maxp)
265 */
266struct mtu3_ep {
267 struct usb_ep ep;
268 char name[12];
269 struct mtu3 *mtu;
270 u8 epnum;
271 u8 type;
272 u8 is_in;
273 u16 maxp;
274 int slot;
275 u32 fifo_size;
276 u32 fifo_addr;
277 u32 fifo_seg_size;
278 struct mtu3_fifo_info *fifo;
279
280 struct list_head req_list;
281 struct mtu3_gpd_ring gpd_ring;
282 const struct usb_ss_ep_comp_descriptor *comp_desc;
283 const struct usb_endpoint_descriptor *desc;
284
285 int flags;
286};
287
288struct mtu3_request {
289 struct usb_request request;
290 struct list_head list;
291 struct mtu3_ep *mep;
292 struct mtu3 *mtu;
293 struct qmu_gpd *gpd;
294 int epnum;
295};
296
297static inline struct ssusb_mtk *dev_to_ssusb(struct device *dev)
298{
299 return dev_get_drvdata(dev);
300}
301
302/**
303 * struct mtu3 - device driver instance data.
304 * @slot: MTU3_U2_IP_SLOT_DEFAULT for U2 IP only,
305 * MTU3_U3_IP_SLOT_DEFAULT for U3 IP
306 * @may_wakeup: means device's remote wakeup is enabled
307 * @is_self_powered: is reported in device status and the config descriptor
308 * @delayed_status: true when function drivers ask for delayed status
309 * @gen2cp: compatible with USB3 Gen2 IP
310 * @ep0_req: dummy request used while handling standard USB requests
311 * for GET_STATUS and SET_SEL
312 * @setup_buf: ep0 response buffer for GET_STATUS and SET_SEL requests
313 */
314struct mtu3 {
315 spinlock_t lock;
316 struct ssusb_mtk *ssusb;
317 struct device *dev;
318 void __iomem *mac_base;
319 void __iomem *ippc_base;
320 int irq;
321
322 struct mtu3_fifo_info tx_fifo;
323 struct mtu3_fifo_info rx_fifo;
324
325 struct mtu3_ep *ep_array;
326 struct mtu3_ep *in_eps;
327 struct mtu3_ep *out_eps;
328 struct mtu3_ep *ep0;
329 int num_eps;
330 int slot;
331 int active_ep;
332
333 struct dma_pool *qmu_gpd_pool;
334 enum mtu3_g_ep0_state ep0_state;
335 struct usb_gadget g; /* the gadget */
336 struct usb_gadget_driver *gadget_driver;
337 struct mtu3_request ep0_req;
338 u8 setup_buf[EP0_RESPONSE_BUF];
339 enum usb_device_speed max_speed;
340 enum usb_device_speed speed;
341
342 unsigned is_active:1;
343 unsigned may_wakeup:1;
344 unsigned is_self_powered:1;
345 unsigned test_mode:1;
346 unsigned softconnect:1;
347 unsigned u1_enable:1;
348 unsigned u2_enable:1;
349 unsigned is_u3_ip:1;
350 unsigned delayed_status:1;
351 unsigned gen2cp:1;
352
353 u8 address;
354 u8 test_mode_nr;
355 u32 hw_version;
356};
357
358static inline struct mtu3 *gadget_to_mtu3(struct usb_gadget *g)
359{
360 return container_of(g, struct mtu3, g);
361}
362
363static inline struct mtu3_request *to_mtu3_request(struct usb_request *req)
364{
365 return req ? container_of(req, struct mtu3_request, request) : NULL;
366}
367
368static inline struct mtu3_ep *to_mtu3_ep(struct usb_ep *ep)
369{
370 return ep ? container_of(ep, struct mtu3_ep, ep) : NULL;
371}
372
373static inline struct mtu3_request *next_request(struct mtu3_ep *mep)
374{
375 return list_first_entry_or_null(&mep->req_list, struct mtu3_request,
376 list);
377}
378
379static inline void mtu3_writel(void __iomem *base, u32 offset, u32 data)
380{
381 writel(data, base + offset);
382}
383
384static inline u32 mtu3_readl(void __iomem *base, u32 offset)
385{
386 return readl(base + offset);
387}
388
389static inline void mtu3_setbits(void __iomem *base, u32 offset, u32 bits)
390{
391 void __iomem *addr = base + offset;
392 u32 tmp = readl(addr);
393
394 writel((tmp | (bits)), addr);
395}
396
397static inline void mtu3_clrbits(void __iomem *base, u32 offset, u32 bits)
398{
399 void __iomem *addr = base + offset;
400 u32 tmp = readl(addr);
401
402 writel((tmp & ~(bits)), addr);
403}
404
405int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks);
406struct usb_request *mtu3_alloc_request(struct usb_ep *ep, gfp_t gfp_flags);
407void mtu3_free_request(struct usb_ep *ep, struct usb_request *req);
408void mtu3_req_complete(struct mtu3_ep *mep,
409 struct usb_request *req, int status);
410
411int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
412 int interval, int burst, int mult);
413void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep);
414void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set);
415void mtu3_start(struct mtu3 *mtu);
416void mtu3_stop(struct mtu3 *mtu);
417void mtu3_dev_on_off(struct mtu3 *mtu, int is_on);
418
419int mtu3_gadget_setup(struct mtu3 *mtu);
420void mtu3_gadget_cleanup(struct mtu3 *mtu);
421void mtu3_gadget_reset(struct mtu3 *mtu);
422void mtu3_gadget_suspend(struct mtu3 *mtu);
423void mtu3_gadget_resume(struct mtu3 *mtu);
424void mtu3_gadget_disconnect(struct mtu3 *mtu);
425
426irqreturn_t mtu3_ep0_isr(struct mtu3 *mtu);
427extern const struct usb_ep_ops mtu3_ep0_ops;
428
429#endif