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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * mtu3.h - MediaTek USB3 DRD header
4 *
5 * Copyright (C) 2016 MediaTek Inc.
6 *
7 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
8 */
9
10#ifndef __MTU3_H__
11#define __MTU3_H__
12
13#include <linux/device.h>
14#include <linux/dmapool.h>
15#include <linux/extcon.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/phy/phy.h>
19#include <linux/regulator/consumer.h>
20#include <linux/usb.h>
21#include <linux/usb/ch9.h>
22#include <linux/usb/gadget.h>
23#include <linux/usb/otg.h>
24
25struct mtu3;
26struct mtu3_ep;
27struct mtu3_request;
28
29#include "mtu3_hw_regs.h"
30#include "mtu3_qmu.h"
31
32#define MU3D_EP_TXCR0(epnum) (U3D_TX1CSR0 + (((epnum) - 1) * 0x10))
33#define MU3D_EP_TXCR1(epnum) (U3D_TX1CSR1 + (((epnum) - 1) * 0x10))
34#define MU3D_EP_TXCR2(epnum) (U3D_TX1CSR2 + (((epnum) - 1) * 0x10))
35
36#define MU3D_EP_RXCR0(epnum) (U3D_RX1CSR0 + (((epnum) - 1) * 0x10))
37#define MU3D_EP_RXCR1(epnum) (U3D_RX1CSR1 + (((epnum) - 1) * 0x10))
38#define MU3D_EP_RXCR2(epnum) (U3D_RX1CSR2 + (((epnum) - 1) * 0x10))
39
40#define USB_QMU_TQHIAR(epnum) (U3D_TXQHIAR1 + (((epnum) - 1) * 0x4))
41#define USB_QMU_RQHIAR(epnum) (U3D_RXQHIAR1 + (((epnum) - 1) * 0x4))
42
43#define USB_QMU_RQCSR(epnum) (U3D_RXQCSR1 + (((epnum) - 1) * 0x10))
44#define USB_QMU_RQSAR(epnum) (U3D_RXQSAR1 + (((epnum) - 1) * 0x10))
45#define USB_QMU_RQCPR(epnum) (U3D_RXQCPR1 + (((epnum) - 1) * 0x10))
46
47#define USB_QMU_TQCSR(epnum) (U3D_TXQCSR1 + (((epnum) - 1) * 0x10))
48#define USB_QMU_TQSAR(epnum) (U3D_TXQSAR1 + (((epnum) - 1) * 0x10))
49#define USB_QMU_TQCPR(epnum) (U3D_TXQCPR1 + (((epnum) - 1) * 0x10))
50
51#define SSUSB_U3_CTRL(p) (U3D_SSUSB_U3_CTRL_0P + ((p) * 0x08))
52#define SSUSB_U2_CTRL(p) (U3D_SSUSB_U2_CTRL_0P + ((p) * 0x08))
53
54#define MTU3_DRIVER_NAME "mtu3"
55#define DMA_ADDR_INVALID (~(dma_addr_t)0)
56
57#define MTU3_EP_ENABLED BIT(0)
58#define MTU3_EP_STALL BIT(1)
59#define MTU3_EP_WEDGE BIT(2)
60#define MTU3_EP_BUSY BIT(3)
61
62#define MTU3_U3_IP_SLOT_DEFAULT 2
63#define MTU3_U2_IP_SLOT_DEFAULT 1
64
65/**
66 * Normally the device works on HS or SS, to simplify fifo management,
67 * devide fifo into some 512B parts, use bitmap to manage it; And
68 * 128 bits size of bitmap is large enough, that means it can manage
69 * up to 64KB fifo size.
70 * NOTE: MTU3_EP_FIFO_UNIT should be power of two
71 */
72#define MTU3_EP_FIFO_UNIT (1 << 9)
73#define MTU3_FIFO_BIT_SIZE 128
74#define MTU3_U2_IP_EP0_FIFO_SIZE 64
75
76/**
77 * Maximum size of ep0 response buffer for ch9 requests,
78 * the SET_SEL request uses 6 so far, and GET_STATUS is 2
79 */
80#define EP0_RESPONSE_BUF 6
81
82/* device operated link and speed got from DEVICE_CONF register */
83enum mtu3_speed {
84 MTU3_SPEED_INACTIVE = 0,
85 MTU3_SPEED_FULL = 1,
86 MTU3_SPEED_HIGH = 3,
87 MTU3_SPEED_SUPER = 4,
88 MTU3_SPEED_SUPER_PLUS = 5,
89};
90
91/**
92 * @MU3D_EP0_STATE_SETUP: waits for SETUP or received a SETUP
93 * without data stage.
94 * @MU3D_EP0_STATE_TX: IN data stage
95 * @MU3D_EP0_STATE_RX: OUT data stage
96 * @MU3D_EP0_STATE_TX_END: the last IN data is transferred, and
97 * waits for its completion interrupt
98 * @MU3D_EP0_STATE_STALL: ep0 is in stall status, will be auto-cleared
99 * after receives a SETUP.
100 */
101enum mtu3_g_ep0_state {
102 MU3D_EP0_STATE_SETUP = 1,
103 MU3D_EP0_STATE_TX,
104 MU3D_EP0_STATE_RX,
105 MU3D_EP0_STATE_TX_END,
106 MU3D_EP0_STATE_STALL,
107};
108
109/**
110 * MTU3_DR_FORCE_NONE: automatically switch host and periperal mode
111 * by IDPIN signal.
112 * MTU3_DR_FORCE_HOST: force to enter host mode and override OTG
113 * IDPIN signal.
114 * MTU3_DR_FORCE_DEVICE: force to enter peripheral mode.
115 */
116enum mtu3_dr_force_mode {
117 MTU3_DR_FORCE_NONE = 0,
118 MTU3_DR_FORCE_HOST,
119 MTU3_DR_FORCE_DEVICE,
120};
121
122/**
123 * @base: the base address of fifo
124 * @limit: the bitmap size in bits
125 * @bitmap: fifo bitmap in unit of @MTU3_EP_FIFO_UNIT
126 */
127struct mtu3_fifo_info {
128 u32 base;
129 u32 limit;
130 DECLARE_BITMAP(bitmap, MTU3_FIFO_BIT_SIZE);
131};
132
133/**
134 * General Purpose Descriptor (GPD):
135 * The format of TX GPD is a little different from RX one.
136 * And the size of GPD is 16 bytes.
137 *
138 * @flag:
139 * bit0: Hardware Own (HWO)
140 * bit1: Buffer Descriptor Present (BDP), always 0, BD is not supported
141 * bit2: Bypass (BPS), 1: HW skips this GPD if HWO = 1
142 * bit7: Interrupt On Completion (IOC)
143 * @chksum: This is used to validate the contents of this GPD;
144 * If TXQ_CS_EN / RXQ_CS_EN bit is set, an interrupt is issued
145 * when checksum validation fails;
146 * Checksum value is calculated over the 16 bytes of the GPD by default;
147 * @data_buf_len (RX ONLY): This value indicates the length of
148 * the assigned data buffer
149 * @tx_ext_addr (TX ONLY): [3:0] are 4 extension bits of @buffer,
150 * [7:4] are 4 extension bits of @next_gpd
151 * @next_gpd: Physical address of the next GPD
152 * @buffer: Physical address of the data buffer
153 * @buf_len:
154 * (TX): This value indicates the length of the assigned data buffer
155 * (RX): The total length of data received
156 * @ext_len: reserved
157 * @rx_ext_addr(RX ONLY): [3:0] are 4 extension bits of @buffer,
158 * [7:4] are 4 extension bits of @next_gpd
159 * @ext_flag:
160 * bit5 (TX ONLY): Zero Length Packet (ZLP),
161 */
162struct qmu_gpd {
163 __u8 flag;
164 __u8 chksum;
165 union {
166 __le16 data_buf_len;
167 __le16 tx_ext_addr;
168 };
169 __le32 next_gpd;
170 __le32 buffer;
171 __le16 buf_len;
172 union {
173 __u8 ext_len;
174 __u8 rx_ext_addr;
175 };
176 __u8 ext_flag;
177} __packed;
178
179/**
180* dma: physical base address of GPD segment
181* start: virtual base address of GPD segment
182* end: the last GPD element
183* enqueue: the first empty GPD to use
184* dequeue: the first completed GPD serviced by ISR
185* NOTE: the size of GPD ring should be >= 2
186*/
187struct mtu3_gpd_ring {
188 dma_addr_t dma;
189 struct qmu_gpd *start;
190 struct qmu_gpd *end;
191 struct qmu_gpd *enqueue;
192 struct qmu_gpd *dequeue;
193};
194
195/**
196* @vbus: vbus 5V used by host mode
197* @edev: external connector used to detect vbus and iddig changes
198* @vbus_nb: notifier for vbus detection
199* @vbus_nb: notifier for iddig(idpin) detection
200* @extcon_reg_dwork: delay work for extcon notifier register, waiting for
201* xHCI driver initialization, it's necessary for system bootup
202* as device.
203* @is_u3_drd: whether port0 supports usb3.0 dual-role device or not
204* @manual_drd_enabled: it's true when supports dual-role device by debugfs
205* to switch host/device modes depending on user input.
206*/
207struct otg_switch_mtk {
208 struct regulator *vbus;
209 struct extcon_dev *edev;
210 struct notifier_block vbus_nb;
211 struct notifier_block id_nb;
212 struct delayed_work extcon_reg_dwork;
213 bool is_u3_drd;
214 bool manual_drd_enabled;
215};
216
217/**
218 * @mac_base: register base address of device MAC, exclude xHCI's
219 * @ippc_base: register base address of IP Power and Clock interface (IPPC)
220 * @vusb33: usb3.3V shared by device/host IP
221 * @sys_clk: system clock of mtu3, shared by device/host IP
222 * @ref_clk: reference clock
223 * @mcu_clk: mcu_bus_ck clock for AHB bus etc
224 * @dma_clk: dma_bus_ck clock for AXI bus etc
225 * @dr_mode: works in which mode:
226 * host only, device only or dual-role mode
227 * @u2_ports: number of usb2.0 host ports
228 * @u3_ports: number of usb3.0 host ports
229 * @u3p_dis_msk: mask of disabling usb3 ports, for example, bit0==1 to
230 * disable u3port0, bit1==1 to disable u3port1,... etc
231 * @dbgfs_root: only used when supports manual dual-role switch via debugfs
232 * @uwk_en: it's true when supports remote wakeup in host mode
233 * @uwk: syscon including usb wakeup glue layer between SSUSB IP and SPM
234 * @uwk_reg_base: the base address of the wakeup glue layer in @uwk
235 * @uwk_vers: the version of the wakeup glue layer
236 */
237struct ssusb_mtk {
238 struct device *dev;
239 struct mtu3 *u3d;
240 void __iomem *mac_base;
241 void __iomem *ippc_base;
242 struct phy **phys;
243 int num_phys;
244 /* common power & clock */
245 struct regulator *vusb33;
246 struct clk *sys_clk;
247 struct clk *ref_clk;
248 struct clk *mcu_clk;
249 struct clk *dma_clk;
250 /* otg */
251 struct otg_switch_mtk otg_switch;
252 enum usb_dr_mode dr_mode;
253 bool is_host;
254 int u2_ports;
255 int u3_ports;
256 int u3p_dis_msk;
257 struct dentry *dbgfs_root;
258 /* usb wakeup for host mode */
259 bool uwk_en;
260 struct regmap *uwk;
261 u32 uwk_reg_base;
262 u32 uwk_vers;
263};
264
265/**
266 * @fifo_size: it is (@slot + 1) * @fifo_seg_size
267 * @fifo_seg_size: it is roundup_pow_of_two(@maxp)
268 */
269struct mtu3_ep {
270 struct usb_ep ep;
271 char name[12];
272 struct mtu3 *mtu;
273 u8 epnum;
274 u8 type;
275 u8 is_in;
276 u16 maxp;
277 int slot;
278 u32 fifo_size;
279 u32 fifo_addr;
280 u32 fifo_seg_size;
281 struct mtu3_fifo_info *fifo;
282
283 struct list_head req_list;
284 struct mtu3_gpd_ring gpd_ring;
285 const struct usb_ss_ep_comp_descriptor *comp_desc;
286 const struct usb_endpoint_descriptor *desc;
287
288 int flags;
289 u8 wedged;
290 u8 busy;
291};
292
293struct mtu3_request {
294 struct usb_request request;
295 struct list_head list;
296 struct mtu3_ep *mep;
297 struct mtu3 *mtu;
298 struct qmu_gpd *gpd;
299 int epnum;
300};
301
302static inline struct ssusb_mtk *dev_to_ssusb(struct device *dev)
303{
304 return dev_get_drvdata(dev);
305}
306
307/**
308 * struct mtu3 - device driver instance data.
309 * @slot: MTU3_U2_IP_SLOT_DEFAULT for U2 IP only,
310 * MTU3_U3_IP_SLOT_DEFAULT for U3 IP
311 * @may_wakeup: means device's remote wakeup is enabled
312 * @is_self_powered: is reported in device status and the config descriptor
313 * @delayed_status: true when function drivers ask for delayed status
314 * @ep0_req: dummy request used while handling standard USB requests
315 * for GET_STATUS and SET_SEL
316 * @setup_buf: ep0 response buffer for GET_STATUS and SET_SEL requests
317 */
318struct mtu3 {
319 spinlock_t lock;
320 struct ssusb_mtk *ssusb;
321 struct device *dev;
322 void __iomem *mac_base;
323 void __iomem *ippc_base;
324 int irq;
325
326 struct mtu3_fifo_info tx_fifo;
327 struct mtu3_fifo_info rx_fifo;
328
329 struct mtu3_ep *ep_array;
330 struct mtu3_ep *in_eps;
331 struct mtu3_ep *out_eps;
332 struct mtu3_ep *ep0;
333 int num_eps;
334 int slot;
335 int active_ep;
336
337 struct dma_pool *qmu_gpd_pool;
338 enum mtu3_g_ep0_state ep0_state;
339 struct usb_gadget g; /* the gadget */
340 struct usb_gadget_driver *gadget_driver;
341 struct mtu3_request ep0_req;
342 u8 setup_buf[EP0_RESPONSE_BUF];
343 u32 max_speed;
344
345 unsigned is_active:1;
346 unsigned may_wakeup:1;
347 unsigned is_self_powered:1;
348 unsigned test_mode:1;
349 unsigned softconnect:1;
350 unsigned u1_enable:1;
351 unsigned u2_enable:1;
352 unsigned is_u3_ip:1;
353 unsigned delayed_status:1;
354
355 u8 address;
356 u8 test_mode_nr;
357 u32 hw_version;
358};
359
360static inline struct mtu3 *gadget_to_mtu3(struct usb_gadget *g)
361{
362 return container_of(g, struct mtu3, g);
363}
364
365static inline int is_first_entry(const struct list_head *list,
366 const struct list_head *head)
367{
368 return list_is_last(head, list);
369}
370
371static inline struct mtu3_request *to_mtu3_request(struct usb_request *req)
372{
373 return req ? container_of(req, struct mtu3_request, request) : NULL;
374}
375
376static inline struct mtu3_ep *to_mtu3_ep(struct usb_ep *ep)
377{
378 return ep ? container_of(ep, struct mtu3_ep, ep) : NULL;
379}
380
381static inline struct mtu3_request *next_request(struct mtu3_ep *mep)
382{
383 return list_first_entry_or_null(&mep->req_list, struct mtu3_request,
384 list);
385}
386
387static inline void mtu3_writel(void __iomem *base, u32 offset, u32 data)
388{
389 writel(data, base + offset);
390}
391
392static inline u32 mtu3_readl(void __iomem *base, u32 offset)
393{
394 return readl(base + offset);
395}
396
397static inline void mtu3_setbits(void __iomem *base, u32 offset, u32 bits)
398{
399 void __iomem *addr = base + offset;
400 u32 tmp = readl(addr);
401
402 writel((tmp | (bits)), addr);
403}
404
405static inline void mtu3_clrbits(void __iomem *base, u32 offset, u32 bits)
406{
407 void __iomem *addr = base + offset;
408 u32 tmp = readl(addr);
409
410 writel((tmp & ~(bits)), addr);
411}
412
413int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks);
414struct usb_request *mtu3_alloc_request(struct usb_ep *ep, gfp_t gfp_flags);
415void mtu3_free_request(struct usb_ep *ep, struct usb_request *req);
416void mtu3_req_complete(struct mtu3_ep *mep,
417 struct usb_request *req, int status);
418
419int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
420 int interval, int burst, int mult);
421void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep);
422void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set);
423void mtu3_ep0_setup(struct mtu3 *mtu);
424void mtu3_start(struct mtu3 *mtu);
425void mtu3_stop(struct mtu3 *mtu);
426void mtu3_dev_on_off(struct mtu3 *mtu, int is_on);
427
428int mtu3_gadget_setup(struct mtu3 *mtu);
429void mtu3_gadget_cleanup(struct mtu3 *mtu);
430void mtu3_gadget_reset(struct mtu3 *mtu);
431void mtu3_gadget_suspend(struct mtu3 *mtu);
432void mtu3_gadget_resume(struct mtu3 *mtu);
433void mtu3_gadget_disconnect(struct mtu3 *mtu);
434
435irqreturn_t mtu3_ep0_isr(struct mtu3 *mtu);
436extern const struct usb_ep_ops mtu3_ep0_ops;
437
438#endif