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1/*
2 * ipr.h -- driver for IBM Power Linux RAID adapters
3 *
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5 *
6 * Copyright (C) 2003, 2004 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
24 */
25
26#ifndef _IPR_H
27#define _IPR_H
28
29#include <asm/unaligned.h>
30#include <linux/types.h>
31#include <linux/completion.h>
32#include <linux/libata.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <scsi/scsi.h>
36#include <scsi/scsi_cmnd.h>
37
38/*
39 * Literals
40 */
41#define IPR_DRIVER_VERSION "2.5.2"
42#define IPR_DRIVER_DATE "(April 27, 2011)"
43
44/*
45 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
46 * ops per device for devices not running tagged command queuing.
47 * This can be adjusted at runtime through sysfs device attributes.
48 */
49#define IPR_MAX_CMD_PER_LUN 6
50#define IPR_MAX_CMD_PER_ATA_LUN 1
51
52/*
53 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
54 * ops the mid-layer can send to the adapter.
55 */
56#define IPR_NUM_BASE_CMD_BLKS 100
57
58#define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
59
60#define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
61#define PCI_DEVICE_ID_IBM_CROC_ASIC_E2 0x034A
62
63#define IPR_SUBS_DEV_ID_2780 0x0264
64#define IPR_SUBS_DEV_ID_5702 0x0266
65#define IPR_SUBS_DEV_ID_5703 0x0278
66#define IPR_SUBS_DEV_ID_572E 0x028D
67#define IPR_SUBS_DEV_ID_573E 0x02D3
68#define IPR_SUBS_DEV_ID_573D 0x02D4
69#define IPR_SUBS_DEV_ID_571A 0x02C0
70#define IPR_SUBS_DEV_ID_571B 0x02BE
71#define IPR_SUBS_DEV_ID_571E 0x02BF
72#define IPR_SUBS_DEV_ID_571F 0x02D5
73#define IPR_SUBS_DEV_ID_572A 0x02C1
74#define IPR_SUBS_DEV_ID_572B 0x02C2
75#define IPR_SUBS_DEV_ID_572F 0x02C3
76#define IPR_SUBS_DEV_ID_574E 0x030A
77#define IPR_SUBS_DEV_ID_575B 0x030D
78#define IPR_SUBS_DEV_ID_575C 0x0338
79#define IPR_SUBS_DEV_ID_57B3 0x033A
80#define IPR_SUBS_DEV_ID_57B7 0x0360
81#define IPR_SUBS_DEV_ID_57B8 0x02C2
82
83#define IPR_SUBS_DEV_ID_57B4 0x033B
84#define IPR_SUBS_DEV_ID_57B2 0x035F
85#define IPR_SUBS_DEV_ID_57C4 0x0354
86#define IPR_SUBS_DEV_ID_57C6 0x0357
87#define IPR_SUBS_DEV_ID_57CC 0x035C
88
89#define IPR_SUBS_DEV_ID_57B5 0x033C
90#define IPR_SUBS_DEV_ID_57CE 0x035E
91#define IPR_SUBS_DEV_ID_57B1 0x0355
92
93#define IPR_SUBS_DEV_ID_574D 0x0356
94#define IPR_SUBS_DEV_ID_575D 0x035D
95
96#define IPR_NAME "ipr"
97
98/*
99 * Return codes
100 */
101#define IPR_RC_JOB_CONTINUE 1
102#define IPR_RC_JOB_RETURN 2
103
104/*
105 * IOASCs
106 */
107#define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
108#define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
109#define IPR_IOASC_SYNC_REQUIRED 0x023f0000
110#define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
111#define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
112#define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
113#define IPR_IOASC_IOASC_MASK 0xFFFFFF00
114#define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
115#define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
116#define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
117#define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
118#define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
119#define IPR_IOASC_BUS_WAS_RESET 0x06290000
120#define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
121#define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
122
123#define IPR_FIRST_DRIVER_IOASC 0x10000000
124#define IPR_IOASC_IOA_WAS_RESET 0x10000001
125#define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
126
127/* Driver data flags */
128#define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
129#define IPR_USE_PCI_WARM_RESET 0x00000002
130
131#define IPR_DEFAULT_MAX_ERROR_DUMP 984
132#define IPR_NUM_LOG_HCAMS 2
133#define IPR_NUM_CFG_CHG_HCAMS 2
134#define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
135
136#define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
137#define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
138
139#define IPR_MAX_NUM_TARGETS_PER_BUS 256
140#define IPR_MAX_NUM_LUNS_PER_TARGET 256
141#define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
142#define IPR_VSET_BUS 0xff
143#define IPR_IOA_BUS 0xff
144#define IPR_IOA_TARGET 0xff
145#define IPR_IOA_LUN 0xff
146#define IPR_MAX_NUM_BUSES 16
147#define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
148
149#define IPR_NUM_RESET_RELOAD_RETRIES 3
150
151/* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
152#define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
153 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
154
155#define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
156#define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
157 IPR_NUM_INTERNAL_CMD_BLKS)
158
159#define IPR_MAX_PHYSICAL_DEVS 192
160#define IPR_DEFAULT_SIS64_DEVS 1024
161#define IPR_MAX_SIS64_DEVS 4096
162
163#define IPR_MAX_SGLIST 64
164#define IPR_IOA_MAX_SECTORS 32767
165#define IPR_VSET_MAX_SECTORS 512
166#define IPR_MAX_CDB_LEN 16
167#define IPR_MAX_HRRQ_RETRIES 3
168
169#define IPR_DEFAULT_BUS_WIDTH 16
170#define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
171#define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
172#define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
173#define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
174
175#define IPR_IOA_RES_HANDLE 0xffffffff
176#define IPR_INVALID_RES_HANDLE 0
177#define IPR_IOA_RES_ADDR 0x00ffffff
178
179/*
180 * Adapter Commands
181 */
182#define IPR_QUERY_RSRC_STATE 0xC2
183#define IPR_RESET_DEVICE 0xC3
184#define IPR_RESET_TYPE_SELECT 0x80
185#define IPR_LUN_RESET 0x40
186#define IPR_TARGET_RESET 0x20
187#define IPR_BUS_RESET 0x10
188#define IPR_ATA_PHY_RESET 0x80
189#define IPR_ID_HOST_RR_Q 0xC4
190#define IPR_QUERY_IOA_CONFIG 0xC5
191#define IPR_CANCEL_ALL_REQUESTS 0xCE
192#define IPR_HOST_CONTROLLED_ASYNC 0xCF
193#define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
194#define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
195#define IPR_SET_SUPPORTED_DEVICES 0xFB
196#define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
197#define IPR_IOA_SHUTDOWN 0xF7
198#define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
199
200/*
201 * Timeouts
202 */
203#define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
204#define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
205#define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
206#define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
207#define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
208#define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
209#define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
210#define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
211#define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
212#define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
213#define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
214#define IPR_OPERATIONAL_TIMEOUT (5 * 60)
215#define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
216#define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
217#define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
218#define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
219#define IPR_PCI_RESET_TIMEOUT (HZ / 2)
220#define IPR_SIS32_DUMP_TIMEOUT (15 * HZ)
221#define IPR_SIS64_DUMP_TIMEOUT (40 * HZ)
222#define IPR_DUMP_DELAY_SECONDS 4
223#define IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ)
224
225/*
226 * SCSI Literals
227 */
228#define IPR_VENDOR_ID_LEN 8
229#define IPR_PROD_ID_LEN 16
230#define IPR_SERIAL_NUM_LEN 8
231
232/*
233 * Hardware literals
234 */
235#define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
236#define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
237#define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
238#define IPR_GET_FMT2_BAR_SEL(mbx) \
239(((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
240#define IPR_SDT_FMT2_BAR0_SEL 0x0
241#define IPR_SDT_FMT2_BAR1_SEL 0x1
242#define IPR_SDT_FMT2_BAR2_SEL 0x2
243#define IPR_SDT_FMT2_BAR3_SEL 0x3
244#define IPR_SDT_FMT2_BAR4_SEL 0x4
245#define IPR_SDT_FMT2_BAR5_SEL 0x5
246#define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
247#define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
248#define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
249#define IPR_DOORBELL 0x82800000
250#define IPR_RUNTIME_RESET 0x40000000
251
252#define IPR_IPL_INIT_MIN_STAGE_TIME 5
253#define IPR_IPL_INIT_DEFAULT_STAGE_TIME 15
254#define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
255#define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
256#define IPR_IPL_INIT_STAGE_MASK 0xff000000
257#define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
258#define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
259
260#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
261#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
262#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
263#define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
264#define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
265#define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
266#define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
267#define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
268#define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
269#define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
270#define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
271
272#define IPR_PCII_ERROR_INTERRUPTS \
273(IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
274IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
275
276#define IPR_PCII_OPER_INTERRUPTS \
277(IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
278
279#define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
280#define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
281#define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23)
282
283#define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
284#define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
285
286/*
287 * Dump literals
288 */
289#define IPR_FMT2_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
290#define IPR_FMT3_MAX_IOA_DUMP_SIZE (32 * 1024 * 1024)
291#define IPR_FMT2_NUM_SDT_ENTRIES 511
292#define IPR_FMT3_NUM_SDT_ENTRIES 0xFFF
293#define IPR_FMT2_MAX_NUM_DUMP_PAGES ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
294#define IPR_FMT3_MAX_NUM_DUMP_PAGES ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
295
296/*
297 * Misc literals
298 */
299#define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
300
301/*
302 * Adapter interface types
303 */
304
305struct ipr_res_addr {
306 u8 reserved;
307 u8 bus;
308 u8 target;
309 u8 lun;
310#define IPR_GET_PHYS_LOC(res_addr) \
311 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
312}__attribute__((packed, aligned (4)));
313
314struct ipr_std_inq_vpids {
315 u8 vendor_id[IPR_VENDOR_ID_LEN];
316 u8 product_id[IPR_PROD_ID_LEN];
317}__attribute__((packed));
318
319struct ipr_vpd {
320 struct ipr_std_inq_vpids vpids;
321 u8 sn[IPR_SERIAL_NUM_LEN];
322}__attribute__((packed));
323
324struct ipr_ext_vpd {
325 struct ipr_vpd vpd;
326 __be32 wwid[2];
327}__attribute__((packed));
328
329struct ipr_ext_vpd64 {
330 struct ipr_vpd vpd;
331 __be32 wwid[4];
332}__attribute__((packed));
333
334struct ipr_std_inq_data {
335 u8 peri_qual_dev_type;
336#define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
337#define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
338
339 u8 removeable_medium_rsvd;
340#define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
341
342#define IPR_IS_DASD_DEVICE(std_inq) \
343((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
344!(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
345
346#define IPR_IS_SES_DEVICE(std_inq) \
347(IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
348
349 u8 version;
350 u8 aen_naca_fmt;
351 u8 additional_len;
352 u8 sccs_rsvd;
353 u8 bq_enc_multi;
354 u8 sync_cmdq_flags;
355
356 struct ipr_std_inq_vpids vpids;
357
358 u8 ros_rsvd_ram_rsvd[4];
359
360 u8 serial_num[IPR_SERIAL_NUM_LEN];
361}__attribute__ ((packed));
362
363#define IPR_RES_TYPE_AF_DASD 0x00
364#define IPR_RES_TYPE_GENERIC_SCSI 0x01
365#define IPR_RES_TYPE_VOLUME_SET 0x02
366#define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
367#define IPR_RES_TYPE_GENERIC_ATA 0x04
368#define IPR_RES_TYPE_ARRAY 0x05
369#define IPR_RES_TYPE_IOAFP 0xff
370
371struct ipr_config_table_entry {
372 u8 proto;
373#define IPR_PROTO_SATA 0x02
374#define IPR_PROTO_SATA_ATAPI 0x03
375#define IPR_PROTO_SAS_STP 0x06
376#define IPR_PROTO_SAS_STP_ATAPI 0x07
377 u8 array_id;
378 u8 flags;
379#define IPR_IS_IOA_RESOURCE 0x80
380 u8 rsvd_subtype;
381
382#define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
383#define IPR_QUEUE_FROZEN_MODEL 0
384#define IPR_QUEUE_NACA_MODEL 1
385
386 struct ipr_res_addr res_addr;
387 __be32 res_handle;
388 __be32 lun_wwn[2];
389 struct ipr_std_inq_data std_inq_data;
390}__attribute__ ((packed, aligned (4)));
391
392struct ipr_config_table_entry64 {
393 u8 res_type;
394 u8 proto;
395 u8 vset_num;
396 u8 array_id;
397 __be16 flags;
398 __be16 res_flags;
399#define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
400 __be32 res_handle;
401 u8 dev_id_type;
402 u8 reserved[3];
403 __be64 dev_id;
404 __be64 lun;
405 __be64 lun_wwn[2];
406#define IPR_MAX_RES_PATH_LENGTH 24
407 __be64 res_path;
408 struct ipr_std_inq_data std_inq_data;
409 u8 reserved2[4];
410 __be64 reserved3[2];
411 u8 reserved4[8];
412}__attribute__ ((packed, aligned (8)));
413
414struct ipr_config_table_hdr {
415 u8 num_entries;
416 u8 flags;
417#define IPR_UCODE_DOWNLOAD_REQ 0x10
418 __be16 reserved;
419}__attribute__((packed, aligned (4)));
420
421struct ipr_config_table_hdr64 {
422 __be16 num_entries;
423 __be16 reserved;
424 u8 flags;
425 u8 reserved2[11];
426}__attribute__((packed, aligned (4)));
427
428struct ipr_config_table {
429 struct ipr_config_table_hdr hdr;
430 struct ipr_config_table_entry dev[0];
431}__attribute__((packed, aligned (4)));
432
433struct ipr_config_table64 {
434 struct ipr_config_table_hdr64 hdr64;
435 struct ipr_config_table_entry64 dev[0];
436}__attribute__((packed, aligned (8)));
437
438struct ipr_config_table_entry_wrapper {
439 union {
440 struct ipr_config_table_entry *cfgte;
441 struct ipr_config_table_entry64 *cfgte64;
442 } u;
443};
444
445struct ipr_hostrcb_cfg_ch_not {
446 union {
447 struct ipr_config_table_entry cfgte;
448 struct ipr_config_table_entry64 cfgte64;
449 } u;
450 u8 reserved[936];
451}__attribute__((packed, aligned (4)));
452
453struct ipr_supported_device {
454 __be16 data_length;
455 u8 reserved;
456 u8 num_records;
457 struct ipr_std_inq_vpids vpids;
458 u8 reserved2[16];
459}__attribute__((packed, aligned (4)));
460
461/* Command packet structure */
462struct ipr_cmd_pkt {
463 __be16 reserved; /* Reserved by IOA */
464 u8 request_type;
465#define IPR_RQTYPE_SCSICDB 0x00
466#define IPR_RQTYPE_IOACMD 0x01
467#define IPR_RQTYPE_HCAM 0x02
468#define IPR_RQTYPE_ATA_PASSTHRU 0x04
469
470 u8 reserved2;
471
472 u8 flags_hi;
473#define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
474#define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
475#define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
476#define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
477#define IPR_FLAGS_HI_NO_LINK_DESC 0x04
478
479 u8 flags_lo;
480#define IPR_FLAGS_LO_ALIGNED_BFR 0x20
481#define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
482#define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
483#define IPR_FLAGS_LO_SIMPLE_TASK 0x02
484#define IPR_FLAGS_LO_ORDERED_TASK 0x04
485#define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
486#define IPR_FLAGS_LO_ACA_TASK 0x08
487
488 u8 cdb[16];
489 __be16 timeout;
490}__attribute__ ((packed, aligned(4)));
491
492struct ipr_ioarcb_ata_regs { /* 22 bytes */
493 u8 flags;
494#define IPR_ATA_FLAG_PACKET_CMD 0x80
495#define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
496#define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
497 u8 reserved[3];
498
499 __be16 data;
500 u8 feature;
501 u8 nsect;
502 u8 lbal;
503 u8 lbam;
504 u8 lbah;
505 u8 device;
506 u8 command;
507 u8 reserved2[3];
508 u8 hob_feature;
509 u8 hob_nsect;
510 u8 hob_lbal;
511 u8 hob_lbam;
512 u8 hob_lbah;
513 u8 ctl;
514}__attribute__ ((packed, aligned(4)));
515
516struct ipr_ioadl_desc {
517 __be32 flags_and_data_len;
518#define IPR_IOADL_FLAGS_MASK 0xff000000
519#define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
520#define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
521#define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
522#define IPR_IOADL_FLAGS_READ 0x48000000
523#define IPR_IOADL_FLAGS_READ_LAST 0x49000000
524#define IPR_IOADL_FLAGS_WRITE 0x68000000
525#define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
526#define IPR_IOADL_FLAGS_LAST 0x01000000
527
528 __be32 address;
529}__attribute__((packed, aligned (8)));
530
531struct ipr_ioadl64_desc {
532 __be32 flags;
533 __be32 data_len;
534 __be64 address;
535}__attribute__((packed, aligned (16)));
536
537struct ipr_ata64_ioadl {
538 struct ipr_ioarcb_ata_regs regs;
539 u16 reserved[5];
540 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
541}__attribute__((packed, aligned (16)));
542
543struct ipr_ioarcb_add_data {
544 union {
545 struct ipr_ioarcb_ata_regs regs;
546 struct ipr_ioadl_desc ioadl[5];
547 __be32 add_cmd_parms[10];
548 } u;
549}__attribute__ ((packed, aligned (4)));
550
551struct ipr_ioarcb_sis64_add_addr_ecb {
552 __be64 ioasa_host_pci_addr;
553 __be64 data_ioadl_addr;
554 __be64 reserved;
555 __be32 ext_control_buf[4];
556}__attribute__((packed, aligned (8)));
557
558/* IOA Request Control Block 128 bytes */
559struct ipr_ioarcb {
560 union {
561 __be32 ioarcb_host_pci_addr;
562 __be64 ioarcb_host_pci_addr64;
563 } a;
564 __be32 res_handle;
565 __be32 host_response_handle;
566 __be32 reserved1;
567 __be32 reserved2;
568 __be32 reserved3;
569
570 __be32 data_transfer_length;
571 __be32 read_data_transfer_length;
572 __be32 write_ioadl_addr;
573 __be32 ioadl_len;
574 __be32 read_ioadl_addr;
575 __be32 read_ioadl_len;
576
577 __be32 ioasa_host_pci_addr;
578 __be16 ioasa_len;
579 __be16 reserved4;
580
581 struct ipr_cmd_pkt cmd_pkt;
582
583 __be16 add_cmd_parms_offset;
584 __be16 add_cmd_parms_len;
585
586 union {
587 struct ipr_ioarcb_add_data add_data;
588 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
589 } u;
590
591}__attribute__((packed, aligned (4)));
592
593struct ipr_ioasa_vset {
594 __be32 failing_lba_hi;
595 __be32 failing_lba_lo;
596 __be32 reserved;
597}__attribute__((packed, aligned (4)));
598
599struct ipr_ioasa_af_dasd {
600 __be32 failing_lba;
601 __be32 reserved[2];
602}__attribute__((packed, aligned (4)));
603
604struct ipr_ioasa_gpdd {
605 u8 end_state;
606 u8 bus_phase;
607 __be16 reserved;
608 __be32 ioa_data[2];
609}__attribute__((packed, aligned (4)));
610
611struct ipr_ioasa_gata {
612 u8 error;
613 u8 nsect; /* Interrupt reason */
614 u8 lbal;
615 u8 lbam;
616 u8 lbah;
617 u8 device;
618 u8 status;
619 u8 alt_status; /* ATA CTL */
620 u8 hob_nsect;
621 u8 hob_lbal;
622 u8 hob_lbam;
623 u8 hob_lbah;
624}__attribute__((packed, aligned (4)));
625
626struct ipr_auto_sense {
627 __be16 auto_sense_len;
628 __be16 ioa_data_len;
629 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
630};
631
632struct ipr_ioasa_hdr {
633 __be32 ioasc;
634#define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
635#define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
636#define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
637#define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
638
639 __be16 ret_stat_len; /* Length of the returned IOASA */
640
641 __be16 avail_stat_len; /* Total Length of status available. */
642
643 __be32 residual_data_len; /* number of bytes in the host data */
644 /* buffers that were not used by the IOARCB command. */
645
646 __be32 ilid;
647#define IPR_NO_ILID 0
648#define IPR_DRIVER_ILID 0xffffffff
649
650 __be32 fd_ioasc;
651
652 __be32 fd_phys_locator;
653
654 __be32 fd_res_handle;
655
656 __be32 ioasc_specific; /* status code specific field */
657#define IPR_ADDITIONAL_STATUS_FMT 0x80000000
658#define IPR_AUTOSENSE_VALID 0x40000000
659#define IPR_ATA_DEVICE_WAS_RESET 0x20000000
660#define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
661#define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
662#define IPR_FIELD_POINTER_MASK 0x0000ffff
663
664}__attribute__((packed, aligned (4)));
665
666struct ipr_ioasa {
667 struct ipr_ioasa_hdr hdr;
668
669 union {
670 struct ipr_ioasa_vset vset;
671 struct ipr_ioasa_af_dasd dasd;
672 struct ipr_ioasa_gpdd gpdd;
673 struct ipr_ioasa_gata gata;
674 } u;
675
676 struct ipr_auto_sense auto_sense;
677}__attribute__((packed, aligned (4)));
678
679struct ipr_ioasa64 {
680 struct ipr_ioasa_hdr hdr;
681 u8 fd_res_path[8];
682
683 union {
684 struct ipr_ioasa_vset vset;
685 struct ipr_ioasa_af_dasd dasd;
686 struct ipr_ioasa_gpdd gpdd;
687 struct ipr_ioasa_gata gata;
688 } u;
689
690 struct ipr_auto_sense auto_sense;
691}__attribute__((packed, aligned (4)));
692
693struct ipr_mode_parm_hdr {
694 u8 length;
695 u8 medium_type;
696 u8 device_spec_parms;
697 u8 block_desc_len;
698}__attribute__((packed));
699
700struct ipr_mode_pages {
701 struct ipr_mode_parm_hdr hdr;
702 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
703}__attribute__((packed));
704
705struct ipr_mode_page_hdr {
706 u8 ps_page_code;
707#define IPR_MODE_PAGE_PS 0x80
708#define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
709 u8 page_length;
710}__attribute__ ((packed));
711
712struct ipr_dev_bus_entry {
713 struct ipr_res_addr res_addr;
714 u8 flags;
715#define IPR_SCSI_ATTR_ENABLE_QAS 0x80
716#define IPR_SCSI_ATTR_DISABLE_QAS 0x40
717#define IPR_SCSI_ATTR_QAS_MASK 0xC0
718#define IPR_SCSI_ATTR_ENABLE_TM 0x20
719#define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
720#define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
721#define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
722
723 u8 scsi_id;
724 u8 bus_width;
725 u8 extended_reset_delay;
726#define IPR_EXTENDED_RESET_DELAY 7
727
728 __be32 max_xfer_rate;
729
730 u8 spinup_delay;
731 u8 reserved3;
732 __be16 reserved4;
733}__attribute__((packed, aligned (4)));
734
735struct ipr_mode_page28 {
736 struct ipr_mode_page_hdr hdr;
737 u8 num_entries;
738 u8 entry_length;
739 struct ipr_dev_bus_entry bus[0];
740}__attribute__((packed));
741
742struct ipr_mode_page24 {
743 struct ipr_mode_page_hdr hdr;
744 u8 flags;
745#define IPR_ENABLE_DUAL_IOA_AF 0x80
746}__attribute__((packed));
747
748struct ipr_ioa_vpd {
749 struct ipr_std_inq_data std_inq_data;
750 u8 ascii_part_num[12];
751 u8 reserved[40];
752 u8 ascii_plant_code[4];
753}__attribute__((packed));
754
755struct ipr_inquiry_page3 {
756 u8 peri_qual_dev_type;
757 u8 page_code;
758 u8 reserved1;
759 u8 page_length;
760 u8 ascii_len;
761 u8 reserved2[3];
762 u8 load_id[4];
763 u8 major_release;
764 u8 card_type;
765 u8 minor_release[2];
766 u8 ptf_number[4];
767 u8 patch_number[4];
768}__attribute__((packed));
769
770struct ipr_inquiry_cap {
771 u8 peri_qual_dev_type;
772 u8 page_code;
773 u8 reserved1;
774 u8 page_length;
775 u8 ascii_len;
776 u8 reserved2;
777 u8 sis_version[2];
778 u8 cap;
779#define IPR_CAP_DUAL_IOA_RAID 0x80
780 u8 reserved3[15];
781}__attribute__((packed));
782
783#define IPR_INQUIRY_PAGE0_ENTRIES 20
784struct ipr_inquiry_page0 {
785 u8 peri_qual_dev_type;
786 u8 page_code;
787 u8 reserved1;
788 u8 len;
789 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
790}__attribute__((packed));
791
792struct ipr_hostrcb_device_data_entry {
793 struct ipr_vpd vpd;
794 struct ipr_res_addr dev_res_addr;
795 struct ipr_vpd new_vpd;
796 struct ipr_vpd ioa_last_with_dev_vpd;
797 struct ipr_vpd cfc_last_with_dev_vpd;
798 __be32 ioa_data[5];
799}__attribute__((packed, aligned (4)));
800
801struct ipr_hostrcb_device_data_entry_enhanced {
802 struct ipr_ext_vpd vpd;
803 u8 ccin[4];
804 struct ipr_res_addr dev_res_addr;
805 struct ipr_ext_vpd new_vpd;
806 u8 new_ccin[4];
807 struct ipr_ext_vpd ioa_last_with_dev_vpd;
808 struct ipr_ext_vpd cfc_last_with_dev_vpd;
809}__attribute__((packed, aligned (4)));
810
811struct ipr_hostrcb64_device_data_entry_enhanced {
812 struct ipr_ext_vpd vpd;
813 u8 ccin[4];
814 u8 res_path[8];
815 struct ipr_ext_vpd new_vpd;
816 u8 new_ccin[4];
817 struct ipr_ext_vpd ioa_last_with_dev_vpd;
818 struct ipr_ext_vpd cfc_last_with_dev_vpd;
819}__attribute__((packed, aligned (4)));
820
821struct ipr_hostrcb_array_data_entry {
822 struct ipr_vpd vpd;
823 struct ipr_res_addr expected_dev_res_addr;
824 struct ipr_res_addr dev_res_addr;
825}__attribute__((packed, aligned (4)));
826
827struct ipr_hostrcb64_array_data_entry {
828 struct ipr_ext_vpd vpd;
829 u8 ccin[4];
830 u8 expected_res_path[8];
831 u8 res_path[8];
832}__attribute__((packed, aligned (4)));
833
834struct ipr_hostrcb_array_data_entry_enhanced {
835 struct ipr_ext_vpd vpd;
836 u8 ccin[4];
837 struct ipr_res_addr expected_dev_res_addr;
838 struct ipr_res_addr dev_res_addr;
839}__attribute__((packed, aligned (4)));
840
841struct ipr_hostrcb_type_ff_error {
842 __be32 ioa_data[758];
843}__attribute__((packed, aligned (4)));
844
845struct ipr_hostrcb_type_01_error {
846 __be32 seek_counter;
847 __be32 read_counter;
848 u8 sense_data[32];
849 __be32 ioa_data[236];
850}__attribute__((packed, aligned (4)));
851
852struct ipr_hostrcb_type_02_error {
853 struct ipr_vpd ioa_vpd;
854 struct ipr_vpd cfc_vpd;
855 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
856 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
857 __be32 ioa_data[3];
858}__attribute__((packed, aligned (4)));
859
860struct ipr_hostrcb_type_12_error {
861 struct ipr_ext_vpd ioa_vpd;
862 struct ipr_ext_vpd cfc_vpd;
863 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
864 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
865 __be32 ioa_data[3];
866}__attribute__((packed, aligned (4)));
867
868struct ipr_hostrcb_type_03_error {
869 struct ipr_vpd ioa_vpd;
870 struct ipr_vpd cfc_vpd;
871 __be32 errors_detected;
872 __be32 errors_logged;
873 u8 ioa_data[12];
874 struct ipr_hostrcb_device_data_entry dev[3];
875}__attribute__((packed, aligned (4)));
876
877struct ipr_hostrcb_type_13_error {
878 struct ipr_ext_vpd ioa_vpd;
879 struct ipr_ext_vpd cfc_vpd;
880 __be32 errors_detected;
881 __be32 errors_logged;
882 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
883}__attribute__((packed, aligned (4)));
884
885struct ipr_hostrcb_type_23_error {
886 struct ipr_ext_vpd ioa_vpd;
887 struct ipr_ext_vpd cfc_vpd;
888 __be32 errors_detected;
889 __be32 errors_logged;
890 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
891}__attribute__((packed, aligned (4)));
892
893struct ipr_hostrcb_type_04_error {
894 struct ipr_vpd ioa_vpd;
895 struct ipr_vpd cfc_vpd;
896 u8 ioa_data[12];
897 struct ipr_hostrcb_array_data_entry array_member[10];
898 __be32 exposed_mode_adn;
899 __be32 array_id;
900 struct ipr_vpd incomp_dev_vpd;
901 __be32 ioa_data2;
902 struct ipr_hostrcb_array_data_entry array_member2[8];
903 struct ipr_res_addr last_func_vset_res_addr;
904 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
905 u8 protection_level[8];
906}__attribute__((packed, aligned (4)));
907
908struct ipr_hostrcb_type_14_error {
909 struct ipr_ext_vpd ioa_vpd;
910 struct ipr_ext_vpd cfc_vpd;
911 __be32 exposed_mode_adn;
912 __be32 array_id;
913 struct ipr_res_addr last_func_vset_res_addr;
914 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
915 u8 protection_level[8];
916 __be32 num_entries;
917 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
918}__attribute__((packed, aligned (4)));
919
920struct ipr_hostrcb_type_24_error {
921 struct ipr_ext_vpd ioa_vpd;
922 struct ipr_ext_vpd cfc_vpd;
923 u8 reserved[2];
924 u8 exposed_mode_adn;
925#define IPR_INVALID_ARRAY_DEV_NUM 0xff
926 u8 array_id;
927 u8 last_res_path[8];
928 u8 protection_level[8];
929 struct ipr_ext_vpd64 array_vpd;
930 u8 description[16];
931 u8 reserved2[3];
932 u8 num_entries;
933 struct ipr_hostrcb64_array_data_entry array_member[32];
934}__attribute__((packed, aligned (4)));
935
936struct ipr_hostrcb_type_07_error {
937 u8 failure_reason[64];
938 struct ipr_vpd vpd;
939 u32 data[222];
940}__attribute__((packed, aligned (4)));
941
942struct ipr_hostrcb_type_17_error {
943 u8 failure_reason[64];
944 struct ipr_ext_vpd vpd;
945 u32 data[476];
946}__attribute__((packed, aligned (4)));
947
948struct ipr_hostrcb_config_element {
949 u8 type_status;
950#define IPR_PATH_CFG_TYPE_MASK 0xF0
951#define IPR_PATH_CFG_NOT_EXIST 0x00
952#define IPR_PATH_CFG_IOA_PORT 0x10
953#define IPR_PATH_CFG_EXP_PORT 0x20
954#define IPR_PATH_CFG_DEVICE_PORT 0x30
955#define IPR_PATH_CFG_DEVICE_LUN 0x40
956
957#define IPR_PATH_CFG_STATUS_MASK 0x0F
958#define IPR_PATH_CFG_NO_PROB 0x00
959#define IPR_PATH_CFG_DEGRADED 0x01
960#define IPR_PATH_CFG_FAILED 0x02
961#define IPR_PATH_CFG_SUSPECT 0x03
962#define IPR_PATH_NOT_DETECTED 0x04
963#define IPR_PATH_INCORRECT_CONN 0x05
964
965 u8 cascaded_expander;
966 u8 phy;
967 u8 link_rate;
968#define IPR_PHY_LINK_RATE_MASK 0x0F
969
970 __be32 wwid[2];
971}__attribute__((packed, aligned (4)));
972
973struct ipr_hostrcb64_config_element {
974 __be16 length;
975 u8 descriptor_id;
976#define IPR_DESCRIPTOR_MASK 0xC0
977#define IPR_DESCRIPTOR_SIS64 0x00
978
979 u8 reserved;
980 u8 type_status;
981
982 u8 reserved2[2];
983 u8 link_rate;
984
985 u8 res_path[8];
986 __be32 wwid[2];
987}__attribute__((packed, aligned (8)));
988
989struct ipr_hostrcb_fabric_desc {
990 __be16 length;
991 u8 ioa_port;
992 u8 cascaded_expander;
993 u8 phy;
994 u8 path_state;
995#define IPR_PATH_ACTIVE_MASK 0xC0
996#define IPR_PATH_NO_INFO 0x00
997#define IPR_PATH_ACTIVE 0x40
998#define IPR_PATH_NOT_ACTIVE 0x80
999
1000#define IPR_PATH_STATE_MASK 0x0F
1001#define IPR_PATH_STATE_NO_INFO 0x00
1002#define IPR_PATH_HEALTHY 0x01
1003#define IPR_PATH_DEGRADED 0x02
1004#define IPR_PATH_FAILED 0x03
1005
1006 __be16 num_entries;
1007 struct ipr_hostrcb_config_element elem[1];
1008}__attribute__((packed, aligned (4)));
1009
1010struct ipr_hostrcb64_fabric_desc {
1011 __be16 length;
1012 u8 descriptor_id;
1013
1014 u8 reserved[2];
1015 u8 path_state;
1016
1017 u8 reserved2[2];
1018 u8 res_path[8];
1019 u8 reserved3[6];
1020 __be16 num_entries;
1021 struct ipr_hostrcb64_config_element elem[1];
1022}__attribute__((packed, aligned (8)));
1023
1024#define for_each_fabric_cfg(fabric, cfg) \
1025 for (cfg = (fabric)->elem; \
1026 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1027 cfg++)
1028
1029struct ipr_hostrcb_type_20_error {
1030 u8 failure_reason[64];
1031 u8 reserved[3];
1032 u8 num_entries;
1033 struct ipr_hostrcb_fabric_desc desc[1];
1034}__attribute__((packed, aligned (4)));
1035
1036struct ipr_hostrcb_type_30_error {
1037 u8 failure_reason[64];
1038 u8 reserved[3];
1039 u8 num_entries;
1040 struct ipr_hostrcb64_fabric_desc desc[1];
1041}__attribute__((packed, aligned (4)));
1042
1043struct ipr_hostrcb_error {
1044 __be32 fd_ioasc;
1045 struct ipr_res_addr fd_res_addr;
1046 __be32 fd_res_handle;
1047 __be32 prc;
1048 union {
1049 struct ipr_hostrcb_type_ff_error type_ff_error;
1050 struct ipr_hostrcb_type_01_error type_01_error;
1051 struct ipr_hostrcb_type_02_error type_02_error;
1052 struct ipr_hostrcb_type_03_error type_03_error;
1053 struct ipr_hostrcb_type_04_error type_04_error;
1054 struct ipr_hostrcb_type_07_error type_07_error;
1055 struct ipr_hostrcb_type_12_error type_12_error;
1056 struct ipr_hostrcb_type_13_error type_13_error;
1057 struct ipr_hostrcb_type_14_error type_14_error;
1058 struct ipr_hostrcb_type_17_error type_17_error;
1059 struct ipr_hostrcb_type_20_error type_20_error;
1060 } u;
1061}__attribute__((packed, aligned (4)));
1062
1063struct ipr_hostrcb64_error {
1064 __be32 fd_ioasc;
1065 __be32 ioa_fw_level;
1066 __be32 fd_res_handle;
1067 __be32 prc;
1068 __be64 fd_dev_id;
1069 __be64 fd_lun;
1070 u8 fd_res_path[8];
1071 __be64 time_stamp;
1072 u8 reserved[16];
1073 union {
1074 struct ipr_hostrcb_type_ff_error type_ff_error;
1075 struct ipr_hostrcb_type_12_error type_12_error;
1076 struct ipr_hostrcb_type_17_error type_17_error;
1077 struct ipr_hostrcb_type_23_error type_23_error;
1078 struct ipr_hostrcb_type_24_error type_24_error;
1079 struct ipr_hostrcb_type_30_error type_30_error;
1080 } u;
1081}__attribute__((packed, aligned (8)));
1082
1083struct ipr_hostrcb_raw {
1084 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1085}__attribute__((packed, aligned (4)));
1086
1087struct ipr_hcam {
1088 u8 op_code;
1089#define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1090#define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1091
1092 u8 notify_type;
1093#define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1094#define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1095#define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1096#define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1097#define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1098
1099 u8 notifications_lost;
1100#define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1101#define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1102
1103 u8 flags;
1104#define IPR_HOSTRCB_INTERNAL_OPER 0x80
1105#define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1106
1107 u8 overlay_id;
1108#define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1109#define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1110#define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1111#define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1112#define IPR_HOST_RCB_OVERLAY_ID_6 0x06
1113#define IPR_HOST_RCB_OVERLAY_ID_7 0x07
1114#define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1115#define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1116#define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1117#define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1118#define IPR_HOST_RCB_OVERLAY_ID_17 0x17
1119#define IPR_HOST_RCB_OVERLAY_ID_20 0x20
1120#define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1121#define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1122#define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1123#define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1124#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1125
1126 u8 reserved1[3];
1127 __be32 ilid;
1128 __be32 time_since_last_ioa_reset;
1129 __be32 reserved2;
1130 __be32 length;
1131
1132 union {
1133 struct ipr_hostrcb_error error;
1134 struct ipr_hostrcb64_error error64;
1135 struct ipr_hostrcb_cfg_ch_not ccn;
1136 struct ipr_hostrcb_raw raw;
1137 } u;
1138}__attribute__((packed, aligned (4)));
1139
1140struct ipr_hostrcb {
1141 struct ipr_hcam hcam;
1142 dma_addr_t hostrcb_dma;
1143 struct list_head queue;
1144 struct ipr_ioa_cfg *ioa_cfg;
1145 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1146};
1147
1148/* IPR smart dump table structures */
1149struct ipr_sdt_entry {
1150 __be32 start_token;
1151 __be32 end_token;
1152 u8 reserved[4];
1153
1154 u8 flags;
1155#define IPR_SDT_ENDIAN 0x80
1156#define IPR_SDT_VALID_ENTRY 0x20
1157
1158 u8 resv;
1159 __be16 priority;
1160}__attribute__((packed, aligned (4)));
1161
1162struct ipr_sdt_header {
1163 __be32 state;
1164 __be32 num_entries;
1165 __be32 num_entries_used;
1166 __be32 dump_size;
1167}__attribute__((packed, aligned (4)));
1168
1169struct ipr_sdt {
1170 struct ipr_sdt_header hdr;
1171 struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES];
1172}__attribute__((packed, aligned (4)));
1173
1174struct ipr_uc_sdt {
1175 struct ipr_sdt_header hdr;
1176 struct ipr_sdt_entry entry[1];
1177}__attribute__((packed, aligned (4)));
1178
1179/*
1180 * Driver types
1181 */
1182struct ipr_bus_attributes {
1183 u8 bus;
1184 u8 qas_enabled;
1185 u8 bus_width;
1186 u8 reserved;
1187 u32 max_xfer_rate;
1188};
1189
1190struct ipr_sata_port {
1191 struct ipr_ioa_cfg *ioa_cfg;
1192 struct ata_port *ap;
1193 struct ipr_resource_entry *res;
1194 struct ipr_ioasa_gata ioasa;
1195};
1196
1197struct ipr_resource_entry {
1198 u8 needs_sync_complete:1;
1199 u8 in_erp:1;
1200 u8 add_to_ml:1;
1201 u8 del_from_ml:1;
1202 u8 resetting_device:1;
1203
1204 u32 bus; /* AKA channel */
1205 u32 target; /* AKA id */
1206 u32 lun;
1207#define IPR_ARRAY_VIRTUAL_BUS 0x1
1208#define IPR_VSET_VIRTUAL_BUS 0x2
1209#define IPR_IOAFP_VIRTUAL_BUS 0x3
1210
1211#define IPR_GET_RES_PHYS_LOC(res) \
1212 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1213
1214 u8 ata_class;
1215
1216 u8 flags;
1217 __be16 res_flags;
1218
1219 u8 type;
1220
1221 u8 qmodel;
1222 struct ipr_std_inq_data std_inq_data;
1223
1224 __be32 res_handle;
1225 __be64 dev_id;
1226 __be64 lun_wwn;
1227 struct scsi_lun dev_lun;
1228 u8 res_path[8];
1229
1230 struct ipr_ioa_cfg *ioa_cfg;
1231 struct scsi_device *sdev;
1232 struct ipr_sata_port *sata_port;
1233 struct list_head queue;
1234}; /* struct ipr_resource_entry */
1235
1236struct ipr_resource_hdr {
1237 u16 num_entries;
1238 u16 reserved;
1239};
1240
1241struct ipr_misc_cbs {
1242 struct ipr_ioa_vpd ioa_vpd;
1243 struct ipr_inquiry_page0 page0_data;
1244 struct ipr_inquiry_page3 page3_data;
1245 struct ipr_inquiry_cap cap;
1246 struct ipr_mode_pages mode_pages;
1247 struct ipr_supported_device supp_dev;
1248};
1249
1250struct ipr_interrupt_offsets {
1251 unsigned long set_interrupt_mask_reg;
1252 unsigned long clr_interrupt_mask_reg;
1253 unsigned long clr_interrupt_mask_reg32;
1254 unsigned long sense_interrupt_mask_reg;
1255 unsigned long sense_interrupt_mask_reg32;
1256 unsigned long clr_interrupt_reg;
1257 unsigned long clr_interrupt_reg32;
1258
1259 unsigned long sense_interrupt_reg;
1260 unsigned long sense_interrupt_reg32;
1261 unsigned long ioarrin_reg;
1262 unsigned long sense_uproc_interrupt_reg;
1263 unsigned long sense_uproc_interrupt_reg32;
1264 unsigned long set_uproc_interrupt_reg;
1265 unsigned long set_uproc_interrupt_reg32;
1266 unsigned long clr_uproc_interrupt_reg;
1267 unsigned long clr_uproc_interrupt_reg32;
1268
1269 unsigned long init_feedback_reg;
1270
1271 unsigned long dump_addr_reg;
1272 unsigned long dump_data_reg;
1273
1274#define IPR_ENDIAN_SWAP_KEY 0x00080800
1275 unsigned long endian_swap_reg;
1276};
1277
1278struct ipr_interrupts {
1279 void __iomem *set_interrupt_mask_reg;
1280 void __iomem *clr_interrupt_mask_reg;
1281 void __iomem *clr_interrupt_mask_reg32;
1282 void __iomem *sense_interrupt_mask_reg;
1283 void __iomem *sense_interrupt_mask_reg32;
1284 void __iomem *clr_interrupt_reg;
1285 void __iomem *clr_interrupt_reg32;
1286
1287 void __iomem *sense_interrupt_reg;
1288 void __iomem *sense_interrupt_reg32;
1289 void __iomem *ioarrin_reg;
1290 void __iomem *sense_uproc_interrupt_reg;
1291 void __iomem *sense_uproc_interrupt_reg32;
1292 void __iomem *set_uproc_interrupt_reg;
1293 void __iomem *set_uproc_interrupt_reg32;
1294 void __iomem *clr_uproc_interrupt_reg;
1295 void __iomem *clr_uproc_interrupt_reg32;
1296
1297 void __iomem *init_feedback_reg;
1298
1299 void __iomem *dump_addr_reg;
1300 void __iomem *dump_data_reg;
1301
1302 void __iomem *endian_swap_reg;
1303};
1304
1305struct ipr_chip_cfg_t {
1306 u32 mailbox;
1307 u8 cache_line_size;
1308 struct ipr_interrupt_offsets regs;
1309};
1310
1311struct ipr_chip_t {
1312 u16 vendor;
1313 u16 device;
1314 u16 intr_type;
1315#define IPR_USE_LSI 0x00
1316#define IPR_USE_MSI 0x01
1317 u16 sis_type;
1318#define IPR_SIS32 0x00
1319#define IPR_SIS64 0x01
1320 u16 bist_method;
1321#define IPR_PCI_CFG 0x00
1322#define IPR_MMIO 0x01
1323 const struct ipr_chip_cfg_t *cfg;
1324};
1325
1326enum ipr_shutdown_type {
1327 IPR_SHUTDOWN_NORMAL = 0x00,
1328 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1329 IPR_SHUTDOWN_ABBREV = 0x80,
1330 IPR_SHUTDOWN_NONE = 0x100
1331};
1332
1333struct ipr_trace_entry {
1334 u32 time;
1335
1336 u8 op_code;
1337 u8 ata_op_code;
1338 u8 type;
1339#define IPR_TRACE_START 0x00
1340#define IPR_TRACE_FINISH 0xff
1341 u8 cmd_index;
1342
1343 __be32 res_handle;
1344 union {
1345 u32 ioasc;
1346 u32 add_data;
1347 u32 res_addr;
1348 } u;
1349};
1350
1351struct ipr_sglist {
1352 u32 order;
1353 u32 num_sg;
1354 u32 num_dma_sg;
1355 u32 buffer_len;
1356 struct scatterlist scatterlist[1];
1357};
1358
1359enum ipr_sdt_state {
1360 INACTIVE,
1361 WAIT_FOR_DUMP,
1362 GET_DUMP,
1363 ABORT_DUMP,
1364 DUMP_OBTAINED
1365};
1366
1367/* Per-controller data */
1368struct ipr_ioa_cfg {
1369 char eye_catcher[8];
1370#define IPR_EYECATCHER "iprcfg"
1371
1372 struct list_head queue;
1373
1374 u8 allow_interrupts:1;
1375 u8 in_reset_reload:1;
1376 u8 in_ioa_bringdown:1;
1377 u8 ioa_unit_checked:1;
1378 u8 ioa_is_dead:1;
1379 u8 dump_taken:1;
1380 u8 allow_cmds:1;
1381 u8 allow_ml_add_del:1;
1382 u8 needs_hard_reset:1;
1383 u8 dual_raid:1;
1384 u8 needs_warm_reset:1;
1385 u8 msi_received:1;
1386 u8 sis64:1;
1387
1388 u8 revid;
1389
1390 /*
1391 * Bitmaps for SIS64 generated target values
1392 */
1393 unsigned long *target_ids;
1394 unsigned long *array_ids;
1395 unsigned long *vset_ids;
1396
1397 u16 type; /* CCIN of the card */
1398
1399 u8 log_level;
1400#define IPR_MAX_LOG_LEVEL 4
1401#define IPR_DEFAULT_LOG_LEVEL 2
1402
1403#define IPR_NUM_TRACE_INDEX_BITS 8
1404#define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1405#define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1406 char trace_start[8];
1407#define IPR_TRACE_START_LABEL "trace"
1408 struct ipr_trace_entry *trace;
1409 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1410
1411 /*
1412 * Queue for free command blocks
1413 */
1414 char ipr_free_label[8];
1415#define IPR_FREEQ_LABEL "free-q"
1416 struct list_head free_q;
1417
1418 /*
1419 * Queue for command blocks outstanding to the adapter
1420 */
1421 char ipr_pending_label[8];
1422#define IPR_PENDQ_LABEL "pend-q"
1423 struct list_head pending_q;
1424
1425 char cfg_table_start[8];
1426#define IPR_CFG_TBL_START "cfg"
1427 union {
1428 struct ipr_config_table *cfg_table;
1429 struct ipr_config_table64 *cfg_table64;
1430 } u;
1431 dma_addr_t cfg_table_dma;
1432 u32 cfg_table_size;
1433 u32 max_devs_supported;
1434
1435 char resource_table_label[8];
1436#define IPR_RES_TABLE_LABEL "res_tbl"
1437 struct ipr_resource_entry *res_entries;
1438 struct list_head free_res_q;
1439 struct list_head used_res_q;
1440
1441 char ipr_hcam_label[8];
1442#define IPR_HCAM_LABEL "hcams"
1443 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1444 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1445 struct list_head hostrcb_free_q;
1446 struct list_head hostrcb_pending_q;
1447
1448 __be32 *host_rrq;
1449 dma_addr_t host_rrq_dma;
1450#define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
1451#define IPR_HRRQ_RESP_BIT_SET 0x00000002
1452#define IPR_HRRQ_TOGGLE_BIT 0x00000001
1453#define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
1454 volatile __be32 *hrrq_start;
1455 volatile __be32 *hrrq_end;
1456 volatile __be32 *hrrq_curr;
1457 volatile u32 toggle_bit;
1458
1459 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1460
1461 unsigned int transop_timeout;
1462 const struct ipr_chip_cfg_t *chip_cfg;
1463 const struct ipr_chip_t *ipr_chip;
1464
1465 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1466 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1467 void __iomem *ioa_mailbox;
1468 struct ipr_interrupts regs;
1469
1470 u16 saved_pcix_cmd_reg;
1471 u16 reset_retries;
1472
1473 u32 errors_logged;
1474 u32 doorbell;
1475
1476 struct Scsi_Host *host;
1477 struct pci_dev *pdev;
1478 struct ipr_sglist *ucode_sglist;
1479 u8 saved_mode_page_len;
1480
1481 struct work_struct work_q;
1482
1483 wait_queue_head_t reset_wait_q;
1484 wait_queue_head_t msi_wait_q;
1485
1486 struct ipr_dump *dump;
1487 enum ipr_sdt_state sdt_state;
1488
1489 struct ipr_misc_cbs *vpd_cbs;
1490 dma_addr_t vpd_cbs_dma;
1491
1492 struct pci_pool *ipr_cmd_pool;
1493
1494 struct ipr_cmnd *reset_cmd;
1495 int (*reset) (struct ipr_cmnd *);
1496
1497 struct ata_host ata_host;
1498 char ipr_cmd_label[8];
1499#define IPR_CMD_LABEL "ipr_cmd"
1500 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
1501 dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
1502}; /* struct ipr_ioa_cfg */
1503
1504struct ipr_cmnd {
1505 struct ipr_ioarcb ioarcb;
1506 union {
1507 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1508 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1509 struct ipr_ata64_ioadl ata_ioadl;
1510 } i;
1511 union {
1512 struct ipr_ioasa ioasa;
1513 struct ipr_ioasa64 ioasa64;
1514 } s;
1515 struct list_head queue;
1516 struct scsi_cmnd *scsi_cmd;
1517 struct ata_queued_cmd *qc;
1518 struct completion completion;
1519 struct timer_list timer;
1520 void (*done) (struct ipr_cmnd *);
1521 int (*job_step) (struct ipr_cmnd *);
1522 int (*job_step_failed) (struct ipr_cmnd *);
1523 u16 cmd_index;
1524 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1525 dma_addr_t sense_buffer_dma;
1526 unsigned short dma_use_sg;
1527 dma_addr_t dma_addr;
1528 struct ipr_cmnd *sibling;
1529 union {
1530 enum ipr_shutdown_type shutdown_type;
1531 struct ipr_hostrcb *hostrcb;
1532 unsigned long time_left;
1533 unsigned long scratch;
1534 struct ipr_resource_entry *res;
1535 struct scsi_device *sdev;
1536 } u;
1537
1538 struct ipr_ioa_cfg *ioa_cfg;
1539};
1540
1541struct ipr_ses_table_entry {
1542 char product_id[17];
1543 char compare_product_id_byte[17];
1544 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1545};
1546
1547struct ipr_dump_header {
1548 u32 eye_catcher;
1549#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1550 u32 len;
1551 u32 num_entries;
1552 u32 first_entry_offset;
1553 u32 status;
1554#define IPR_DUMP_STATUS_SUCCESS 0
1555#define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1556#define IPR_DUMP_STATUS_FAILED 0xffffffff
1557 u32 os;
1558#define IPR_DUMP_OS_LINUX 0x4C4E5558
1559 u32 driver_name;
1560#define IPR_DUMP_DRIVER_NAME 0x49505232
1561}__attribute__((packed, aligned (4)));
1562
1563struct ipr_dump_entry_header {
1564 u32 eye_catcher;
1565#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1566 u32 len;
1567 u32 num_elems;
1568 u32 offset;
1569 u32 data_type;
1570#define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1571#define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1572 u32 id;
1573#define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1574#define IPR_DUMP_LOCATION_ID 0x4C4F4341
1575#define IPR_DUMP_TRACE_ID 0x54524143
1576#define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1577#define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1578#define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1579#define IPR_DUMP_PEND_OPS 0x414F5053
1580 u32 status;
1581}__attribute__((packed, aligned (4)));
1582
1583struct ipr_dump_location_entry {
1584 struct ipr_dump_entry_header hdr;
1585 u8 location[20];
1586}__attribute__((packed));
1587
1588struct ipr_dump_trace_entry {
1589 struct ipr_dump_entry_header hdr;
1590 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1591}__attribute__((packed, aligned (4)));
1592
1593struct ipr_dump_version_entry {
1594 struct ipr_dump_entry_header hdr;
1595 u8 version[sizeof(IPR_DRIVER_VERSION)];
1596};
1597
1598struct ipr_dump_ioa_type_entry {
1599 struct ipr_dump_entry_header hdr;
1600 u32 type;
1601 u32 fw_version;
1602};
1603
1604struct ipr_driver_dump {
1605 struct ipr_dump_header hdr;
1606 struct ipr_dump_version_entry version_entry;
1607 struct ipr_dump_location_entry location_entry;
1608 struct ipr_dump_ioa_type_entry ioa_type_entry;
1609 struct ipr_dump_trace_entry trace_entry;
1610}__attribute__((packed));
1611
1612struct ipr_ioa_dump {
1613 struct ipr_dump_entry_header hdr;
1614 struct ipr_sdt sdt;
1615 __be32 **ioa_data;
1616 u32 reserved;
1617 u32 next_page_index;
1618 u32 page_offset;
1619 u32 format;
1620}__attribute__((packed, aligned (4)));
1621
1622struct ipr_dump {
1623 struct kref kref;
1624 struct ipr_ioa_cfg *ioa_cfg;
1625 struct ipr_driver_dump driver_dump;
1626 struct ipr_ioa_dump ioa_dump;
1627};
1628
1629struct ipr_error_table_t {
1630 u32 ioasc;
1631 int log_ioasa;
1632 int log_hcam;
1633 char *error;
1634};
1635
1636struct ipr_software_inq_lid_info {
1637 __be32 load_id;
1638 __be32 timestamp[3];
1639}__attribute__((packed, aligned (4)));
1640
1641struct ipr_ucode_image_header {
1642 __be32 header_length;
1643 __be32 lid_table_offset;
1644 u8 major_release;
1645 u8 card_type;
1646 u8 minor_release[2];
1647 u8 reserved[20];
1648 char eyecatcher[16];
1649 __be32 num_lids;
1650 struct ipr_software_inq_lid_info lid[1];
1651}__attribute__((packed, aligned (4)));
1652
1653/*
1654 * Macros
1655 */
1656#define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1657
1658#ifdef CONFIG_SCSI_IPR_TRACE
1659#define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1660#define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1661#else
1662#define ipr_create_trace_file(kobj, attr) 0
1663#define ipr_remove_trace_file(kobj, attr) do { } while(0)
1664#endif
1665
1666#ifdef CONFIG_SCSI_IPR_DUMP
1667#define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1668#define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1669#else
1670#define ipr_create_dump_file(kobj, attr) 0
1671#define ipr_remove_dump_file(kobj, attr) do { } while(0)
1672#endif
1673
1674/*
1675 * Error logging macros
1676 */
1677#define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1678#define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1679#define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1680
1681#define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1682 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1683 bus, target, lun, ##__VA_ARGS__)
1684
1685#define ipr_res_err(ioa_cfg, res, fmt, ...) \
1686 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1687
1688#define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1689 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1690 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1691
1692#define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1693 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1694
1695#define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1696{ \
1697 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1698 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1699 } else { \
1700 ipr_err(fmt": %d:%d:%d:%d\n", \
1701 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1702 (res).bus, (res).target, (res).lun); \
1703 } \
1704}
1705
1706#define ipr_hcam_err(hostrcb, fmt, ...) \
1707{ \
1708 if (ipr_is_device(hostrcb)) { \
1709 if ((hostrcb)->ioa_cfg->sis64) { \
1710 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1711 ipr_format_res_path(hostrcb->hcam.u.error64.fd_res_path, \
1712 hostrcb->rp_buffer, \
1713 sizeof(hostrcb->rp_buffer)), \
1714 __VA_ARGS__); \
1715 } else { \
1716 ipr_ra_err((hostrcb)->ioa_cfg, \
1717 (hostrcb)->hcam.u.error.fd_res_addr, \
1718 fmt, __VA_ARGS__); \
1719 } \
1720 } else { \
1721 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1722 } \
1723}
1724
1725#define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1726 __FILE__, __func__, __LINE__)
1727
1728#define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1729#define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1730
1731#define ipr_err_separator \
1732ipr_err("----------------------------------------------------------\n")
1733
1734
1735/*
1736 * Inlines
1737 */
1738
1739/**
1740 * ipr_is_ioa_resource - Determine if a resource is the IOA
1741 * @res: resource entry struct
1742 *
1743 * Return value:
1744 * 1 if IOA / 0 if not IOA
1745 **/
1746static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1747{
1748 return res->type == IPR_RES_TYPE_IOAFP;
1749}
1750
1751/**
1752 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1753 * @res: resource entry struct
1754 *
1755 * Return value:
1756 * 1 if AF DASD / 0 if not AF DASD
1757 **/
1758static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1759{
1760 return res->type == IPR_RES_TYPE_AF_DASD ||
1761 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1762}
1763
1764/**
1765 * ipr_is_vset_device - Determine if a resource is a VSET
1766 * @res: resource entry struct
1767 *
1768 * Return value:
1769 * 1 if VSET / 0 if not VSET
1770 **/
1771static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1772{
1773 return res->type == IPR_RES_TYPE_VOLUME_SET;
1774}
1775
1776/**
1777 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1778 * @res: resource entry struct
1779 *
1780 * Return value:
1781 * 1 if GSCSI / 0 if not GSCSI
1782 **/
1783static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1784{
1785 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1786}
1787
1788/**
1789 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1790 * @res: resource entry struct
1791 *
1792 * Return value:
1793 * 1 if SCSI disk / 0 if not SCSI disk
1794 **/
1795static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1796{
1797 if (ipr_is_af_dasd_device(res) ||
1798 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1799 return 1;
1800 else
1801 return 0;
1802}
1803
1804/**
1805 * ipr_is_gata - Determine if a resource is a generic ATA resource
1806 * @res: resource entry struct
1807 *
1808 * Return value:
1809 * 1 if GATA / 0 if not GATA
1810 **/
1811static inline int ipr_is_gata(struct ipr_resource_entry *res)
1812{
1813 return res->type == IPR_RES_TYPE_GENERIC_ATA;
1814}
1815
1816/**
1817 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1818 * @res: resource entry struct
1819 *
1820 * Return value:
1821 * 1 if NACA queueing model / 0 if not NACA queueing model
1822 **/
1823static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1824{
1825 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1826 return 1;
1827 return 0;
1828}
1829
1830/**
1831 * ipr_is_device - Determine if the hostrcb structure is related to a device
1832 * @hostrcb: host resource control blocks struct
1833 *
1834 * Return value:
1835 * 1 if AF / 0 if not AF
1836 **/
1837static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1838{
1839 struct ipr_res_addr *res_addr;
1840 u8 *res_path;
1841
1842 if (hostrcb->ioa_cfg->sis64) {
1843 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1844 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1845 res_path[0] == 0x81) && res_path[2] != 0xFF)
1846 return 1;
1847 } else {
1848 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1849
1850 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1851 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1852 return 1;
1853 }
1854 return 0;
1855}
1856
1857/**
1858 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1859 * @sdt_word: SDT address
1860 *
1861 * Return value:
1862 * 1 if format 2 / 0 if not
1863 **/
1864static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1865{
1866 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1867
1868 switch (bar_sel) {
1869 case IPR_SDT_FMT2_BAR0_SEL:
1870 case IPR_SDT_FMT2_BAR1_SEL:
1871 case IPR_SDT_FMT2_BAR2_SEL:
1872 case IPR_SDT_FMT2_BAR3_SEL:
1873 case IPR_SDT_FMT2_BAR4_SEL:
1874 case IPR_SDT_FMT2_BAR5_SEL:
1875 case IPR_SDT_FMT2_EXP_ROM_SEL:
1876 return 1;
1877 };
1878
1879 return 0;
1880}
1881
1882#ifndef writeq
1883static inline void writeq(u64 val, void __iomem *addr)
1884{
1885 writel(((u32) (val >> 32)), addr);
1886 writel(((u32) (val)), (addr + 4));
1887}
1888#endif
1889
1890#endif /* _IPR_H */
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * ipr.h -- driver for IBM Power Linux RAID adapters
4 *
5 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
6 *
7 * Copyright (C) 2003, 2004 IBM Corporation
8 *
9 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
10 * that broke 64bit platforms.
11 */
12
13#ifndef _IPR_H
14#define _IPR_H
15
16#include <asm/unaligned.h>
17#include <linux/types.h>
18#include <linux/completion.h>
19#include <linux/libata.h>
20#include <linux/list.h>
21#include <linux/kref.h>
22#include <linux/irq_poll.h>
23#include <scsi/scsi.h>
24#include <scsi/scsi_cmnd.h>
25
26/*
27 * Literals
28 */
29#define IPR_DRIVER_VERSION "2.6.4"
30#define IPR_DRIVER_DATE "(March 14, 2017)"
31
32/*
33 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
34 * ops per device for devices not running tagged command queuing.
35 * This can be adjusted at runtime through sysfs device attributes.
36 */
37#define IPR_MAX_CMD_PER_LUN 6
38#define IPR_MAX_CMD_PER_ATA_LUN 1
39
40/*
41 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
42 * ops the mid-layer can send to the adapter.
43 */
44#define IPR_NUM_BASE_CMD_BLKS (ioa_cfg->max_cmds)
45
46#define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
47
48#define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
49#define PCI_DEVICE_ID_IBM_CROCODILE 0x034A
50#define PCI_DEVICE_ID_IBM_RATTLESNAKE 0x04DA
51
52#define IPR_SUBS_DEV_ID_2780 0x0264
53#define IPR_SUBS_DEV_ID_5702 0x0266
54#define IPR_SUBS_DEV_ID_5703 0x0278
55#define IPR_SUBS_DEV_ID_572E 0x028D
56#define IPR_SUBS_DEV_ID_573E 0x02D3
57#define IPR_SUBS_DEV_ID_573D 0x02D4
58#define IPR_SUBS_DEV_ID_571A 0x02C0
59#define IPR_SUBS_DEV_ID_571B 0x02BE
60#define IPR_SUBS_DEV_ID_571E 0x02BF
61#define IPR_SUBS_DEV_ID_571F 0x02D5
62#define IPR_SUBS_DEV_ID_572A 0x02C1
63#define IPR_SUBS_DEV_ID_572B 0x02C2
64#define IPR_SUBS_DEV_ID_572F 0x02C3
65#define IPR_SUBS_DEV_ID_574E 0x030A
66#define IPR_SUBS_DEV_ID_575B 0x030D
67#define IPR_SUBS_DEV_ID_575C 0x0338
68#define IPR_SUBS_DEV_ID_57B3 0x033A
69#define IPR_SUBS_DEV_ID_57B7 0x0360
70#define IPR_SUBS_DEV_ID_57B8 0x02C2
71
72#define IPR_SUBS_DEV_ID_57B4 0x033B
73#define IPR_SUBS_DEV_ID_57B2 0x035F
74#define IPR_SUBS_DEV_ID_57C0 0x0352
75#define IPR_SUBS_DEV_ID_57C3 0x0353
76#define IPR_SUBS_DEV_ID_57C4 0x0354
77#define IPR_SUBS_DEV_ID_57C6 0x0357
78#define IPR_SUBS_DEV_ID_57CC 0x035C
79
80#define IPR_SUBS_DEV_ID_57B5 0x033C
81#define IPR_SUBS_DEV_ID_57CE 0x035E
82#define IPR_SUBS_DEV_ID_57B1 0x0355
83
84#define IPR_SUBS_DEV_ID_574D 0x0356
85#define IPR_SUBS_DEV_ID_57C8 0x035D
86
87#define IPR_SUBS_DEV_ID_57D5 0x03FB
88#define IPR_SUBS_DEV_ID_57D6 0x03FC
89#define IPR_SUBS_DEV_ID_57D7 0x03FF
90#define IPR_SUBS_DEV_ID_57D8 0x03FE
91#define IPR_SUBS_DEV_ID_57D9 0x046D
92#define IPR_SUBS_DEV_ID_57DA 0x04CA
93#define IPR_SUBS_DEV_ID_57EB 0x0474
94#define IPR_SUBS_DEV_ID_57EC 0x0475
95#define IPR_SUBS_DEV_ID_57ED 0x0499
96#define IPR_SUBS_DEV_ID_57EE 0x049A
97#define IPR_SUBS_DEV_ID_57EF 0x049B
98#define IPR_SUBS_DEV_ID_57F0 0x049C
99#define IPR_SUBS_DEV_ID_2CCA 0x04C7
100#define IPR_SUBS_DEV_ID_2CD2 0x04C8
101#define IPR_SUBS_DEV_ID_2CCD 0x04C9
102#define IPR_SUBS_DEV_ID_580A 0x04FC
103#define IPR_SUBS_DEV_ID_580B 0x04FB
104#define IPR_NAME "ipr"
105
106/*
107 * Return codes
108 */
109#define IPR_RC_JOB_CONTINUE 1
110#define IPR_RC_JOB_RETURN 2
111
112/*
113 * IOASCs
114 */
115#define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
116#define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
117#define IPR_IOASC_SYNC_REQUIRED 0x023f0000
118#define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
119#define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
120#define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
121#define IPR_IOASC_IOASC_MASK 0xFFFFFF00
122#define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
123#define IPR_IOASC_HW_CMD_FAILED 0x046E0000
124#define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
125#define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
126#define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
127#define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
128#define IPR_IOASC_BUS_WAS_RESET 0x06290000
129#define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
130#define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
131#define IPR_IOASC_IR_NON_OPTIMIZED 0x05258200
132
133#define IPR_FIRST_DRIVER_IOASC 0x10000000
134#define IPR_IOASC_IOA_WAS_RESET 0x10000001
135#define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
136
137/* Driver data flags */
138#define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
139#define IPR_USE_PCI_WARM_RESET 0x00000002
140
141#define IPR_DEFAULT_MAX_ERROR_DUMP 984
142#define IPR_NUM_LOG_HCAMS 2
143#define IPR_NUM_CFG_CHG_HCAMS 2
144#define IPR_NUM_HCAM_QUEUE 12
145#define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
146#define IPR_MAX_HCAMS (IPR_NUM_HCAMS + IPR_NUM_HCAM_QUEUE)
147
148#define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
149#define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
150
151#define IPR_MAX_NUM_TARGETS_PER_BUS 256
152#define IPR_MAX_NUM_LUNS_PER_TARGET 256
153#define IPR_VSET_BUS 0xff
154#define IPR_IOA_BUS 0xff
155#define IPR_IOA_TARGET 0xff
156#define IPR_IOA_LUN 0xff
157#define IPR_MAX_NUM_BUSES 16
158
159#define IPR_NUM_RESET_RELOAD_RETRIES 3
160
161/* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
162#define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
163 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
164
165#define IPR_MAX_COMMANDS 100
166#define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
167 IPR_NUM_INTERNAL_CMD_BLKS)
168
169#define IPR_MAX_PHYSICAL_DEVS 192
170#define IPR_DEFAULT_SIS64_DEVS 1024
171#define IPR_MAX_SIS64_DEVS 4096
172
173#define IPR_MAX_SGLIST 64
174#define IPR_IOA_MAX_SECTORS 32767
175#define IPR_VSET_MAX_SECTORS 512
176#define IPR_MAX_CDB_LEN 16
177#define IPR_MAX_HRRQ_RETRIES 3
178
179#define IPR_DEFAULT_BUS_WIDTH 16
180#define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
181#define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
182#define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
183#define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
184
185#define IPR_IOA_RES_HANDLE 0xffffffff
186#define IPR_INVALID_RES_HANDLE 0
187#define IPR_IOA_RES_ADDR 0x00ffffff
188
189/*
190 * Adapter Commands
191 */
192#define IPR_CANCEL_REQUEST 0xC0
193#define IPR_CANCEL_64BIT_IOARCB 0x01
194#define IPR_QUERY_RSRC_STATE 0xC2
195#define IPR_RESET_DEVICE 0xC3
196#define IPR_RESET_TYPE_SELECT 0x80
197#define IPR_LUN_RESET 0x40
198#define IPR_TARGET_RESET 0x20
199#define IPR_BUS_RESET 0x10
200#define IPR_ATA_PHY_RESET 0x80
201#define IPR_ID_HOST_RR_Q 0xC4
202#define IPR_QUERY_IOA_CONFIG 0xC5
203#define IPR_CANCEL_ALL_REQUESTS 0xCE
204#define IPR_HOST_CONTROLLED_ASYNC 0xCF
205#define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
206#define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
207#define IPR_SET_SUPPORTED_DEVICES 0xFB
208#define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
209#define IPR_IOA_SHUTDOWN 0xF7
210#define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
211#define IPR_IOA_SERVICE_ACTION 0xD2
212
213/* IOA Service Actions */
214#define IPR_IOA_SA_CHANGE_CACHE_PARAMS 0x14
215
216/*
217 * Timeouts
218 */
219#define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
220#define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
221#define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
222#define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
223#define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
224#define IPR_CANCEL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
225#define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
226#define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
227#define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
228#define IPR_WRITE_BUFFER_TIMEOUT (30 * 60 * HZ)
229#define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
230#define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
231#define IPR_OPERATIONAL_TIMEOUT (5 * 60)
232#define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
233#define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
234#define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
235#define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
236#define IPR_PCI_ERROR_RECOVERY_TIMEOUT (120 * HZ)
237#define IPR_PCI_RESET_TIMEOUT (HZ / 2)
238#define IPR_SIS32_DUMP_TIMEOUT (15 * HZ)
239#define IPR_SIS64_DUMP_TIMEOUT (40 * HZ)
240#define IPR_DUMP_DELAY_SECONDS 4
241#define IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ)
242
243/*
244 * SCSI Literals
245 */
246#define IPR_VENDOR_ID_LEN 8
247#define IPR_PROD_ID_LEN 16
248#define IPR_SERIAL_NUM_LEN 8
249
250/*
251 * Hardware literals
252 */
253#define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
254#define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
255#define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
256#define IPR_GET_FMT2_BAR_SEL(mbx) \
257(((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
258#define IPR_SDT_FMT2_BAR0_SEL 0x0
259#define IPR_SDT_FMT2_BAR1_SEL 0x1
260#define IPR_SDT_FMT2_BAR2_SEL 0x2
261#define IPR_SDT_FMT2_BAR3_SEL 0x3
262#define IPR_SDT_FMT2_BAR4_SEL 0x4
263#define IPR_SDT_FMT2_BAR5_SEL 0x5
264#define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
265#define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
266#define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
267#define IPR_DOORBELL 0x82800000
268#define IPR_RUNTIME_RESET 0x40000000
269
270#define IPR_IPL_INIT_MIN_STAGE_TIME 5
271#define IPR_IPL_INIT_DEFAULT_STAGE_TIME 30
272#define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
273#define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
274#define IPR_IPL_INIT_STAGE_MASK 0xff000000
275#define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
276#define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
277
278#define IPR_PCII_MAILBOX_STABLE (0x80000000 >> 4)
279#define IPR_WAIT_FOR_MAILBOX (2 * HZ)
280
281#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
282#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
283#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
284#define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
285#define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
286#define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
287#define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
288#define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
289#define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
290#define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
291#define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
292
293#define IPR_PCII_ERROR_INTERRUPTS \
294(IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
295IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
296
297#define IPR_PCII_OPER_INTERRUPTS \
298(IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
299
300#define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
301#define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
302#define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23)
303
304#define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
305#define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
306
307/*
308 * Dump literals
309 */
310#define IPR_FMT2_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
311#define IPR_FMT3_MAX_IOA_DUMP_SIZE (80 * 1024 * 1024)
312#define IPR_FMT2_NUM_SDT_ENTRIES 511
313#define IPR_FMT3_NUM_SDT_ENTRIES 0xFFF
314#define IPR_FMT2_MAX_NUM_DUMP_PAGES ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
315#define IPR_FMT3_MAX_NUM_DUMP_PAGES ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
316
317/*
318 * Misc literals
319 */
320#define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
321#define IPR_MAX_MSIX_VECTORS 0x10
322#define IPR_MAX_HRRQ_NUM 0x10
323#define IPR_INIT_HRRQ 0x0
324
325/*
326 * Adapter interface types
327 */
328
329struct ipr_res_addr {
330 u8 reserved;
331 u8 bus;
332 u8 target;
333 u8 lun;
334#define IPR_GET_PHYS_LOC(res_addr) \
335 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
336}__attribute__((packed, aligned (4)));
337
338struct ipr_std_inq_vpids {
339 u8 vendor_id[IPR_VENDOR_ID_LEN];
340 u8 product_id[IPR_PROD_ID_LEN];
341}__attribute__((packed));
342
343struct ipr_vpd {
344 struct ipr_std_inq_vpids vpids;
345 u8 sn[IPR_SERIAL_NUM_LEN];
346}__attribute__((packed));
347
348struct ipr_ext_vpd {
349 struct ipr_vpd vpd;
350 __be32 wwid[2];
351}__attribute__((packed));
352
353struct ipr_ext_vpd64 {
354 struct ipr_vpd vpd;
355 __be32 wwid[4];
356}__attribute__((packed));
357
358struct ipr_std_inq_data {
359 u8 peri_qual_dev_type;
360#define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
361#define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
362
363 u8 removeable_medium_rsvd;
364#define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
365
366#define IPR_IS_DASD_DEVICE(std_inq) \
367((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
368!(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
369
370#define IPR_IS_SES_DEVICE(std_inq) \
371(IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
372
373 u8 version;
374 u8 aen_naca_fmt;
375 u8 additional_len;
376 u8 sccs_rsvd;
377 u8 bq_enc_multi;
378 u8 sync_cmdq_flags;
379
380 struct ipr_std_inq_vpids vpids;
381
382 u8 ros_rsvd_ram_rsvd[4];
383
384 u8 serial_num[IPR_SERIAL_NUM_LEN];
385}__attribute__ ((packed));
386
387#define IPR_RES_TYPE_AF_DASD 0x00
388#define IPR_RES_TYPE_GENERIC_SCSI 0x01
389#define IPR_RES_TYPE_VOLUME_SET 0x02
390#define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
391#define IPR_RES_TYPE_GENERIC_ATA 0x04
392#define IPR_RES_TYPE_ARRAY 0x05
393#define IPR_RES_TYPE_IOAFP 0xff
394
395struct ipr_config_table_entry {
396 u8 proto;
397#define IPR_PROTO_SATA 0x02
398#define IPR_PROTO_SATA_ATAPI 0x03
399#define IPR_PROTO_SAS_STP 0x06
400#define IPR_PROTO_SAS_STP_ATAPI 0x07
401 u8 array_id;
402 u8 flags;
403#define IPR_IS_IOA_RESOURCE 0x80
404 u8 rsvd_subtype;
405
406#define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
407#define IPR_QUEUE_FROZEN_MODEL 0
408#define IPR_QUEUE_NACA_MODEL 1
409
410 struct ipr_res_addr res_addr;
411 __be32 res_handle;
412 __be32 lun_wwn[2];
413 struct ipr_std_inq_data std_inq_data;
414}__attribute__ ((packed, aligned (4)));
415
416struct ipr_config_table_entry64 {
417 u8 res_type;
418 u8 proto;
419 u8 vset_num;
420 u8 array_id;
421 __be16 flags;
422 __be16 res_flags;
423#define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
424 __be32 res_handle;
425 u8 dev_id_type;
426 u8 reserved[3];
427 __be64 dev_id;
428 __be64 lun;
429 __be64 lun_wwn[2];
430#define IPR_MAX_RES_PATH_LENGTH 48
431#define IPR_RES_PATH_BYTES 8
432 __be64 res_path;
433 struct ipr_std_inq_data std_inq_data;
434 u8 reserved2[4];
435 __be64 reserved3[2];
436 u8 reserved4[8];
437}__attribute__ ((packed, aligned (8)));
438
439struct ipr_config_table_hdr {
440 u8 num_entries;
441 u8 flags;
442#define IPR_UCODE_DOWNLOAD_REQ 0x10
443 __be16 reserved;
444}__attribute__((packed, aligned (4)));
445
446struct ipr_config_table_hdr64 {
447 __be16 num_entries;
448 __be16 reserved;
449 u8 flags;
450 u8 reserved2[11];
451}__attribute__((packed, aligned (4)));
452
453struct ipr_config_table {
454 struct ipr_config_table_hdr hdr;
455 struct ipr_config_table_entry dev[];
456}__attribute__((packed, aligned (4)));
457
458struct ipr_config_table64 {
459 struct ipr_config_table_hdr64 hdr64;
460 struct ipr_config_table_entry64 dev[];
461}__attribute__((packed, aligned (8)));
462
463struct ipr_config_table_entry_wrapper {
464 union {
465 struct ipr_config_table_entry *cfgte;
466 struct ipr_config_table_entry64 *cfgte64;
467 } u;
468};
469
470struct ipr_hostrcb_cfg_ch_not {
471 union {
472 struct ipr_config_table_entry cfgte;
473 struct ipr_config_table_entry64 cfgte64;
474 } u;
475 u8 reserved[936];
476}__attribute__((packed, aligned (4)));
477
478struct ipr_supported_device {
479 __be16 data_length;
480 u8 reserved;
481 u8 num_records;
482 struct ipr_std_inq_vpids vpids;
483 u8 reserved2[16];
484}__attribute__((packed, aligned (4)));
485
486struct ipr_hrr_queue {
487 struct ipr_ioa_cfg *ioa_cfg;
488 __be32 *host_rrq;
489 dma_addr_t host_rrq_dma;
490#define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
491#define IPR_HRRQ_RESP_BIT_SET 0x00000002
492#define IPR_HRRQ_TOGGLE_BIT 0x00000001
493#define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
494#define IPR_ID_HRRQ_SELE_ENABLE 0x02
495 volatile __be32 *hrrq_start;
496 volatile __be32 *hrrq_end;
497 volatile __be32 *hrrq_curr;
498
499 struct list_head hrrq_free_q;
500 struct list_head hrrq_pending_q;
501 spinlock_t _lock;
502 spinlock_t *lock;
503
504 volatile u32 toggle_bit;
505 u32 size;
506 u32 min_cmd_id;
507 u32 max_cmd_id;
508 u8 allow_interrupts:1;
509 u8 ioa_is_dead:1;
510 u8 allow_cmds:1;
511 u8 removing_ioa:1;
512
513 struct irq_poll iopoll;
514};
515
516/* Command packet structure */
517struct ipr_cmd_pkt {
518 u8 reserved; /* Reserved by IOA */
519 u8 hrrq_id;
520 u8 request_type;
521#define IPR_RQTYPE_SCSICDB 0x00
522#define IPR_RQTYPE_IOACMD 0x01
523#define IPR_RQTYPE_HCAM 0x02
524#define IPR_RQTYPE_ATA_PASSTHRU 0x04
525#define IPR_RQTYPE_PIPE 0x05
526
527 u8 reserved2;
528
529 u8 flags_hi;
530#define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
531#define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
532#define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
533#define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
534#define IPR_FLAGS_HI_NO_LINK_DESC 0x04
535
536 u8 flags_lo;
537#define IPR_FLAGS_LO_ALIGNED_BFR 0x20
538#define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
539#define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
540#define IPR_FLAGS_LO_SIMPLE_TASK 0x02
541#define IPR_FLAGS_LO_ORDERED_TASK 0x04
542#define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
543#define IPR_FLAGS_LO_ACA_TASK 0x08
544
545 u8 cdb[16];
546 __be16 timeout;
547}__attribute__ ((packed, aligned(4)));
548
549struct ipr_ioarcb_ata_regs { /* 22 bytes */
550 u8 flags;
551#define IPR_ATA_FLAG_PACKET_CMD 0x80
552#define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
553#define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
554 u8 reserved[3];
555
556 __be16 data;
557 u8 feature;
558 u8 nsect;
559 u8 lbal;
560 u8 lbam;
561 u8 lbah;
562 u8 device;
563 u8 command;
564 u8 reserved2[3];
565 u8 hob_feature;
566 u8 hob_nsect;
567 u8 hob_lbal;
568 u8 hob_lbam;
569 u8 hob_lbah;
570 u8 ctl;
571}__attribute__ ((packed, aligned(2)));
572
573struct ipr_ioadl_desc {
574 __be32 flags_and_data_len;
575#define IPR_IOADL_FLAGS_MASK 0xff000000
576#define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
577#define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
578#define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
579#define IPR_IOADL_FLAGS_READ 0x48000000
580#define IPR_IOADL_FLAGS_READ_LAST 0x49000000
581#define IPR_IOADL_FLAGS_WRITE 0x68000000
582#define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
583#define IPR_IOADL_FLAGS_LAST 0x01000000
584
585 __be32 address;
586}__attribute__((packed, aligned (8)));
587
588struct ipr_ioadl64_desc {
589 __be32 flags;
590 __be32 data_len;
591 __be64 address;
592}__attribute__((packed, aligned (16)));
593
594struct ipr_ata64_ioadl {
595 struct ipr_ioarcb_ata_regs regs;
596 u16 reserved[5];
597 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
598}__attribute__((packed, aligned (16)));
599
600struct ipr_ioarcb_add_data {
601 union {
602 struct ipr_ioarcb_ata_regs regs;
603 struct ipr_ioadl_desc ioadl[5];
604 __be32 add_cmd_parms[10];
605 } u;
606}__attribute__ ((packed, aligned (4)));
607
608struct ipr_ioarcb_sis64_add_addr_ecb {
609 __be64 ioasa_host_pci_addr;
610 __be64 data_ioadl_addr;
611 __be64 reserved;
612 __be32 ext_control_buf[4];
613}__attribute__((packed, aligned (8)));
614
615/* IOA Request Control Block 128 bytes */
616struct ipr_ioarcb {
617 union {
618 __be32 ioarcb_host_pci_addr;
619 __be64 ioarcb_host_pci_addr64;
620 } a;
621 __be32 res_handle;
622 __be32 host_response_handle;
623 __be32 reserved1;
624 __be32 reserved2;
625 __be32 reserved3;
626
627 __be32 data_transfer_length;
628 __be32 read_data_transfer_length;
629 __be32 write_ioadl_addr;
630 __be32 ioadl_len;
631 __be32 read_ioadl_addr;
632 __be32 read_ioadl_len;
633
634 __be32 ioasa_host_pci_addr;
635 __be16 ioasa_len;
636 __be16 reserved4;
637
638 struct ipr_cmd_pkt cmd_pkt;
639
640 __be16 add_cmd_parms_offset;
641 __be16 add_cmd_parms_len;
642
643 union {
644 struct ipr_ioarcb_add_data add_data;
645 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
646 } u;
647
648}__attribute__((packed, aligned (4)));
649
650struct ipr_ioasa_vset {
651 __be32 failing_lba_hi;
652 __be32 failing_lba_lo;
653 __be32 reserved;
654}__attribute__((packed, aligned (4)));
655
656struct ipr_ioasa_af_dasd {
657 __be32 failing_lba;
658 __be32 reserved[2];
659}__attribute__((packed, aligned (4)));
660
661struct ipr_ioasa_gpdd {
662 u8 end_state;
663 u8 bus_phase;
664 __be16 reserved;
665 __be32 ioa_data[2];
666}__attribute__((packed, aligned (4)));
667
668struct ipr_ioasa_gata {
669 u8 error;
670 u8 nsect; /* Interrupt reason */
671 u8 lbal;
672 u8 lbam;
673 u8 lbah;
674 u8 device;
675 u8 status;
676 u8 alt_status; /* ATA CTL */
677 u8 hob_nsect;
678 u8 hob_lbal;
679 u8 hob_lbam;
680 u8 hob_lbah;
681}__attribute__((packed, aligned (4)));
682
683struct ipr_auto_sense {
684 __be16 auto_sense_len;
685 __be16 ioa_data_len;
686 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
687};
688
689struct ipr_ioasa_hdr {
690 __be32 ioasc;
691#define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
692#define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
693#define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
694#define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
695
696 __be16 ret_stat_len; /* Length of the returned IOASA */
697
698 __be16 avail_stat_len; /* Total Length of status available. */
699
700 __be32 residual_data_len; /* number of bytes in the host data */
701 /* buffers that were not used by the IOARCB command. */
702
703 __be32 ilid;
704#define IPR_NO_ILID 0
705#define IPR_DRIVER_ILID 0xffffffff
706
707 __be32 fd_ioasc;
708
709 __be32 fd_phys_locator;
710
711 __be32 fd_res_handle;
712
713 __be32 ioasc_specific; /* status code specific field */
714#define IPR_ADDITIONAL_STATUS_FMT 0x80000000
715#define IPR_AUTOSENSE_VALID 0x40000000
716#define IPR_ATA_DEVICE_WAS_RESET 0x20000000
717#define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
718#define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
719#define IPR_FIELD_POINTER_MASK 0x0000ffff
720
721}__attribute__((packed, aligned (4)));
722
723struct ipr_ioasa {
724 struct ipr_ioasa_hdr hdr;
725
726 union {
727 struct ipr_ioasa_vset vset;
728 struct ipr_ioasa_af_dasd dasd;
729 struct ipr_ioasa_gpdd gpdd;
730 struct ipr_ioasa_gata gata;
731 } u;
732
733 struct ipr_auto_sense auto_sense;
734}__attribute__((packed, aligned (4)));
735
736struct ipr_ioasa64 {
737 struct ipr_ioasa_hdr hdr;
738 u8 fd_res_path[8];
739
740 union {
741 struct ipr_ioasa_vset vset;
742 struct ipr_ioasa_af_dasd dasd;
743 struct ipr_ioasa_gpdd gpdd;
744 struct ipr_ioasa_gata gata;
745 } u;
746
747 struct ipr_auto_sense auto_sense;
748}__attribute__((packed, aligned (4)));
749
750struct ipr_mode_parm_hdr {
751 u8 length;
752 u8 medium_type;
753 u8 device_spec_parms;
754 u8 block_desc_len;
755}__attribute__((packed));
756
757struct ipr_mode_pages {
758 struct ipr_mode_parm_hdr hdr;
759 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
760}__attribute__((packed));
761
762struct ipr_mode_page_hdr {
763 u8 ps_page_code;
764#define IPR_MODE_PAGE_PS 0x80
765#define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
766 u8 page_length;
767}__attribute__ ((packed));
768
769struct ipr_dev_bus_entry {
770 struct ipr_res_addr res_addr;
771 u8 flags;
772#define IPR_SCSI_ATTR_ENABLE_QAS 0x80
773#define IPR_SCSI_ATTR_DISABLE_QAS 0x40
774#define IPR_SCSI_ATTR_QAS_MASK 0xC0
775#define IPR_SCSI_ATTR_ENABLE_TM 0x20
776#define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
777#define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
778#define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
779
780 u8 scsi_id;
781 u8 bus_width;
782 u8 extended_reset_delay;
783#define IPR_EXTENDED_RESET_DELAY 7
784
785 __be32 max_xfer_rate;
786
787 u8 spinup_delay;
788 u8 reserved3;
789 __be16 reserved4;
790}__attribute__((packed, aligned (4)));
791
792struct ipr_mode_page28 {
793 struct ipr_mode_page_hdr hdr;
794 u8 num_entries;
795 u8 entry_length;
796 struct ipr_dev_bus_entry bus[];
797}__attribute__((packed));
798
799struct ipr_mode_page24 {
800 struct ipr_mode_page_hdr hdr;
801 u8 flags;
802#define IPR_ENABLE_DUAL_IOA_AF 0x80
803}__attribute__((packed));
804
805struct ipr_ioa_vpd {
806 struct ipr_std_inq_data std_inq_data;
807 u8 ascii_part_num[12];
808 u8 reserved[40];
809 u8 ascii_plant_code[4];
810}__attribute__((packed));
811
812struct ipr_inquiry_page3 {
813 u8 peri_qual_dev_type;
814 u8 page_code;
815 u8 reserved1;
816 u8 page_length;
817 u8 ascii_len;
818 u8 reserved2[3];
819 u8 load_id[4];
820 u8 major_release;
821 u8 card_type;
822 u8 minor_release[2];
823 u8 ptf_number[4];
824 u8 patch_number[4];
825}__attribute__((packed));
826
827struct ipr_inquiry_cap {
828 u8 peri_qual_dev_type;
829 u8 page_code;
830 u8 reserved1;
831 u8 page_length;
832 u8 ascii_len;
833 u8 reserved2;
834 u8 sis_version[2];
835 u8 cap;
836#define IPR_CAP_DUAL_IOA_RAID 0x80
837 u8 reserved3[15];
838}__attribute__((packed));
839
840#define IPR_INQUIRY_PAGE0_ENTRIES 20
841struct ipr_inquiry_page0 {
842 u8 peri_qual_dev_type;
843 u8 page_code;
844 u8 reserved1;
845 u8 len;
846 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
847}__attribute__((packed));
848
849struct ipr_inquiry_pageC4 {
850 u8 peri_qual_dev_type;
851 u8 page_code;
852 u8 reserved1;
853 u8 len;
854 u8 cache_cap[4];
855#define IPR_CAP_SYNC_CACHE 0x08
856 u8 reserved2[20];
857} __packed;
858
859struct ipr_hostrcb_device_data_entry {
860 struct ipr_vpd vpd;
861 struct ipr_res_addr dev_res_addr;
862 struct ipr_vpd new_vpd;
863 struct ipr_vpd ioa_last_with_dev_vpd;
864 struct ipr_vpd cfc_last_with_dev_vpd;
865 __be32 ioa_data[5];
866}__attribute__((packed, aligned (4)));
867
868struct ipr_hostrcb_device_data_entry_enhanced {
869 struct ipr_ext_vpd vpd;
870 u8 ccin[4];
871 struct ipr_res_addr dev_res_addr;
872 struct ipr_ext_vpd new_vpd;
873 u8 new_ccin[4];
874 struct ipr_ext_vpd ioa_last_with_dev_vpd;
875 struct ipr_ext_vpd cfc_last_with_dev_vpd;
876}__attribute__((packed, aligned (4)));
877
878struct ipr_hostrcb64_device_data_entry_enhanced {
879 struct ipr_ext_vpd vpd;
880 u8 ccin[4];
881 u8 res_path[8];
882 struct ipr_ext_vpd new_vpd;
883 u8 new_ccin[4];
884 struct ipr_ext_vpd ioa_last_with_dev_vpd;
885 struct ipr_ext_vpd cfc_last_with_dev_vpd;
886}__attribute__((packed, aligned (4)));
887
888struct ipr_hostrcb_array_data_entry {
889 struct ipr_vpd vpd;
890 struct ipr_res_addr expected_dev_res_addr;
891 struct ipr_res_addr dev_res_addr;
892}__attribute__((packed, aligned (4)));
893
894struct ipr_hostrcb64_array_data_entry {
895 struct ipr_ext_vpd vpd;
896 u8 ccin[4];
897 u8 expected_res_path[8];
898 u8 res_path[8];
899}__attribute__((packed, aligned (4)));
900
901struct ipr_hostrcb_array_data_entry_enhanced {
902 struct ipr_ext_vpd vpd;
903 u8 ccin[4];
904 struct ipr_res_addr expected_dev_res_addr;
905 struct ipr_res_addr dev_res_addr;
906}__attribute__((packed, aligned (4)));
907
908struct ipr_hostrcb_type_ff_error {
909 __be32 ioa_data[758];
910}__attribute__((packed, aligned (4)));
911
912struct ipr_hostrcb_type_01_error {
913 __be32 seek_counter;
914 __be32 read_counter;
915 u8 sense_data[32];
916 __be32 ioa_data[236];
917}__attribute__((packed, aligned (4)));
918
919struct ipr_hostrcb_type_21_error {
920 __be32 wwn[4];
921 u8 res_path[8];
922 u8 primary_problem_desc[32];
923 u8 second_problem_desc[32];
924 __be32 sense_data[8];
925 __be32 cdb[4];
926 __be32 residual_trans_length;
927 __be32 length_of_error;
928 __be32 ioa_data[236];
929}__attribute__((packed, aligned (4)));
930
931struct ipr_hostrcb_type_02_error {
932 struct ipr_vpd ioa_vpd;
933 struct ipr_vpd cfc_vpd;
934 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
935 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
936 __be32 ioa_data[3];
937}__attribute__((packed, aligned (4)));
938
939struct ipr_hostrcb_type_12_error {
940 struct ipr_ext_vpd ioa_vpd;
941 struct ipr_ext_vpd cfc_vpd;
942 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
943 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
944 __be32 ioa_data[3];
945}__attribute__((packed, aligned (4)));
946
947struct ipr_hostrcb_type_03_error {
948 struct ipr_vpd ioa_vpd;
949 struct ipr_vpd cfc_vpd;
950 __be32 errors_detected;
951 __be32 errors_logged;
952 u8 ioa_data[12];
953 struct ipr_hostrcb_device_data_entry dev[3];
954}__attribute__((packed, aligned (4)));
955
956struct ipr_hostrcb_type_13_error {
957 struct ipr_ext_vpd ioa_vpd;
958 struct ipr_ext_vpd cfc_vpd;
959 __be32 errors_detected;
960 __be32 errors_logged;
961 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
962}__attribute__((packed, aligned (4)));
963
964struct ipr_hostrcb_type_23_error {
965 struct ipr_ext_vpd ioa_vpd;
966 struct ipr_ext_vpd cfc_vpd;
967 __be32 errors_detected;
968 __be32 errors_logged;
969 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
970}__attribute__((packed, aligned (4)));
971
972struct ipr_hostrcb_type_04_error {
973 struct ipr_vpd ioa_vpd;
974 struct ipr_vpd cfc_vpd;
975 u8 ioa_data[12];
976 struct ipr_hostrcb_array_data_entry array_member[10];
977 __be32 exposed_mode_adn;
978 __be32 array_id;
979 struct ipr_vpd incomp_dev_vpd;
980 __be32 ioa_data2;
981 struct ipr_hostrcb_array_data_entry array_member2[8];
982 struct ipr_res_addr last_func_vset_res_addr;
983 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
984 u8 protection_level[8];
985}__attribute__((packed, aligned (4)));
986
987struct ipr_hostrcb_type_14_error {
988 struct ipr_ext_vpd ioa_vpd;
989 struct ipr_ext_vpd cfc_vpd;
990 __be32 exposed_mode_adn;
991 __be32 array_id;
992 struct ipr_res_addr last_func_vset_res_addr;
993 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
994 u8 protection_level[8];
995 __be32 num_entries;
996 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
997}__attribute__((packed, aligned (4)));
998
999struct ipr_hostrcb_type_24_error {
1000 struct ipr_ext_vpd ioa_vpd;
1001 struct ipr_ext_vpd cfc_vpd;
1002 u8 reserved[2];
1003 u8 exposed_mode_adn;
1004#define IPR_INVALID_ARRAY_DEV_NUM 0xff
1005 u8 array_id;
1006 u8 last_res_path[8];
1007 u8 protection_level[8];
1008 struct ipr_ext_vpd64 array_vpd;
1009 u8 description[16];
1010 u8 reserved2[3];
1011 u8 num_entries;
1012 struct ipr_hostrcb64_array_data_entry array_member[32];
1013}__attribute__((packed, aligned (4)));
1014
1015struct ipr_hostrcb_type_07_error {
1016 u8 failure_reason[64];
1017 struct ipr_vpd vpd;
1018 __be32 data[222];
1019}__attribute__((packed, aligned (4)));
1020
1021struct ipr_hostrcb_type_17_error {
1022 u8 failure_reason[64];
1023 struct ipr_ext_vpd vpd;
1024 __be32 data[476];
1025}__attribute__((packed, aligned (4)));
1026
1027struct ipr_hostrcb_config_element {
1028 u8 type_status;
1029#define IPR_PATH_CFG_TYPE_MASK 0xF0
1030#define IPR_PATH_CFG_NOT_EXIST 0x00
1031#define IPR_PATH_CFG_IOA_PORT 0x10
1032#define IPR_PATH_CFG_EXP_PORT 0x20
1033#define IPR_PATH_CFG_DEVICE_PORT 0x30
1034#define IPR_PATH_CFG_DEVICE_LUN 0x40
1035
1036#define IPR_PATH_CFG_STATUS_MASK 0x0F
1037#define IPR_PATH_CFG_NO_PROB 0x00
1038#define IPR_PATH_CFG_DEGRADED 0x01
1039#define IPR_PATH_CFG_FAILED 0x02
1040#define IPR_PATH_CFG_SUSPECT 0x03
1041#define IPR_PATH_NOT_DETECTED 0x04
1042#define IPR_PATH_INCORRECT_CONN 0x05
1043
1044 u8 cascaded_expander;
1045 u8 phy;
1046 u8 link_rate;
1047#define IPR_PHY_LINK_RATE_MASK 0x0F
1048
1049 __be32 wwid[2];
1050}__attribute__((packed, aligned (4)));
1051
1052struct ipr_hostrcb64_config_element {
1053 __be16 length;
1054 u8 descriptor_id;
1055#define IPR_DESCRIPTOR_MASK 0xC0
1056#define IPR_DESCRIPTOR_SIS64 0x00
1057
1058 u8 reserved;
1059 u8 type_status;
1060
1061 u8 reserved2[2];
1062 u8 link_rate;
1063
1064 u8 res_path[8];
1065 __be32 wwid[2];
1066}__attribute__((packed, aligned (8)));
1067
1068struct ipr_hostrcb_fabric_desc {
1069 __be16 length;
1070 u8 ioa_port;
1071 u8 cascaded_expander;
1072 u8 phy;
1073 u8 path_state;
1074#define IPR_PATH_ACTIVE_MASK 0xC0
1075#define IPR_PATH_NO_INFO 0x00
1076#define IPR_PATH_ACTIVE 0x40
1077#define IPR_PATH_NOT_ACTIVE 0x80
1078
1079#define IPR_PATH_STATE_MASK 0x0F
1080#define IPR_PATH_STATE_NO_INFO 0x00
1081#define IPR_PATH_HEALTHY 0x01
1082#define IPR_PATH_DEGRADED 0x02
1083#define IPR_PATH_FAILED 0x03
1084
1085 __be16 num_entries;
1086 struct ipr_hostrcb_config_element elem[1];
1087}__attribute__((packed, aligned (4)));
1088
1089struct ipr_hostrcb64_fabric_desc {
1090 __be16 length;
1091 u8 descriptor_id;
1092
1093 u8 reserved[2];
1094 u8 path_state;
1095
1096 u8 reserved2[2];
1097 u8 res_path[8];
1098 u8 reserved3[6];
1099 __be16 num_entries;
1100 struct ipr_hostrcb64_config_element elem[1];
1101}__attribute__((packed, aligned (8)));
1102
1103#define for_each_hrrq(hrrq, ioa_cfg) \
1104 for (hrrq = (ioa_cfg)->hrrq; \
1105 hrrq < ((ioa_cfg)->hrrq + (ioa_cfg)->hrrq_num); hrrq++)
1106
1107#define for_each_fabric_cfg(fabric, cfg) \
1108 for (cfg = (fabric)->elem; \
1109 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1110 cfg++)
1111
1112struct ipr_hostrcb_type_20_error {
1113 u8 failure_reason[64];
1114 u8 reserved[3];
1115 u8 num_entries;
1116 struct ipr_hostrcb_fabric_desc desc[1];
1117}__attribute__((packed, aligned (4)));
1118
1119struct ipr_hostrcb_type_30_error {
1120 u8 failure_reason[64];
1121 u8 reserved[3];
1122 u8 num_entries;
1123 struct ipr_hostrcb64_fabric_desc desc[1];
1124}__attribute__((packed, aligned (4)));
1125
1126struct ipr_hostrcb_type_41_error {
1127 u8 failure_reason[64];
1128 __be32 data[200];
1129}__attribute__((packed, aligned (4)));
1130
1131struct ipr_hostrcb_error {
1132 __be32 fd_ioasc;
1133 struct ipr_res_addr fd_res_addr;
1134 __be32 fd_res_handle;
1135 __be32 prc;
1136 union {
1137 struct ipr_hostrcb_type_ff_error type_ff_error;
1138 struct ipr_hostrcb_type_01_error type_01_error;
1139 struct ipr_hostrcb_type_02_error type_02_error;
1140 struct ipr_hostrcb_type_03_error type_03_error;
1141 struct ipr_hostrcb_type_04_error type_04_error;
1142 struct ipr_hostrcb_type_07_error type_07_error;
1143 struct ipr_hostrcb_type_12_error type_12_error;
1144 struct ipr_hostrcb_type_13_error type_13_error;
1145 struct ipr_hostrcb_type_14_error type_14_error;
1146 struct ipr_hostrcb_type_17_error type_17_error;
1147 struct ipr_hostrcb_type_20_error type_20_error;
1148 } u;
1149}__attribute__((packed, aligned (4)));
1150
1151struct ipr_hostrcb64_error {
1152 __be32 fd_ioasc;
1153 __be32 ioa_fw_level;
1154 __be32 fd_res_handle;
1155 __be32 prc;
1156 __be64 fd_dev_id;
1157 __be64 fd_lun;
1158 u8 fd_res_path[8];
1159 __be64 time_stamp;
1160 u8 reserved[16];
1161 union {
1162 struct ipr_hostrcb_type_ff_error type_ff_error;
1163 struct ipr_hostrcb_type_12_error type_12_error;
1164 struct ipr_hostrcb_type_17_error type_17_error;
1165 struct ipr_hostrcb_type_21_error type_21_error;
1166 struct ipr_hostrcb_type_23_error type_23_error;
1167 struct ipr_hostrcb_type_24_error type_24_error;
1168 struct ipr_hostrcb_type_30_error type_30_error;
1169 struct ipr_hostrcb_type_41_error type_41_error;
1170 } u;
1171}__attribute__((packed, aligned (8)));
1172
1173struct ipr_hostrcb_raw {
1174 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1175}__attribute__((packed, aligned (4)));
1176
1177struct ipr_hcam {
1178 u8 op_code;
1179#define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1180#define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1181
1182 u8 notify_type;
1183#define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1184#define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1185#define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1186#define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1187#define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1188
1189 u8 notifications_lost;
1190#define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1191#define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1192
1193 u8 flags;
1194#define IPR_HOSTRCB_INTERNAL_OPER 0x80
1195#define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1196
1197 u8 overlay_id;
1198#define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1199#define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1200#define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1201#define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1202#define IPR_HOST_RCB_OVERLAY_ID_6 0x06
1203#define IPR_HOST_RCB_OVERLAY_ID_7 0x07
1204#define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1205#define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1206#define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1207#define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1208#define IPR_HOST_RCB_OVERLAY_ID_17 0x17
1209#define IPR_HOST_RCB_OVERLAY_ID_20 0x20
1210#define IPR_HOST_RCB_OVERLAY_ID_21 0x21
1211#define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1212#define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1213#define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1214#define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1215#define IPR_HOST_RCB_OVERLAY_ID_41 0x41
1216#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1217
1218 u8 reserved1[3];
1219 __be32 ilid;
1220 __be32 time_since_last_ioa_reset;
1221 __be32 reserved2;
1222 __be32 length;
1223
1224 union {
1225 struct ipr_hostrcb_error error;
1226 struct ipr_hostrcb64_error error64;
1227 struct ipr_hostrcb_cfg_ch_not ccn;
1228 struct ipr_hostrcb_raw raw;
1229 } u;
1230}__attribute__((packed, aligned (4)));
1231
1232struct ipr_hostrcb {
1233 struct ipr_hcam hcam;
1234 dma_addr_t hostrcb_dma;
1235 struct list_head queue;
1236 struct ipr_ioa_cfg *ioa_cfg;
1237 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1238};
1239
1240/* IPR smart dump table structures */
1241struct ipr_sdt_entry {
1242 __be32 start_token;
1243 __be32 end_token;
1244 u8 reserved[4];
1245
1246 u8 flags;
1247#define IPR_SDT_ENDIAN 0x80
1248#define IPR_SDT_VALID_ENTRY 0x20
1249
1250 u8 resv;
1251 __be16 priority;
1252}__attribute__((packed, aligned (4)));
1253
1254struct ipr_sdt_header {
1255 __be32 state;
1256 __be32 num_entries;
1257 __be32 num_entries_used;
1258 __be32 dump_size;
1259}__attribute__((packed, aligned (4)));
1260
1261struct ipr_sdt {
1262 struct ipr_sdt_header hdr;
1263 struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES];
1264}__attribute__((packed, aligned (4)));
1265
1266struct ipr_uc_sdt {
1267 struct ipr_sdt_header hdr;
1268 struct ipr_sdt_entry entry[1];
1269}__attribute__((packed, aligned (4)));
1270
1271/*
1272 * Driver types
1273 */
1274struct ipr_bus_attributes {
1275 u8 bus;
1276 u8 qas_enabled;
1277 u8 bus_width;
1278 u8 reserved;
1279 u32 max_xfer_rate;
1280};
1281
1282struct ipr_sata_port {
1283 struct ipr_ioa_cfg *ioa_cfg;
1284 struct ata_port *ap;
1285 struct ipr_resource_entry *res;
1286 struct ipr_ioasa_gata ioasa;
1287};
1288
1289struct ipr_resource_entry {
1290 u8 needs_sync_complete:1;
1291 u8 in_erp:1;
1292 u8 add_to_ml:1;
1293 u8 del_from_ml:1;
1294 u8 resetting_device:1;
1295 u8 reset_occurred:1;
1296 u8 raw_mode:1;
1297
1298 u32 bus; /* AKA channel */
1299 u32 target; /* AKA id */
1300 u32 lun;
1301#define IPR_ARRAY_VIRTUAL_BUS 0x1
1302#define IPR_VSET_VIRTUAL_BUS 0x2
1303#define IPR_IOAFP_VIRTUAL_BUS 0x3
1304#define IPR_MAX_SIS64_BUSES 0x4
1305
1306#define IPR_GET_RES_PHYS_LOC(res) \
1307 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1308
1309 u8 ata_class;
1310 u8 type;
1311
1312 u16 flags;
1313 u16 res_flags;
1314
1315 u8 qmodel;
1316 struct ipr_std_inq_data std_inq_data;
1317
1318 __be32 res_handle;
1319 __be64 dev_id;
1320 u64 lun_wwn;
1321 struct scsi_lun dev_lun;
1322 u8 res_path[8];
1323
1324 struct ipr_ioa_cfg *ioa_cfg;
1325 struct scsi_device *sdev;
1326 struct ipr_sata_port *sata_port;
1327 struct list_head queue;
1328}; /* struct ipr_resource_entry */
1329
1330struct ipr_resource_hdr {
1331 u16 num_entries;
1332 u16 reserved;
1333};
1334
1335struct ipr_misc_cbs {
1336 struct ipr_ioa_vpd ioa_vpd;
1337 struct ipr_inquiry_page0 page0_data;
1338 struct ipr_inquiry_page3 page3_data;
1339 struct ipr_inquiry_cap cap;
1340 struct ipr_inquiry_pageC4 pageC4_data;
1341 struct ipr_mode_pages mode_pages;
1342 struct ipr_supported_device supp_dev;
1343};
1344
1345struct ipr_interrupt_offsets {
1346 unsigned long set_interrupt_mask_reg;
1347 unsigned long clr_interrupt_mask_reg;
1348 unsigned long clr_interrupt_mask_reg32;
1349 unsigned long sense_interrupt_mask_reg;
1350 unsigned long sense_interrupt_mask_reg32;
1351 unsigned long clr_interrupt_reg;
1352 unsigned long clr_interrupt_reg32;
1353
1354 unsigned long sense_interrupt_reg;
1355 unsigned long sense_interrupt_reg32;
1356 unsigned long ioarrin_reg;
1357 unsigned long sense_uproc_interrupt_reg;
1358 unsigned long sense_uproc_interrupt_reg32;
1359 unsigned long set_uproc_interrupt_reg;
1360 unsigned long set_uproc_interrupt_reg32;
1361 unsigned long clr_uproc_interrupt_reg;
1362 unsigned long clr_uproc_interrupt_reg32;
1363
1364 unsigned long init_feedback_reg;
1365
1366 unsigned long dump_addr_reg;
1367 unsigned long dump_data_reg;
1368
1369#define IPR_ENDIAN_SWAP_KEY 0x00080800
1370 unsigned long endian_swap_reg;
1371};
1372
1373struct ipr_interrupts {
1374 void __iomem *set_interrupt_mask_reg;
1375 void __iomem *clr_interrupt_mask_reg;
1376 void __iomem *clr_interrupt_mask_reg32;
1377 void __iomem *sense_interrupt_mask_reg;
1378 void __iomem *sense_interrupt_mask_reg32;
1379 void __iomem *clr_interrupt_reg;
1380 void __iomem *clr_interrupt_reg32;
1381
1382 void __iomem *sense_interrupt_reg;
1383 void __iomem *sense_interrupt_reg32;
1384 void __iomem *ioarrin_reg;
1385 void __iomem *sense_uproc_interrupt_reg;
1386 void __iomem *sense_uproc_interrupt_reg32;
1387 void __iomem *set_uproc_interrupt_reg;
1388 void __iomem *set_uproc_interrupt_reg32;
1389 void __iomem *clr_uproc_interrupt_reg;
1390 void __iomem *clr_uproc_interrupt_reg32;
1391
1392 void __iomem *init_feedback_reg;
1393
1394 void __iomem *dump_addr_reg;
1395 void __iomem *dump_data_reg;
1396
1397 void __iomem *endian_swap_reg;
1398};
1399
1400struct ipr_chip_cfg_t {
1401 u32 mailbox;
1402 u16 max_cmds;
1403 u8 cache_line_size;
1404 u8 clear_isr;
1405 u32 iopoll_weight;
1406 struct ipr_interrupt_offsets regs;
1407};
1408
1409struct ipr_chip_t {
1410 u16 vendor;
1411 u16 device;
1412 bool has_msi;
1413 u16 sis_type;
1414#define IPR_SIS32 0x00
1415#define IPR_SIS64 0x01
1416 u16 bist_method;
1417#define IPR_PCI_CFG 0x00
1418#define IPR_MMIO 0x01
1419 const struct ipr_chip_cfg_t *cfg;
1420};
1421
1422enum ipr_shutdown_type {
1423 IPR_SHUTDOWN_NORMAL = 0x00,
1424 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1425 IPR_SHUTDOWN_ABBREV = 0x80,
1426 IPR_SHUTDOWN_NONE = 0x100,
1427 IPR_SHUTDOWN_QUIESCE = 0x101,
1428};
1429
1430struct ipr_trace_entry {
1431 u32 time;
1432
1433 u8 op_code;
1434 u8 ata_op_code;
1435 u8 type;
1436#define IPR_TRACE_START 0x00
1437#define IPR_TRACE_FINISH 0xff
1438 u8 cmd_index;
1439
1440 __be32 res_handle;
1441 union {
1442 u32 ioasc;
1443 u32 add_data;
1444 u32 res_addr;
1445 } u;
1446};
1447
1448struct ipr_sglist {
1449 u32 order;
1450 u32 num_sg;
1451 u32 num_dma_sg;
1452 u32 buffer_len;
1453 struct scatterlist *scatterlist;
1454};
1455
1456enum ipr_sdt_state {
1457 INACTIVE,
1458 WAIT_FOR_DUMP,
1459 GET_DUMP,
1460 READ_DUMP,
1461 ABORT_DUMP,
1462 DUMP_OBTAINED
1463};
1464
1465/* Per-controller data */
1466struct ipr_ioa_cfg {
1467 char eye_catcher[8];
1468#define IPR_EYECATCHER "iprcfg"
1469
1470 struct list_head queue;
1471
1472 u8 in_reset_reload:1;
1473 u8 in_ioa_bringdown:1;
1474 u8 ioa_unit_checked:1;
1475 u8 dump_taken:1;
1476 u8 scan_enabled:1;
1477 u8 scan_done:1;
1478 u8 needs_hard_reset:1;
1479 u8 dual_raid:1;
1480 u8 needs_warm_reset:1;
1481 u8 msi_received:1;
1482 u8 sis64:1;
1483 u8 dump_timeout:1;
1484 u8 cfg_locked:1;
1485 u8 clear_isr:1;
1486 u8 probe_done:1;
1487 u8 scsi_unblock:1;
1488 u8 scsi_blocked:1;
1489
1490 u8 revid;
1491
1492 /*
1493 * Bitmaps for SIS64 generated target values
1494 */
1495 unsigned long target_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1496 unsigned long array_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1497 unsigned long vset_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1498
1499 u16 type; /* CCIN of the card */
1500
1501 u8 log_level;
1502#define IPR_MAX_LOG_LEVEL 4
1503#define IPR_DEFAULT_LOG_LEVEL 2
1504#define IPR_DEBUG_LOG_LEVEL 3
1505
1506#define IPR_NUM_TRACE_INDEX_BITS 8
1507#define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1508#define IPR_TRACE_INDEX_MASK (IPR_NUM_TRACE_ENTRIES - 1)
1509#define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1510 char trace_start[8];
1511#define IPR_TRACE_START_LABEL "trace"
1512 struct ipr_trace_entry *trace;
1513 atomic_t trace_index;
1514
1515 char cfg_table_start[8];
1516#define IPR_CFG_TBL_START "cfg"
1517 union {
1518 struct ipr_config_table *cfg_table;
1519 struct ipr_config_table64 *cfg_table64;
1520 } u;
1521 dma_addr_t cfg_table_dma;
1522 u32 cfg_table_size;
1523 u32 max_devs_supported;
1524
1525 char resource_table_label[8];
1526#define IPR_RES_TABLE_LABEL "res_tbl"
1527 struct ipr_resource_entry *res_entries;
1528 struct list_head free_res_q;
1529 struct list_head used_res_q;
1530
1531 char ipr_hcam_label[8];
1532#define IPR_HCAM_LABEL "hcams"
1533 struct ipr_hostrcb *hostrcb[IPR_MAX_HCAMS];
1534 dma_addr_t hostrcb_dma[IPR_MAX_HCAMS];
1535 struct list_head hostrcb_free_q;
1536 struct list_head hostrcb_pending_q;
1537 struct list_head hostrcb_report_q;
1538
1539 struct ipr_hrr_queue hrrq[IPR_MAX_HRRQ_NUM];
1540 u32 hrrq_num;
1541 atomic_t hrrq_index;
1542 u16 identify_hrrq_index;
1543
1544 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1545
1546 unsigned int transop_timeout;
1547 const struct ipr_chip_cfg_t *chip_cfg;
1548 const struct ipr_chip_t *ipr_chip;
1549
1550 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1551 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1552 void __iomem *ioa_mailbox;
1553 struct ipr_interrupts regs;
1554
1555 u16 saved_pcix_cmd_reg;
1556 u16 reset_retries;
1557
1558 u32 errors_logged;
1559 u32 doorbell;
1560
1561 struct Scsi_Host *host;
1562 struct pci_dev *pdev;
1563 struct ipr_sglist *ucode_sglist;
1564 u8 saved_mode_page_len;
1565
1566 struct work_struct work_q;
1567 struct work_struct scsi_add_work_q;
1568 struct workqueue_struct *reset_work_q;
1569
1570 wait_queue_head_t reset_wait_q;
1571 wait_queue_head_t msi_wait_q;
1572 wait_queue_head_t eeh_wait_q;
1573
1574 struct ipr_dump *dump;
1575 enum ipr_sdt_state sdt_state;
1576
1577 struct ipr_misc_cbs *vpd_cbs;
1578 dma_addr_t vpd_cbs_dma;
1579
1580 struct dma_pool *ipr_cmd_pool;
1581
1582 struct ipr_cmnd *reset_cmd;
1583 int (*reset) (struct ipr_cmnd *);
1584
1585 struct ata_host ata_host;
1586 char ipr_cmd_label[8];
1587#define IPR_CMD_LABEL "ipr_cmd"
1588 u32 max_cmds;
1589 struct ipr_cmnd **ipr_cmnd_list;
1590 dma_addr_t *ipr_cmnd_list_dma;
1591
1592 unsigned int nvectors;
1593
1594 struct {
1595 char desc[22];
1596 } vectors_info[IPR_MAX_MSIX_VECTORS];
1597
1598 u32 iopoll_weight;
1599
1600}; /* struct ipr_ioa_cfg */
1601
1602struct ipr_cmnd {
1603 struct ipr_ioarcb ioarcb;
1604 union {
1605 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1606 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1607 struct ipr_ata64_ioadl ata_ioadl;
1608 } i;
1609 union {
1610 struct ipr_ioasa ioasa;
1611 struct ipr_ioasa64 ioasa64;
1612 } s;
1613 struct list_head queue;
1614 struct scsi_cmnd *scsi_cmd;
1615 struct ata_queued_cmd *qc;
1616 struct completion completion;
1617 struct timer_list timer;
1618 struct work_struct work;
1619 void (*fast_done) (struct ipr_cmnd *);
1620 void (*done) (struct ipr_cmnd *);
1621 int (*job_step) (struct ipr_cmnd *);
1622 int (*job_step_failed) (struct ipr_cmnd *);
1623 u16 cmd_index;
1624 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1625 dma_addr_t sense_buffer_dma;
1626 unsigned short dma_use_sg;
1627 dma_addr_t dma_addr;
1628 struct ipr_cmnd *sibling;
1629 union {
1630 enum ipr_shutdown_type shutdown_type;
1631 struct ipr_hostrcb *hostrcb;
1632 unsigned long time_left;
1633 unsigned long scratch;
1634 struct ipr_resource_entry *res;
1635 struct scsi_device *sdev;
1636 } u;
1637
1638 struct completion *eh_comp;
1639 struct ipr_hrr_queue *hrrq;
1640 struct ipr_ioa_cfg *ioa_cfg;
1641};
1642
1643struct ipr_ses_table_entry {
1644 char product_id[17];
1645 char compare_product_id_byte[17];
1646 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1647};
1648
1649struct ipr_dump_header {
1650 u32 eye_catcher;
1651#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1652 u32 len;
1653 u32 num_entries;
1654 u32 first_entry_offset;
1655 u32 status;
1656#define IPR_DUMP_STATUS_SUCCESS 0
1657#define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1658#define IPR_DUMP_STATUS_FAILED 0xffffffff
1659 u32 os;
1660#define IPR_DUMP_OS_LINUX 0x4C4E5558
1661 u32 driver_name;
1662#define IPR_DUMP_DRIVER_NAME 0x49505232
1663}__attribute__((packed, aligned (4)));
1664
1665struct ipr_dump_entry_header {
1666 u32 eye_catcher;
1667#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1668 u32 len;
1669 u32 num_elems;
1670 u32 offset;
1671 u32 data_type;
1672#define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1673#define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1674 u32 id;
1675#define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1676#define IPR_DUMP_LOCATION_ID 0x4C4F4341
1677#define IPR_DUMP_TRACE_ID 0x54524143
1678#define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1679#define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1680#define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1681#define IPR_DUMP_PEND_OPS 0x414F5053
1682 u32 status;
1683}__attribute__((packed, aligned (4)));
1684
1685struct ipr_dump_location_entry {
1686 struct ipr_dump_entry_header hdr;
1687 u8 location[20];
1688}__attribute__((packed, aligned (4)));
1689
1690struct ipr_dump_trace_entry {
1691 struct ipr_dump_entry_header hdr;
1692 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1693}__attribute__((packed, aligned (4)));
1694
1695struct ipr_dump_version_entry {
1696 struct ipr_dump_entry_header hdr;
1697 u8 version[sizeof(IPR_DRIVER_VERSION)];
1698};
1699
1700struct ipr_dump_ioa_type_entry {
1701 struct ipr_dump_entry_header hdr;
1702 u32 type;
1703 u32 fw_version;
1704};
1705
1706struct ipr_driver_dump {
1707 struct ipr_dump_header hdr;
1708 struct ipr_dump_version_entry version_entry;
1709 struct ipr_dump_location_entry location_entry;
1710 struct ipr_dump_ioa_type_entry ioa_type_entry;
1711 struct ipr_dump_trace_entry trace_entry;
1712}__attribute__((packed, aligned (4)));
1713
1714struct ipr_ioa_dump {
1715 struct ipr_dump_entry_header hdr;
1716 struct ipr_sdt sdt;
1717 __be32 **ioa_data;
1718 u32 reserved;
1719 u32 next_page_index;
1720 u32 page_offset;
1721 u32 format;
1722}__attribute__((packed, aligned (4)));
1723
1724struct ipr_dump {
1725 struct kref kref;
1726 struct ipr_ioa_cfg *ioa_cfg;
1727 struct ipr_driver_dump driver_dump;
1728 struct ipr_ioa_dump ioa_dump;
1729};
1730
1731struct ipr_error_table_t {
1732 u32 ioasc;
1733 int log_ioasa;
1734 int log_hcam;
1735 char *error;
1736};
1737
1738struct ipr_software_inq_lid_info {
1739 __be32 load_id;
1740 __be32 timestamp[3];
1741}__attribute__((packed, aligned (4)));
1742
1743struct ipr_ucode_image_header {
1744 __be32 header_length;
1745 __be32 lid_table_offset;
1746 u8 major_release;
1747 u8 card_type;
1748 u8 minor_release[2];
1749 u8 reserved[20];
1750 char eyecatcher[16];
1751 __be32 num_lids;
1752 struct ipr_software_inq_lid_info lid[1];
1753}__attribute__((packed, aligned (4)));
1754
1755/*
1756 * Macros
1757 */
1758#define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1759
1760#ifdef CONFIG_SCSI_IPR_TRACE
1761#define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1762#define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1763#else
1764#define ipr_create_trace_file(kobj, attr) 0
1765#define ipr_remove_trace_file(kobj, attr) do { } while(0)
1766#endif
1767
1768#ifdef CONFIG_SCSI_IPR_DUMP
1769#define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1770#define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1771#else
1772#define ipr_create_dump_file(kobj, attr) 0
1773#define ipr_remove_dump_file(kobj, attr) do { } while(0)
1774#endif
1775
1776/*
1777 * Error logging macros
1778 */
1779#define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1780#define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1781#define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1782
1783#define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1784 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1785 bus, target, lun, ##__VA_ARGS__)
1786
1787#define ipr_res_err(ioa_cfg, res, fmt, ...) \
1788 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1789
1790#define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1791 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1792 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1793
1794#define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1795 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1796
1797#define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1798{ \
1799 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1800 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1801 } else { \
1802 ipr_err(fmt": %d:%d:%d:%d\n", \
1803 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1804 (res).bus, (res).target, (res).lun); \
1805 } \
1806}
1807
1808#define ipr_hcam_err(hostrcb, fmt, ...) \
1809{ \
1810 if (ipr_is_device(hostrcb)) { \
1811 if ((hostrcb)->ioa_cfg->sis64) { \
1812 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1813 ipr_format_res_path(hostrcb->ioa_cfg, \
1814 hostrcb->hcam.u.error64.fd_res_path, \
1815 hostrcb->rp_buffer, \
1816 sizeof(hostrcb->rp_buffer)), \
1817 __VA_ARGS__); \
1818 } else { \
1819 ipr_ra_err((hostrcb)->ioa_cfg, \
1820 (hostrcb)->hcam.u.error.fd_res_addr, \
1821 fmt, __VA_ARGS__); \
1822 } \
1823 } else { \
1824 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1825 } \
1826}
1827
1828#define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1829 __FILE__, __func__, __LINE__)
1830
1831#define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1832#define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1833
1834#define ipr_err_separator \
1835ipr_err("----------------------------------------------------------\n")
1836
1837
1838/*
1839 * Inlines
1840 */
1841
1842/**
1843 * ipr_is_ioa_resource - Determine if a resource is the IOA
1844 * @res: resource entry struct
1845 *
1846 * Return value:
1847 * 1 if IOA / 0 if not IOA
1848 **/
1849static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1850{
1851 return res->type == IPR_RES_TYPE_IOAFP;
1852}
1853
1854/**
1855 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1856 * @res: resource entry struct
1857 *
1858 * Return value:
1859 * 1 if AF DASD / 0 if not AF DASD
1860 **/
1861static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1862{
1863 return res->type == IPR_RES_TYPE_AF_DASD ||
1864 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1865}
1866
1867/**
1868 * ipr_is_vset_device - Determine if a resource is a VSET
1869 * @res: resource entry struct
1870 *
1871 * Return value:
1872 * 1 if VSET / 0 if not VSET
1873 **/
1874static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1875{
1876 return res->type == IPR_RES_TYPE_VOLUME_SET;
1877}
1878
1879/**
1880 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1881 * @res: resource entry struct
1882 *
1883 * Return value:
1884 * 1 if GSCSI / 0 if not GSCSI
1885 **/
1886static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1887{
1888 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1889}
1890
1891/**
1892 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1893 * @res: resource entry struct
1894 *
1895 * Return value:
1896 * 1 if SCSI disk / 0 if not SCSI disk
1897 **/
1898static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1899{
1900 if (ipr_is_af_dasd_device(res) ||
1901 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1902 return 1;
1903 else
1904 return 0;
1905}
1906
1907/**
1908 * ipr_is_gata - Determine if a resource is a generic ATA resource
1909 * @res: resource entry struct
1910 *
1911 * Return value:
1912 * 1 if GATA / 0 if not GATA
1913 **/
1914static inline int ipr_is_gata(struct ipr_resource_entry *res)
1915{
1916 return res->type == IPR_RES_TYPE_GENERIC_ATA;
1917}
1918
1919/**
1920 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1921 * @res: resource entry struct
1922 *
1923 * Return value:
1924 * 1 if NACA queueing model / 0 if not NACA queueing model
1925 **/
1926static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1927{
1928 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1929 return 1;
1930 return 0;
1931}
1932
1933/**
1934 * ipr_is_device - Determine if the hostrcb structure is related to a device
1935 * @hostrcb: host resource control blocks struct
1936 *
1937 * Return value:
1938 * 1 if AF / 0 if not AF
1939 **/
1940static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1941{
1942 struct ipr_res_addr *res_addr;
1943 u8 *res_path;
1944
1945 if (hostrcb->ioa_cfg->sis64) {
1946 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1947 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1948 res_path[0] == 0x81) && res_path[2] != 0xFF)
1949 return 1;
1950 } else {
1951 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1952
1953 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1954 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1955 return 1;
1956 }
1957 return 0;
1958}
1959
1960/**
1961 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1962 * @sdt_word: SDT address
1963 *
1964 * Return value:
1965 * 1 if format 2 / 0 if not
1966 **/
1967static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1968{
1969 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1970
1971 switch (bar_sel) {
1972 case IPR_SDT_FMT2_BAR0_SEL:
1973 case IPR_SDT_FMT2_BAR1_SEL:
1974 case IPR_SDT_FMT2_BAR2_SEL:
1975 case IPR_SDT_FMT2_BAR3_SEL:
1976 case IPR_SDT_FMT2_BAR4_SEL:
1977 case IPR_SDT_FMT2_BAR5_SEL:
1978 case IPR_SDT_FMT2_EXP_ROM_SEL:
1979 return 1;
1980 };
1981
1982 return 0;
1983}
1984
1985#ifndef writeq
1986static inline void writeq(u64 val, void __iomem *addr)
1987{
1988 writel(((u32) (val >> 32)), addr);
1989 writel(((u32) (val)), (addr + 4));
1990}
1991#endif
1992
1993#endif /* _IPR_H */