Loading...
1/*
2 * ipr.h -- driver for IBM Power Linux RAID adapters
3 *
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5 *
6 * Copyright (C) 2003, 2004 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
24 */
25
26#ifndef _IPR_H
27#define _IPR_H
28
29#include <asm/unaligned.h>
30#include <linux/types.h>
31#include <linux/completion.h>
32#include <linux/libata.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <scsi/scsi.h>
36#include <scsi/scsi_cmnd.h>
37
38/*
39 * Literals
40 */
41#define IPR_DRIVER_VERSION "2.5.3"
42#define IPR_DRIVER_DATE "(March 10, 2012)"
43
44/*
45 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
46 * ops per device for devices not running tagged command queuing.
47 * This can be adjusted at runtime through sysfs device attributes.
48 */
49#define IPR_MAX_CMD_PER_LUN 6
50#define IPR_MAX_CMD_PER_ATA_LUN 1
51
52/*
53 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
54 * ops the mid-layer can send to the adapter.
55 */
56#define IPR_NUM_BASE_CMD_BLKS (ioa_cfg->max_cmds)
57
58#define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
59
60#define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
61#define PCI_DEVICE_ID_IBM_CROCODILE 0x034A
62
63#define IPR_SUBS_DEV_ID_2780 0x0264
64#define IPR_SUBS_DEV_ID_5702 0x0266
65#define IPR_SUBS_DEV_ID_5703 0x0278
66#define IPR_SUBS_DEV_ID_572E 0x028D
67#define IPR_SUBS_DEV_ID_573E 0x02D3
68#define IPR_SUBS_DEV_ID_573D 0x02D4
69#define IPR_SUBS_DEV_ID_571A 0x02C0
70#define IPR_SUBS_DEV_ID_571B 0x02BE
71#define IPR_SUBS_DEV_ID_571E 0x02BF
72#define IPR_SUBS_DEV_ID_571F 0x02D5
73#define IPR_SUBS_DEV_ID_572A 0x02C1
74#define IPR_SUBS_DEV_ID_572B 0x02C2
75#define IPR_SUBS_DEV_ID_572F 0x02C3
76#define IPR_SUBS_DEV_ID_574E 0x030A
77#define IPR_SUBS_DEV_ID_575B 0x030D
78#define IPR_SUBS_DEV_ID_575C 0x0338
79#define IPR_SUBS_DEV_ID_57B3 0x033A
80#define IPR_SUBS_DEV_ID_57B7 0x0360
81#define IPR_SUBS_DEV_ID_57B8 0x02C2
82
83#define IPR_SUBS_DEV_ID_57B4 0x033B
84#define IPR_SUBS_DEV_ID_57B2 0x035F
85#define IPR_SUBS_DEV_ID_57C3 0x0353
86#define IPR_SUBS_DEV_ID_57C4 0x0354
87#define IPR_SUBS_DEV_ID_57C6 0x0357
88#define IPR_SUBS_DEV_ID_57CC 0x035C
89
90#define IPR_SUBS_DEV_ID_57B5 0x033C
91#define IPR_SUBS_DEV_ID_57CE 0x035E
92#define IPR_SUBS_DEV_ID_57B1 0x0355
93
94#define IPR_SUBS_DEV_ID_574D 0x0356
95#define IPR_SUBS_DEV_ID_57C8 0x035D
96
97#define IPR_NAME "ipr"
98
99/*
100 * Return codes
101 */
102#define IPR_RC_JOB_CONTINUE 1
103#define IPR_RC_JOB_RETURN 2
104
105/*
106 * IOASCs
107 */
108#define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
109#define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
110#define IPR_IOASC_SYNC_REQUIRED 0x023f0000
111#define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
112#define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
113#define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
114#define IPR_IOASC_IOASC_MASK 0xFFFFFF00
115#define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
116#define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
117#define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
118#define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
119#define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
120#define IPR_IOASC_BUS_WAS_RESET 0x06290000
121#define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
122#define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
123
124#define IPR_FIRST_DRIVER_IOASC 0x10000000
125#define IPR_IOASC_IOA_WAS_RESET 0x10000001
126#define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
127
128/* Driver data flags */
129#define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
130#define IPR_USE_PCI_WARM_RESET 0x00000002
131
132#define IPR_DEFAULT_MAX_ERROR_DUMP 984
133#define IPR_NUM_LOG_HCAMS 2
134#define IPR_NUM_CFG_CHG_HCAMS 2
135#define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
136
137#define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
138#define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
139
140#define IPR_MAX_NUM_TARGETS_PER_BUS 256
141#define IPR_MAX_NUM_LUNS_PER_TARGET 256
142#define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
143#define IPR_VSET_BUS 0xff
144#define IPR_IOA_BUS 0xff
145#define IPR_IOA_TARGET 0xff
146#define IPR_IOA_LUN 0xff
147#define IPR_MAX_NUM_BUSES 16
148#define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
149
150#define IPR_NUM_RESET_RELOAD_RETRIES 3
151
152/* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
153#define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
154 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
155
156#define IPR_MAX_COMMANDS 100
157#define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
158 IPR_NUM_INTERNAL_CMD_BLKS)
159
160#define IPR_MAX_PHYSICAL_DEVS 192
161#define IPR_DEFAULT_SIS64_DEVS 1024
162#define IPR_MAX_SIS64_DEVS 4096
163
164#define IPR_MAX_SGLIST 64
165#define IPR_IOA_MAX_SECTORS 32767
166#define IPR_VSET_MAX_SECTORS 512
167#define IPR_MAX_CDB_LEN 16
168#define IPR_MAX_HRRQ_RETRIES 3
169
170#define IPR_DEFAULT_BUS_WIDTH 16
171#define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
172#define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
173#define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
174#define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
175
176#define IPR_IOA_RES_HANDLE 0xffffffff
177#define IPR_INVALID_RES_HANDLE 0
178#define IPR_IOA_RES_ADDR 0x00ffffff
179
180/*
181 * Adapter Commands
182 */
183#define IPR_QUERY_RSRC_STATE 0xC2
184#define IPR_RESET_DEVICE 0xC3
185#define IPR_RESET_TYPE_SELECT 0x80
186#define IPR_LUN_RESET 0x40
187#define IPR_TARGET_RESET 0x20
188#define IPR_BUS_RESET 0x10
189#define IPR_ATA_PHY_RESET 0x80
190#define IPR_ID_HOST_RR_Q 0xC4
191#define IPR_QUERY_IOA_CONFIG 0xC5
192#define IPR_CANCEL_ALL_REQUESTS 0xCE
193#define IPR_HOST_CONTROLLED_ASYNC 0xCF
194#define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
195#define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
196#define IPR_SET_SUPPORTED_DEVICES 0xFB
197#define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
198#define IPR_IOA_SHUTDOWN 0xF7
199#define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
200
201/*
202 * Timeouts
203 */
204#define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
205#define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
206#define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
207#define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
208#define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
209#define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
210#define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
211#define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
212#define IPR_WRITE_BUFFER_TIMEOUT (30 * 60 * HZ)
213#define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
214#define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
215#define IPR_OPERATIONAL_TIMEOUT (5 * 60)
216#define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
217#define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
218#define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
219#define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
220#define IPR_PCI_RESET_TIMEOUT (HZ / 2)
221#define IPR_SIS32_DUMP_TIMEOUT (15 * HZ)
222#define IPR_SIS64_DUMP_TIMEOUT (40 * HZ)
223#define IPR_DUMP_DELAY_SECONDS 4
224#define IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ)
225
226/*
227 * SCSI Literals
228 */
229#define IPR_VENDOR_ID_LEN 8
230#define IPR_PROD_ID_LEN 16
231#define IPR_SERIAL_NUM_LEN 8
232
233/*
234 * Hardware literals
235 */
236#define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
237#define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
238#define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
239#define IPR_GET_FMT2_BAR_SEL(mbx) \
240(((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
241#define IPR_SDT_FMT2_BAR0_SEL 0x0
242#define IPR_SDT_FMT2_BAR1_SEL 0x1
243#define IPR_SDT_FMT2_BAR2_SEL 0x2
244#define IPR_SDT_FMT2_BAR3_SEL 0x3
245#define IPR_SDT_FMT2_BAR4_SEL 0x4
246#define IPR_SDT_FMT2_BAR5_SEL 0x5
247#define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
248#define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
249#define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
250#define IPR_DOORBELL 0x82800000
251#define IPR_RUNTIME_RESET 0x40000000
252
253#define IPR_IPL_INIT_MIN_STAGE_TIME 5
254#define IPR_IPL_INIT_DEFAULT_STAGE_TIME 15
255#define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
256#define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
257#define IPR_IPL_INIT_STAGE_MASK 0xff000000
258#define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
259#define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
260
261#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
262#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
263#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
264#define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
265#define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
266#define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
267#define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
268#define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
269#define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
270#define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
271#define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
272
273#define IPR_PCII_ERROR_INTERRUPTS \
274(IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
275IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
276
277#define IPR_PCII_OPER_INTERRUPTS \
278(IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
279
280#define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
281#define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
282#define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23)
283
284#define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
285#define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
286
287/*
288 * Dump literals
289 */
290#define IPR_FMT2_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
291#define IPR_FMT3_MAX_IOA_DUMP_SIZE (32 * 1024 * 1024)
292#define IPR_FMT2_NUM_SDT_ENTRIES 511
293#define IPR_FMT3_NUM_SDT_ENTRIES 0xFFF
294#define IPR_FMT2_MAX_NUM_DUMP_PAGES ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
295#define IPR_FMT3_MAX_NUM_DUMP_PAGES ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
296
297/*
298 * Misc literals
299 */
300#define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
301
302/*
303 * Adapter interface types
304 */
305
306struct ipr_res_addr {
307 u8 reserved;
308 u8 bus;
309 u8 target;
310 u8 lun;
311#define IPR_GET_PHYS_LOC(res_addr) \
312 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
313}__attribute__((packed, aligned (4)));
314
315struct ipr_std_inq_vpids {
316 u8 vendor_id[IPR_VENDOR_ID_LEN];
317 u8 product_id[IPR_PROD_ID_LEN];
318}__attribute__((packed));
319
320struct ipr_vpd {
321 struct ipr_std_inq_vpids vpids;
322 u8 sn[IPR_SERIAL_NUM_LEN];
323}__attribute__((packed));
324
325struct ipr_ext_vpd {
326 struct ipr_vpd vpd;
327 __be32 wwid[2];
328}__attribute__((packed));
329
330struct ipr_ext_vpd64 {
331 struct ipr_vpd vpd;
332 __be32 wwid[4];
333}__attribute__((packed));
334
335struct ipr_std_inq_data {
336 u8 peri_qual_dev_type;
337#define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
338#define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
339
340 u8 removeable_medium_rsvd;
341#define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
342
343#define IPR_IS_DASD_DEVICE(std_inq) \
344((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
345!(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
346
347#define IPR_IS_SES_DEVICE(std_inq) \
348(IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
349
350 u8 version;
351 u8 aen_naca_fmt;
352 u8 additional_len;
353 u8 sccs_rsvd;
354 u8 bq_enc_multi;
355 u8 sync_cmdq_flags;
356
357 struct ipr_std_inq_vpids vpids;
358
359 u8 ros_rsvd_ram_rsvd[4];
360
361 u8 serial_num[IPR_SERIAL_NUM_LEN];
362}__attribute__ ((packed));
363
364#define IPR_RES_TYPE_AF_DASD 0x00
365#define IPR_RES_TYPE_GENERIC_SCSI 0x01
366#define IPR_RES_TYPE_VOLUME_SET 0x02
367#define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
368#define IPR_RES_TYPE_GENERIC_ATA 0x04
369#define IPR_RES_TYPE_ARRAY 0x05
370#define IPR_RES_TYPE_IOAFP 0xff
371
372struct ipr_config_table_entry {
373 u8 proto;
374#define IPR_PROTO_SATA 0x02
375#define IPR_PROTO_SATA_ATAPI 0x03
376#define IPR_PROTO_SAS_STP 0x06
377#define IPR_PROTO_SAS_STP_ATAPI 0x07
378 u8 array_id;
379 u8 flags;
380#define IPR_IS_IOA_RESOURCE 0x80
381 u8 rsvd_subtype;
382
383#define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
384#define IPR_QUEUE_FROZEN_MODEL 0
385#define IPR_QUEUE_NACA_MODEL 1
386
387 struct ipr_res_addr res_addr;
388 __be32 res_handle;
389 __be32 lun_wwn[2];
390 struct ipr_std_inq_data std_inq_data;
391}__attribute__ ((packed, aligned (4)));
392
393struct ipr_config_table_entry64 {
394 u8 res_type;
395 u8 proto;
396 u8 vset_num;
397 u8 array_id;
398 __be16 flags;
399 __be16 res_flags;
400#define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
401 __be32 res_handle;
402 u8 dev_id_type;
403 u8 reserved[3];
404 __be64 dev_id;
405 __be64 lun;
406 __be64 lun_wwn[2];
407#define IPR_MAX_RES_PATH_LENGTH 24
408 __be64 res_path;
409 struct ipr_std_inq_data std_inq_data;
410 u8 reserved2[4];
411 __be64 reserved3[2];
412 u8 reserved4[8];
413}__attribute__ ((packed, aligned (8)));
414
415struct ipr_config_table_hdr {
416 u8 num_entries;
417 u8 flags;
418#define IPR_UCODE_DOWNLOAD_REQ 0x10
419 __be16 reserved;
420}__attribute__((packed, aligned (4)));
421
422struct ipr_config_table_hdr64 {
423 __be16 num_entries;
424 __be16 reserved;
425 u8 flags;
426 u8 reserved2[11];
427}__attribute__((packed, aligned (4)));
428
429struct ipr_config_table {
430 struct ipr_config_table_hdr hdr;
431 struct ipr_config_table_entry dev[0];
432}__attribute__((packed, aligned (4)));
433
434struct ipr_config_table64 {
435 struct ipr_config_table_hdr64 hdr64;
436 struct ipr_config_table_entry64 dev[0];
437}__attribute__((packed, aligned (8)));
438
439struct ipr_config_table_entry_wrapper {
440 union {
441 struct ipr_config_table_entry *cfgte;
442 struct ipr_config_table_entry64 *cfgte64;
443 } u;
444};
445
446struct ipr_hostrcb_cfg_ch_not {
447 union {
448 struct ipr_config_table_entry cfgte;
449 struct ipr_config_table_entry64 cfgte64;
450 } u;
451 u8 reserved[936];
452}__attribute__((packed, aligned (4)));
453
454struct ipr_supported_device {
455 __be16 data_length;
456 u8 reserved;
457 u8 num_records;
458 struct ipr_std_inq_vpids vpids;
459 u8 reserved2[16];
460}__attribute__((packed, aligned (4)));
461
462/* Command packet structure */
463struct ipr_cmd_pkt {
464 __be16 reserved; /* Reserved by IOA */
465 u8 request_type;
466#define IPR_RQTYPE_SCSICDB 0x00
467#define IPR_RQTYPE_IOACMD 0x01
468#define IPR_RQTYPE_HCAM 0x02
469#define IPR_RQTYPE_ATA_PASSTHRU 0x04
470
471 u8 reserved2;
472
473 u8 flags_hi;
474#define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
475#define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
476#define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
477#define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
478#define IPR_FLAGS_HI_NO_LINK_DESC 0x04
479
480 u8 flags_lo;
481#define IPR_FLAGS_LO_ALIGNED_BFR 0x20
482#define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
483#define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
484#define IPR_FLAGS_LO_SIMPLE_TASK 0x02
485#define IPR_FLAGS_LO_ORDERED_TASK 0x04
486#define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
487#define IPR_FLAGS_LO_ACA_TASK 0x08
488
489 u8 cdb[16];
490 __be16 timeout;
491}__attribute__ ((packed, aligned(4)));
492
493struct ipr_ioarcb_ata_regs { /* 22 bytes */
494 u8 flags;
495#define IPR_ATA_FLAG_PACKET_CMD 0x80
496#define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
497#define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
498 u8 reserved[3];
499
500 __be16 data;
501 u8 feature;
502 u8 nsect;
503 u8 lbal;
504 u8 lbam;
505 u8 lbah;
506 u8 device;
507 u8 command;
508 u8 reserved2[3];
509 u8 hob_feature;
510 u8 hob_nsect;
511 u8 hob_lbal;
512 u8 hob_lbam;
513 u8 hob_lbah;
514 u8 ctl;
515}__attribute__ ((packed, aligned(4)));
516
517struct ipr_ioadl_desc {
518 __be32 flags_and_data_len;
519#define IPR_IOADL_FLAGS_MASK 0xff000000
520#define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
521#define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
522#define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
523#define IPR_IOADL_FLAGS_READ 0x48000000
524#define IPR_IOADL_FLAGS_READ_LAST 0x49000000
525#define IPR_IOADL_FLAGS_WRITE 0x68000000
526#define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
527#define IPR_IOADL_FLAGS_LAST 0x01000000
528
529 __be32 address;
530}__attribute__((packed, aligned (8)));
531
532struct ipr_ioadl64_desc {
533 __be32 flags;
534 __be32 data_len;
535 __be64 address;
536}__attribute__((packed, aligned (16)));
537
538struct ipr_ata64_ioadl {
539 struct ipr_ioarcb_ata_regs regs;
540 u16 reserved[5];
541 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
542}__attribute__((packed, aligned (16)));
543
544struct ipr_ioarcb_add_data {
545 union {
546 struct ipr_ioarcb_ata_regs regs;
547 struct ipr_ioadl_desc ioadl[5];
548 __be32 add_cmd_parms[10];
549 } u;
550}__attribute__ ((packed, aligned (4)));
551
552struct ipr_ioarcb_sis64_add_addr_ecb {
553 __be64 ioasa_host_pci_addr;
554 __be64 data_ioadl_addr;
555 __be64 reserved;
556 __be32 ext_control_buf[4];
557}__attribute__((packed, aligned (8)));
558
559/* IOA Request Control Block 128 bytes */
560struct ipr_ioarcb {
561 union {
562 __be32 ioarcb_host_pci_addr;
563 __be64 ioarcb_host_pci_addr64;
564 } a;
565 __be32 res_handle;
566 __be32 host_response_handle;
567 __be32 reserved1;
568 __be32 reserved2;
569 __be32 reserved3;
570
571 __be32 data_transfer_length;
572 __be32 read_data_transfer_length;
573 __be32 write_ioadl_addr;
574 __be32 ioadl_len;
575 __be32 read_ioadl_addr;
576 __be32 read_ioadl_len;
577
578 __be32 ioasa_host_pci_addr;
579 __be16 ioasa_len;
580 __be16 reserved4;
581
582 struct ipr_cmd_pkt cmd_pkt;
583
584 __be16 add_cmd_parms_offset;
585 __be16 add_cmd_parms_len;
586
587 union {
588 struct ipr_ioarcb_add_data add_data;
589 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
590 } u;
591
592}__attribute__((packed, aligned (4)));
593
594struct ipr_ioasa_vset {
595 __be32 failing_lba_hi;
596 __be32 failing_lba_lo;
597 __be32 reserved;
598}__attribute__((packed, aligned (4)));
599
600struct ipr_ioasa_af_dasd {
601 __be32 failing_lba;
602 __be32 reserved[2];
603}__attribute__((packed, aligned (4)));
604
605struct ipr_ioasa_gpdd {
606 u8 end_state;
607 u8 bus_phase;
608 __be16 reserved;
609 __be32 ioa_data[2];
610}__attribute__((packed, aligned (4)));
611
612struct ipr_ioasa_gata {
613 u8 error;
614 u8 nsect; /* Interrupt reason */
615 u8 lbal;
616 u8 lbam;
617 u8 lbah;
618 u8 device;
619 u8 status;
620 u8 alt_status; /* ATA CTL */
621 u8 hob_nsect;
622 u8 hob_lbal;
623 u8 hob_lbam;
624 u8 hob_lbah;
625}__attribute__((packed, aligned (4)));
626
627struct ipr_auto_sense {
628 __be16 auto_sense_len;
629 __be16 ioa_data_len;
630 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
631};
632
633struct ipr_ioasa_hdr {
634 __be32 ioasc;
635#define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
636#define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
637#define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
638#define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
639
640 __be16 ret_stat_len; /* Length of the returned IOASA */
641
642 __be16 avail_stat_len; /* Total Length of status available. */
643
644 __be32 residual_data_len; /* number of bytes in the host data */
645 /* buffers that were not used by the IOARCB command. */
646
647 __be32 ilid;
648#define IPR_NO_ILID 0
649#define IPR_DRIVER_ILID 0xffffffff
650
651 __be32 fd_ioasc;
652
653 __be32 fd_phys_locator;
654
655 __be32 fd_res_handle;
656
657 __be32 ioasc_specific; /* status code specific field */
658#define IPR_ADDITIONAL_STATUS_FMT 0x80000000
659#define IPR_AUTOSENSE_VALID 0x40000000
660#define IPR_ATA_DEVICE_WAS_RESET 0x20000000
661#define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
662#define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
663#define IPR_FIELD_POINTER_MASK 0x0000ffff
664
665}__attribute__((packed, aligned (4)));
666
667struct ipr_ioasa {
668 struct ipr_ioasa_hdr hdr;
669
670 union {
671 struct ipr_ioasa_vset vset;
672 struct ipr_ioasa_af_dasd dasd;
673 struct ipr_ioasa_gpdd gpdd;
674 struct ipr_ioasa_gata gata;
675 } u;
676
677 struct ipr_auto_sense auto_sense;
678}__attribute__((packed, aligned (4)));
679
680struct ipr_ioasa64 {
681 struct ipr_ioasa_hdr hdr;
682 u8 fd_res_path[8];
683
684 union {
685 struct ipr_ioasa_vset vset;
686 struct ipr_ioasa_af_dasd dasd;
687 struct ipr_ioasa_gpdd gpdd;
688 struct ipr_ioasa_gata gata;
689 } u;
690
691 struct ipr_auto_sense auto_sense;
692}__attribute__((packed, aligned (4)));
693
694struct ipr_mode_parm_hdr {
695 u8 length;
696 u8 medium_type;
697 u8 device_spec_parms;
698 u8 block_desc_len;
699}__attribute__((packed));
700
701struct ipr_mode_pages {
702 struct ipr_mode_parm_hdr hdr;
703 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
704}__attribute__((packed));
705
706struct ipr_mode_page_hdr {
707 u8 ps_page_code;
708#define IPR_MODE_PAGE_PS 0x80
709#define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
710 u8 page_length;
711}__attribute__ ((packed));
712
713struct ipr_dev_bus_entry {
714 struct ipr_res_addr res_addr;
715 u8 flags;
716#define IPR_SCSI_ATTR_ENABLE_QAS 0x80
717#define IPR_SCSI_ATTR_DISABLE_QAS 0x40
718#define IPR_SCSI_ATTR_QAS_MASK 0xC0
719#define IPR_SCSI_ATTR_ENABLE_TM 0x20
720#define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
721#define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
722#define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
723
724 u8 scsi_id;
725 u8 bus_width;
726 u8 extended_reset_delay;
727#define IPR_EXTENDED_RESET_DELAY 7
728
729 __be32 max_xfer_rate;
730
731 u8 spinup_delay;
732 u8 reserved3;
733 __be16 reserved4;
734}__attribute__((packed, aligned (4)));
735
736struct ipr_mode_page28 {
737 struct ipr_mode_page_hdr hdr;
738 u8 num_entries;
739 u8 entry_length;
740 struct ipr_dev_bus_entry bus[0];
741}__attribute__((packed));
742
743struct ipr_mode_page24 {
744 struct ipr_mode_page_hdr hdr;
745 u8 flags;
746#define IPR_ENABLE_DUAL_IOA_AF 0x80
747}__attribute__((packed));
748
749struct ipr_ioa_vpd {
750 struct ipr_std_inq_data std_inq_data;
751 u8 ascii_part_num[12];
752 u8 reserved[40];
753 u8 ascii_plant_code[4];
754}__attribute__((packed));
755
756struct ipr_inquiry_page3 {
757 u8 peri_qual_dev_type;
758 u8 page_code;
759 u8 reserved1;
760 u8 page_length;
761 u8 ascii_len;
762 u8 reserved2[3];
763 u8 load_id[4];
764 u8 major_release;
765 u8 card_type;
766 u8 minor_release[2];
767 u8 ptf_number[4];
768 u8 patch_number[4];
769}__attribute__((packed));
770
771struct ipr_inquiry_cap {
772 u8 peri_qual_dev_type;
773 u8 page_code;
774 u8 reserved1;
775 u8 page_length;
776 u8 ascii_len;
777 u8 reserved2;
778 u8 sis_version[2];
779 u8 cap;
780#define IPR_CAP_DUAL_IOA_RAID 0x80
781 u8 reserved3[15];
782}__attribute__((packed));
783
784#define IPR_INQUIRY_PAGE0_ENTRIES 20
785struct ipr_inquiry_page0 {
786 u8 peri_qual_dev_type;
787 u8 page_code;
788 u8 reserved1;
789 u8 len;
790 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
791}__attribute__((packed));
792
793struct ipr_hostrcb_device_data_entry {
794 struct ipr_vpd vpd;
795 struct ipr_res_addr dev_res_addr;
796 struct ipr_vpd new_vpd;
797 struct ipr_vpd ioa_last_with_dev_vpd;
798 struct ipr_vpd cfc_last_with_dev_vpd;
799 __be32 ioa_data[5];
800}__attribute__((packed, aligned (4)));
801
802struct ipr_hostrcb_device_data_entry_enhanced {
803 struct ipr_ext_vpd vpd;
804 u8 ccin[4];
805 struct ipr_res_addr dev_res_addr;
806 struct ipr_ext_vpd new_vpd;
807 u8 new_ccin[4];
808 struct ipr_ext_vpd ioa_last_with_dev_vpd;
809 struct ipr_ext_vpd cfc_last_with_dev_vpd;
810}__attribute__((packed, aligned (4)));
811
812struct ipr_hostrcb64_device_data_entry_enhanced {
813 struct ipr_ext_vpd vpd;
814 u8 ccin[4];
815 u8 res_path[8];
816 struct ipr_ext_vpd new_vpd;
817 u8 new_ccin[4];
818 struct ipr_ext_vpd ioa_last_with_dev_vpd;
819 struct ipr_ext_vpd cfc_last_with_dev_vpd;
820}__attribute__((packed, aligned (4)));
821
822struct ipr_hostrcb_array_data_entry {
823 struct ipr_vpd vpd;
824 struct ipr_res_addr expected_dev_res_addr;
825 struct ipr_res_addr dev_res_addr;
826}__attribute__((packed, aligned (4)));
827
828struct ipr_hostrcb64_array_data_entry {
829 struct ipr_ext_vpd vpd;
830 u8 ccin[4];
831 u8 expected_res_path[8];
832 u8 res_path[8];
833}__attribute__((packed, aligned (4)));
834
835struct ipr_hostrcb_array_data_entry_enhanced {
836 struct ipr_ext_vpd vpd;
837 u8 ccin[4];
838 struct ipr_res_addr expected_dev_res_addr;
839 struct ipr_res_addr dev_res_addr;
840}__attribute__((packed, aligned (4)));
841
842struct ipr_hostrcb_type_ff_error {
843 __be32 ioa_data[758];
844}__attribute__((packed, aligned (4)));
845
846struct ipr_hostrcb_type_01_error {
847 __be32 seek_counter;
848 __be32 read_counter;
849 u8 sense_data[32];
850 __be32 ioa_data[236];
851}__attribute__((packed, aligned (4)));
852
853struct ipr_hostrcb_type_02_error {
854 struct ipr_vpd ioa_vpd;
855 struct ipr_vpd cfc_vpd;
856 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
857 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
858 __be32 ioa_data[3];
859}__attribute__((packed, aligned (4)));
860
861struct ipr_hostrcb_type_12_error {
862 struct ipr_ext_vpd ioa_vpd;
863 struct ipr_ext_vpd cfc_vpd;
864 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
865 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
866 __be32 ioa_data[3];
867}__attribute__((packed, aligned (4)));
868
869struct ipr_hostrcb_type_03_error {
870 struct ipr_vpd ioa_vpd;
871 struct ipr_vpd cfc_vpd;
872 __be32 errors_detected;
873 __be32 errors_logged;
874 u8 ioa_data[12];
875 struct ipr_hostrcb_device_data_entry dev[3];
876}__attribute__((packed, aligned (4)));
877
878struct ipr_hostrcb_type_13_error {
879 struct ipr_ext_vpd ioa_vpd;
880 struct ipr_ext_vpd cfc_vpd;
881 __be32 errors_detected;
882 __be32 errors_logged;
883 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
884}__attribute__((packed, aligned (4)));
885
886struct ipr_hostrcb_type_23_error {
887 struct ipr_ext_vpd ioa_vpd;
888 struct ipr_ext_vpd cfc_vpd;
889 __be32 errors_detected;
890 __be32 errors_logged;
891 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
892}__attribute__((packed, aligned (4)));
893
894struct ipr_hostrcb_type_04_error {
895 struct ipr_vpd ioa_vpd;
896 struct ipr_vpd cfc_vpd;
897 u8 ioa_data[12];
898 struct ipr_hostrcb_array_data_entry array_member[10];
899 __be32 exposed_mode_adn;
900 __be32 array_id;
901 struct ipr_vpd incomp_dev_vpd;
902 __be32 ioa_data2;
903 struct ipr_hostrcb_array_data_entry array_member2[8];
904 struct ipr_res_addr last_func_vset_res_addr;
905 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
906 u8 protection_level[8];
907}__attribute__((packed, aligned (4)));
908
909struct ipr_hostrcb_type_14_error {
910 struct ipr_ext_vpd ioa_vpd;
911 struct ipr_ext_vpd cfc_vpd;
912 __be32 exposed_mode_adn;
913 __be32 array_id;
914 struct ipr_res_addr last_func_vset_res_addr;
915 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
916 u8 protection_level[8];
917 __be32 num_entries;
918 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
919}__attribute__((packed, aligned (4)));
920
921struct ipr_hostrcb_type_24_error {
922 struct ipr_ext_vpd ioa_vpd;
923 struct ipr_ext_vpd cfc_vpd;
924 u8 reserved[2];
925 u8 exposed_mode_adn;
926#define IPR_INVALID_ARRAY_DEV_NUM 0xff
927 u8 array_id;
928 u8 last_res_path[8];
929 u8 protection_level[8];
930 struct ipr_ext_vpd64 array_vpd;
931 u8 description[16];
932 u8 reserved2[3];
933 u8 num_entries;
934 struct ipr_hostrcb64_array_data_entry array_member[32];
935}__attribute__((packed, aligned (4)));
936
937struct ipr_hostrcb_type_07_error {
938 u8 failure_reason[64];
939 struct ipr_vpd vpd;
940 u32 data[222];
941}__attribute__((packed, aligned (4)));
942
943struct ipr_hostrcb_type_17_error {
944 u8 failure_reason[64];
945 struct ipr_ext_vpd vpd;
946 u32 data[476];
947}__attribute__((packed, aligned (4)));
948
949struct ipr_hostrcb_config_element {
950 u8 type_status;
951#define IPR_PATH_CFG_TYPE_MASK 0xF0
952#define IPR_PATH_CFG_NOT_EXIST 0x00
953#define IPR_PATH_CFG_IOA_PORT 0x10
954#define IPR_PATH_CFG_EXP_PORT 0x20
955#define IPR_PATH_CFG_DEVICE_PORT 0x30
956#define IPR_PATH_CFG_DEVICE_LUN 0x40
957
958#define IPR_PATH_CFG_STATUS_MASK 0x0F
959#define IPR_PATH_CFG_NO_PROB 0x00
960#define IPR_PATH_CFG_DEGRADED 0x01
961#define IPR_PATH_CFG_FAILED 0x02
962#define IPR_PATH_CFG_SUSPECT 0x03
963#define IPR_PATH_NOT_DETECTED 0x04
964#define IPR_PATH_INCORRECT_CONN 0x05
965
966 u8 cascaded_expander;
967 u8 phy;
968 u8 link_rate;
969#define IPR_PHY_LINK_RATE_MASK 0x0F
970
971 __be32 wwid[2];
972}__attribute__((packed, aligned (4)));
973
974struct ipr_hostrcb64_config_element {
975 __be16 length;
976 u8 descriptor_id;
977#define IPR_DESCRIPTOR_MASK 0xC0
978#define IPR_DESCRIPTOR_SIS64 0x00
979
980 u8 reserved;
981 u8 type_status;
982
983 u8 reserved2[2];
984 u8 link_rate;
985
986 u8 res_path[8];
987 __be32 wwid[2];
988}__attribute__((packed, aligned (8)));
989
990struct ipr_hostrcb_fabric_desc {
991 __be16 length;
992 u8 ioa_port;
993 u8 cascaded_expander;
994 u8 phy;
995 u8 path_state;
996#define IPR_PATH_ACTIVE_MASK 0xC0
997#define IPR_PATH_NO_INFO 0x00
998#define IPR_PATH_ACTIVE 0x40
999#define IPR_PATH_NOT_ACTIVE 0x80
1000
1001#define IPR_PATH_STATE_MASK 0x0F
1002#define IPR_PATH_STATE_NO_INFO 0x00
1003#define IPR_PATH_HEALTHY 0x01
1004#define IPR_PATH_DEGRADED 0x02
1005#define IPR_PATH_FAILED 0x03
1006
1007 __be16 num_entries;
1008 struct ipr_hostrcb_config_element elem[1];
1009}__attribute__((packed, aligned (4)));
1010
1011struct ipr_hostrcb64_fabric_desc {
1012 __be16 length;
1013 u8 descriptor_id;
1014
1015 u8 reserved[2];
1016 u8 path_state;
1017
1018 u8 reserved2[2];
1019 u8 res_path[8];
1020 u8 reserved3[6];
1021 __be16 num_entries;
1022 struct ipr_hostrcb64_config_element elem[1];
1023}__attribute__((packed, aligned (8)));
1024
1025#define for_each_fabric_cfg(fabric, cfg) \
1026 for (cfg = (fabric)->elem; \
1027 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1028 cfg++)
1029
1030struct ipr_hostrcb_type_20_error {
1031 u8 failure_reason[64];
1032 u8 reserved[3];
1033 u8 num_entries;
1034 struct ipr_hostrcb_fabric_desc desc[1];
1035}__attribute__((packed, aligned (4)));
1036
1037struct ipr_hostrcb_type_30_error {
1038 u8 failure_reason[64];
1039 u8 reserved[3];
1040 u8 num_entries;
1041 struct ipr_hostrcb64_fabric_desc desc[1];
1042}__attribute__((packed, aligned (4)));
1043
1044struct ipr_hostrcb_error {
1045 __be32 fd_ioasc;
1046 struct ipr_res_addr fd_res_addr;
1047 __be32 fd_res_handle;
1048 __be32 prc;
1049 union {
1050 struct ipr_hostrcb_type_ff_error type_ff_error;
1051 struct ipr_hostrcb_type_01_error type_01_error;
1052 struct ipr_hostrcb_type_02_error type_02_error;
1053 struct ipr_hostrcb_type_03_error type_03_error;
1054 struct ipr_hostrcb_type_04_error type_04_error;
1055 struct ipr_hostrcb_type_07_error type_07_error;
1056 struct ipr_hostrcb_type_12_error type_12_error;
1057 struct ipr_hostrcb_type_13_error type_13_error;
1058 struct ipr_hostrcb_type_14_error type_14_error;
1059 struct ipr_hostrcb_type_17_error type_17_error;
1060 struct ipr_hostrcb_type_20_error type_20_error;
1061 } u;
1062}__attribute__((packed, aligned (4)));
1063
1064struct ipr_hostrcb64_error {
1065 __be32 fd_ioasc;
1066 __be32 ioa_fw_level;
1067 __be32 fd_res_handle;
1068 __be32 prc;
1069 __be64 fd_dev_id;
1070 __be64 fd_lun;
1071 u8 fd_res_path[8];
1072 __be64 time_stamp;
1073 u8 reserved[16];
1074 union {
1075 struct ipr_hostrcb_type_ff_error type_ff_error;
1076 struct ipr_hostrcb_type_12_error type_12_error;
1077 struct ipr_hostrcb_type_17_error type_17_error;
1078 struct ipr_hostrcb_type_23_error type_23_error;
1079 struct ipr_hostrcb_type_24_error type_24_error;
1080 struct ipr_hostrcb_type_30_error type_30_error;
1081 } u;
1082}__attribute__((packed, aligned (8)));
1083
1084struct ipr_hostrcb_raw {
1085 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1086}__attribute__((packed, aligned (4)));
1087
1088struct ipr_hcam {
1089 u8 op_code;
1090#define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1091#define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1092
1093 u8 notify_type;
1094#define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1095#define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1096#define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1097#define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1098#define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1099
1100 u8 notifications_lost;
1101#define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1102#define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1103
1104 u8 flags;
1105#define IPR_HOSTRCB_INTERNAL_OPER 0x80
1106#define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1107
1108 u8 overlay_id;
1109#define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1110#define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1111#define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1112#define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1113#define IPR_HOST_RCB_OVERLAY_ID_6 0x06
1114#define IPR_HOST_RCB_OVERLAY_ID_7 0x07
1115#define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1116#define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1117#define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1118#define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1119#define IPR_HOST_RCB_OVERLAY_ID_17 0x17
1120#define IPR_HOST_RCB_OVERLAY_ID_20 0x20
1121#define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1122#define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1123#define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1124#define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1125#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1126
1127 u8 reserved1[3];
1128 __be32 ilid;
1129 __be32 time_since_last_ioa_reset;
1130 __be32 reserved2;
1131 __be32 length;
1132
1133 union {
1134 struct ipr_hostrcb_error error;
1135 struct ipr_hostrcb64_error error64;
1136 struct ipr_hostrcb_cfg_ch_not ccn;
1137 struct ipr_hostrcb_raw raw;
1138 } u;
1139}__attribute__((packed, aligned (4)));
1140
1141struct ipr_hostrcb {
1142 struct ipr_hcam hcam;
1143 dma_addr_t hostrcb_dma;
1144 struct list_head queue;
1145 struct ipr_ioa_cfg *ioa_cfg;
1146 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1147};
1148
1149/* IPR smart dump table structures */
1150struct ipr_sdt_entry {
1151 __be32 start_token;
1152 __be32 end_token;
1153 u8 reserved[4];
1154
1155 u8 flags;
1156#define IPR_SDT_ENDIAN 0x80
1157#define IPR_SDT_VALID_ENTRY 0x20
1158
1159 u8 resv;
1160 __be16 priority;
1161}__attribute__((packed, aligned (4)));
1162
1163struct ipr_sdt_header {
1164 __be32 state;
1165 __be32 num_entries;
1166 __be32 num_entries_used;
1167 __be32 dump_size;
1168}__attribute__((packed, aligned (4)));
1169
1170struct ipr_sdt {
1171 struct ipr_sdt_header hdr;
1172 struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES];
1173}__attribute__((packed, aligned (4)));
1174
1175struct ipr_uc_sdt {
1176 struct ipr_sdt_header hdr;
1177 struct ipr_sdt_entry entry[1];
1178}__attribute__((packed, aligned (4)));
1179
1180/*
1181 * Driver types
1182 */
1183struct ipr_bus_attributes {
1184 u8 bus;
1185 u8 qas_enabled;
1186 u8 bus_width;
1187 u8 reserved;
1188 u32 max_xfer_rate;
1189};
1190
1191struct ipr_sata_port {
1192 struct ipr_ioa_cfg *ioa_cfg;
1193 struct ata_port *ap;
1194 struct ipr_resource_entry *res;
1195 struct ipr_ioasa_gata ioasa;
1196};
1197
1198struct ipr_resource_entry {
1199 u8 needs_sync_complete:1;
1200 u8 in_erp:1;
1201 u8 add_to_ml:1;
1202 u8 del_from_ml:1;
1203 u8 resetting_device:1;
1204
1205 u32 bus; /* AKA channel */
1206 u32 target; /* AKA id */
1207 u32 lun;
1208#define IPR_ARRAY_VIRTUAL_BUS 0x1
1209#define IPR_VSET_VIRTUAL_BUS 0x2
1210#define IPR_IOAFP_VIRTUAL_BUS 0x3
1211
1212#define IPR_GET_RES_PHYS_LOC(res) \
1213 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1214
1215 u8 ata_class;
1216
1217 u8 flags;
1218 __be16 res_flags;
1219
1220 u8 type;
1221
1222 u8 qmodel;
1223 struct ipr_std_inq_data std_inq_data;
1224
1225 __be32 res_handle;
1226 __be64 dev_id;
1227 __be64 lun_wwn;
1228 struct scsi_lun dev_lun;
1229 u8 res_path[8];
1230
1231 struct ipr_ioa_cfg *ioa_cfg;
1232 struct scsi_device *sdev;
1233 struct ipr_sata_port *sata_port;
1234 struct list_head queue;
1235}; /* struct ipr_resource_entry */
1236
1237struct ipr_resource_hdr {
1238 u16 num_entries;
1239 u16 reserved;
1240};
1241
1242struct ipr_misc_cbs {
1243 struct ipr_ioa_vpd ioa_vpd;
1244 struct ipr_inquiry_page0 page0_data;
1245 struct ipr_inquiry_page3 page3_data;
1246 struct ipr_inquiry_cap cap;
1247 struct ipr_mode_pages mode_pages;
1248 struct ipr_supported_device supp_dev;
1249};
1250
1251struct ipr_interrupt_offsets {
1252 unsigned long set_interrupt_mask_reg;
1253 unsigned long clr_interrupt_mask_reg;
1254 unsigned long clr_interrupt_mask_reg32;
1255 unsigned long sense_interrupt_mask_reg;
1256 unsigned long sense_interrupt_mask_reg32;
1257 unsigned long clr_interrupt_reg;
1258 unsigned long clr_interrupt_reg32;
1259
1260 unsigned long sense_interrupt_reg;
1261 unsigned long sense_interrupt_reg32;
1262 unsigned long ioarrin_reg;
1263 unsigned long sense_uproc_interrupt_reg;
1264 unsigned long sense_uproc_interrupt_reg32;
1265 unsigned long set_uproc_interrupt_reg;
1266 unsigned long set_uproc_interrupt_reg32;
1267 unsigned long clr_uproc_interrupt_reg;
1268 unsigned long clr_uproc_interrupt_reg32;
1269
1270 unsigned long init_feedback_reg;
1271
1272 unsigned long dump_addr_reg;
1273 unsigned long dump_data_reg;
1274
1275#define IPR_ENDIAN_SWAP_KEY 0x00080800
1276 unsigned long endian_swap_reg;
1277};
1278
1279struct ipr_interrupts {
1280 void __iomem *set_interrupt_mask_reg;
1281 void __iomem *clr_interrupt_mask_reg;
1282 void __iomem *clr_interrupt_mask_reg32;
1283 void __iomem *sense_interrupt_mask_reg;
1284 void __iomem *sense_interrupt_mask_reg32;
1285 void __iomem *clr_interrupt_reg;
1286 void __iomem *clr_interrupt_reg32;
1287
1288 void __iomem *sense_interrupt_reg;
1289 void __iomem *sense_interrupt_reg32;
1290 void __iomem *ioarrin_reg;
1291 void __iomem *sense_uproc_interrupt_reg;
1292 void __iomem *sense_uproc_interrupt_reg32;
1293 void __iomem *set_uproc_interrupt_reg;
1294 void __iomem *set_uproc_interrupt_reg32;
1295 void __iomem *clr_uproc_interrupt_reg;
1296 void __iomem *clr_uproc_interrupt_reg32;
1297
1298 void __iomem *init_feedback_reg;
1299
1300 void __iomem *dump_addr_reg;
1301 void __iomem *dump_data_reg;
1302
1303 void __iomem *endian_swap_reg;
1304};
1305
1306struct ipr_chip_cfg_t {
1307 u32 mailbox;
1308 u16 max_cmds;
1309 u8 cache_line_size;
1310 u8 clear_isr;
1311 struct ipr_interrupt_offsets regs;
1312};
1313
1314struct ipr_chip_t {
1315 u16 vendor;
1316 u16 device;
1317 u16 intr_type;
1318#define IPR_USE_LSI 0x00
1319#define IPR_USE_MSI 0x01
1320 u16 sis_type;
1321#define IPR_SIS32 0x00
1322#define IPR_SIS64 0x01
1323 u16 bist_method;
1324#define IPR_PCI_CFG 0x00
1325#define IPR_MMIO 0x01
1326 const struct ipr_chip_cfg_t *cfg;
1327};
1328
1329enum ipr_shutdown_type {
1330 IPR_SHUTDOWN_NORMAL = 0x00,
1331 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1332 IPR_SHUTDOWN_ABBREV = 0x80,
1333 IPR_SHUTDOWN_NONE = 0x100
1334};
1335
1336struct ipr_trace_entry {
1337 u32 time;
1338
1339 u8 op_code;
1340 u8 ata_op_code;
1341 u8 type;
1342#define IPR_TRACE_START 0x00
1343#define IPR_TRACE_FINISH 0xff
1344 u8 cmd_index;
1345
1346 __be32 res_handle;
1347 union {
1348 u32 ioasc;
1349 u32 add_data;
1350 u32 res_addr;
1351 } u;
1352};
1353
1354struct ipr_sglist {
1355 u32 order;
1356 u32 num_sg;
1357 u32 num_dma_sg;
1358 u32 buffer_len;
1359 struct scatterlist scatterlist[1];
1360};
1361
1362enum ipr_sdt_state {
1363 INACTIVE,
1364 WAIT_FOR_DUMP,
1365 GET_DUMP,
1366 READ_DUMP,
1367 ABORT_DUMP,
1368 DUMP_OBTAINED
1369};
1370
1371/* Per-controller data */
1372struct ipr_ioa_cfg {
1373 char eye_catcher[8];
1374#define IPR_EYECATCHER "iprcfg"
1375
1376 struct list_head queue;
1377
1378 u8 allow_interrupts:1;
1379 u8 in_reset_reload:1;
1380 u8 in_ioa_bringdown:1;
1381 u8 ioa_unit_checked:1;
1382 u8 ioa_is_dead:1;
1383 u8 dump_taken:1;
1384 u8 allow_cmds:1;
1385 u8 allow_ml_add_del:1;
1386 u8 needs_hard_reset:1;
1387 u8 dual_raid:1;
1388 u8 needs_warm_reset:1;
1389 u8 msi_received:1;
1390 u8 sis64:1;
1391 u8 dump_timeout:1;
1392 u8 cfg_locked:1;
1393 u8 clear_isr:1;
1394
1395 u8 revid;
1396
1397 /*
1398 * Bitmaps for SIS64 generated target values
1399 */
1400 unsigned long *target_ids;
1401 unsigned long *array_ids;
1402 unsigned long *vset_ids;
1403
1404 u16 type; /* CCIN of the card */
1405
1406 u8 log_level;
1407#define IPR_MAX_LOG_LEVEL 4
1408#define IPR_DEFAULT_LOG_LEVEL 2
1409
1410#define IPR_NUM_TRACE_INDEX_BITS 8
1411#define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1412#define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1413 char trace_start[8];
1414#define IPR_TRACE_START_LABEL "trace"
1415 struct ipr_trace_entry *trace;
1416 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1417
1418 /*
1419 * Queue for free command blocks
1420 */
1421 char ipr_free_label[8];
1422#define IPR_FREEQ_LABEL "free-q"
1423 struct list_head free_q;
1424
1425 /*
1426 * Queue for command blocks outstanding to the adapter
1427 */
1428 char ipr_pending_label[8];
1429#define IPR_PENDQ_LABEL "pend-q"
1430 struct list_head pending_q;
1431
1432 char cfg_table_start[8];
1433#define IPR_CFG_TBL_START "cfg"
1434 union {
1435 struct ipr_config_table *cfg_table;
1436 struct ipr_config_table64 *cfg_table64;
1437 } u;
1438 dma_addr_t cfg_table_dma;
1439 u32 cfg_table_size;
1440 u32 max_devs_supported;
1441
1442 char resource_table_label[8];
1443#define IPR_RES_TABLE_LABEL "res_tbl"
1444 struct ipr_resource_entry *res_entries;
1445 struct list_head free_res_q;
1446 struct list_head used_res_q;
1447
1448 char ipr_hcam_label[8];
1449#define IPR_HCAM_LABEL "hcams"
1450 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1451 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1452 struct list_head hostrcb_free_q;
1453 struct list_head hostrcb_pending_q;
1454
1455 __be32 *host_rrq;
1456 dma_addr_t host_rrq_dma;
1457#define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
1458#define IPR_HRRQ_RESP_BIT_SET 0x00000002
1459#define IPR_HRRQ_TOGGLE_BIT 0x00000001
1460#define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
1461 volatile __be32 *hrrq_start;
1462 volatile __be32 *hrrq_end;
1463 volatile __be32 *hrrq_curr;
1464 volatile u32 toggle_bit;
1465
1466 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1467
1468 unsigned int transop_timeout;
1469 const struct ipr_chip_cfg_t *chip_cfg;
1470 const struct ipr_chip_t *ipr_chip;
1471
1472 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1473 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1474 void __iomem *ioa_mailbox;
1475 struct ipr_interrupts regs;
1476
1477 u16 saved_pcix_cmd_reg;
1478 u16 reset_retries;
1479
1480 u32 errors_logged;
1481 u32 doorbell;
1482
1483 struct Scsi_Host *host;
1484 struct pci_dev *pdev;
1485 struct ipr_sglist *ucode_sglist;
1486 u8 saved_mode_page_len;
1487
1488 struct work_struct work_q;
1489
1490 wait_queue_head_t reset_wait_q;
1491 wait_queue_head_t msi_wait_q;
1492
1493 struct ipr_dump *dump;
1494 enum ipr_sdt_state sdt_state;
1495
1496 struct ipr_misc_cbs *vpd_cbs;
1497 dma_addr_t vpd_cbs_dma;
1498
1499 struct pci_pool *ipr_cmd_pool;
1500
1501 struct ipr_cmnd *reset_cmd;
1502 int (*reset) (struct ipr_cmnd *);
1503
1504 struct ata_host ata_host;
1505 char ipr_cmd_label[8];
1506#define IPR_CMD_LABEL "ipr_cmd"
1507 u32 max_cmds;
1508 struct ipr_cmnd **ipr_cmnd_list;
1509 dma_addr_t *ipr_cmnd_list_dma;
1510}; /* struct ipr_ioa_cfg */
1511
1512struct ipr_cmnd {
1513 struct ipr_ioarcb ioarcb;
1514 union {
1515 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1516 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1517 struct ipr_ata64_ioadl ata_ioadl;
1518 } i;
1519 union {
1520 struct ipr_ioasa ioasa;
1521 struct ipr_ioasa64 ioasa64;
1522 } s;
1523 struct list_head queue;
1524 struct scsi_cmnd *scsi_cmd;
1525 struct ata_queued_cmd *qc;
1526 struct completion completion;
1527 struct timer_list timer;
1528 void (*done) (struct ipr_cmnd *);
1529 int (*job_step) (struct ipr_cmnd *);
1530 int (*job_step_failed) (struct ipr_cmnd *);
1531 u16 cmd_index;
1532 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1533 dma_addr_t sense_buffer_dma;
1534 unsigned short dma_use_sg;
1535 dma_addr_t dma_addr;
1536 struct ipr_cmnd *sibling;
1537 union {
1538 enum ipr_shutdown_type shutdown_type;
1539 struct ipr_hostrcb *hostrcb;
1540 unsigned long time_left;
1541 unsigned long scratch;
1542 struct ipr_resource_entry *res;
1543 struct scsi_device *sdev;
1544 } u;
1545
1546 struct ipr_ioa_cfg *ioa_cfg;
1547};
1548
1549struct ipr_ses_table_entry {
1550 char product_id[17];
1551 char compare_product_id_byte[17];
1552 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1553};
1554
1555struct ipr_dump_header {
1556 u32 eye_catcher;
1557#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1558 u32 len;
1559 u32 num_entries;
1560 u32 first_entry_offset;
1561 u32 status;
1562#define IPR_DUMP_STATUS_SUCCESS 0
1563#define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1564#define IPR_DUMP_STATUS_FAILED 0xffffffff
1565 u32 os;
1566#define IPR_DUMP_OS_LINUX 0x4C4E5558
1567 u32 driver_name;
1568#define IPR_DUMP_DRIVER_NAME 0x49505232
1569}__attribute__((packed, aligned (4)));
1570
1571struct ipr_dump_entry_header {
1572 u32 eye_catcher;
1573#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1574 u32 len;
1575 u32 num_elems;
1576 u32 offset;
1577 u32 data_type;
1578#define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1579#define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1580 u32 id;
1581#define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1582#define IPR_DUMP_LOCATION_ID 0x4C4F4341
1583#define IPR_DUMP_TRACE_ID 0x54524143
1584#define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1585#define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1586#define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1587#define IPR_DUMP_PEND_OPS 0x414F5053
1588 u32 status;
1589}__attribute__((packed, aligned (4)));
1590
1591struct ipr_dump_location_entry {
1592 struct ipr_dump_entry_header hdr;
1593 u8 location[20];
1594}__attribute__((packed));
1595
1596struct ipr_dump_trace_entry {
1597 struct ipr_dump_entry_header hdr;
1598 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1599}__attribute__((packed, aligned (4)));
1600
1601struct ipr_dump_version_entry {
1602 struct ipr_dump_entry_header hdr;
1603 u8 version[sizeof(IPR_DRIVER_VERSION)];
1604};
1605
1606struct ipr_dump_ioa_type_entry {
1607 struct ipr_dump_entry_header hdr;
1608 u32 type;
1609 u32 fw_version;
1610};
1611
1612struct ipr_driver_dump {
1613 struct ipr_dump_header hdr;
1614 struct ipr_dump_version_entry version_entry;
1615 struct ipr_dump_location_entry location_entry;
1616 struct ipr_dump_ioa_type_entry ioa_type_entry;
1617 struct ipr_dump_trace_entry trace_entry;
1618}__attribute__((packed));
1619
1620struct ipr_ioa_dump {
1621 struct ipr_dump_entry_header hdr;
1622 struct ipr_sdt sdt;
1623 __be32 **ioa_data;
1624 u32 reserved;
1625 u32 next_page_index;
1626 u32 page_offset;
1627 u32 format;
1628}__attribute__((packed, aligned (4)));
1629
1630struct ipr_dump {
1631 struct kref kref;
1632 struct ipr_ioa_cfg *ioa_cfg;
1633 struct ipr_driver_dump driver_dump;
1634 struct ipr_ioa_dump ioa_dump;
1635};
1636
1637struct ipr_error_table_t {
1638 u32 ioasc;
1639 int log_ioasa;
1640 int log_hcam;
1641 char *error;
1642};
1643
1644struct ipr_software_inq_lid_info {
1645 __be32 load_id;
1646 __be32 timestamp[3];
1647}__attribute__((packed, aligned (4)));
1648
1649struct ipr_ucode_image_header {
1650 __be32 header_length;
1651 __be32 lid_table_offset;
1652 u8 major_release;
1653 u8 card_type;
1654 u8 minor_release[2];
1655 u8 reserved[20];
1656 char eyecatcher[16];
1657 __be32 num_lids;
1658 struct ipr_software_inq_lid_info lid[1];
1659}__attribute__((packed, aligned (4)));
1660
1661/*
1662 * Macros
1663 */
1664#define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1665
1666#ifdef CONFIG_SCSI_IPR_TRACE
1667#define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1668#define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1669#else
1670#define ipr_create_trace_file(kobj, attr) 0
1671#define ipr_remove_trace_file(kobj, attr) do { } while(0)
1672#endif
1673
1674#ifdef CONFIG_SCSI_IPR_DUMP
1675#define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1676#define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1677#else
1678#define ipr_create_dump_file(kobj, attr) 0
1679#define ipr_remove_dump_file(kobj, attr) do { } while(0)
1680#endif
1681
1682/*
1683 * Error logging macros
1684 */
1685#define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1686#define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1687#define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1688
1689#define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1690 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1691 bus, target, lun, ##__VA_ARGS__)
1692
1693#define ipr_res_err(ioa_cfg, res, fmt, ...) \
1694 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1695
1696#define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1697 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1698 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1699
1700#define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1701 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1702
1703#define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1704{ \
1705 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1706 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1707 } else { \
1708 ipr_err(fmt": %d:%d:%d:%d\n", \
1709 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1710 (res).bus, (res).target, (res).lun); \
1711 } \
1712}
1713
1714#define ipr_hcam_err(hostrcb, fmt, ...) \
1715{ \
1716 if (ipr_is_device(hostrcb)) { \
1717 if ((hostrcb)->ioa_cfg->sis64) { \
1718 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1719 ipr_format_res_path(hostrcb->hcam.u.error64.fd_res_path, \
1720 hostrcb->rp_buffer, \
1721 sizeof(hostrcb->rp_buffer)), \
1722 __VA_ARGS__); \
1723 } else { \
1724 ipr_ra_err((hostrcb)->ioa_cfg, \
1725 (hostrcb)->hcam.u.error.fd_res_addr, \
1726 fmt, __VA_ARGS__); \
1727 } \
1728 } else { \
1729 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1730 } \
1731}
1732
1733#define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1734 __FILE__, __func__, __LINE__)
1735
1736#define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1737#define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1738
1739#define ipr_err_separator \
1740ipr_err("----------------------------------------------------------\n")
1741
1742
1743/*
1744 * Inlines
1745 */
1746
1747/**
1748 * ipr_is_ioa_resource - Determine if a resource is the IOA
1749 * @res: resource entry struct
1750 *
1751 * Return value:
1752 * 1 if IOA / 0 if not IOA
1753 **/
1754static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1755{
1756 return res->type == IPR_RES_TYPE_IOAFP;
1757}
1758
1759/**
1760 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1761 * @res: resource entry struct
1762 *
1763 * Return value:
1764 * 1 if AF DASD / 0 if not AF DASD
1765 **/
1766static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1767{
1768 return res->type == IPR_RES_TYPE_AF_DASD ||
1769 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1770}
1771
1772/**
1773 * ipr_is_vset_device - Determine if a resource is a VSET
1774 * @res: resource entry struct
1775 *
1776 * Return value:
1777 * 1 if VSET / 0 if not VSET
1778 **/
1779static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1780{
1781 return res->type == IPR_RES_TYPE_VOLUME_SET;
1782}
1783
1784/**
1785 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1786 * @res: resource entry struct
1787 *
1788 * Return value:
1789 * 1 if GSCSI / 0 if not GSCSI
1790 **/
1791static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1792{
1793 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1794}
1795
1796/**
1797 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1798 * @res: resource entry struct
1799 *
1800 * Return value:
1801 * 1 if SCSI disk / 0 if not SCSI disk
1802 **/
1803static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1804{
1805 if (ipr_is_af_dasd_device(res) ||
1806 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1807 return 1;
1808 else
1809 return 0;
1810}
1811
1812/**
1813 * ipr_is_gata - Determine if a resource is a generic ATA resource
1814 * @res: resource entry struct
1815 *
1816 * Return value:
1817 * 1 if GATA / 0 if not GATA
1818 **/
1819static inline int ipr_is_gata(struct ipr_resource_entry *res)
1820{
1821 return res->type == IPR_RES_TYPE_GENERIC_ATA;
1822}
1823
1824/**
1825 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1826 * @res: resource entry struct
1827 *
1828 * Return value:
1829 * 1 if NACA queueing model / 0 if not NACA queueing model
1830 **/
1831static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1832{
1833 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1834 return 1;
1835 return 0;
1836}
1837
1838/**
1839 * ipr_is_device - Determine if the hostrcb structure is related to a device
1840 * @hostrcb: host resource control blocks struct
1841 *
1842 * Return value:
1843 * 1 if AF / 0 if not AF
1844 **/
1845static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1846{
1847 struct ipr_res_addr *res_addr;
1848 u8 *res_path;
1849
1850 if (hostrcb->ioa_cfg->sis64) {
1851 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1852 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1853 res_path[0] == 0x81) && res_path[2] != 0xFF)
1854 return 1;
1855 } else {
1856 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1857
1858 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1859 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1860 return 1;
1861 }
1862 return 0;
1863}
1864
1865/**
1866 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1867 * @sdt_word: SDT address
1868 *
1869 * Return value:
1870 * 1 if format 2 / 0 if not
1871 **/
1872static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1873{
1874 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1875
1876 switch (bar_sel) {
1877 case IPR_SDT_FMT2_BAR0_SEL:
1878 case IPR_SDT_FMT2_BAR1_SEL:
1879 case IPR_SDT_FMT2_BAR2_SEL:
1880 case IPR_SDT_FMT2_BAR3_SEL:
1881 case IPR_SDT_FMT2_BAR4_SEL:
1882 case IPR_SDT_FMT2_BAR5_SEL:
1883 case IPR_SDT_FMT2_EXP_ROM_SEL:
1884 return 1;
1885 };
1886
1887 return 0;
1888}
1889
1890#ifndef writeq
1891static inline void writeq(u64 val, void __iomem *addr)
1892{
1893 writel(((u32) (val >> 32)), addr);
1894 writel(((u32) (val)), (addr + 4));
1895}
1896#endif
1897
1898#endif /* _IPR_H */