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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Renesas SDHI
4 *
5 * Copyright (C) 2015-19 Renesas Electronics Corporation
6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
8 * Copyright (C) 2009 Magnus Damm
9 *
10 * Based on "Compaq ASIC3 support":
11 *
12 * Copyright 2001 Compaq Computer Corporation.
13 * Copyright 2004-2005 Phil Blundell
14 * Copyright 2007-2008 OpenedHand Ltd.
15 *
16 * Authors: Phil Blundell <pb@handhelds.org>,
17 * Samuel Ortiz <sameo@openedhand.com>
18 *
19 */
20
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/iopoll.h>
24#include <linux/kernel.h>
25#include <linux/mfd/tmio.h>
26#include <linux/mmc/host.h>
27#include <linux/mmc/mmc.h>
28#include <linux/mmc/slot-gpio.h>
29#include <linux/module.h>
30#include <linux/of_device.h>
31#include <linux/pinctrl/consumer.h>
32#include <linux/pinctrl/pinctrl-state.h>
33#include <linux/platform_device.h>
34#include <linux/pm_domain.h>
35#include <linux/regulator/consumer.h>
36#include <linux/reset.h>
37#include <linux/sh_dma.h>
38#include <linux/slab.h>
39#include <linux/sys_soc.h>
40
41#include "renesas_sdhi.h"
42#include "tmio_mmc.h"
43
44#define CTL_HOST_MODE 0xe4
45#define HOST_MODE_GEN2_SDR50_WMODE BIT(0)
46#define HOST_MODE_GEN2_SDR104_WMODE BIT(0)
47#define HOST_MODE_GEN3_WMODE BIT(0)
48#define HOST_MODE_GEN3_BUSWIDTH BIT(8)
49
50#define HOST_MODE_GEN3_16BIT HOST_MODE_GEN3_WMODE
51#define HOST_MODE_GEN3_32BIT (HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH)
52#define HOST_MODE_GEN3_64BIT 0
53
54#define CTL_SDIF_MODE 0xe6
55#define SDIF_MODE_HS400 BIT(0)
56
57#define SDHI_VER_GEN2_SDR50 0x490c
58#define SDHI_VER_RZ_A1 0x820b
59/* very old datasheets said 0x490c for SDR104, too. They are wrong! */
60#define SDHI_VER_GEN2_SDR104 0xcb0d
61#define SDHI_VER_GEN3_SD 0xcc10
62#define SDHI_VER_GEN3_SDMMC 0xcd10
63
64#define SDHI_GEN3_MMC0_ADDR 0xee140000
65
66static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
67{
68 u32 val;
69
70 /*
71 * see also
72 * renesas_sdhi_of_data :: dma_buswidth
73 */
74 switch (sd_ctrl_read16(host, CTL_VERSION)) {
75 case SDHI_VER_GEN2_SDR50:
76 val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0;
77 break;
78 case SDHI_VER_GEN2_SDR104:
79 val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE;
80 break;
81 case SDHI_VER_GEN3_SD:
82 case SDHI_VER_GEN3_SDMMC:
83 if (width == 64)
84 val = HOST_MODE_GEN3_64BIT;
85 else if (width == 32)
86 val = HOST_MODE_GEN3_32BIT;
87 else
88 val = HOST_MODE_GEN3_16BIT;
89 break;
90 default:
91 /* nothing to do */
92 return;
93 }
94
95 sd_ctrl_write16(host, CTL_HOST_MODE, val);
96}
97
98static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
99{
100 struct mmc_host *mmc = host->mmc;
101 struct renesas_sdhi *priv = host_to_priv(host);
102 int ret;
103
104 ret = clk_prepare_enable(priv->clk_cd);
105 if (ret < 0)
106 return ret;
107
108 /*
109 * The clock driver may not know what maximum frequency
110 * actually works, so it should be set with the max-frequency
111 * property which will already have been read to f_max. If it
112 * was missing, assume the current frequency is the maximum.
113 */
114 if (!mmc->f_max)
115 mmc->f_max = clk_get_rate(priv->clk);
116
117 /*
118 * Minimum frequency is the minimum input clock frequency
119 * divided by our maximum divider.
120 */
121 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
122
123 /* enable 16bit data access on SDBUF as default */
124 renesas_sdhi_sdbuf_width(host, 16);
125
126 return 0;
127}
128
129static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
130 unsigned int new_clock)
131{
132 struct renesas_sdhi *priv = host_to_priv(host);
133 unsigned int freq, diff, best_freq = 0, diff_min = ~0;
134 int i;
135
136 /*
137 * We simply return the current rate if a) we are not on a R-Car Gen2+
138 * SoC (may work for others, but untested) or b) if the SCC needs its
139 * clock during tuning, so we don't change the external clock setup.
140 */
141 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc))
142 return clk_get_rate(priv->clk);
143
144 /*
145 * We want the bus clock to be as close as possible to, but no
146 * greater than, new_clock. As we can divide by 1 << i for
147 * any i in [0, 9] we want the input clock to be as close as
148 * possible, but no greater than, new_clock << i.
149 */
150 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
151 freq = clk_round_rate(priv->clk, new_clock << i);
152 if (freq > (new_clock << i)) {
153 /* Too fast; look for a slightly slower option */
154 freq = clk_round_rate(priv->clk,
155 (new_clock << i) / 4 * 3);
156 if (freq > (new_clock << i))
157 continue;
158 }
159
160 diff = new_clock - (freq >> i);
161 if (diff <= diff_min) {
162 best_freq = freq;
163 diff_min = diff;
164 }
165 }
166
167 clk_set_rate(priv->clk, best_freq);
168
169 return clk_get_rate(priv->clk);
170}
171
172static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
173 unsigned int new_clock)
174{
175 u32 clk = 0, clock;
176
177 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
178 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
179
180 if (new_clock == 0) {
181 host->mmc->actual_clock = 0;
182 goto out;
183 }
184
185 host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
186 clock = host->mmc->actual_clock / 512;
187
188 for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
189 clock <<= 1;
190
191 /* 1/1 clock is option */
192 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
193 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
194 clk |= 0xff;
195 else
196 clk &= ~0xff;
197 }
198
199 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
200 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
201 usleep_range(10000, 11000);
202
203 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
204 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
205
206out:
207 /* HW engineers overrode docs: no sleep needed on R-Car2+ */
208 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
209 usleep_range(10000, 11000);
210}
211
212static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
213{
214 struct renesas_sdhi *priv = host_to_priv(host);
215
216 clk_disable_unprepare(priv->clk_cd);
217}
218
219static int renesas_sdhi_card_busy(struct mmc_host *mmc)
220{
221 struct tmio_mmc_host *host = mmc_priv(mmc);
222
223 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
224 TMIO_STAT_DAT0);
225}
226
227static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
228 struct mmc_ios *ios)
229{
230 struct tmio_mmc_host *host = mmc_priv(mmc);
231 struct renesas_sdhi *priv = host_to_priv(host);
232 struct pinctrl_state *pin_state;
233 int ret;
234
235 switch (ios->signal_voltage) {
236 case MMC_SIGNAL_VOLTAGE_330:
237 pin_state = priv->pins_default;
238 break;
239 case MMC_SIGNAL_VOLTAGE_180:
240 pin_state = priv->pins_uhs;
241 break;
242 default:
243 return -EINVAL;
244 }
245
246 /*
247 * If anything is missing, assume signal voltage is fixed at
248 * 3.3V and succeed/fail accordingly.
249 */
250 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
251 return ios->signal_voltage ==
252 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
253
254 ret = mmc_regulator_set_vqmmc(host->mmc, ios);
255 if (ret < 0)
256 return ret;
257
258 return pinctrl_select_state(priv->pinctrl, pin_state);
259}
260
261/* SCC registers */
262#define SH_MOBILE_SDHI_SCC_DTCNTL 0x000
263#define SH_MOBILE_SDHI_SCC_TAPSET 0x002
264#define SH_MOBILE_SDHI_SCC_DT2FF 0x004
265#define SH_MOBILE_SDHI_SCC_CKSEL 0x006
266#define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008
267#define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A
268#define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C
269#define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E
270#define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014
271#define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016
272#define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018
273#define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A
274#define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C
275
276#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0)
277#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
278#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
279
280#define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0)
281
282#define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
283
284#define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0)
285#define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1)
286#define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2)
287
288#define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8)
289#define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24)
290#define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24))
291
292#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
293#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
294
295/* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */
296#define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
297
298/* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */
299#define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8)
300#define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8)
301#define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F
302
303/* Definitions for values the SH_MOBILE_SDHI_SCC register */
304#define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000
305#define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f
306#define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7)
307
308static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
309 { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15,
310 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 },
311 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11,
312 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 }
313};
314
315static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
316 { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16,
317 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 },
318 { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17,
319 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 }
320};
321
322static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
323 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
324 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
325 { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10,
326 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 }
327};
328
329static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
330 struct renesas_sdhi *priv, int addr)
331{
332 return readl(priv->scc_ctl + (addr << host->bus_shift));
333}
334
335static inline void sd_scc_write32(struct tmio_mmc_host *host,
336 struct renesas_sdhi *priv,
337 int addr, u32 val)
338{
339 writel(val, priv->scc_ctl + (addr << host->bus_shift));
340}
341
342static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
343{
344 struct renesas_sdhi *priv;
345
346 priv = host_to_priv(host);
347
348 /* Initialize SCC */
349 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
350
351 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
352 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
353
354 /* set sampling clock selection range */
355 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
356 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
357 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
358
359 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
360 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
361 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
362
363 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
364 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
365 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
366
367 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
368
369 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
370 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
371
372 /* Read TAPNUM */
373 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
374 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
375 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
376}
377
378static void renesas_sdhi_hs400_complete(struct mmc_host *mmc)
379{
380 struct tmio_mmc_host *host = mmc_priv(mmc);
381 struct renesas_sdhi *priv = host_to_priv(host);
382 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
383 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
384
385 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
386 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
387
388 /* Set HS400 mode */
389 sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 |
390 sd_ctrl_read16(host, CTL_SDIF_MODE));
391
392 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF,
393 priv->scc_tappos_hs400);
394
395 /* Gen3 can't do automatic tap correction with HS400, so disable it */
396 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC)
397 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
398 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
399 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
400
401 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
402 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
403 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
404 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
405
406 /* Set the sampling clock selection range of HS400 mode */
407 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
408 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
409 0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
410
411 /* Avoid bad TAP */
412 if (bad_taps & BIT(priv->tap_set)) {
413 u32 new_tap = (priv->tap_set + 1) % priv->tap_num;
414
415 if (bad_taps & BIT(new_tap))
416 new_tap = (priv->tap_set - 1) % priv->tap_num;
417
418 if (bad_taps & BIT(new_tap)) {
419 new_tap = priv->tap_set;
420 dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n");
421 }
422
423 priv->tap_set = new_tap;
424 }
425
426 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
427 priv->tap_set / (use_4tap ? 2 : 1));
428
429 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
430 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
431 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
432
433 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
434 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
435
436 if (priv->adjust_hs400_calib_table)
437 priv->needs_adjust_hs400 = true;
438}
439
440static void renesas_sdhi_disable_scc(struct mmc_host *mmc)
441{
442 struct tmio_mmc_host *host = mmc_priv(mmc);
443 struct renesas_sdhi *priv = host_to_priv(host);
444
445 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
446 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
447
448 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
449 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
450 sd_scc_read32(host, priv,
451 SH_MOBILE_SDHI_SCC_CKSEL));
452
453 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
454 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
455 sd_scc_read32(host, priv,
456 SH_MOBILE_SDHI_SCC_DTCNTL));
457
458 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
459 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
460}
461
462static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host,
463 struct renesas_sdhi *priv, u32 addr)
464{
465 /* read mode */
466 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
467 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
468 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
469
470 /* access start and stop */
471 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
472 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
473 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
474
475 return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7);
476}
477
478static void sd_scc_tmpport_write32(struct tmio_mmc_host *host,
479 struct renesas_sdhi *priv, u32 addr, u32 val)
480{
481 /* write mode */
482 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
483 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
484 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
485
486 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val);
487
488 /* access start and stop */
489 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
490 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
491 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
492}
493
494static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host)
495{
496 struct renesas_sdhi *priv = host_to_priv(host);
497 u32 calib_code;
498
499 /* disable write protect */
500 sd_scc_tmpport_write32(host, priv, 0x00,
501 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
502 /* read calibration code and adjust */
503 calib_code = sd_scc_tmpport_read32(host, priv, 0x26);
504 calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
505
506 sd_scc_tmpport_write32(host, priv, 0x22,
507 SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE |
508 priv->adjust_hs400_calib_table[calib_code]);
509
510 /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */
511 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3);
512
513 /* adjustment done, clear flag */
514 priv->needs_adjust_hs400 = false;
515}
516
517static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host)
518{
519 struct renesas_sdhi *priv = host_to_priv(host);
520
521 /* disable write protect */
522 sd_scc_tmpport_write32(host, priv, 0x00,
523 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
524 /* disable manual calibration */
525 sd_scc_tmpport_write32(host, priv, 0x22, 0);
526 /* clear offset value of TMPPORT3 */
527 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0);
528}
529
530static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
531 struct renesas_sdhi *priv)
532{
533 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
534 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
535
536 /* Reset HS400 mode */
537 sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 &
538 sd_ctrl_read16(host, CTL_SDIF_MODE));
539
540 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
541
542 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
543 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
544 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
545 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
546
547 if (priv->adjust_hs400_calib_table)
548 renesas_sdhi_adjust_hs400_mode_disable(host);
549
550 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
551 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
552}
553
554static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
555{
556 struct tmio_mmc_host *host = mmc_priv(mmc);
557
558 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
559 return 0;
560}
561
562static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv)
563{
564 renesas_sdhi_disable_scc(host->mmc);
565 renesas_sdhi_reset_hs400_mode(host, priv);
566 priv->needs_adjust_hs400 = false;
567
568 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
569 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
570 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
571}
572
573/* only populated for TMIO_MMC_MIN_RCAR2 */
574static void renesas_sdhi_reset(struct tmio_mmc_host *host)
575{
576 struct renesas_sdhi *priv = host_to_priv(host);
577 int ret;
578 u16 val;
579
580 if (priv->rstc) {
581 reset_control_reset(priv->rstc);
582 /* Unknown why but without polling reset status, it will hang */
583 read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100,
584 false, priv->rstc);
585 /* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */
586 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
587 priv->needs_adjust_hs400 = false;
588 renesas_sdhi_set_clock(host, host->clk_cache);
589 } else if (priv->scc_ctl) {
590 renesas_sdhi_scc_reset(host, priv);
591 }
592
593 if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) {
594 val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
595 val |= CARD_OPT_EXTOP;
596 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val);
597 }
598}
599
600static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host)
601{
602 u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
603
604 num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT;
605 return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num);
606
607}
608
609#define SH_MOBILE_SDHI_MIN_TAP_ROW 3
610
611static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
612{
613 struct renesas_sdhi *priv = host_to_priv(host);
614 unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i;
615 unsigned int taps_size = priv->tap_num * 2, min_tap_row;
616 unsigned long *bitmap;
617
618 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
619
620 /*
621 * When tuning CMD19 is issued twice for each tap, merge the
622 * result requiring the tap to be good in both runs before
623 * considering it for tuning selection.
624 */
625 for (i = 0; i < taps_size; i++) {
626 int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1);
627
628 if (!test_bit(i, priv->taps))
629 clear_bit(i + offset, priv->taps);
630
631 if (!test_bit(i, priv->smpcmp))
632 clear_bit(i + offset, priv->smpcmp);
633 }
634
635 /*
636 * If all TAP are OK, the sampling clock position is selected by
637 * identifying the change point of data.
638 */
639 if (bitmap_full(priv->taps, taps_size)) {
640 bitmap = priv->smpcmp;
641 min_tap_row = 1;
642 } else {
643 bitmap = priv->taps;
644 min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW;
645 }
646
647 /*
648 * Find the longest consecutive run of successful probes. If that
649 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the
650 * center index as the tap, otherwise bail out.
651 */
652 bitmap_for_each_set_region(bitmap, rs, re, 0, taps_size) {
653 if (re - rs > tap_cnt) {
654 tap_end = re;
655 tap_start = rs;
656 tap_cnt = tap_end - tap_start;
657 }
658 }
659
660 if (tap_cnt >= min_tap_row)
661 priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num;
662 else
663 return -EIO;
664
665 /* Set SCC */
666 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set);
667
668 /* Enable auto re-tuning */
669 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
670 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
671 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
672
673 return 0;
674}
675
676static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode)
677{
678 struct tmio_mmc_host *host = mmc_priv(mmc);
679 struct renesas_sdhi *priv = host_to_priv(host);
680 int i, ret;
681
682 priv->tap_num = renesas_sdhi_init_tuning(host);
683 if (!priv->tap_num)
684 return 0; /* Tuning is not supported */
685
686 if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) {
687 dev_err(&host->pdev->dev,
688 "Too many taps, please update 'taps' in tmio_mmc_host!\n");
689 return -EINVAL;
690 }
691
692 bitmap_zero(priv->taps, priv->tap_num * 2);
693 bitmap_zero(priv->smpcmp, priv->tap_num * 2);
694
695 /* Issue CMD19 twice for each tap */
696 for (i = 0; i < 2 * priv->tap_num; i++) {
697 int cmd_error;
698
699 /* Set sampling clock position */
700 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num);
701
702 if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0)
703 set_bit(i, priv->taps);
704
705 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0)
706 set_bit(i, priv->smpcmp);
707
708 if (cmd_error)
709 mmc_send_abort_tuning(mmc, opcode);
710 }
711
712 ret = renesas_sdhi_select_tuning(host);
713 if (ret < 0)
714 renesas_sdhi_scc_reset(host, priv);
715 return ret;
716}
717
718static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap)
719{
720 struct renesas_sdhi *priv = host_to_priv(host);
721 unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set;
722 u32 val;
723
724 val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ);
725 if (!val)
726 return false;
727
728 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
729
730 /* Change TAP position according to correction status */
731 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC &&
732 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
733 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
734 /*
735 * With HS400, the DAT signal is based on DS, not CLK.
736 * Therefore, use only CMD status.
737 */
738 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) &
739 SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR;
740 if (!smpcmp) {
741 return false; /* no error in CMD signal */
742 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) {
743 new_tap++;
744 error_tap--;
745 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) {
746 new_tap--;
747 error_tap++;
748 } else {
749 return true; /* need retune */
750 }
751
752 /*
753 * When new_tap is a bad tap, we cannot change. Then, we compare
754 * with the HS200 tuning result. When smpcmp[error_tap] is OK,
755 * we can at least retune.
756 */
757 if (bad_taps & BIT(new_tap % priv->tap_num))
758 return test_bit(error_tap % priv->tap_num, priv->smpcmp);
759 } else {
760 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)
761 return true; /* need retune */
762 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP)
763 new_tap++;
764 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN)
765 new_tap--;
766 else
767 return false;
768 }
769
770 priv->tap_set = (new_tap % priv->tap_num);
771 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
772 priv->tap_set / (use_4tap ? 2 : 1));
773
774 return false;
775}
776
777static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host)
778{
779 struct renesas_sdhi *priv = host_to_priv(host);
780
781 /* Check SCC error */
782 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
783 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
784 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
785 return true;
786 }
787
788 return false;
789}
790
791static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host,
792 struct mmc_request *mrq)
793{
794 struct renesas_sdhi *priv = host_to_priv(host);
795 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
796 bool ret = false;
797
798 /*
799 * Skip checking SCC errors when running on 4 taps in HS400 mode as
800 * any retuning would still result in the same 4 taps being used.
801 */
802 if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
803 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
804 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
805 return false;
806
807 if (mmc_doing_tune(host->mmc))
808 return false;
809
810 if (((mrq->cmd->error == -ETIMEDOUT) ||
811 (mrq->data && mrq->data->error == -ETIMEDOUT)) &&
812 ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
813 (host->ops.get_cd && host->ops.get_cd(host->mmc))))
814 ret |= true;
815
816 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
817 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN)
818 ret |= renesas_sdhi_auto_correction(host);
819 else
820 ret |= renesas_sdhi_manual_correction(host, use_4tap);
821
822 return ret;
823}
824
825static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
826{
827 int timeout = 1000;
828 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
829 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
830
831 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
832 & bit) == wait_state)
833 udelay(1);
834
835 if (!timeout) {
836 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
837 return -EBUSY;
838 }
839
840 return 0;
841}
842
843static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
844{
845 u32 bit = TMIO_STAT_SCLKDIVEN;
846
847 switch (addr) {
848 case CTL_SD_CMD:
849 case CTL_STOP_INTERNAL_ACTION:
850 case CTL_XFER_BLK_COUNT:
851 case CTL_SD_XFER_LEN:
852 case CTL_SD_MEM_CARD_OPT:
853 case CTL_TRANSACTION_CTL:
854 case CTL_DMA_ENABLE:
855 case CTL_HOST_MODE:
856 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
857 bit = TMIO_STAT_CMD_BUSY;
858 fallthrough;
859 case CTL_SD_CARD_CLK_CTL:
860 return renesas_sdhi_wait_idle(host, bit);
861 }
862
863 return 0;
864}
865
866static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
867 unsigned int direction, int blk_size)
868{
869 /*
870 * In Renesas controllers, when performing a
871 * multiple block read of one or two blocks,
872 * depending on the timing with which the
873 * response register is read, the response
874 * value may not be read properly.
875 * Use single block read for this HW bug
876 */
877 if ((direction == MMC_DATA_READ) &&
878 blk_size == 2)
879 return 1;
880
881 return blk_size;
882}
883
884static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq)
885{
886 struct renesas_sdhi *priv = host_to_priv(host);
887
888 if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS)
889 renesas_sdhi_adjust_hs400_mode_enable(host);
890}
891static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
892{
893 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
894 int width = (host->bus_shift == 2) ? 64 : 32;
895
896 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
897 renesas_sdhi_sdbuf_width(host, enable ? width : 16);
898}
899
900static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
901 .hs400_disabled = true,
902 .hs400_4taps = true,
903};
904
905static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
906 .hs400_4taps = true,
907 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
908};
909
910static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = {
911 .hs400_disabled = true,
912};
913
914static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = {
915 .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
916};
917
918static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = {
919 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
920};
921
922static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
923 .hs400_4taps = true,
924 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
925 .hs400_calib_table = r8a7796_es13_calib_table,
926};
927
928static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
929 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
930 .hs400_calib_table = r8a77965_calib_table,
931};
932
933static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = {
934 .hs400_calib_table = r8a77990_calib_table,
935};
936
937/*
938 * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
939 * So, we want to treat them equally and only have a match for ES1.2 to enforce
940 * this if there ever will be a way to distinguish ES1.2.
941 */
942static const struct soc_device_attribute sdhi_quirks_match[] = {
943 { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
944 { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 },
945 { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap },
946 { .soc_id = "r8a7795", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps2367 },
947 { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
948 { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 },
949 { .soc_id = "r8a77961", .data = &sdhi_quirks_bad_taps1357 },
950 { .soc_id = "r8a77965", .data = &sdhi_quirks_r8a77965 },
951 { .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 },
952 { .soc_id = "r8a77990", .data = &sdhi_quirks_r8a77990 },
953 { /* Sentinel. */ },
954};
955
956int renesas_sdhi_probe(struct platform_device *pdev,
957 const struct tmio_mmc_dma_ops *dma_ops)
958{
959 struct tmio_mmc_data *mmd = pdev->dev.platform_data;
960 const struct renesas_sdhi_quirks *quirks = NULL;
961 const struct renesas_sdhi_of_data *of_data;
962 const struct soc_device_attribute *attr;
963 struct tmio_mmc_data *mmc_data;
964 struct tmio_mmc_dma *dma_priv;
965 struct tmio_mmc_host *host;
966 struct renesas_sdhi *priv;
967 int num_irqs, irq, ret, i;
968 struct resource *res;
969 u16 ver;
970
971 of_data = of_device_get_match_data(&pdev->dev);
972
973 attr = soc_device_match(sdhi_quirks_match);
974 if (attr)
975 quirks = attr->data;
976
977 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
978 if (!res)
979 return -EINVAL;
980
981 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
982 GFP_KERNEL);
983 if (!priv)
984 return -ENOMEM;
985
986 priv->quirks = quirks;
987 mmc_data = &priv->mmc_data;
988 dma_priv = &priv->dma_priv;
989
990 priv->clk = devm_clk_get(&pdev->dev, NULL);
991 if (IS_ERR(priv->clk)) {
992 ret = PTR_ERR(priv->clk);
993 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
994 return ret;
995 }
996
997 /*
998 * Some controllers provide a 2nd clock just to run the internal card
999 * detection logic. Unfortunately, the existing driver architecture does
1000 * not support a separation of clocks for runtime PM usage. When
1001 * native hotplug is used, the tmio driver assumes that the core
1002 * must continue to run for card detect to stay active, so we cannot
1003 * disable it.
1004 * Additionally, it is prohibited to supply a clock to the core but not
1005 * to the card detect circuit. That leaves us with if separate clocks
1006 * are presented, we must treat them both as virtually 1 clock.
1007 */
1008 priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
1009 if (IS_ERR(priv->clk_cd))
1010 priv->clk_cd = NULL;
1011
1012 priv->pinctrl = devm_pinctrl_get(&pdev->dev);
1013 if (!IS_ERR(priv->pinctrl)) {
1014 priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
1015 PINCTRL_STATE_DEFAULT);
1016 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
1017 "state_uhs");
1018 }
1019
1020 host = tmio_mmc_host_alloc(pdev, mmc_data);
1021 if (IS_ERR(host))
1022 return PTR_ERR(host);
1023
1024 if (of_data) {
1025 mmc_data->flags |= of_data->tmio_flags;
1026 mmc_data->ocr_mask = of_data->tmio_ocr_mask;
1027 mmc_data->capabilities |= of_data->capabilities;
1028 mmc_data->capabilities2 |= of_data->capabilities2;
1029 mmc_data->dma_rx_offset = of_data->dma_rx_offset;
1030 mmc_data->max_blk_count = of_data->max_blk_count;
1031 mmc_data->max_segs = of_data->max_segs;
1032 dma_priv->dma_buswidth = of_data->dma_buswidth;
1033 host->bus_shift = of_data->bus_shift;
1034 }
1035
1036 host->write16_hook = renesas_sdhi_write16_hook;
1037 host->clk_enable = renesas_sdhi_clk_enable;
1038 host->clk_disable = renesas_sdhi_clk_disable;
1039 host->set_clock = renesas_sdhi_set_clock;
1040 host->multi_io_quirk = renesas_sdhi_multi_io_quirk;
1041 host->dma_ops = dma_ops;
1042
1043 if (quirks && quirks->hs400_disabled)
1044 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
1045
1046 /* For some SoC, we disable internal WP. GPIO may override this */
1047 if (mmc_can_gpio_ro(host->mmc))
1048 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
1049
1050 /* SDR speeds are only available on Gen2+ */
1051 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
1052 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
1053 host->ops.card_busy = renesas_sdhi_card_busy;
1054 host->ops.start_signal_voltage_switch =
1055 renesas_sdhi_start_signal_voltage_switch;
1056 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27;
1057 host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2;
1058 host->reset = renesas_sdhi_reset;
1059 }
1060
1061 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
1062 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
1063 host->bus_shift = 1;
1064
1065 if (mmd)
1066 *mmc_data = *mmd;
1067
1068 dma_priv->filter = shdma_chan_filter;
1069 dma_priv->enable = renesas_sdhi_enable_dma;
1070
1071 mmc_data->alignment_shift = 1; /* 2-byte alignment */
1072 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
1073
1074 /*
1075 * All SDHI blocks support 2-byte and larger block sizes in 4-bit
1076 * bus width mode.
1077 */
1078 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
1079
1080 /*
1081 * All SDHI blocks support SDIO IRQ signalling.
1082 */
1083 mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
1084
1085 /* All SDHI have CMD12 control bit */
1086 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
1087
1088 /* All SDHI have SDIO status bits which must be 1 */
1089 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
1090
1091 /* All SDHI support HW busy detection */
1092 mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT;
1093
1094 dev_pm_domain_start(&pdev->dev);
1095
1096 ret = renesas_sdhi_clk_enable(host);
1097 if (ret)
1098 goto efree;
1099
1100 priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1101 if (IS_ERR(priv->rstc))
1102 return PTR_ERR(priv->rstc);
1103
1104 ver = sd_ctrl_read16(host, CTL_VERSION);
1105 /* GEN2_SDR104 is first known SDHI to use 32bit block count */
1106 if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
1107 mmc_data->max_blk_count = U16_MAX;
1108
1109 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */
1110 if (ver == SDHI_VER_GEN2_SDR50)
1111 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
1112
1113 if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) {
1114 host->fixup_request = renesas_sdhi_fixup_request;
1115 priv->adjust_hs400_calib_table = *(
1116 res->start == SDHI_GEN3_MMC0_ADDR ?
1117 quirks->hs400_calib_table :
1118 quirks->hs400_calib_table + 1);
1119 }
1120
1121 /* these have an EXTOP bit */
1122 if (ver >= SDHI_VER_GEN3_SD)
1123 host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles;
1124
1125 /* Enable tuning iff we have an SCC and a supported mode */
1126 if (of_data && of_data->scc_offset &&
1127 (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
1128 host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
1129 MMC_CAP2_HS400_1_8V))) {
1130 const struct renesas_sdhi_scc *taps = of_data->taps;
1131 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
1132 bool hit = false;
1133
1134 for (i = 0; i < of_data->taps_num; i++) {
1135 if (taps[i].clk_rate == 0 ||
1136 taps[i].clk_rate == host->mmc->f_max) {
1137 priv->scc_tappos = taps->tap;
1138 priv->scc_tappos_hs400 = use_4tap ?
1139 taps->tap_hs400_4tap :
1140 taps->tap;
1141 hit = true;
1142 break;
1143 }
1144 }
1145
1146 if (!hit)
1147 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n");
1148
1149 priv->scc_ctl = host->ctl + of_data->scc_offset;
1150 host->check_retune = renesas_sdhi_check_scc_error;
1151 host->ops.execute_tuning = renesas_sdhi_execute_tuning;
1152 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning;
1153 host->ops.hs400_downgrade = renesas_sdhi_disable_scc;
1154 host->ops.hs400_complete = renesas_sdhi_hs400_complete;
1155 }
1156
1157 ret = tmio_mmc_host_probe(host);
1158 if (ret < 0)
1159 goto edisclk;
1160
1161 num_irqs = platform_irq_count(pdev);
1162 if (num_irqs < 0) {
1163 ret = num_irqs;
1164 goto eirq;
1165 }
1166
1167 /* There must be at least one IRQ source */
1168 if (!num_irqs) {
1169 ret = -ENXIO;
1170 goto eirq;
1171 }
1172
1173 for (i = 0; i < num_irqs; i++) {
1174 irq = platform_get_irq(pdev, i);
1175 if (irq < 0) {
1176 ret = irq;
1177 goto eirq;
1178 }
1179
1180 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
1181 dev_name(&pdev->dev), host);
1182 if (ret)
1183 goto eirq;
1184 }
1185
1186 dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n",
1187 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000);
1188
1189 return ret;
1190
1191eirq:
1192 tmio_mmc_host_remove(host);
1193edisclk:
1194 renesas_sdhi_clk_disable(host);
1195efree:
1196 tmio_mmc_host_free(host);
1197
1198 return ret;
1199}
1200EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
1201
1202int renesas_sdhi_remove(struct platform_device *pdev)
1203{
1204 struct tmio_mmc_host *host = platform_get_drvdata(pdev);
1205
1206 tmio_mmc_host_remove(host);
1207 renesas_sdhi_clk_disable(host);
1208 tmio_mmc_host_free(host);
1209
1210 return 0;
1211}
1212EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
1213
1214MODULE_LICENSE("GPL v2");