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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
4 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
5 *
6 * ARM Mali DP500/DP550/DP650 KMS/DRM driver
7 */
8
9#include <linux/module.h>
10#include <linux/clk.h>
11#include <linux/component.h>
12#include <linux/of_device.h>
13#include <linux/of_graph.h>
14#include <linux/of_reserved_mem.h>
15#include <linux/pm_runtime.h>
16#include <linux/debugfs.h>
17
18#include <drm/drm_atomic.h>
19#include <drm/drm_atomic_helper.h>
20#include <drm/drm_crtc.h>
21#include <drm/drm_drv.h>
22#include <drm/drm_fb_cma_helper.h>
23#include <drm/drm_fb_helper.h>
24#include <drm/drm_fourcc.h>
25#include <drm/drm_gem_cma_helper.h>
26#include <drm/drm_gem_framebuffer_helper.h>
27#include <drm/drm_modeset_helper.h>
28#include <drm/drm_of.h>
29#include <drm/drm_probe_helper.h>
30#include <drm/drm_vblank.h>
31
32#include "malidp_drv.h"
33#include "malidp_mw.h"
34#include "malidp_regs.h"
35#include "malidp_hw.h"
36
37#define MALIDP_CONF_VALID_TIMEOUT 250
38#define AFBC_HEADER_SIZE 16
39#define AFBC_SUPERBLK_ALIGNMENT 128
40
41static void malidp_write_gamma_table(struct malidp_hw_device *hwdev,
42 u32 data[MALIDP_COEFFTAB_NUM_COEFFS])
43{
44 int i;
45 /* Update all channels with a single gamma curve. */
46 const u32 gamma_write_mask = GENMASK(18, 16);
47 /*
48 * Always write an entire table, so the address field in
49 * DE_COEFFTAB_ADDR is 0 and we can use the gamma_write_mask bitmask
50 * directly.
51 */
52 malidp_hw_write(hwdev, gamma_write_mask,
53 hwdev->hw->map.coeffs_base + MALIDP_COEF_TABLE_ADDR);
54 for (i = 0; i < MALIDP_COEFFTAB_NUM_COEFFS; ++i)
55 malidp_hw_write(hwdev, data[i],
56 hwdev->hw->map.coeffs_base +
57 MALIDP_COEF_TABLE_DATA);
58}
59
60static void malidp_atomic_commit_update_gamma(struct drm_crtc *crtc,
61 struct drm_crtc_state *old_state)
62{
63 struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
64 struct malidp_hw_device *hwdev = malidp->dev;
65
66 if (!crtc->state->color_mgmt_changed)
67 return;
68
69 if (!crtc->state->gamma_lut) {
70 malidp_hw_clearbits(hwdev,
71 MALIDP_DISP_FUNC_GAMMA,
72 MALIDP_DE_DISPLAY_FUNC);
73 } else {
74 struct malidp_crtc_state *mc =
75 to_malidp_crtc_state(crtc->state);
76
77 if (!old_state->gamma_lut || (crtc->state->gamma_lut->base.id !=
78 old_state->gamma_lut->base.id))
79 malidp_write_gamma_table(hwdev, mc->gamma_coeffs);
80
81 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_GAMMA,
82 MALIDP_DE_DISPLAY_FUNC);
83 }
84}
85
86static
87void malidp_atomic_commit_update_coloradj(struct drm_crtc *crtc,
88 struct drm_crtc_state *old_state)
89{
90 struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
91 struct malidp_hw_device *hwdev = malidp->dev;
92 int i;
93
94 if (!crtc->state->color_mgmt_changed)
95 return;
96
97 if (!crtc->state->ctm) {
98 malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_CADJ,
99 MALIDP_DE_DISPLAY_FUNC);
100 } else {
101 struct malidp_crtc_state *mc =
102 to_malidp_crtc_state(crtc->state);
103
104 if (!old_state->ctm || (crtc->state->ctm->base.id !=
105 old_state->ctm->base.id))
106 for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; ++i)
107 malidp_hw_write(hwdev,
108 mc->coloradj_coeffs[i],
109 hwdev->hw->map.coeffs_base +
110 MALIDP_COLOR_ADJ_COEF + 4 * i);
111
112 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_CADJ,
113 MALIDP_DE_DISPLAY_FUNC);
114 }
115}
116
117static void malidp_atomic_commit_se_config(struct drm_crtc *crtc,
118 struct drm_crtc_state *old_state)
119{
120 struct malidp_crtc_state *cs = to_malidp_crtc_state(crtc->state);
121 struct malidp_crtc_state *old_cs = to_malidp_crtc_state(old_state);
122 struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
123 struct malidp_hw_device *hwdev = malidp->dev;
124 struct malidp_se_config *s = &cs->scaler_config;
125 struct malidp_se_config *old_s = &old_cs->scaler_config;
126 u32 se_control = hwdev->hw->map.se_base +
127 ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ?
128 0x10 : 0xC);
129 u32 layer_control = se_control + MALIDP_SE_LAYER_CONTROL;
130 u32 scr = se_control + MALIDP_SE_SCALING_CONTROL;
131 u32 val;
132
133 /* Set SE_CONTROL */
134 if (!s->scale_enable) {
135 val = malidp_hw_read(hwdev, se_control);
136 val &= ~MALIDP_SE_SCALING_EN;
137 malidp_hw_write(hwdev, val, se_control);
138 return;
139 }
140
141 hwdev->hw->se_set_scaling_coeffs(hwdev, s, old_s);
142 val = malidp_hw_read(hwdev, se_control);
143 val |= MALIDP_SE_SCALING_EN | MALIDP_SE_ALPHA_EN;
144
145 val &= ~MALIDP_SE_ENH(MALIDP_SE_ENH_MASK);
146 val |= s->enhancer_enable ? MALIDP_SE_ENH(3) : 0;
147
148 val |= MALIDP_SE_RGBO_IF_EN;
149 malidp_hw_write(hwdev, val, se_control);
150
151 /* Set IN_SIZE & OUT_SIZE. */
152 val = MALIDP_SE_SET_V_SIZE(s->input_h) |
153 MALIDP_SE_SET_H_SIZE(s->input_w);
154 malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_IN_SIZE);
155 val = MALIDP_SE_SET_V_SIZE(s->output_h) |
156 MALIDP_SE_SET_H_SIZE(s->output_w);
157 malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_OUT_SIZE);
158
159 /* Set phase regs. */
160 malidp_hw_write(hwdev, s->h_init_phase, scr + MALIDP_SE_H_INIT_PH);
161 malidp_hw_write(hwdev, s->h_delta_phase, scr + MALIDP_SE_H_DELTA_PH);
162 malidp_hw_write(hwdev, s->v_init_phase, scr + MALIDP_SE_V_INIT_PH);
163 malidp_hw_write(hwdev, s->v_delta_phase, scr + MALIDP_SE_V_DELTA_PH);
164}
165
166/*
167 * set the "config valid" bit and wait until the hardware acts on it
168 */
169static int malidp_set_and_wait_config_valid(struct drm_device *drm)
170{
171 struct malidp_drm *malidp = drm->dev_private;
172 struct malidp_hw_device *hwdev = malidp->dev;
173 int ret;
174
175 hwdev->hw->set_config_valid(hwdev, 1);
176 /* don't wait for config_valid flag if we are in config mode */
177 if (hwdev->hw->in_config_mode(hwdev)) {
178 atomic_set(&malidp->config_valid, MALIDP_CONFIG_VALID_DONE);
179 return 0;
180 }
181
182 ret = wait_event_interruptible_timeout(malidp->wq,
183 atomic_read(&malidp->config_valid) == MALIDP_CONFIG_VALID_DONE,
184 msecs_to_jiffies(MALIDP_CONF_VALID_TIMEOUT));
185
186 return (ret > 0) ? 0 : -ETIMEDOUT;
187}
188
189static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state)
190{
191 struct drm_device *drm = state->dev;
192 struct malidp_drm *malidp = drm->dev_private;
193 int loop = 5;
194
195 malidp->event = malidp->crtc.state->event;
196 malidp->crtc.state->event = NULL;
197
198 if (malidp->crtc.state->active) {
199 /*
200 * if we have an event to deliver to userspace, make sure
201 * the vblank is enabled as we are sending it from the IRQ
202 * handler.
203 */
204 if (malidp->event)
205 drm_crtc_vblank_get(&malidp->crtc);
206
207 /* only set config_valid if the CRTC is enabled */
208 if (malidp_set_and_wait_config_valid(drm) < 0) {
209 /*
210 * make a loop around the second CVAL setting and
211 * try 5 times before giving up.
212 */
213 while (loop--) {
214 if (!malidp_set_and_wait_config_valid(drm))
215 break;
216 }
217 DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n");
218 }
219
220 } else if (malidp->event) {
221 /* CRTC inactive means vblank IRQ is disabled, send event directly */
222 spin_lock_irq(&drm->event_lock);
223 drm_crtc_send_vblank_event(&malidp->crtc, malidp->event);
224 malidp->event = NULL;
225 spin_unlock_irq(&drm->event_lock);
226 }
227 drm_atomic_helper_commit_hw_done(state);
228}
229
230static void malidp_atomic_commit_tail(struct drm_atomic_state *state)
231{
232 struct drm_device *drm = state->dev;
233 struct malidp_drm *malidp = drm->dev_private;
234 struct drm_crtc *crtc;
235 struct drm_crtc_state *old_crtc_state;
236 int i;
237 bool fence_cookie = dma_fence_begin_signalling();
238
239 pm_runtime_get_sync(drm->dev);
240
241 /*
242 * set config_valid to a special value to let IRQ handlers
243 * know that we are updating registers
244 */
245 atomic_set(&malidp->config_valid, MALIDP_CONFIG_START);
246 malidp->dev->hw->set_config_valid(malidp->dev, 0);
247
248 drm_atomic_helper_commit_modeset_disables(drm, state);
249
250 for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
251 malidp_atomic_commit_update_gamma(crtc, old_crtc_state);
252 malidp_atomic_commit_update_coloradj(crtc, old_crtc_state);
253 malidp_atomic_commit_se_config(crtc, old_crtc_state);
254 }
255
256 drm_atomic_helper_commit_planes(drm, state, DRM_PLANE_COMMIT_ACTIVE_ONLY);
257
258 malidp_mw_atomic_commit(drm, state);
259
260 drm_atomic_helper_commit_modeset_enables(drm, state);
261
262 malidp_atomic_commit_hw_done(state);
263
264 dma_fence_end_signalling(fence_cookie);
265
266 pm_runtime_put(drm->dev);
267
268 drm_atomic_helper_cleanup_planes(drm, state);
269}
270
271static const struct drm_mode_config_helper_funcs malidp_mode_config_helpers = {
272 .atomic_commit_tail = malidp_atomic_commit_tail,
273};
274
275static bool
276malidp_verify_afbc_framebuffer_caps(struct drm_device *dev,
277 const struct drm_mode_fb_cmd2 *mode_cmd)
278{
279 if (malidp_format_mod_supported(dev, mode_cmd->pixel_format,
280 mode_cmd->modifier[0]) == false)
281 return false;
282
283 if (mode_cmd->offsets[0] != 0) {
284 DRM_DEBUG_KMS("AFBC buffers' plane offset should be 0\n");
285 return false;
286 }
287
288 switch (mode_cmd->modifier[0] & AFBC_SIZE_MASK) {
289 case AFBC_SIZE_16X16:
290 if ((mode_cmd->width % 16) || (mode_cmd->height % 16)) {
291 DRM_DEBUG_KMS("AFBC buffers must be aligned to 16 pixels\n");
292 return false;
293 }
294 break;
295 default:
296 DRM_DEBUG_KMS("Unsupported AFBC block size\n");
297 return false;
298 }
299
300 return true;
301}
302
303static bool
304malidp_verify_afbc_framebuffer_size(struct drm_device *dev,
305 struct drm_file *file,
306 const struct drm_mode_fb_cmd2 *mode_cmd)
307{
308 int n_superblocks = 0;
309 const struct drm_format_info *info;
310 struct drm_gem_object *objs = NULL;
311 u32 afbc_superblock_size = 0, afbc_superblock_height = 0;
312 u32 afbc_superblock_width = 0, afbc_size = 0;
313 int bpp = 0;
314
315 switch (mode_cmd->modifier[0] & AFBC_SIZE_MASK) {
316 case AFBC_SIZE_16X16:
317 afbc_superblock_height = 16;
318 afbc_superblock_width = 16;
319 break;
320 default:
321 DRM_DEBUG_KMS("AFBC superblock size is not supported\n");
322 return false;
323 }
324
325 info = drm_get_format_info(dev, mode_cmd);
326
327 n_superblocks = (mode_cmd->width / afbc_superblock_width) *
328 (mode_cmd->height / afbc_superblock_height);
329
330 bpp = malidp_format_get_bpp(info->format);
331
332 afbc_superblock_size = (bpp * afbc_superblock_width * afbc_superblock_height)
333 / BITS_PER_BYTE;
334
335 afbc_size = ALIGN(n_superblocks * AFBC_HEADER_SIZE, AFBC_SUPERBLK_ALIGNMENT);
336 afbc_size += n_superblocks * ALIGN(afbc_superblock_size, AFBC_SUPERBLK_ALIGNMENT);
337
338 if ((mode_cmd->width * bpp) != (mode_cmd->pitches[0] * BITS_PER_BYTE)) {
339 DRM_DEBUG_KMS("Invalid value of (pitch * BITS_PER_BYTE) (=%u) "
340 "should be same as width (=%u) * bpp (=%u)\n",
341 (mode_cmd->pitches[0] * BITS_PER_BYTE),
342 mode_cmd->width, bpp);
343 return false;
344 }
345
346 objs = drm_gem_object_lookup(file, mode_cmd->handles[0]);
347 if (!objs) {
348 DRM_DEBUG_KMS("Failed to lookup GEM object\n");
349 return false;
350 }
351
352 if (objs->size < afbc_size) {
353 DRM_DEBUG_KMS("buffer size (%zu) too small for AFBC buffer size = %u\n",
354 objs->size, afbc_size);
355 drm_gem_object_put(objs);
356 return false;
357 }
358
359 drm_gem_object_put(objs);
360
361 return true;
362}
363
364static bool
365malidp_verify_afbc_framebuffer(struct drm_device *dev, struct drm_file *file,
366 const struct drm_mode_fb_cmd2 *mode_cmd)
367{
368 if (malidp_verify_afbc_framebuffer_caps(dev, mode_cmd))
369 return malidp_verify_afbc_framebuffer_size(dev, file, mode_cmd);
370
371 return false;
372}
373
374static struct drm_framebuffer *
375malidp_fb_create(struct drm_device *dev, struct drm_file *file,
376 const struct drm_mode_fb_cmd2 *mode_cmd)
377{
378 if (mode_cmd->modifier[0]) {
379 if (!malidp_verify_afbc_framebuffer(dev, file, mode_cmd))
380 return ERR_PTR(-EINVAL);
381 }
382
383 return drm_gem_fb_create(dev, file, mode_cmd);
384}
385
386static const struct drm_mode_config_funcs malidp_mode_config_funcs = {
387 .fb_create = malidp_fb_create,
388 .atomic_check = drm_atomic_helper_check,
389 .atomic_commit = drm_atomic_helper_commit,
390};
391
392static int malidp_init(struct drm_device *drm)
393{
394 int ret;
395 struct malidp_drm *malidp = drm->dev_private;
396 struct malidp_hw_device *hwdev = malidp->dev;
397
398 drm_mode_config_init(drm);
399
400 drm->mode_config.min_width = hwdev->min_line_size;
401 drm->mode_config.min_height = hwdev->min_line_size;
402 drm->mode_config.max_width = hwdev->max_line_size;
403 drm->mode_config.max_height = hwdev->max_line_size;
404 drm->mode_config.funcs = &malidp_mode_config_funcs;
405 drm->mode_config.helper_private = &malidp_mode_config_helpers;
406
407 ret = malidp_crtc_init(drm);
408 if (ret)
409 goto crtc_fail;
410
411 ret = malidp_mw_connector_init(drm);
412 if (ret)
413 goto crtc_fail;
414
415 return 0;
416
417crtc_fail:
418 drm_mode_config_cleanup(drm);
419 return ret;
420}
421
422static void malidp_fini(struct drm_device *drm)
423{
424 drm_mode_config_cleanup(drm);
425}
426
427static int malidp_irq_init(struct platform_device *pdev)
428{
429 int irq_de, irq_se, ret = 0;
430 struct drm_device *drm = dev_get_drvdata(&pdev->dev);
431 struct malidp_drm *malidp = drm->dev_private;
432 struct malidp_hw_device *hwdev = malidp->dev;
433
434 /* fetch the interrupts from DT */
435 irq_de = platform_get_irq_byname(pdev, "DE");
436 if (irq_de < 0) {
437 DRM_ERROR("no 'DE' IRQ specified!\n");
438 return irq_de;
439 }
440 irq_se = platform_get_irq_byname(pdev, "SE");
441 if (irq_se < 0) {
442 DRM_ERROR("no 'SE' IRQ specified!\n");
443 return irq_se;
444 }
445
446 ret = malidp_de_irq_init(drm, irq_de);
447 if (ret)
448 return ret;
449
450 ret = malidp_se_irq_init(drm, irq_se);
451 if (ret) {
452 malidp_de_irq_fini(hwdev);
453 return ret;
454 }
455
456 return 0;
457}
458
459DEFINE_DRM_GEM_CMA_FOPS(fops);
460
461static int malidp_dumb_create(struct drm_file *file_priv,
462 struct drm_device *drm,
463 struct drm_mode_create_dumb *args)
464{
465 struct malidp_drm *malidp = drm->dev_private;
466 /* allocate for the worst case scenario, i.e. rotated buffers */
467 u8 alignment = malidp_hw_get_pitch_align(malidp->dev, 1);
468
469 args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), alignment);
470
471 return drm_gem_cma_dumb_create_internal(file_priv, drm, args);
472}
473
474#ifdef CONFIG_DEBUG_FS
475
476static void malidp_error_stats_init(struct malidp_error_stats *error_stats)
477{
478 error_stats->num_errors = 0;
479 error_stats->last_error_status = 0;
480 error_stats->last_error_vblank = -1;
481}
482
483void malidp_error(struct malidp_drm *malidp,
484 struct malidp_error_stats *error_stats, u32 status,
485 u64 vblank)
486{
487 unsigned long irqflags;
488
489 spin_lock_irqsave(&malidp->errors_lock, irqflags);
490 error_stats->last_error_status = status;
491 error_stats->last_error_vblank = vblank;
492 error_stats->num_errors++;
493 spin_unlock_irqrestore(&malidp->errors_lock, irqflags);
494}
495
496static void malidp_error_stats_dump(const char *prefix,
497 struct malidp_error_stats error_stats,
498 struct seq_file *m)
499{
500 seq_printf(m, "[%s] num_errors : %d\n", prefix,
501 error_stats.num_errors);
502 seq_printf(m, "[%s] last_error_status : 0x%08x\n", prefix,
503 error_stats.last_error_status);
504 seq_printf(m, "[%s] last_error_vblank : %lld\n", prefix,
505 error_stats.last_error_vblank);
506}
507
508static int malidp_show_stats(struct seq_file *m, void *arg)
509{
510 struct drm_device *drm = m->private;
511 struct malidp_drm *malidp = drm->dev_private;
512 unsigned long irqflags;
513 struct malidp_error_stats de_errors, se_errors;
514
515 spin_lock_irqsave(&malidp->errors_lock, irqflags);
516 de_errors = malidp->de_errors;
517 se_errors = malidp->se_errors;
518 spin_unlock_irqrestore(&malidp->errors_lock, irqflags);
519 malidp_error_stats_dump("DE", de_errors, m);
520 malidp_error_stats_dump("SE", se_errors, m);
521 return 0;
522}
523
524static int malidp_debugfs_open(struct inode *inode, struct file *file)
525{
526 return single_open(file, malidp_show_stats, inode->i_private);
527}
528
529static ssize_t malidp_debugfs_write(struct file *file, const char __user *ubuf,
530 size_t len, loff_t *offp)
531{
532 struct seq_file *m = file->private_data;
533 struct drm_device *drm = m->private;
534 struct malidp_drm *malidp = drm->dev_private;
535 unsigned long irqflags;
536
537 spin_lock_irqsave(&malidp->errors_lock, irqflags);
538 malidp_error_stats_init(&malidp->de_errors);
539 malidp_error_stats_init(&malidp->se_errors);
540 spin_unlock_irqrestore(&malidp->errors_lock, irqflags);
541 return len;
542}
543
544static const struct file_operations malidp_debugfs_fops = {
545 .owner = THIS_MODULE,
546 .open = malidp_debugfs_open,
547 .read = seq_read,
548 .write = malidp_debugfs_write,
549 .llseek = seq_lseek,
550 .release = single_release,
551};
552
553static void malidp_debugfs_init(struct drm_minor *minor)
554{
555 struct malidp_drm *malidp = minor->dev->dev_private;
556
557 malidp_error_stats_init(&malidp->de_errors);
558 malidp_error_stats_init(&malidp->se_errors);
559 spin_lock_init(&malidp->errors_lock);
560 debugfs_create_file("debug", S_IRUGO | S_IWUSR, minor->debugfs_root,
561 minor->dev, &malidp_debugfs_fops);
562}
563
564#endif //CONFIG_DEBUG_FS
565
566static const struct drm_driver malidp_driver = {
567 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
568 DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(malidp_dumb_create),
569#ifdef CONFIG_DEBUG_FS
570 .debugfs_init = malidp_debugfs_init,
571#endif
572 .fops = &fops,
573 .name = "mali-dp",
574 .desc = "ARM Mali Display Processor driver",
575 .date = "20160106",
576 .major = 1,
577 .minor = 0,
578};
579
580static const struct of_device_id malidp_drm_of_match[] = {
581 {
582 .compatible = "arm,mali-dp500",
583 .data = &malidp_device[MALIDP_500]
584 },
585 {
586 .compatible = "arm,mali-dp550",
587 .data = &malidp_device[MALIDP_550]
588 },
589 {
590 .compatible = "arm,mali-dp650",
591 .data = &malidp_device[MALIDP_650]
592 },
593 {},
594};
595MODULE_DEVICE_TABLE(of, malidp_drm_of_match);
596
597static bool malidp_is_compatible_hw_id(struct malidp_hw_device *hwdev,
598 const struct of_device_id *dev_id)
599{
600 u32 core_id;
601 const char *compatstr_dp500 = "arm,mali-dp500";
602 bool is_dp500;
603 bool dt_is_dp500;
604
605 /*
606 * The DP500 CORE_ID register is in a different location, so check it
607 * first. If the product id field matches, then this is DP500, otherwise
608 * check the DP550/650 CORE_ID register.
609 */
610 core_id = malidp_hw_read(hwdev, MALIDP500_DC_BASE + MALIDP_DE_CORE_ID);
611 /* Offset 0x18 will never read 0x500 on products other than DP500. */
612 is_dp500 = (MALIDP_PRODUCT_ID(core_id) == 0x500);
613 dt_is_dp500 = strnstr(dev_id->compatible, compatstr_dp500,
614 sizeof(dev_id->compatible)) != NULL;
615 if (is_dp500 != dt_is_dp500) {
616 DRM_ERROR("Device-tree expects %s, but hardware %s DP500.\n",
617 dev_id->compatible, is_dp500 ? "is" : "is not");
618 return false;
619 } else if (!dt_is_dp500) {
620 u16 product_id;
621 char buf[32];
622
623 core_id = malidp_hw_read(hwdev,
624 MALIDP550_DC_BASE + MALIDP_DE_CORE_ID);
625 product_id = MALIDP_PRODUCT_ID(core_id);
626 snprintf(buf, sizeof(buf), "arm,mali-dp%X", product_id);
627 if (!strnstr(dev_id->compatible, buf,
628 sizeof(dev_id->compatible))) {
629 DRM_ERROR("Device-tree expects %s, but hardware is DP%03X.\n",
630 dev_id->compatible, product_id);
631 return false;
632 }
633 }
634 return true;
635}
636
637static bool malidp_has_sufficient_address_space(const struct resource *res,
638 const struct of_device_id *dev_id)
639{
640 resource_size_t res_size = resource_size(res);
641 const char *compatstr_dp500 = "arm,mali-dp500";
642
643 if (!strnstr(dev_id->compatible, compatstr_dp500,
644 sizeof(dev_id->compatible)))
645 return res_size >= MALIDP550_ADDR_SPACE_SIZE;
646 else if (res_size < MALIDP500_ADDR_SPACE_SIZE)
647 return false;
648 return true;
649}
650
651static ssize_t core_id_show(struct device *dev, struct device_attribute *attr,
652 char *buf)
653{
654 struct drm_device *drm = dev_get_drvdata(dev);
655 struct malidp_drm *malidp = drm->dev_private;
656
657 return snprintf(buf, PAGE_SIZE, "%08x\n", malidp->core_id);
658}
659
660static DEVICE_ATTR_RO(core_id);
661
662static struct attribute *mali_dp_attrs[] = {
663 &dev_attr_core_id.attr,
664 NULL,
665};
666ATTRIBUTE_GROUPS(mali_dp);
667
668#define MAX_OUTPUT_CHANNELS 3
669
670static int malidp_runtime_pm_suspend(struct device *dev)
671{
672 struct drm_device *drm = dev_get_drvdata(dev);
673 struct malidp_drm *malidp = drm->dev_private;
674 struct malidp_hw_device *hwdev = malidp->dev;
675
676 /* we can only suspend if the hardware is in config mode */
677 WARN_ON(!hwdev->hw->in_config_mode(hwdev));
678
679 malidp_se_irq_fini(hwdev);
680 malidp_de_irq_fini(hwdev);
681 hwdev->pm_suspended = true;
682 clk_disable_unprepare(hwdev->mclk);
683 clk_disable_unprepare(hwdev->aclk);
684 clk_disable_unprepare(hwdev->pclk);
685
686 return 0;
687}
688
689static int malidp_runtime_pm_resume(struct device *dev)
690{
691 struct drm_device *drm = dev_get_drvdata(dev);
692 struct malidp_drm *malidp = drm->dev_private;
693 struct malidp_hw_device *hwdev = malidp->dev;
694
695 clk_prepare_enable(hwdev->pclk);
696 clk_prepare_enable(hwdev->aclk);
697 clk_prepare_enable(hwdev->mclk);
698 hwdev->pm_suspended = false;
699 malidp_de_irq_hw_init(hwdev);
700 malidp_se_irq_hw_init(hwdev);
701
702 return 0;
703}
704
705static int malidp_bind(struct device *dev)
706{
707 struct resource *res;
708 struct drm_device *drm;
709 struct malidp_drm *malidp;
710 struct malidp_hw_device *hwdev;
711 struct platform_device *pdev = to_platform_device(dev);
712 struct of_device_id const *dev_id;
713 struct drm_encoder *encoder;
714 /* number of lines for the R, G and B output */
715 u8 output_width[MAX_OUTPUT_CHANNELS];
716 int ret = 0, i;
717 u32 version, out_depth = 0;
718
719 malidp = devm_kzalloc(dev, sizeof(*malidp), GFP_KERNEL);
720 if (!malidp)
721 return -ENOMEM;
722
723 hwdev = devm_kzalloc(dev, sizeof(*hwdev), GFP_KERNEL);
724 if (!hwdev)
725 return -ENOMEM;
726
727 hwdev->hw = (struct malidp_hw *)of_device_get_match_data(dev);
728 malidp->dev = hwdev;
729
730 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
731 hwdev->regs = devm_ioremap_resource(dev, res);
732 if (IS_ERR(hwdev->regs))
733 return PTR_ERR(hwdev->regs);
734
735 hwdev->pclk = devm_clk_get(dev, "pclk");
736 if (IS_ERR(hwdev->pclk))
737 return PTR_ERR(hwdev->pclk);
738
739 hwdev->aclk = devm_clk_get(dev, "aclk");
740 if (IS_ERR(hwdev->aclk))
741 return PTR_ERR(hwdev->aclk);
742
743 hwdev->mclk = devm_clk_get(dev, "mclk");
744 if (IS_ERR(hwdev->mclk))
745 return PTR_ERR(hwdev->mclk);
746
747 hwdev->pxlclk = devm_clk_get(dev, "pxlclk");
748 if (IS_ERR(hwdev->pxlclk))
749 return PTR_ERR(hwdev->pxlclk);
750
751 /* Get the optional framebuffer memory resource */
752 ret = of_reserved_mem_device_init(dev);
753 if (ret && ret != -ENODEV)
754 return ret;
755
756 drm = drm_dev_alloc(&malidp_driver, dev);
757 if (IS_ERR(drm)) {
758 ret = PTR_ERR(drm);
759 goto alloc_fail;
760 }
761
762 drm->dev_private = malidp;
763 dev_set_drvdata(dev, drm);
764
765 /* Enable power management */
766 pm_runtime_enable(dev);
767
768 /* Resume device to enable the clocks */
769 if (pm_runtime_enabled(dev))
770 pm_runtime_get_sync(dev);
771 else
772 malidp_runtime_pm_resume(dev);
773
774 dev_id = of_match_device(malidp_drm_of_match, dev);
775 if (!dev_id) {
776 ret = -EINVAL;
777 goto query_hw_fail;
778 }
779
780 if (!malidp_has_sufficient_address_space(res, dev_id)) {
781 DRM_ERROR("Insufficient address space in device-tree.\n");
782 ret = -EINVAL;
783 goto query_hw_fail;
784 }
785
786 if (!malidp_is_compatible_hw_id(hwdev, dev_id)) {
787 ret = -EINVAL;
788 goto query_hw_fail;
789 }
790
791 ret = hwdev->hw->query_hw(hwdev);
792 if (ret) {
793 DRM_ERROR("Invalid HW configuration\n");
794 goto query_hw_fail;
795 }
796
797 version = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_DE_CORE_ID);
798 DRM_INFO("found ARM Mali-DP%3x version r%dp%d\n", version >> 16,
799 (version >> 12) & 0xf, (version >> 8) & 0xf);
800
801 malidp->core_id = version;
802
803 ret = of_property_read_u32(dev->of_node,
804 "arm,malidp-arqos-value",
805 &hwdev->arqos_value);
806 if (ret)
807 hwdev->arqos_value = 0x0;
808
809 /* set the number of lines used for output of RGB data */
810 ret = of_property_read_u8_array(dev->of_node,
811 "arm,malidp-output-port-lines",
812 output_width, MAX_OUTPUT_CHANNELS);
813 if (ret)
814 goto query_hw_fail;
815
816 for (i = 0; i < MAX_OUTPUT_CHANNELS; i++)
817 out_depth = (out_depth << 8) | (output_width[i] & 0xf);
818 malidp_hw_write(hwdev, out_depth, hwdev->hw->map.out_depth_base);
819 hwdev->output_color_depth = out_depth;
820
821 atomic_set(&malidp->config_valid, MALIDP_CONFIG_VALID_INIT);
822 init_waitqueue_head(&malidp->wq);
823
824 ret = malidp_init(drm);
825 if (ret < 0)
826 goto query_hw_fail;
827
828 /* Set the CRTC's port so that the encoder component can find it */
829 malidp->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
830
831 ret = component_bind_all(dev, drm);
832 if (ret) {
833 DRM_ERROR("Failed to bind all components\n");
834 goto bind_fail;
835 }
836
837 /* We expect to have a maximum of two encoders one for the actual
838 * display and a virtual one for the writeback connector
839 */
840 WARN_ON(drm->mode_config.num_encoder > 2);
841 list_for_each_entry(encoder, &drm->mode_config.encoder_list, head) {
842 encoder->possible_clones =
843 (1 << drm->mode_config.num_encoder) - 1;
844 }
845
846 ret = malidp_irq_init(pdev);
847 if (ret < 0)
848 goto irq_init_fail;
849
850 drm->irq_enabled = true;
851
852 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
853 if (ret < 0) {
854 DRM_ERROR("failed to initialise vblank\n");
855 goto vblank_fail;
856 }
857 pm_runtime_put(dev);
858
859 drm_mode_config_reset(drm);
860
861 drm_kms_helper_poll_init(drm);
862
863 ret = drm_dev_register(drm, 0);
864 if (ret)
865 goto register_fail;
866
867 drm_fbdev_generic_setup(drm, 32);
868
869 return 0;
870
871register_fail:
872 drm_kms_helper_poll_fini(drm);
873 pm_runtime_get_sync(dev);
874vblank_fail:
875 malidp_se_irq_fini(hwdev);
876 malidp_de_irq_fini(hwdev);
877 drm->irq_enabled = false;
878irq_init_fail:
879 drm_atomic_helper_shutdown(drm);
880 component_unbind_all(dev, drm);
881bind_fail:
882 of_node_put(malidp->crtc.port);
883 malidp->crtc.port = NULL;
884 malidp_fini(drm);
885query_hw_fail:
886 pm_runtime_put(dev);
887 if (pm_runtime_enabled(dev))
888 pm_runtime_disable(dev);
889 else
890 malidp_runtime_pm_suspend(dev);
891 drm->dev_private = NULL;
892 dev_set_drvdata(dev, NULL);
893 drm_dev_put(drm);
894alloc_fail:
895 of_reserved_mem_device_release(dev);
896
897 return ret;
898}
899
900static void malidp_unbind(struct device *dev)
901{
902 struct drm_device *drm = dev_get_drvdata(dev);
903 struct malidp_drm *malidp = drm->dev_private;
904 struct malidp_hw_device *hwdev = malidp->dev;
905
906 drm_dev_unregister(drm);
907 drm_kms_helper_poll_fini(drm);
908 pm_runtime_get_sync(dev);
909 drm_atomic_helper_shutdown(drm);
910 malidp_se_irq_fini(hwdev);
911 malidp_de_irq_fini(hwdev);
912 drm->irq_enabled = false;
913 component_unbind_all(dev, drm);
914 of_node_put(malidp->crtc.port);
915 malidp->crtc.port = NULL;
916 malidp_fini(drm);
917 pm_runtime_put(dev);
918 if (pm_runtime_enabled(dev))
919 pm_runtime_disable(dev);
920 else
921 malidp_runtime_pm_suspend(dev);
922 drm->dev_private = NULL;
923 dev_set_drvdata(dev, NULL);
924 drm_dev_put(drm);
925 of_reserved_mem_device_release(dev);
926}
927
928static const struct component_master_ops malidp_master_ops = {
929 .bind = malidp_bind,
930 .unbind = malidp_unbind,
931};
932
933static int malidp_compare_dev(struct device *dev, void *data)
934{
935 struct device_node *np = data;
936
937 return dev->of_node == np;
938}
939
940static int malidp_platform_probe(struct platform_device *pdev)
941{
942 struct device_node *port;
943 struct component_match *match = NULL;
944
945 if (!pdev->dev.of_node)
946 return -ENODEV;
947
948 /* there is only one output port inside each device, find it */
949 port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
950 if (!port)
951 return -ENODEV;
952
953 drm_of_component_match_add(&pdev->dev, &match, malidp_compare_dev,
954 port);
955 of_node_put(port);
956 return component_master_add_with_match(&pdev->dev, &malidp_master_ops,
957 match);
958}
959
960static int malidp_platform_remove(struct platform_device *pdev)
961{
962 component_master_del(&pdev->dev, &malidp_master_ops);
963 return 0;
964}
965
966static int __maybe_unused malidp_pm_suspend(struct device *dev)
967{
968 struct drm_device *drm = dev_get_drvdata(dev);
969
970 return drm_mode_config_helper_suspend(drm);
971}
972
973static int __maybe_unused malidp_pm_resume(struct device *dev)
974{
975 struct drm_device *drm = dev_get_drvdata(dev);
976
977 drm_mode_config_helper_resume(drm);
978
979 return 0;
980}
981
982static int __maybe_unused malidp_pm_suspend_late(struct device *dev)
983{
984 if (!pm_runtime_status_suspended(dev)) {
985 malidp_runtime_pm_suspend(dev);
986 pm_runtime_set_suspended(dev);
987 }
988 return 0;
989}
990
991static int __maybe_unused malidp_pm_resume_early(struct device *dev)
992{
993 malidp_runtime_pm_resume(dev);
994 pm_runtime_set_active(dev);
995 return 0;
996}
997
998static const struct dev_pm_ops malidp_pm_ops = {
999 SET_SYSTEM_SLEEP_PM_OPS(malidp_pm_suspend, malidp_pm_resume) \
1000 SET_LATE_SYSTEM_SLEEP_PM_OPS(malidp_pm_suspend_late, malidp_pm_resume_early) \
1001 SET_RUNTIME_PM_OPS(malidp_runtime_pm_suspend, malidp_runtime_pm_resume, NULL)
1002};
1003
1004static struct platform_driver malidp_platform_driver = {
1005 .probe = malidp_platform_probe,
1006 .remove = malidp_platform_remove,
1007 .driver = {
1008 .name = "mali-dp",
1009 .pm = &malidp_pm_ops,
1010 .of_match_table = malidp_drm_of_match,
1011 .dev_groups = mali_dp_groups,
1012 },
1013};
1014
1015module_platform_driver(malidp_platform_driver);
1016
1017MODULE_AUTHOR("Liviu Dudau <Liviu.Dudau@arm.com>");
1018MODULE_DESCRIPTION("ARM Mali DP DRM driver");
1019MODULE_LICENSE("GPL v2");