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1/*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/dma-mapping.h>
43#include <linux/device.h>
44#include <linux/dmi.h>
45#include <linux/gfp.h>
46#include <scsi/scsi_host.h>
47#include <scsi/scsi_cmnd.h>
48#include <linux/libata.h>
49#include "ahci.h"
50
51#define DRV_NAME "ahci"
52#define DRV_VERSION "3.0"
53
54enum {
55 AHCI_PCI_BAR = 5,
56};
57
58enum board_ids {
59 /* board IDs by feature in alphabetical order */
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
63 board_ahci_yes_fbs,
64
65 /* board IDs for specific chipsets in alphabetical order */
66 board_ahci_mcp65,
67 board_ahci_mcp77,
68 board_ahci_mcp89,
69 board_ahci_mv,
70 board_ahci_sb600,
71 board_ahci_sb700, /* for SB700 and SB800 */
72 board_ahci_vt8251,
73
74 /* aliases */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
78 board_ahci_mcp79 = board_ahci_mcp77,
79};
80
81static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
82static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
84static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86#ifdef CONFIG_PM
87static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
88static int ahci_pci_device_resume(struct pci_dev *pdev);
89#endif
90
91static struct scsi_host_template ahci_sht = {
92 AHCI_SHT("ahci"),
93};
94
95static struct ata_port_operations ahci_vt8251_ops = {
96 .inherits = &ahci_ops,
97 .hardreset = ahci_vt8251_hardreset,
98};
99
100static struct ata_port_operations ahci_p5wdh_ops = {
101 .inherits = &ahci_ops,
102 .hardreset = ahci_p5wdh_hardreset,
103};
104
105#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
106
107static const struct ata_port_info ahci_port_info[] = {
108 /* by features */
109 [board_ahci] =
110 {
111 .flags = AHCI_FLAG_COMMON,
112 .pio_mask = ATA_PIO4,
113 .udma_mask = ATA_UDMA6,
114 .port_ops = &ahci_ops,
115 },
116 [board_ahci_ign_iferr] =
117 {
118 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
119 .flags = AHCI_FLAG_COMMON,
120 .pio_mask = ATA_PIO4,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &ahci_ops,
123 },
124 [board_ahci_nosntf] =
125 {
126 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
131 },
132 [board_ahci_yes_fbs] =
133 {
134 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
139 },
140 /* by chipsets */
141 [board_ahci_mcp65] =
142 {
143 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
144 AHCI_HFLAG_YES_NCQ),
145 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
149 },
150 [board_ahci_mcp77] =
151 {
152 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_mcp89] =
159 {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
165 },
166 [board_ahci_mv] =
167 {
168 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
169 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
170 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
171 .pio_mask = ATA_PIO4,
172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_ops,
174 },
175 [board_ahci_sb600] =
176 {
177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
178 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
179 AHCI_HFLAG_32BIT_ONLY),
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_pmp_retry_srst_ops,
184 },
185 [board_ahci_sb700] = /* for SB700 and SB800 */
186 {
187 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_pmp_retry_srst_ops,
192 },
193 [board_ahci_vt8251] =
194 {
195 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_vt8251_ops,
200 },
201};
202
203static const struct pci_device_id ahci_pci_tbl[] = {
204 /* Intel */
205 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
206 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
207 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
208 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
209 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
210 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
211 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
213 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
214 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
215 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
216 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
217 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
218 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
219 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
220 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
225 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
230 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
233 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
234 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
235 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
236 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
237 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
238 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
239 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
240 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
241 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
242 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
243 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
244 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
246 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
247 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
251 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
252 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
253 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
254 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
255 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
256 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
257 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
258 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
262 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
263
264 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
265 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
266 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
267
268 /* ATI */
269 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
270 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
271 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
272 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
273 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
274 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
275 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
276
277 /* AMD */
278 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
279 /* AMD is using RAID class only for ahci controllers */
280 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
281 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
282
283 /* VIA */
284 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
285 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
286
287 /* NVIDIA */
288 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
289 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
290 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
291 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
292 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
293 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
294 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
295 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
297 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
309 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
325 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
349 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
361 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
372
373 /* SiS */
374 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
375 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
376 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
377
378 /* Marvell */
379 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
380 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
381 { PCI_DEVICE(0x1b4b, 0x9123),
382 .class = PCI_CLASS_STORAGE_SATA_AHCI,
383 .class_mask = 0xffffff,
384 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
385 { PCI_DEVICE(0x1b4b, 0x9125),
386 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
387 { PCI_DEVICE(0x1b4b, 0x91a3),
388 .driver_data = board_ahci_yes_fbs },
389
390 /* Promise */
391 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
392
393 /* Generic, PCI class code for AHCI */
394 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
395 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
396
397 { } /* terminate list */
398};
399
400
401static struct pci_driver ahci_pci_driver = {
402 .name = DRV_NAME,
403 .id_table = ahci_pci_tbl,
404 .probe = ahci_init_one,
405 .remove = ata_pci_remove_one,
406#ifdef CONFIG_PM
407 .suspend = ahci_pci_device_suspend,
408 .resume = ahci_pci_device_resume,
409#endif
410};
411
412#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
413static int marvell_enable;
414#else
415static int marvell_enable = 1;
416#endif
417module_param(marvell_enable, int, 0644);
418MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
419
420
421static void ahci_pci_save_initial_config(struct pci_dev *pdev,
422 struct ahci_host_priv *hpriv)
423{
424 unsigned int force_port_map = 0;
425 unsigned int mask_port_map = 0;
426
427 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
428 dev_info(&pdev->dev, "JMB361 has only one port\n");
429 force_port_map = 1;
430 }
431
432 /*
433 * Temporary Marvell 6145 hack: PATA port presence
434 * is asserted through the standard AHCI port
435 * presence register, as bit 4 (counting from 0)
436 */
437 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
438 if (pdev->device == 0x6121)
439 mask_port_map = 0x3;
440 else
441 mask_port_map = 0xf;
442 dev_info(&pdev->dev,
443 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
444 }
445
446 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
447 mask_port_map);
448}
449
450static int ahci_pci_reset_controller(struct ata_host *host)
451{
452 struct pci_dev *pdev = to_pci_dev(host->dev);
453
454 ahci_reset_controller(host);
455
456 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
457 struct ahci_host_priv *hpriv = host->private_data;
458 u16 tmp16;
459
460 /* configure PCS */
461 pci_read_config_word(pdev, 0x92, &tmp16);
462 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
463 tmp16 |= hpriv->port_map;
464 pci_write_config_word(pdev, 0x92, tmp16);
465 }
466 }
467
468 return 0;
469}
470
471static void ahci_pci_init_controller(struct ata_host *host)
472{
473 struct ahci_host_priv *hpriv = host->private_data;
474 struct pci_dev *pdev = to_pci_dev(host->dev);
475 void __iomem *port_mmio;
476 u32 tmp;
477 int mv;
478
479 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
480 if (pdev->device == 0x6121)
481 mv = 2;
482 else
483 mv = 4;
484 port_mmio = __ahci_port_base(host, mv);
485
486 writel(0, port_mmio + PORT_IRQ_MASK);
487
488 /* clear port IRQ */
489 tmp = readl(port_mmio + PORT_IRQ_STAT);
490 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
491 if (tmp)
492 writel(tmp, port_mmio + PORT_IRQ_STAT);
493 }
494
495 ahci_init_controller(host);
496}
497
498static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
499 unsigned long deadline)
500{
501 struct ata_port *ap = link->ap;
502 bool online;
503 int rc;
504
505 DPRINTK("ENTER\n");
506
507 ahci_stop_engine(ap);
508
509 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
510 deadline, &online, NULL);
511
512 ahci_start_engine(ap);
513
514 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
515
516 /* vt8251 doesn't clear BSY on signature FIS reception,
517 * request follow-up softreset.
518 */
519 return online ? -EAGAIN : rc;
520}
521
522static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
523 unsigned long deadline)
524{
525 struct ata_port *ap = link->ap;
526 struct ahci_port_priv *pp = ap->private_data;
527 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
528 struct ata_taskfile tf;
529 bool online;
530 int rc;
531
532 ahci_stop_engine(ap);
533
534 /* clear D2H reception area to properly wait for D2H FIS */
535 ata_tf_init(link->device, &tf);
536 tf.command = 0x80;
537 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
538
539 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
540 deadline, &online, NULL);
541
542 ahci_start_engine(ap);
543
544 /* The pseudo configuration device on SIMG4726 attached to
545 * ASUS P5W-DH Deluxe doesn't send signature FIS after
546 * hardreset if no device is attached to the first downstream
547 * port && the pseudo device locks up on SRST w/ PMP==0. To
548 * work around this, wait for !BSY only briefly. If BSY isn't
549 * cleared, perform CLO and proceed to IDENTIFY (achieved by
550 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
551 *
552 * Wait for two seconds. Devices attached to downstream port
553 * which can't process the following IDENTIFY after this will
554 * have to be reset again. For most cases, this should
555 * suffice while making probing snappish enough.
556 */
557 if (online) {
558 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
559 ahci_check_ready);
560 if (rc)
561 ahci_kick_engine(ap);
562 }
563 return rc;
564}
565
566#ifdef CONFIG_PM
567static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
568{
569 struct ata_host *host = dev_get_drvdata(&pdev->dev);
570 struct ahci_host_priv *hpriv = host->private_data;
571 void __iomem *mmio = hpriv->mmio;
572 u32 ctl;
573
574 if (mesg.event & PM_EVENT_SUSPEND &&
575 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
576 dev_err(&pdev->dev,
577 "BIOS update required for suspend/resume\n");
578 return -EIO;
579 }
580
581 if (mesg.event & PM_EVENT_SLEEP) {
582 /* AHCI spec rev1.1 section 8.3.3:
583 * Software must disable interrupts prior to requesting a
584 * transition of the HBA to D3 state.
585 */
586 ctl = readl(mmio + HOST_CTL);
587 ctl &= ~HOST_IRQ_EN;
588 writel(ctl, mmio + HOST_CTL);
589 readl(mmio + HOST_CTL); /* flush */
590 }
591
592 return ata_pci_device_suspend(pdev, mesg);
593}
594
595static int ahci_pci_device_resume(struct pci_dev *pdev)
596{
597 struct ata_host *host = dev_get_drvdata(&pdev->dev);
598 int rc;
599
600 rc = ata_pci_device_do_resume(pdev);
601 if (rc)
602 return rc;
603
604 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
605 rc = ahci_pci_reset_controller(host);
606 if (rc)
607 return rc;
608
609 ahci_pci_init_controller(host);
610 }
611
612 ata_host_resume(host);
613
614 return 0;
615}
616#endif
617
618static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
619{
620 int rc;
621
622 if (using_dac &&
623 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
624 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
625 if (rc) {
626 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
627 if (rc) {
628 dev_err(&pdev->dev,
629 "64-bit DMA enable failed\n");
630 return rc;
631 }
632 }
633 } else {
634 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
635 if (rc) {
636 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
637 return rc;
638 }
639 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
640 if (rc) {
641 dev_err(&pdev->dev,
642 "32-bit consistent DMA enable failed\n");
643 return rc;
644 }
645 }
646 return 0;
647}
648
649static void ahci_pci_print_info(struct ata_host *host)
650{
651 struct pci_dev *pdev = to_pci_dev(host->dev);
652 u16 cc;
653 const char *scc_s;
654
655 pci_read_config_word(pdev, 0x0a, &cc);
656 if (cc == PCI_CLASS_STORAGE_IDE)
657 scc_s = "IDE";
658 else if (cc == PCI_CLASS_STORAGE_SATA)
659 scc_s = "SATA";
660 else if (cc == PCI_CLASS_STORAGE_RAID)
661 scc_s = "RAID";
662 else
663 scc_s = "unknown";
664
665 ahci_print_info(host, scc_s);
666}
667
668/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
669 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
670 * support PMP and the 4726 either directly exports the device
671 * attached to the first downstream port or acts as a hardware storage
672 * controller and emulate a single ATA device (can be RAID 0/1 or some
673 * other configuration).
674 *
675 * When there's no device attached to the first downstream port of the
676 * 4726, "Config Disk" appears, which is a pseudo ATA device to
677 * configure the 4726. However, ATA emulation of the device is very
678 * lame. It doesn't send signature D2H Reg FIS after the initial
679 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
680 *
681 * The following function works around the problem by always using
682 * hardreset on the port and not depending on receiving signature FIS
683 * afterward. If signature FIS isn't received soon, ATA class is
684 * assumed without follow-up softreset.
685 */
686static void ahci_p5wdh_workaround(struct ata_host *host)
687{
688 static struct dmi_system_id sysids[] = {
689 {
690 .ident = "P5W DH Deluxe",
691 .matches = {
692 DMI_MATCH(DMI_SYS_VENDOR,
693 "ASUSTEK COMPUTER INC"),
694 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
695 },
696 },
697 { }
698 };
699 struct pci_dev *pdev = to_pci_dev(host->dev);
700
701 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
702 dmi_check_system(sysids)) {
703 struct ata_port *ap = host->ports[1];
704
705 dev_info(&pdev->dev,
706 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
707
708 ap->ops = &ahci_p5wdh_ops;
709 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
710 }
711}
712
713/* only some SB600 ahci controllers can do 64bit DMA */
714static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
715{
716 static const struct dmi_system_id sysids[] = {
717 /*
718 * The oldest version known to be broken is 0901 and
719 * working is 1501 which was released on 2007-10-26.
720 * Enable 64bit DMA on 1501 and anything newer.
721 *
722 * Please read bko#9412 for more info.
723 */
724 {
725 .ident = "ASUS M2A-VM",
726 .matches = {
727 DMI_MATCH(DMI_BOARD_VENDOR,
728 "ASUSTeK Computer INC."),
729 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
730 },
731 .driver_data = "20071026", /* yyyymmdd */
732 },
733 /*
734 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
735 * support 64bit DMA.
736 *
737 * BIOS versions earlier than 1.5 had the Manufacturer DMI
738 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
739 * This spelling mistake was fixed in BIOS version 1.5, so
740 * 1.5 and later have the Manufacturer as
741 * "MICRO-STAR INTERNATIONAL CO.,LTD".
742 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
743 *
744 * BIOS versions earlier than 1.9 had a Board Product Name
745 * DMI field of "MS-7376". This was changed to be
746 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
747 * match on DMI_BOARD_NAME of "MS-7376".
748 */
749 {
750 .ident = "MSI K9A2 Platinum",
751 .matches = {
752 DMI_MATCH(DMI_BOARD_VENDOR,
753 "MICRO-STAR INTER"),
754 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
755 },
756 },
757 /*
758 * All BIOS versions for the Asus M3A support 64bit DMA.
759 * (all release versions from 0301 to 1206 were tested)
760 */
761 {
762 .ident = "ASUS M3A",
763 .matches = {
764 DMI_MATCH(DMI_BOARD_VENDOR,
765 "ASUSTeK Computer INC."),
766 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
767 },
768 },
769 { }
770 };
771 const struct dmi_system_id *match;
772 int year, month, date;
773 char buf[9];
774
775 match = dmi_first_match(sysids);
776 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
777 !match)
778 return false;
779
780 if (!match->driver_data)
781 goto enable_64bit;
782
783 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
784 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
785
786 if (strcmp(buf, match->driver_data) >= 0)
787 goto enable_64bit;
788 else {
789 dev_warn(&pdev->dev,
790 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
791 match->ident);
792 return false;
793 }
794
795enable_64bit:
796 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
797 return true;
798}
799
800static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
801{
802 static const struct dmi_system_id broken_systems[] = {
803 {
804 .ident = "HP Compaq nx6310",
805 .matches = {
806 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
807 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
808 },
809 /* PCI slot number of the controller */
810 .driver_data = (void *)0x1FUL,
811 },
812 {
813 .ident = "HP Compaq 6720s",
814 .matches = {
815 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
816 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
817 },
818 /* PCI slot number of the controller */
819 .driver_data = (void *)0x1FUL,
820 },
821
822 { } /* terminate list */
823 };
824 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
825
826 if (dmi) {
827 unsigned long slot = (unsigned long)dmi->driver_data;
828 /* apply the quirk only to on-board controllers */
829 return slot == PCI_SLOT(pdev->devfn);
830 }
831
832 return false;
833}
834
835static bool ahci_broken_suspend(struct pci_dev *pdev)
836{
837 static const struct dmi_system_id sysids[] = {
838 /*
839 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
840 * to the harddisk doesn't become online after
841 * resuming from STR. Warn and fail suspend.
842 *
843 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
844 *
845 * Use dates instead of versions to match as HP is
846 * apparently recycling both product and version
847 * strings.
848 *
849 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
850 */
851 {
852 .ident = "dv4",
853 .matches = {
854 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
855 DMI_MATCH(DMI_PRODUCT_NAME,
856 "HP Pavilion dv4 Notebook PC"),
857 },
858 .driver_data = "20090105", /* F.30 */
859 },
860 {
861 .ident = "dv5",
862 .matches = {
863 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
864 DMI_MATCH(DMI_PRODUCT_NAME,
865 "HP Pavilion dv5 Notebook PC"),
866 },
867 .driver_data = "20090506", /* F.16 */
868 },
869 {
870 .ident = "dv6",
871 .matches = {
872 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
873 DMI_MATCH(DMI_PRODUCT_NAME,
874 "HP Pavilion dv6 Notebook PC"),
875 },
876 .driver_data = "20090423", /* F.21 */
877 },
878 {
879 .ident = "HDX18",
880 .matches = {
881 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
882 DMI_MATCH(DMI_PRODUCT_NAME,
883 "HP HDX18 Notebook PC"),
884 },
885 .driver_data = "20090430", /* F.23 */
886 },
887 /*
888 * Acer eMachines G725 has the same problem. BIOS
889 * V1.03 is known to be broken. V3.04 is known to
890 * work. Between, there are V1.06, V2.06 and V3.03
891 * that we don't have much idea about. For now,
892 * blacklist anything older than V3.04.
893 *
894 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
895 */
896 {
897 .ident = "G725",
898 .matches = {
899 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
900 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
901 },
902 .driver_data = "20091216", /* V3.04 */
903 },
904 { } /* terminate list */
905 };
906 const struct dmi_system_id *dmi = dmi_first_match(sysids);
907 int year, month, date;
908 char buf[9];
909
910 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
911 return false;
912
913 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
914 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
915
916 return strcmp(buf, dmi->driver_data) < 0;
917}
918
919static bool ahci_broken_online(struct pci_dev *pdev)
920{
921#define ENCODE_BUSDEVFN(bus, slot, func) \
922 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
923 static const struct dmi_system_id sysids[] = {
924 /*
925 * There are several gigabyte boards which use
926 * SIMG5723s configured as hardware RAID. Certain
927 * 5723 firmware revisions shipped there keep the link
928 * online but fail to answer properly to SRST or
929 * IDENTIFY when no device is attached downstream
930 * causing libata to retry quite a few times leading
931 * to excessive detection delay.
932 *
933 * As these firmwares respond to the second reset try
934 * with invalid device signature, considering unknown
935 * sig as offline works around the problem acceptably.
936 */
937 {
938 .ident = "EP45-DQ6",
939 .matches = {
940 DMI_MATCH(DMI_BOARD_VENDOR,
941 "Gigabyte Technology Co., Ltd."),
942 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
943 },
944 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
945 },
946 {
947 .ident = "EP45-DS5",
948 .matches = {
949 DMI_MATCH(DMI_BOARD_VENDOR,
950 "Gigabyte Technology Co., Ltd."),
951 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
952 },
953 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
954 },
955 { } /* terminate list */
956 };
957#undef ENCODE_BUSDEVFN
958 const struct dmi_system_id *dmi = dmi_first_match(sysids);
959 unsigned int val;
960
961 if (!dmi)
962 return false;
963
964 val = (unsigned long)dmi->driver_data;
965
966 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
967}
968
969#ifdef CONFIG_ATA_ACPI
970static void ahci_gtf_filter_workaround(struct ata_host *host)
971{
972 static const struct dmi_system_id sysids[] = {
973 /*
974 * Aspire 3810T issues a bunch of SATA enable commands
975 * via _GTF including an invalid one and one which is
976 * rejected by the device. Among the successful ones
977 * is FPDMA non-zero offset enable which when enabled
978 * only on the drive side leads to NCQ command
979 * failures. Filter it out.
980 */
981 {
982 .ident = "Aspire 3810T",
983 .matches = {
984 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
985 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
986 },
987 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
988 },
989 { }
990 };
991 const struct dmi_system_id *dmi = dmi_first_match(sysids);
992 unsigned int filter;
993 int i;
994
995 if (!dmi)
996 return;
997
998 filter = (unsigned long)dmi->driver_data;
999 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1000 filter, dmi->ident);
1001
1002 for (i = 0; i < host->n_ports; i++) {
1003 struct ata_port *ap = host->ports[i];
1004 struct ata_link *link;
1005 struct ata_device *dev;
1006
1007 ata_for_each_link(link, ap, EDGE)
1008 ata_for_each_dev(dev, link, ALL)
1009 dev->gtf_filter |= filter;
1010 }
1011}
1012#else
1013static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1014{}
1015#endif
1016
1017static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1018{
1019 unsigned int board_id = ent->driver_data;
1020 struct ata_port_info pi = ahci_port_info[board_id];
1021 const struct ata_port_info *ppi[] = { &pi, NULL };
1022 struct device *dev = &pdev->dev;
1023 struct ahci_host_priv *hpriv;
1024 struct ata_host *host;
1025 int n_ports, i, rc;
1026
1027 VPRINTK("ENTER\n");
1028
1029 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1030
1031 ata_print_version_once(&pdev->dev, DRV_VERSION);
1032
1033 /* The AHCI driver can only drive the SATA ports, the PATA driver
1034 can drive them all so if both drivers are selected make sure
1035 AHCI stays out of the way */
1036 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1037 return -ENODEV;
1038
1039 /*
1040 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1041 * ahci, use ata_generic instead.
1042 */
1043 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1044 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1045 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1046 pdev->subsystem_device == 0xcb89)
1047 return -ENODEV;
1048
1049 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1050 * At the moment, we can only use the AHCI mode. Let the users know
1051 * that for SAS drives they're out of luck.
1052 */
1053 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1054 dev_info(&pdev->dev,
1055 "PDC42819 can only drive SATA devices with this driver\n");
1056
1057 /* acquire resources */
1058 rc = pcim_enable_device(pdev);
1059 if (rc)
1060 return rc;
1061
1062 /* AHCI controllers often implement SFF compatible interface.
1063 * Grab all PCI BARs just in case.
1064 */
1065 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1066 if (rc == -EBUSY)
1067 pcim_pin_device(pdev);
1068 if (rc)
1069 return rc;
1070
1071 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1072 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1073 u8 map;
1074
1075 /* ICH6s share the same PCI ID for both piix and ahci
1076 * modes. Enabling ahci mode while MAP indicates
1077 * combined mode is a bad idea. Yield to ata_piix.
1078 */
1079 pci_read_config_byte(pdev, ICH_MAP, &map);
1080 if (map & 0x3) {
1081 dev_info(&pdev->dev,
1082 "controller is in combined mode, can't enable AHCI mode\n");
1083 return -ENODEV;
1084 }
1085 }
1086
1087 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1088 if (!hpriv)
1089 return -ENOMEM;
1090 hpriv->flags |= (unsigned long)pi.private_data;
1091
1092 /* MCP65 revision A1 and A2 can't do MSI */
1093 if (board_id == board_ahci_mcp65 &&
1094 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1095 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1096
1097 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1098 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1099 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1100
1101 /* only some SB600s can do 64bit DMA */
1102 if (ahci_sb600_enable_64bit(pdev))
1103 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1104
1105 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1106 pci_intx(pdev, 1);
1107
1108 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1109
1110 /* save initial config */
1111 ahci_pci_save_initial_config(pdev, hpriv);
1112
1113 /* prepare host */
1114 if (hpriv->cap & HOST_CAP_NCQ) {
1115 pi.flags |= ATA_FLAG_NCQ;
1116 /*
1117 * Auto-activate optimization is supposed to be
1118 * supported on all AHCI controllers indicating NCQ
1119 * capability, but it seems to be broken on some
1120 * chipsets including NVIDIAs.
1121 */
1122 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1123 pi.flags |= ATA_FLAG_FPDMA_AA;
1124 }
1125
1126 if (hpriv->cap & HOST_CAP_PMP)
1127 pi.flags |= ATA_FLAG_PMP;
1128
1129 ahci_set_em_messages(hpriv, &pi);
1130
1131 if (ahci_broken_system_poweroff(pdev)) {
1132 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1133 dev_info(&pdev->dev,
1134 "quirky BIOS, skipping spindown on poweroff\n");
1135 }
1136
1137 if (ahci_broken_suspend(pdev)) {
1138 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1139 dev_warn(&pdev->dev,
1140 "BIOS update required for suspend/resume\n");
1141 }
1142
1143 if (ahci_broken_online(pdev)) {
1144 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1145 dev_info(&pdev->dev,
1146 "online status unreliable, applying workaround\n");
1147 }
1148
1149 /* CAP.NP sometimes indicate the index of the last enabled
1150 * port, at other times, that of the last possible port, so
1151 * determining the maximum port number requires looking at
1152 * both CAP.NP and port_map.
1153 */
1154 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1155
1156 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1157 if (!host)
1158 return -ENOMEM;
1159 host->private_data = hpriv;
1160
1161 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1162 host->flags |= ATA_HOST_PARALLEL_SCAN;
1163 else
1164 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1165
1166 if (pi.flags & ATA_FLAG_EM)
1167 ahci_reset_em(host);
1168
1169 for (i = 0; i < host->n_ports; i++) {
1170 struct ata_port *ap = host->ports[i];
1171
1172 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1173 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1174 0x100 + ap->port_no * 0x80, "port");
1175
1176 /* set enclosure management message type */
1177 if (ap->flags & ATA_FLAG_EM)
1178 ap->em_message_type = hpriv->em_msg_type;
1179
1180
1181 /* disabled/not-implemented port */
1182 if (!(hpriv->port_map & (1 << i)))
1183 ap->ops = &ata_dummy_port_ops;
1184 }
1185
1186 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1187 ahci_p5wdh_workaround(host);
1188
1189 /* apply gtf filter quirk */
1190 ahci_gtf_filter_workaround(host);
1191
1192 /* initialize adapter */
1193 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1194 if (rc)
1195 return rc;
1196
1197 rc = ahci_pci_reset_controller(host);
1198 if (rc)
1199 return rc;
1200
1201 ahci_pci_init_controller(host);
1202 ahci_pci_print_info(host);
1203
1204 pci_set_master(pdev);
1205 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1206 &ahci_sht);
1207}
1208
1209static int __init ahci_init(void)
1210{
1211 return pci_register_driver(&ahci_pci_driver);
1212}
1213
1214static void __exit ahci_exit(void)
1215{
1216 pci_unregister_driver(&ahci_pci_driver);
1217}
1218
1219
1220MODULE_AUTHOR("Jeff Garzik");
1221MODULE_DESCRIPTION("AHCI SATA low-level driver");
1222MODULE_LICENSE("GPL");
1223MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1224MODULE_VERSION(DRV_VERSION);
1225
1226module_init(ahci_init);
1227module_exit(ahci_exit);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * ahci.c - AHCI SATA support
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
25#include <linux/dma-mapping.h>
26#include <linux/device.h>
27#include <linux/dmi.h>
28#include <linux/gfp.h>
29#include <linux/msi.h>
30#include <scsi/scsi_host.h>
31#include <scsi/scsi_cmnd.h>
32#include <linux/libata.h>
33#include <linux/ahci-remap.h>
34#include <linux/io-64-nonatomic-lo-hi.h>
35#include "ahci.h"
36
37#define DRV_NAME "ahci"
38#define DRV_VERSION "3.0"
39
40enum {
41 AHCI_PCI_BAR_STA2X11 = 0,
42 AHCI_PCI_BAR_CAVIUM = 0,
43 AHCI_PCI_BAR_LOONGSON = 0,
44 AHCI_PCI_BAR_ENMOTUS = 2,
45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
46 AHCI_PCI_BAR_STANDARD = 5,
47};
48
49enum board_ids {
50 /* board IDs by feature in alphabetical order */
51 board_ahci,
52 board_ahci_ign_iferr,
53 board_ahci_mobile,
54 board_ahci_nomsi,
55 board_ahci_noncq,
56 board_ahci_nosntf,
57 board_ahci_yes_fbs,
58
59 /* board IDs for specific chipsets in alphabetical order */
60 board_ahci_al,
61 board_ahci_avn,
62 board_ahci_mcp65,
63 board_ahci_mcp77,
64 board_ahci_mcp89,
65 board_ahci_mv,
66 board_ahci_sb600,
67 board_ahci_sb700, /* for SB700 and SB800 */
68 board_ahci_vt8251,
69
70 /*
71 * board IDs for Intel chipsets that support more than 6 ports
72 * *and* end up needing the PCS quirk.
73 */
74 board_ahci_pcs7,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
81};
82
83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84static void ahci_remove_one(struct pci_dev *dev);
85static void ahci_shutdown_one(struct pci_dev *dev);
86static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
91static bool is_mcp89_apple(struct pci_dev *pdev);
92static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
94#ifdef CONFIG_PM
95static int ahci_pci_device_runtime_suspend(struct device *dev);
96static int ahci_pci_device_runtime_resume(struct device *dev);
97#ifdef CONFIG_PM_SLEEP
98static int ahci_pci_device_suspend(struct device *dev);
99static int ahci_pci_device_resume(struct device *dev);
100#endif
101#endif /* CONFIG_PM */
102
103static struct scsi_host_template ahci_sht = {
104 AHCI_SHT("ahci"),
105};
106
107static struct ata_port_operations ahci_vt8251_ops = {
108 .inherits = &ahci_ops,
109 .hardreset = ahci_vt8251_hardreset,
110};
111
112static struct ata_port_operations ahci_p5wdh_ops = {
113 .inherits = &ahci_ops,
114 .hardreset = ahci_p5wdh_hardreset,
115};
116
117static struct ata_port_operations ahci_avn_ops = {
118 .inherits = &ahci_ops,
119 .hardreset = ahci_avn_hardreset,
120};
121
122static const struct ata_port_info ahci_port_info[] = {
123 /* by features */
124 [board_ahci] = {
125 .flags = AHCI_FLAG_COMMON,
126 .pio_mask = ATA_PIO4,
127 .udma_mask = ATA_UDMA6,
128 .port_ops = &ahci_ops,
129 },
130 [board_ahci_ign_iferr] = {
131 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
132 .flags = AHCI_FLAG_COMMON,
133 .pio_mask = ATA_PIO4,
134 .udma_mask = ATA_UDMA6,
135 .port_ops = &ahci_ops,
136 },
137 [board_ahci_mobile] = {
138 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
144 [board_ahci_nomsi] = {
145 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
150 },
151 [board_ahci_noncq] = {
152 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_nosntf] = {
159 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
160 .flags = AHCI_FLAG_COMMON,
161 .pio_mask = ATA_PIO4,
162 .udma_mask = ATA_UDMA6,
163 .port_ops = &ahci_ops,
164 },
165 [board_ahci_yes_fbs] = {
166 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
167 .flags = AHCI_FLAG_COMMON,
168 .pio_mask = ATA_PIO4,
169 .udma_mask = ATA_UDMA6,
170 .port_ops = &ahci_ops,
171 },
172 /* by chipsets */
173 [board_ahci_al] = {
174 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
175 .flags = AHCI_FLAG_COMMON,
176 .pio_mask = ATA_PIO4,
177 .udma_mask = ATA_UDMA6,
178 .port_ops = &ahci_ops,
179 },
180 [board_ahci_avn] = {
181 .flags = AHCI_FLAG_COMMON,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_avn_ops,
185 },
186 [board_ahci_mcp65] = {
187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
188 AHCI_HFLAG_YES_NCQ),
189 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_ops,
193 },
194 [board_ahci_mcp77] = {
195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_ops,
200 },
201 [board_ahci_mcp89] = {
202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
203 .flags = AHCI_FLAG_COMMON,
204 .pio_mask = ATA_PIO4,
205 .udma_mask = ATA_UDMA6,
206 .port_ops = &ahci_ops,
207 },
208 [board_ahci_mv] = {
209 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
210 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
211 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_ops,
215 },
216 [board_ahci_sb600] = {
217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
218 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
219 AHCI_HFLAG_32BIT_ONLY),
220 .flags = AHCI_FLAG_COMMON,
221 .pio_mask = ATA_PIO4,
222 .udma_mask = ATA_UDMA6,
223 .port_ops = &ahci_pmp_retry_srst_ops,
224 },
225 [board_ahci_sb700] = { /* for SB700 and SB800 */
226 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
227 .flags = AHCI_FLAG_COMMON,
228 .pio_mask = ATA_PIO4,
229 .udma_mask = ATA_UDMA6,
230 .port_ops = &ahci_pmp_retry_srst_ops,
231 },
232 [board_ahci_vt8251] = {
233 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
234 .flags = AHCI_FLAG_COMMON,
235 .pio_mask = ATA_PIO4,
236 .udma_mask = ATA_UDMA6,
237 .port_ops = &ahci_vt8251_ops,
238 },
239 [board_ahci_pcs7] = {
240 .flags = AHCI_FLAG_COMMON,
241 .pio_mask = ATA_PIO4,
242 .udma_mask = ATA_UDMA6,
243 .port_ops = &ahci_ops,
244 },
245};
246
247static const struct pci_device_id ahci_pci_tbl[] = {
248 /* Intel */
249 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
250 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
251 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
252 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
253 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
254 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
255 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
256 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
257 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
258 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
259 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
260 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
261 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
262 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
263 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
264 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
265 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
266 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
267 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
268 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
269 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
270 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
271 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
272 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
273 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
274 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
275 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
276 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
277 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
278 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
279 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
280 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
281 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
282 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
283 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
284 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
285 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
286 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
287 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
288 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
289 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
290 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
296 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
298 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
304 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
311 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
312 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
313 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
314 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
315 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
316 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
317 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
318 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
319 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
320 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
321 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
322 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
323 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
324 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
325 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
326 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
327 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
328 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
329 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
330 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
331 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
332 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
333 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
334 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
335 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
336 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
337 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
338 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
339 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
340 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
341 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
342 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
343 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
344 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
345 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
346 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
347 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
348 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
349 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
350 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
351 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
352 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
353 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
354 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
355 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
356 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
357 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
358 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
359 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
360 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
361 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
362 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
363 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
364 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
365 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
366 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
367 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
368 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
369 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
370 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
371 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
372 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
373 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
374 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
375 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
376 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
377 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
378 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
379 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
380 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
381 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
382 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
383 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
384 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
385 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
386 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
387 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
388 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
389 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
390 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
391 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
392 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
393 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
394 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
395 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
396 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
397 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
398 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
399 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
400 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
401 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
402 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
403 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
404 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
405 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
406 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
407 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
408 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
409 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
410 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
411 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
412 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
413 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
414 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
415 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
416 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
417 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile }, /* Comet Lake PCH-U AHCI */
418 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake PCH RAID */
419
420 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
421 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
422 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
423 /* JMicron 362B and 362C have an AHCI function with IDE class code */
424 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
425 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
426 /* May need to update quirk_jmicron_async_suspend() for additions */
427
428 /* ATI */
429 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
430 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
431 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
432 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
433 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
434 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
435 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
436
437 /* Amazon's Annapurna Labs support */
438 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
439 .class = PCI_CLASS_STORAGE_SATA_AHCI,
440 .class_mask = 0xffffff,
441 board_ahci_al },
442 /* AMD */
443 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
444 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
445 /* AMD is using RAID class only for ahci controllers */
446 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
447 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
448
449 /* Dell S140/S150 */
450 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
451 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
452
453 /* VIA */
454 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
455 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
456
457 /* NVIDIA */
458 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
459 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
460 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
461 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
462 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
463 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
464 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
465 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
466 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
467 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
468 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
469 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
470 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
471 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
472 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
473 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
474 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
475 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
476 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
477 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
478 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
479 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
480 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
481 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
482 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
483 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
484 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
485 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
486 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
487 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
488 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
489 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
490 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
491 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
492 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
493 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
494 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
495 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
496 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
497 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
498 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
499 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
500 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
501 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
502 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
503 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
504 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
505 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
506 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
507 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
508 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
509 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
510 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
511 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
512 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
513 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
514 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
515 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
516 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
517 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
518 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
519 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
520 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
521 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
522 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
523 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
524 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
525 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
526 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
527 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
528 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
529 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
530 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
531 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
532 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
533 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
534 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
535 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
536 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
537 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
538 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
539 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
540 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
541 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
542
543 /* SiS */
544 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
545 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
546 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
547
548 /* ST Microelectronics */
549 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
550
551 /* Marvell */
552 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
553 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
554 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
555 .class = PCI_CLASS_STORAGE_SATA_AHCI,
556 .class_mask = 0xffffff,
557 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
558 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
559 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
560 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
561 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
562 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
563 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
564 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
565 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
566 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
567 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
568 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
569 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
570 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
571 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
572 .driver_data = board_ahci_yes_fbs },
573 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
574 .driver_data = board_ahci_yes_fbs },
575 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
576 .driver_data = board_ahci_yes_fbs },
577 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
578 .driver_data = board_ahci_yes_fbs },
579 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
580 .driver_data = board_ahci_yes_fbs },
581 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
582 .driver_data = board_ahci_yes_fbs },
583
584 /* Promise */
585 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
586 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
587
588 /* Asmedia */
589 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
590 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
591 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
592 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
593 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
594 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
595
596 /*
597 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
598 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
599 */
600 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
601 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
602
603 /* Enmotus */
604 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
605
606 /* Loongson */
607 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
608
609 /* Generic, PCI class code for AHCI */
610 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
611 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
612
613 { } /* terminate list */
614};
615
616static const struct dev_pm_ops ahci_pci_pm_ops = {
617 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
618 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
619 ahci_pci_device_runtime_resume, NULL)
620};
621
622static struct pci_driver ahci_pci_driver = {
623 .name = DRV_NAME,
624 .id_table = ahci_pci_tbl,
625 .probe = ahci_init_one,
626 .remove = ahci_remove_one,
627 .shutdown = ahci_shutdown_one,
628 .driver = {
629 .pm = &ahci_pci_pm_ops,
630 },
631};
632
633#if IS_ENABLED(CONFIG_PATA_MARVELL)
634static int marvell_enable;
635#else
636static int marvell_enable = 1;
637#endif
638module_param(marvell_enable, int, 0644);
639MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
640
641static int mobile_lpm_policy = -1;
642module_param(mobile_lpm_policy, int, 0644);
643MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
644
645static void ahci_pci_save_initial_config(struct pci_dev *pdev,
646 struct ahci_host_priv *hpriv)
647{
648 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
649 dev_info(&pdev->dev, "JMB361 has only one port\n");
650 hpriv->force_port_map = 1;
651 }
652
653 /*
654 * Temporary Marvell 6145 hack: PATA port presence
655 * is asserted through the standard AHCI port
656 * presence register, as bit 4 (counting from 0)
657 */
658 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
659 if (pdev->device == 0x6121)
660 hpriv->mask_port_map = 0x3;
661 else
662 hpriv->mask_port_map = 0xf;
663 dev_info(&pdev->dev,
664 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
665 }
666
667 ahci_save_initial_config(&pdev->dev, hpriv);
668}
669
670static void ahci_pci_init_controller(struct ata_host *host)
671{
672 struct ahci_host_priv *hpriv = host->private_data;
673 struct pci_dev *pdev = to_pci_dev(host->dev);
674 void __iomem *port_mmio;
675 u32 tmp;
676 int mv;
677
678 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
679 if (pdev->device == 0x6121)
680 mv = 2;
681 else
682 mv = 4;
683 port_mmio = __ahci_port_base(host, mv);
684
685 writel(0, port_mmio + PORT_IRQ_MASK);
686
687 /* clear port IRQ */
688 tmp = readl(port_mmio + PORT_IRQ_STAT);
689 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
690 if (tmp)
691 writel(tmp, port_mmio + PORT_IRQ_STAT);
692 }
693
694 ahci_init_controller(host);
695}
696
697static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
698 unsigned long deadline)
699{
700 struct ata_port *ap = link->ap;
701 struct ahci_host_priv *hpriv = ap->host->private_data;
702 bool online;
703 int rc;
704
705 DPRINTK("ENTER\n");
706
707 hpriv->stop_engine(ap);
708
709 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
710 deadline, &online, NULL);
711
712 hpriv->start_engine(ap);
713
714 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
715
716 /* vt8251 doesn't clear BSY on signature FIS reception,
717 * request follow-up softreset.
718 */
719 return online ? -EAGAIN : rc;
720}
721
722static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
723 unsigned long deadline)
724{
725 struct ata_port *ap = link->ap;
726 struct ahci_port_priv *pp = ap->private_data;
727 struct ahci_host_priv *hpriv = ap->host->private_data;
728 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
729 struct ata_taskfile tf;
730 bool online;
731 int rc;
732
733 hpriv->stop_engine(ap);
734
735 /* clear D2H reception area to properly wait for D2H FIS */
736 ata_tf_init(link->device, &tf);
737 tf.command = ATA_BUSY;
738 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
739
740 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
741 deadline, &online, NULL);
742
743 hpriv->start_engine(ap);
744
745 /* The pseudo configuration device on SIMG4726 attached to
746 * ASUS P5W-DH Deluxe doesn't send signature FIS after
747 * hardreset if no device is attached to the first downstream
748 * port && the pseudo device locks up on SRST w/ PMP==0. To
749 * work around this, wait for !BSY only briefly. If BSY isn't
750 * cleared, perform CLO and proceed to IDENTIFY (achieved by
751 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
752 *
753 * Wait for two seconds. Devices attached to downstream port
754 * which can't process the following IDENTIFY after this will
755 * have to be reset again. For most cases, this should
756 * suffice while making probing snappish enough.
757 */
758 if (online) {
759 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
760 ahci_check_ready);
761 if (rc)
762 ahci_kick_engine(ap);
763 }
764 return rc;
765}
766
767/*
768 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
769 *
770 * It has been observed with some SSDs that the timing of events in the
771 * link synchronization phase can leave the port in a state that can not
772 * be recovered by a SATA-hard-reset alone. The failing signature is
773 * SStatus.DET stuck at 1 ("Device presence detected but Phy
774 * communication not established"). It was found that unloading and
775 * reloading the driver when this problem occurs allows the drive
776 * connection to be recovered (DET advanced to 0x3). The critical
777 * component of reloading the driver is that the port state machines are
778 * reset by bouncing "port enable" in the AHCI PCS configuration
779 * register. So, reproduce that effect by bouncing a port whenever we
780 * see DET==1 after a reset.
781 */
782static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
783 unsigned long deadline)
784{
785 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
786 struct ata_port *ap = link->ap;
787 struct ahci_port_priv *pp = ap->private_data;
788 struct ahci_host_priv *hpriv = ap->host->private_data;
789 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
790 unsigned long tmo = deadline - jiffies;
791 struct ata_taskfile tf;
792 bool online;
793 int rc, i;
794
795 DPRINTK("ENTER\n");
796
797 hpriv->stop_engine(ap);
798
799 for (i = 0; i < 2; i++) {
800 u16 val;
801 u32 sstatus;
802 int port = ap->port_no;
803 struct ata_host *host = ap->host;
804 struct pci_dev *pdev = to_pci_dev(host->dev);
805
806 /* clear D2H reception area to properly wait for D2H FIS */
807 ata_tf_init(link->device, &tf);
808 tf.command = ATA_BUSY;
809 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
810
811 rc = sata_link_hardreset(link, timing, deadline, &online,
812 ahci_check_ready);
813
814 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
815 (sstatus & 0xf) != 1)
816 break;
817
818 ata_link_info(link, "avn bounce port%d\n", port);
819
820 pci_read_config_word(pdev, 0x92, &val);
821 val &= ~(1 << port);
822 pci_write_config_word(pdev, 0x92, val);
823 ata_msleep(ap, 1000);
824 val |= 1 << port;
825 pci_write_config_word(pdev, 0x92, val);
826 deadline += tmo;
827 }
828
829 hpriv->start_engine(ap);
830
831 if (online)
832 *class = ahci_dev_classify(ap);
833
834 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
835 return rc;
836}
837
838
839#ifdef CONFIG_PM
840static void ahci_pci_disable_interrupts(struct ata_host *host)
841{
842 struct ahci_host_priv *hpriv = host->private_data;
843 void __iomem *mmio = hpriv->mmio;
844 u32 ctl;
845
846 /* AHCI spec rev1.1 section 8.3.3:
847 * Software must disable interrupts prior to requesting a
848 * transition of the HBA to D3 state.
849 */
850 ctl = readl(mmio + HOST_CTL);
851 ctl &= ~HOST_IRQ_EN;
852 writel(ctl, mmio + HOST_CTL);
853 readl(mmio + HOST_CTL); /* flush */
854}
855
856static int ahci_pci_device_runtime_suspend(struct device *dev)
857{
858 struct pci_dev *pdev = to_pci_dev(dev);
859 struct ata_host *host = pci_get_drvdata(pdev);
860
861 ahci_pci_disable_interrupts(host);
862 return 0;
863}
864
865static int ahci_pci_device_runtime_resume(struct device *dev)
866{
867 struct pci_dev *pdev = to_pci_dev(dev);
868 struct ata_host *host = pci_get_drvdata(pdev);
869 int rc;
870
871 rc = ahci_reset_controller(host);
872 if (rc)
873 return rc;
874 ahci_pci_init_controller(host);
875 return 0;
876}
877
878#ifdef CONFIG_PM_SLEEP
879static int ahci_pci_device_suspend(struct device *dev)
880{
881 struct pci_dev *pdev = to_pci_dev(dev);
882 struct ata_host *host = pci_get_drvdata(pdev);
883 struct ahci_host_priv *hpriv = host->private_data;
884
885 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
886 dev_err(&pdev->dev,
887 "BIOS update required for suspend/resume\n");
888 return -EIO;
889 }
890
891 ahci_pci_disable_interrupts(host);
892 return ata_host_suspend(host, PMSG_SUSPEND);
893}
894
895static int ahci_pci_device_resume(struct device *dev)
896{
897 struct pci_dev *pdev = to_pci_dev(dev);
898 struct ata_host *host = pci_get_drvdata(pdev);
899 int rc;
900
901 /* Apple BIOS helpfully mangles the registers on resume */
902 if (is_mcp89_apple(pdev))
903 ahci_mcp89_apple_enable(pdev);
904
905 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
906 rc = ahci_reset_controller(host);
907 if (rc)
908 return rc;
909
910 ahci_pci_init_controller(host);
911 }
912
913 ata_host_resume(host);
914
915 return 0;
916}
917#endif
918
919#endif /* CONFIG_PM */
920
921static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
922{
923 const int dma_bits = using_dac ? 64 : 32;
924 int rc;
925
926 /*
927 * If the device fixup already set the dma_mask to some non-standard
928 * value, don't extend it here. This happens on STA2X11, for example.
929 *
930 * XXX: manipulating the DMA mask from platform code is completely
931 * bogus, platform code should use dev->bus_dma_limit instead..
932 */
933 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
934 return 0;
935
936 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
937 if (rc)
938 dev_err(&pdev->dev, "DMA enable failed\n");
939 return rc;
940}
941
942static void ahci_pci_print_info(struct ata_host *host)
943{
944 struct pci_dev *pdev = to_pci_dev(host->dev);
945 u16 cc;
946 const char *scc_s;
947
948 pci_read_config_word(pdev, 0x0a, &cc);
949 if (cc == PCI_CLASS_STORAGE_IDE)
950 scc_s = "IDE";
951 else if (cc == PCI_CLASS_STORAGE_SATA)
952 scc_s = "SATA";
953 else if (cc == PCI_CLASS_STORAGE_RAID)
954 scc_s = "RAID";
955 else
956 scc_s = "unknown";
957
958 ahci_print_info(host, scc_s);
959}
960
961/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
962 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
963 * support PMP and the 4726 either directly exports the device
964 * attached to the first downstream port or acts as a hardware storage
965 * controller and emulate a single ATA device (can be RAID 0/1 or some
966 * other configuration).
967 *
968 * When there's no device attached to the first downstream port of the
969 * 4726, "Config Disk" appears, which is a pseudo ATA device to
970 * configure the 4726. However, ATA emulation of the device is very
971 * lame. It doesn't send signature D2H Reg FIS after the initial
972 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
973 *
974 * The following function works around the problem by always using
975 * hardreset on the port and not depending on receiving signature FIS
976 * afterward. If signature FIS isn't received soon, ATA class is
977 * assumed without follow-up softreset.
978 */
979static void ahci_p5wdh_workaround(struct ata_host *host)
980{
981 static const struct dmi_system_id sysids[] = {
982 {
983 .ident = "P5W DH Deluxe",
984 .matches = {
985 DMI_MATCH(DMI_SYS_VENDOR,
986 "ASUSTEK COMPUTER INC"),
987 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
988 },
989 },
990 { }
991 };
992 struct pci_dev *pdev = to_pci_dev(host->dev);
993
994 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
995 dmi_check_system(sysids)) {
996 struct ata_port *ap = host->ports[1];
997
998 dev_info(&pdev->dev,
999 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1000
1001 ap->ops = &ahci_p5wdh_ops;
1002 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1003 }
1004}
1005
1006/*
1007 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1008 * booting in BIOS compatibility mode. We restore the registers but not ID.
1009 */
1010static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1011{
1012 u32 val;
1013
1014 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1015
1016 pci_read_config_dword(pdev, 0xf8, &val);
1017 val |= 1 << 0x1b;
1018 /* the following changes the device ID, but appears not to affect function */
1019 /* val = (val & ~0xf0000000) | 0x80000000; */
1020 pci_write_config_dword(pdev, 0xf8, val);
1021
1022 pci_read_config_dword(pdev, 0x54c, &val);
1023 val |= 1 << 0xc;
1024 pci_write_config_dword(pdev, 0x54c, val);
1025
1026 pci_read_config_dword(pdev, 0x4a4, &val);
1027 val &= 0xff;
1028 val |= 0x01060100;
1029 pci_write_config_dword(pdev, 0x4a4, val);
1030
1031 pci_read_config_dword(pdev, 0x54c, &val);
1032 val &= ~(1 << 0xc);
1033 pci_write_config_dword(pdev, 0x54c, val);
1034
1035 pci_read_config_dword(pdev, 0xf8, &val);
1036 val &= ~(1 << 0x1b);
1037 pci_write_config_dword(pdev, 0xf8, val);
1038}
1039
1040static bool is_mcp89_apple(struct pci_dev *pdev)
1041{
1042 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1043 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1044 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1045 pdev->subsystem_device == 0xcb89;
1046}
1047
1048/* only some SB600 ahci controllers can do 64bit DMA */
1049static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1050{
1051 static const struct dmi_system_id sysids[] = {
1052 /*
1053 * The oldest version known to be broken is 0901 and
1054 * working is 1501 which was released on 2007-10-26.
1055 * Enable 64bit DMA on 1501 and anything newer.
1056 *
1057 * Please read bko#9412 for more info.
1058 */
1059 {
1060 .ident = "ASUS M2A-VM",
1061 .matches = {
1062 DMI_MATCH(DMI_BOARD_VENDOR,
1063 "ASUSTeK Computer INC."),
1064 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1065 },
1066 .driver_data = "20071026", /* yyyymmdd */
1067 },
1068 /*
1069 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1070 * support 64bit DMA.
1071 *
1072 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1073 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1074 * This spelling mistake was fixed in BIOS version 1.5, so
1075 * 1.5 and later have the Manufacturer as
1076 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1077 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1078 *
1079 * BIOS versions earlier than 1.9 had a Board Product Name
1080 * DMI field of "MS-7376". This was changed to be
1081 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1082 * match on DMI_BOARD_NAME of "MS-7376".
1083 */
1084 {
1085 .ident = "MSI K9A2 Platinum",
1086 .matches = {
1087 DMI_MATCH(DMI_BOARD_VENDOR,
1088 "MICRO-STAR INTER"),
1089 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1090 },
1091 },
1092 /*
1093 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1094 * 64bit DMA.
1095 *
1096 * This board also had the typo mentioned above in the
1097 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1098 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1099 */
1100 {
1101 .ident = "MSI K9AGM2",
1102 .matches = {
1103 DMI_MATCH(DMI_BOARD_VENDOR,
1104 "MICRO-STAR INTER"),
1105 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1106 },
1107 },
1108 /*
1109 * All BIOS versions for the Asus M3A support 64bit DMA.
1110 * (all release versions from 0301 to 1206 were tested)
1111 */
1112 {
1113 .ident = "ASUS M3A",
1114 .matches = {
1115 DMI_MATCH(DMI_BOARD_VENDOR,
1116 "ASUSTeK Computer INC."),
1117 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1118 },
1119 },
1120 { }
1121 };
1122 const struct dmi_system_id *match;
1123 int year, month, date;
1124 char buf[9];
1125
1126 match = dmi_first_match(sysids);
1127 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1128 !match)
1129 return false;
1130
1131 if (!match->driver_data)
1132 goto enable_64bit;
1133
1134 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1135 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1136
1137 if (strcmp(buf, match->driver_data) >= 0)
1138 goto enable_64bit;
1139 else {
1140 dev_warn(&pdev->dev,
1141 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1142 match->ident);
1143 return false;
1144 }
1145
1146enable_64bit:
1147 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1148 return true;
1149}
1150
1151static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1152{
1153 static const struct dmi_system_id broken_systems[] = {
1154 {
1155 .ident = "HP Compaq nx6310",
1156 .matches = {
1157 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1158 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1159 },
1160 /* PCI slot number of the controller */
1161 .driver_data = (void *)0x1FUL,
1162 },
1163 {
1164 .ident = "HP Compaq 6720s",
1165 .matches = {
1166 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1167 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1168 },
1169 /* PCI slot number of the controller */
1170 .driver_data = (void *)0x1FUL,
1171 },
1172
1173 { } /* terminate list */
1174 };
1175 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1176
1177 if (dmi) {
1178 unsigned long slot = (unsigned long)dmi->driver_data;
1179 /* apply the quirk only to on-board controllers */
1180 return slot == PCI_SLOT(pdev->devfn);
1181 }
1182
1183 return false;
1184}
1185
1186static bool ahci_broken_suspend(struct pci_dev *pdev)
1187{
1188 static const struct dmi_system_id sysids[] = {
1189 /*
1190 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1191 * to the harddisk doesn't become online after
1192 * resuming from STR. Warn and fail suspend.
1193 *
1194 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1195 *
1196 * Use dates instead of versions to match as HP is
1197 * apparently recycling both product and version
1198 * strings.
1199 *
1200 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1201 */
1202 {
1203 .ident = "dv4",
1204 .matches = {
1205 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1206 DMI_MATCH(DMI_PRODUCT_NAME,
1207 "HP Pavilion dv4 Notebook PC"),
1208 },
1209 .driver_data = "20090105", /* F.30 */
1210 },
1211 {
1212 .ident = "dv5",
1213 .matches = {
1214 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1215 DMI_MATCH(DMI_PRODUCT_NAME,
1216 "HP Pavilion dv5 Notebook PC"),
1217 },
1218 .driver_data = "20090506", /* F.16 */
1219 },
1220 {
1221 .ident = "dv6",
1222 .matches = {
1223 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1224 DMI_MATCH(DMI_PRODUCT_NAME,
1225 "HP Pavilion dv6 Notebook PC"),
1226 },
1227 .driver_data = "20090423", /* F.21 */
1228 },
1229 {
1230 .ident = "HDX18",
1231 .matches = {
1232 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1233 DMI_MATCH(DMI_PRODUCT_NAME,
1234 "HP HDX18 Notebook PC"),
1235 },
1236 .driver_data = "20090430", /* F.23 */
1237 },
1238 /*
1239 * Acer eMachines G725 has the same problem. BIOS
1240 * V1.03 is known to be broken. V3.04 is known to
1241 * work. Between, there are V1.06, V2.06 and V3.03
1242 * that we don't have much idea about. For now,
1243 * blacklist anything older than V3.04.
1244 *
1245 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1246 */
1247 {
1248 .ident = "G725",
1249 .matches = {
1250 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1251 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1252 },
1253 .driver_data = "20091216", /* V3.04 */
1254 },
1255 { } /* terminate list */
1256 };
1257 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1258 int year, month, date;
1259 char buf[9];
1260
1261 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1262 return false;
1263
1264 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1265 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1266
1267 return strcmp(buf, dmi->driver_data) < 0;
1268}
1269
1270static bool ahci_broken_lpm(struct pci_dev *pdev)
1271{
1272 static const struct dmi_system_id sysids[] = {
1273 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1274 {
1275 .matches = {
1276 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1277 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1278 },
1279 .driver_data = "20180406", /* 1.31 */
1280 },
1281 {
1282 .matches = {
1283 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1284 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1285 },
1286 .driver_data = "20180420", /* 1.28 */
1287 },
1288 {
1289 .matches = {
1290 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1291 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1292 },
1293 .driver_data = "20180315", /* 1.33 */
1294 },
1295 {
1296 .matches = {
1297 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1298 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1299 },
1300 /*
1301 * Note date based on release notes, 2.35 has been
1302 * reported to be good, but I've been unable to get
1303 * a hold of the reporter to get the DMI BIOS date.
1304 * TODO: fix this.
1305 */
1306 .driver_data = "20180310", /* 2.35 */
1307 },
1308 { } /* terminate list */
1309 };
1310 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1311 int year, month, date;
1312 char buf[9];
1313
1314 if (!dmi)
1315 return false;
1316
1317 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1318 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1319
1320 return strcmp(buf, dmi->driver_data) < 0;
1321}
1322
1323static bool ahci_broken_online(struct pci_dev *pdev)
1324{
1325#define ENCODE_BUSDEVFN(bus, slot, func) \
1326 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1327 static const struct dmi_system_id sysids[] = {
1328 /*
1329 * There are several gigabyte boards which use
1330 * SIMG5723s configured as hardware RAID. Certain
1331 * 5723 firmware revisions shipped there keep the link
1332 * online but fail to answer properly to SRST or
1333 * IDENTIFY when no device is attached downstream
1334 * causing libata to retry quite a few times leading
1335 * to excessive detection delay.
1336 *
1337 * As these firmwares respond to the second reset try
1338 * with invalid device signature, considering unknown
1339 * sig as offline works around the problem acceptably.
1340 */
1341 {
1342 .ident = "EP45-DQ6",
1343 .matches = {
1344 DMI_MATCH(DMI_BOARD_VENDOR,
1345 "Gigabyte Technology Co., Ltd."),
1346 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1347 },
1348 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1349 },
1350 {
1351 .ident = "EP45-DS5",
1352 .matches = {
1353 DMI_MATCH(DMI_BOARD_VENDOR,
1354 "Gigabyte Technology Co., Ltd."),
1355 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1356 },
1357 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1358 },
1359 { } /* terminate list */
1360 };
1361#undef ENCODE_BUSDEVFN
1362 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1363 unsigned int val;
1364
1365 if (!dmi)
1366 return false;
1367
1368 val = (unsigned long)dmi->driver_data;
1369
1370 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1371}
1372
1373static bool ahci_broken_devslp(struct pci_dev *pdev)
1374{
1375 /* device with broken DEVSLP but still showing SDS capability */
1376 static const struct pci_device_id ids[] = {
1377 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1378 {}
1379 };
1380
1381 return pci_match_id(ids, pdev);
1382}
1383
1384#ifdef CONFIG_ATA_ACPI
1385static void ahci_gtf_filter_workaround(struct ata_host *host)
1386{
1387 static const struct dmi_system_id sysids[] = {
1388 /*
1389 * Aspire 3810T issues a bunch of SATA enable commands
1390 * via _GTF including an invalid one and one which is
1391 * rejected by the device. Among the successful ones
1392 * is FPDMA non-zero offset enable which when enabled
1393 * only on the drive side leads to NCQ command
1394 * failures. Filter it out.
1395 */
1396 {
1397 .ident = "Aspire 3810T",
1398 .matches = {
1399 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1400 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1401 },
1402 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1403 },
1404 { }
1405 };
1406 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1407 unsigned int filter;
1408 int i;
1409
1410 if (!dmi)
1411 return;
1412
1413 filter = (unsigned long)dmi->driver_data;
1414 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1415 filter, dmi->ident);
1416
1417 for (i = 0; i < host->n_ports; i++) {
1418 struct ata_port *ap = host->ports[i];
1419 struct ata_link *link;
1420 struct ata_device *dev;
1421
1422 ata_for_each_link(link, ap, EDGE)
1423 ata_for_each_dev(dev, link, ALL)
1424 dev->gtf_filter |= filter;
1425 }
1426}
1427#else
1428static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1429{}
1430#endif
1431
1432/*
1433 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1434 * as DUMMY, or detected but eventually get a "link down" and never get up
1435 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1436 * port_map may hold a value of 0x00.
1437 *
1438 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1439 * and can significantly reduce the occurrence of the problem.
1440 *
1441 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1442 */
1443static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1444 struct pci_dev *pdev)
1445{
1446 static const struct dmi_system_id sysids[] = {
1447 {
1448 .ident = "Acer Switch Alpha 12",
1449 .matches = {
1450 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1451 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1452 },
1453 },
1454 { }
1455 };
1456
1457 if (dmi_check_system(sysids)) {
1458 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1459 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1460 hpriv->port_map = 0x7;
1461 hpriv->cap = 0xC734FF02;
1462 }
1463 }
1464}
1465
1466#ifdef CONFIG_ARM64
1467/*
1468 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1469 * Workaround is to make sure all pending IRQs are served before leaving
1470 * handler.
1471 */
1472static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1473{
1474 struct ata_host *host = dev_instance;
1475 struct ahci_host_priv *hpriv;
1476 unsigned int rc = 0;
1477 void __iomem *mmio;
1478 u32 irq_stat, irq_masked;
1479 unsigned int handled = 1;
1480
1481 VPRINTK("ENTER\n");
1482 hpriv = host->private_data;
1483 mmio = hpriv->mmio;
1484 irq_stat = readl(mmio + HOST_IRQ_STAT);
1485 if (!irq_stat)
1486 return IRQ_NONE;
1487
1488 do {
1489 irq_masked = irq_stat & hpriv->port_map;
1490 spin_lock(&host->lock);
1491 rc = ahci_handle_port_intr(host, irq_masked);
1492 if (!rc)
1493 handled = 0;
1494 writel(irq_stat, mmio + HOST_IRQ_STAT);
1495 irq_stat = readl(mmio + HOST_IRQ_STAT);
1496 spin_unlock(&host->lock);
1497 } while (irq_stat);
1498 VPRINTK("EXIT\n");
1499
1500 return IRQ_RETVAL(handled);
1501}
1502#endif
1503
1504static void ahci_remap_check(struct pci_dev *pdev, int bar,
1505 struct ahci_host_priv *hpriv)
1506{
1507 int i;
1508 u32 cap;
1509
1510 /*
1511 * Check if this device might have remapped nvme devices.
1512 */
1513 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1514 pci_resource_len(pdev, bar) < SZ_512K ||
1515 bar != AHCI_PCI_BAR_STANDARD ||
1516 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1517 return;
1518
1519 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1520 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1521 if ((cap & (1 << i)) == 0)
1522 continue;
1523 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1524 != PCI_CLASS_STORAGE_EXPRESS)
1525 continue;
1526
1527 /* We've found a remapped device */
1528 hpriv->remapped_nvme++;
1529 }
1530
1531 if (!hpriv->remapped_nvme)
1532 return;
1533
1534 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1535 hpriv->remapped_nvme);
1536 dev_warn(&pdev->dev,
1537 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1538
1539 /*
1540 * Don't rely on the msi-x capability in the remap case,
1541 * share the legacy interrupt across ahci and remapped devices.
1542 */
1543 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1544}
1545
1546static int ahci_get_irq_vector(struct ata_host *host, int port)
1547{
1548 return pci_irq_vector(to_pci_dev(host->dev), port);
1549}
1550
1551static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1552 struct ahci_host_priv *hpriv)
1553{
1554 int nvec;
1555
1556 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1557 return -ENODEV;
1558
1559 /*
1560 * If number of MSIs is less than number of ports then Sharing Last
1561 * Message mode could be enforced. In this case assume that advantage
1562 * of multipe MSIs is negated and use single MSI mode instead.
1563 */
1564 if (n_ports > 1) {
1565 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1566 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1567 if (nvec > 0) {
1568 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1569 hpriv->get_irq_vector = ahci_get_irq_vector;
1570 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1571 return nvec;
1572 }
1573
1574 /*
1575 * Fallback to single MSI mode if the controller
1576 * enforced MRSM mode.
1577 */
1578 printk(KERN_INFO
1579 "ahci: MRSM is on, fallback to single MSI\n");
1580 pci_free_irq_vectors(pdev);
1581 }
1582 }
1583
1584 /*
1585 * If the host is not capable of supporting per-port vectors, fall
1586 * back to single MSI before finally attempting single MSI-X.
1587 */
1588 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1589 if (nvec == 1)
1590 return nvec;
1591 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1592}
1593
1594static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1595 struct ahci_host_priv *hpriv)
1596{
1597 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1598
1599
1600 /* Ignore processing for non mobile platforms */
1601 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1602 return;
1603
1604 /* user modified policy via module param */
1605 if (mobile_lpm_policy != -1) {
1606 policy = mobile_lpm_policy;
1607 goto update_policy;
1608 }
1609
1610#ifdef CONFIG_ACPI
1611 if (policy > ATA_LPM_MED_POWER &&
1612 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1613 if (hpriv->cap & HOST_CAP_PART)
1614 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1615 else if (hpriv->cap & HOST_CAP_SSC)
1616 policy = ATA_LPM_MIN_POWER;
1617 }
1618#endif
1619
1620update_policy:
1621 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1622 ap->target_lpm_policy = policy;
1623}
1624
1625static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1626{
1627 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1628 u16 tmp16;
1629
1630 /*
1631 * Only apply the 6-port PCS quirk for known legacy platforms.
1632 */
1633 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1634 return;
1635
1636 /* Skip applying the quirk on Denverton and beyond */
1637 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1638 return;
1639
1640 /*
1641 * port_map is determined from PORTS_IMPL PCI register which is
1642 * implemented as write or write-once register. If the register
1643 * isn't programmed, ahci automatically generates it from number
1644 * of ports, which is good enough for PCS programming. It is
1645 * otherwise expected that platform firmware enables the ports
1646 * before the OS boots.
1647 */
1648 pci_read_config_word(pdev, PCS_6, &tmp16);
1649 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1650 tmp16 |= hpriv->port_map;
1651 pci_write_config_word(pdev, PCS_6, tmp16);
1652 }
1653}
1654
1655static ssize_t remapped_nvme_show(struct device *dev,
1656 struct device_attribute *attr,
1657 char *buf)
1658{
1659 struct ata_host *host = dev_get_drvdata(dev);
1660 struct ahci_host_priv *hpriv = host->private_data;
1661
1662 return sprintf(buf, "%u\n", hpriv->remapped_nvme);
1663}
1664
1665static DEVICE_ATTR_RO(remapped_nvme);
1666
1667static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1668{
1669 unsigned int board_id = ent->driver_data;
1670 struct ata_port_info pi = ahci_port_info[board_id];
1671 const struct ata_port_info *ppi[] = { &pi, NULL };
1672 struct device *dev = &pdev->dev;
1673 struct ahci_host_priv *hpriv;
1674 struct ata_host *host;
1675 int n_ports, i, rc;
1676 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1677
1678 VPRINTK("ENTER\n");
1679
1680 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1681
1682 ata_print_version_once(&pdev->dev, DRV_VERSION);
1683
1684 /* The AHCI driver can only drive the SATA ports, the PATA driver
1685 can drive them all so if both drivers are selected make sure
1686 AHCI stays out of the way */
1687 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1688 return -ENODEV;
1689
1690 /* Apple BIOS on MCP89 prevents us using AHCI */
1691 if (is_mcp89_apple(pdev))
1692 ahci_mcp89_apple_enable(pdev);
1693
1694 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1695 * At the moment, we can only use the AHCI mode. Let the users know
1696 * that for SAS drives they're out of luck.
1697 */
1698 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1699 dev_info(&pdev->dev,
1700 "PDC42819 can only drive SATA devices with this driver\n");
1701
1702 /* Some devices use non-standard BARs */
1703 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1704 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1705 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1706 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1707 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1708 if (pdev->device == 0xa01c)
1709 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1710 if (pdev->device == 0xa084)
1711 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1712 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1713 if (pdev->device == 0x7a08)
1714 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1715 }
1716
1717 /* acquire resources */
1718 rc = pcim_enable_device(pdev);
1719 if (rc)
1720 return rc;
1721
1722 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1723 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1724 u8 map;
1725
1726 /* ICH6s share the same PCI ID for both piix and ahci
1727 * modes. Enabling ahci mode while MAP indicates
1728 * combined mode is a bad idea. Yield to ata_piix.
1729 */
1730 pci_read_config_byte(pdev, ICH_MAP, &map);
1731 if (map & 0x3) {
1732 dev_info(&pdev->dev,
1733 "controller is in combined mode, can't enable AHCI mode\n");
1734 return -ENODEV;
1735 }
1736 }
1737
1738 /* AHCI controllers often implement SFF compatible interface.
1739 * Grab all PCI BARs just in case.
1740 */
1741 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1742 if (rc == -EBUSY)
1743 pcim_pin_device(pdev);
1744 if (rc)
1745 return rc;
1746
1747 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1748 if (!hpriv)
1749 return -ENOMEM;
1750 hpriv->flags |= (unsigned long)pi.private_data;
1751
1752 /* MCP65 revision A1 and A2 can't do MSI */
1753 if (board_id == board_ahci_mcp65 &&
1754 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1755 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1756
1757 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1758 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1759 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1760
1761 /* only some SB600s can do 64bit DMA */
1762 if (ahci_sb600_enable_64bit(pdev))
1763 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1764
1765 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1766
1767 /* detect remapped nvme devices */
1768 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1769
1770 sysfs_add_file_to_group(&pdev->dev.kobj,
1771 &dev_attr_remapped_nvme.attr,
1772 NULL);
1773
1774 /* must set flag prior to save config in order to take effect */
1775 if (ahci_broken_devslp(pdev))
1776 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1777
1778#ifdef CONFIG_ARM64
1779 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1780 pdev->device == 0xa235 &&
1781 pdev->revision < 0x30)
1782 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1783
1784 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1785 hpriv->irq_handler = ahci_thunderx_irq_handler;
1786#endif
1787
1788 /* save initial config */
1789 ahci_pci_save_initial_config(pdev, hpriv);
1790
1791 /*
1792 * If platform firmware failed to enable ports, try to enable
1793 * them here.
1794 */
1795 ahci_intel_pcs_quirk(pdev, hpriv);
1796
1797 /* prepare host */
1798 if (hpriv->cap & HOST_CAP_NCQ) {
1799 pi.flags |= ATA_FLAG_NCQ;
1800 /*
1801 * Auto-activate optimization is supposed to be
1802 * supported on all AHCI controllers indicating NCQ
1803 * capability, but it seems to be broken on some
1804 * chipsets including NVIDIAs.
1805 */
1806 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1807 pi.flags |= ATA_FLAG_FPDMA_AA;
1808
1809 /*
1810 * All AHCI controllers should be forward-compatible
1811 * with the new auxiliary field. This code should be
1812 * conditionalized if any buggy AHCI controllers are
1813 * encountered.
1814 */
1815 pi.flags |= ATA_FLAG_FPDMA_AUX;
1816 }
1817
1818 if (hpriv->cap & HOST_CAP_PMP)
1819 pi.flags |= ATA_FLAG_PMP;
1820
1821 ahci_set_em_messages(hpriv, &pi);
1822
1823 if (ahci_broken_system_poweroff(pdev)) {
1824 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1825 dev_info(&pdev->dev,
1826 "quirky BIOS, skipping spindown on poweroff\n");
1827 }
1828
1829 if (ahci_broken_lpm(pdev)) {
1830 pi.flags |= ATA_FLAG_NO_LPM;
1831 dev_warn(&pdev->dev,
1832 "BIOS update required for Link Power Management support\n");
1833 }
1834
1835 if (ahci_broken_suspend(pdev)) {
1836 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1837 dev_warn(&pdev->dev,
1838 "BIOS update required for suspend/resume\n");
1839 }
1840
1841 if (ahci_broken_online(pdev)) {
1842 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1843 dev_info(&pdev->dev,
1844 "online status unreliable, applying workaround\n");
1845 }
1846
1847
1848 /* Acer SA5-271 workaround modifies private_data */
1849 acer_sa5_271_workaround(hpriv, pdev);
1850
1851 /* CAP.NP sometimes indicate the index of the last enabled
1852 * port, at other times, that of the last possible port, so
1853 * determining the maximum port number requires looking at
1854 * both CAP.NP and port_map.
1855 */
1856 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1857
1858 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1859 if (!host)
1860 return -ENOMEM;
1861 host->private_data = hpriv;
1862
1863 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1864 /* legacy intx interrupts */
1865 pci_intx(pdev, 1);
1866 }
1867 hpriv->irq = pci_irq_vector(pdev, 0);
1868
1869 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1870 host->flags |= ATA_HOST_PARALLEL_SCAN;
1871 else
1872 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1873
1874 if (pi.flags & ATA_FLAG_EM)
1875 ahci_reset_em(host);
1876
1877 for (i = 0; i < host->n_ports; i++) {
1878 struct ata_port *ap = host->ports[i];
1879
1880 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1881 ata_port_pbar_desc(ap, ahci_pci_bar,
1882 0x100 + ap->port_no * 0x80, "port");
1883
1884 /* set enclosure management message type */
1885 if (ap->flags & ATA_FLAG_EM)
1886 ap->em_message_type = hpriv->em_msg_type;
1887
1888 ahci_update_initial_lpm_policy(ap, hpriv);
1889
1890 /* disabled/not-implemented port */
1891 if (!(hpriv->port_map & (1 << i)))
1892 ap->ops = &ata_dummy_port_ops;
1893 }
1894
1895 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1896 ahci_p5wdh_workaround(host);
1897
1898 /* apply gtf filter quirk */
1899 ahci_gtf_filter_workaround(host);
1900
1901 /* initialize adapter */
1902 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1903 if (rc)
1904 return rc;
1905
1906 rc = ahci_reset_controller(host);
1907 if (rc)
1908 return rc;
1909
1910 ahci_pci_init_controller(host);
1911 ahci_pci_print_info(host);
1912
1913 pci_set_master(pdev);
1914
1915 rc = ahci_host_activate(host, &ahci_sht);
1916 if (rc)
1917 return rc;
1918
1919 pm_runtime_put_noidle(&pdev->dev);
1920 return 0;
1921}
1922
1923static void ahci_shutdown_one(struct pci_dev *pdev)
1924{
1925 ata_pci_shutdown_one(pdev);
1926}
1927
1928static void ahci_remove_one(struct pci_dev *pdev)
1929{
1930 sysfs_remove_file_from_group(&pdev->dev.kobj,
1931 &dev_attr_remapped_nvme.attr,
1932 NULL);
1933 pm_runtime_get_noresume(&pdev->dev);
1934 ata_pci_remove_one(pdev);
1935}
1936
1937module_pci_driver(ahci_pci_driver);
1938
1939MODULE_AUTHOR("Jeff Garzik");
1940MODULE_DESCRIPTION("AHCI SATA low-level driver");
1941MODULE_LICENSE("GPL");
1942MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1943MODULE_VERSION(DRV_VERSION);