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1/*
2 * linux/arch/arm/mm/proc-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is the "shell" of the ARMv7 processor support.
11 */
12#include <linux/init.h>
13#include <linux/linkage.h>
14#include <asm/assembler.h>
15#include <asm/asm-offsets.h>
16#include <asm/hwcap.h>
17#include <asm/pgtable-hwdef.h>
18#include <asm/pgtable.h>
19
20#include "proc-macros.S"
21
22#define TTB_S (1 << 1)
23#define TTB_RGN_NC (0 << 3)
24#define TTB_RGN_OC_WBWA (1 << 3)
25#define TTB_RGN_OC_WT (2 << 3)
26#define TTB_RGN_OC_WB (3 << 3)
27#define TTB_NOS (1 << 5)
28#define TTB_IRGN_NC ((0 << 0) | (0 << 6))
29#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
30#define TTB_IRGN_WT ((1 << 0) | (0 << 6))
31#define TTB_IRGN_WB ((1 << 0) | (1 << 6))
32
33/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
34#define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB
35#define PMD_FLAGS_UP PMD_SECT_WB
36
37/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
38#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
39#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
40
41ENTRY(cpu_v7_proc_init)
42 mov pc, lr
43ENDPROC(cpu_v7_proc_init)
44
45ENTRY(cpu_v7_proc_fin)
46 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
47 bic r0, r0, #0x1000 @ ...i............
48 bic r0, r0, #0x0006 @ .............ca.
49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
50 mov pc, lr
51ENDPROC(cpu_v7_proc_fin)
52
53/*
54 * cpu_v7_reset(loc)
55 *
56 * Perform a soft reset of the system. Put the CPU into the
57 * same state as it would be if it had been reset, and branch
58 * to what would be the reset vector.
59 *
60 * - loc - location to jump to for soft reset
61 *
62 * This code must be executed using a flat identity mapping with
63 * caches disabled.
64 */
65 .align 5
66ENTRY(cpu_v7_reset)
67 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
68 bic r1, r1, #0x1 @ ...............m
69 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
70 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
71 isb
72 mov pc, r0
73ENDPROC(cpu_v7_reset)
74
75/*
76 * cpu_v7_do_idle()
77 *
78 * Idle the processor (eg, wait for interrupt).
79 *
80 * IRQs are already disabled.
81 */
82ENTRY(cpu_v7_do_idle)
83 dsb @ WFI may enter a low-power mode
84 wfi
85 mov pc, lr
86ENDPROC(cpu_v7_do_idle)
87
88ENTRY(cpu_v7_dcache_clean_area)
89#ifndef TLB_CAN_READ_FROM_L1_CACHE
90 dcache_line_size r2, r3
911: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
92 add r0, r0, r2
93 subs r1, r1, r2
94 bhi 1b
95 dsb
96#endif
97 mov pc, lr
98ENDPROC(cpu_v7_dcache_clean_area)
99
100/*
101 * cpu_v7_switch_mm(pgd_phys, tsk)
102 *
103 * Set the translation table base pointer to be pgd_phys
104 *
105 * - pgd_phys - physical address of new TTB
106 *
107 * It is assumed that:
108 * - we are not using split page tables
109 */
110ENTRY(cpu_v7_switch_mm)
111#ifdef CONFIG_MMU
112 mov r2, #0
113 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
114 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
115 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
116#ifdef CONFIG_ARM_ERRATA_430973
117 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
118#endif
119#ifdef CONFIG_ARM_ERRATA_754322
120 dsb
121#endif
122 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
123 isb
1241: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
125 isb
126#ifdef CONFIG_ARM_ERRATA_754322
127 dsb
128#endif
129 mcr p15, 0, r1, c13, c0, 1 @ set context ID
130 isb
131#endif
132 mov pc, lr
133ENDPROC(cpu_v7_switch_mm)
134
135/*
136 * cpu_v7_set_pte_ext(ptep, pte)
137 *
138 * Set a level 2 translation table entry.
139 *
140 * - ptep - pointer to level 2 translation table entry
141 * (hardware version is stored at +2048 bytes)
142 * - pte - PTE value to store
143 * - ext - value for extended PTE bits
144 */
145ENTRY(cpu_v7_set_pte_ext)
146#ifdef CONFIG_MMU
147 str r1, [r0] @ linux version
148
149 bic r3, r1, #0x000003f0
150 bic r3, r3, #PTE_TYPE_MASK
151 orr r3, r3, r2
152 orr r3, r3, #PTE_EXT_AP0 | 2
153
154 tst r1, #1 << 4
155 orrne r3, r3, #PTE_EXT_TEX(1)
156
157 eor r1, r1, #L_PTE_DIRTY
158 tst r1, #L_PTE_RDONLY | L_PTE_DIRTY
159 orrne r3, r3, #PTE_EXT_APX
160
161 tst r1, #L_PTE_USER
162 orrne r3, r3, #PTE_EXT_AP1
163#ifdef CONFIG_CPU_USE_DOMAINS
164 @ allow kernel read/write access to read-only user pages
165 tstne r3, #PTE_EXT_APX
166 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
167#endif
168
169 tst r1, #L_PTE_XN
170 orrne r3, r3, #PTE_EXT_XN
171
172 tst r1, #L_PTE_YOUNG
173 tstne r1, #L_PTE_PRESENT
174 moveq r3, #0
175
176 ARM( str r3, [r0, #2048]! )
177 THUMB( add r0, r0, #2048 )
178 THUMB( str r3, [r0] )
179 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
180#endif
181 mov pc, lr
182ENDPROC(cpu_v7_set_pte_ext)
183
184 string cpu_v7_name, "ARMv7 Processor"
185 .align
186
187 /*
188 * Memory region attributes with SCTLR.TRE=1
189 *
190 * n = TEX[0],C,B
191 * TR = PRRR[2n+1:2n] - memory type
192 * IR = NMRR[2n+1:2n] - inner cacheable property
193 * OR = NMRR[2n+17:2n+16] - outer cacheable property
194 *
195 * n TR IR OR
196 * UNCACHED 000 00
197 * BUFFERABLE 001 10 00 00
198 * WRITETHROUGH 010 10 10 10
199 * WRITEBACK 011 10 11 11
200 * reserved 110
201 * WRITEALLOC 111 10 01 01
202 * DEV_SHARED 100 01
203 * DEV_NONSHARED 100 01
204 * DEV_WC 001 10
205 * DEV_CACHED 011 10
206 *
207 * Other attributes:
208 *
209 * DS0 = PRRR[16] = 0 - device shareable property
210 * DS1 = PRRR[17] = 1 - device shareable property
211 * NS0 = PRRR[18] = 0 - normal shareable property
212 * NS1 = PRRR[19] = 1 - normal shareable property
213 * NOS = PRRR[24+n] = 1 - not outer shareable
214 */
215.equ PRRR, 0xff0a81a8
216.equ NMRR, 0x40e040e0
217
218/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
219.globl cpu_v7_suspend_size
220.equ cpu_v7_suspend_size, 4 * 9
221#ifdef CONFIG_PM_SLEEP
222ENTRY(cpu_v7_do_suspend)
223 stmfd sp!, {r4 - r11, lr}
224 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
225 mrc p15, 0, r5, c13, c0, 1 @ Context ID
226 mrc p15, 0, r6, c13, c0, 3 @ User r/o thread ID
227 stmia r0!, {r4 - r6}
228 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
229 mrc p15, 0, r7, c2, c0, 0 @ TTB 0
230 mrc p15, 0, r8, c2, c0, 1 @ TTB 1
231 mrc p15, 0, r9, c1, c0, 0 @ Control register
232 mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
233 mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control
234 stmia r0, {r6 - r11}
235 ldmfd sp!, {r4 - r11, pc}
236ENDPROC(cpu_v7_do_suspend)
237
238ENTRY(cpu_v7_do_resume)
239 mov ip, #0
240 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
241 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
242 ldmia r0!, {r4 - r6}
243 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
244 mcr p15, 0, r5, c13, c0, 1 @ Context ID
245 mcr p15, 0, r6, c13, c0, 3 @ User r/o thread ID
246 ldmia r0, {r6 - r11}
247 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
248 mcr p15, 0, r7, c2, c0, 0 @ TTB 0
249 mcr p15, 0, r8, c2, c0, 1 @ TTB 1
250 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
251 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
252 teq r4, r10 @ Is it already set?
253 mcrne p15, 0, r10, c1, c0, 1 @ No, so write it
254 mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control
255 ldr r4, =PRRR @ PRRR
256 ldr r5, =NMRR @ NMRR
257 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
258 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
259 isb
260 dsb
261 mov r0, r9 @ control register
262 mov r2, r7, lsr #14 @ get TTB0 base
263 mov r2, r2, lsl #14
264 ldr r3, cpu_resume_l1_flags
265 b cpu_resume_mmu
266ENDPROC(cpu_v7_do_resume)
267cpu_resume_l1_flags:
268 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
269 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
270#endif
271
272 __CPUINIT
273
274/*
275 * __v7_setup
276 *
277 * Initialise TLB, Caches, and MMU state ready to switch the MMU
278 * on. Return in r0 the new CP15 C1 control register setting.
279 *
280 * We automatically detect if we have a Harvard cache, and use the
281 * Harvard cache control instructions insead of the unified cache
282 * control instructions.
283 *
284 * This should be able to cover all ARMv7 cores.
285 *
286 * It is assumed that:
287 * - cache type register is implemented
288 */
289__v7_ca5mp_setup:
290__v7_ca9mp_setup:
291 mov r10, #(1 << 0) @ TLB ops broadcasting
292 b 1f
293__v7_ca15mp_setup:
294 mov r10, #0
2951:
296#ifdef CONFIG_SMP
297 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
298 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
299 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
300 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
301 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
302 mcreq p15, 0, r0, c1, c0, 1
303#endif
304__v7_setup:
305 adr r12, __v7_setup_stack @ the local stack
306 stmia r12, {r0-r5, r7, r9, r11, lr}
307 bl v7_flush_dcache_all
308 ldmia r12, {r0-r5, r7, r9, r11, lr}
309
310 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
311 and r10, r0, #0xff000000 @ ARM?
312 teq r10, #0x41000000
313 bne 3f
314 and r5, r0, #0x00f00000 @ variant
315 and r6, r0, #0x0000000f @ revision
316 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
317 ubfx r0, r0, #4, #12 @ primary part number
318
319 /* Cortex-A8 Errata */
320 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
321 teq r0, r10
322 bne 2f
323#ifdef CONFIG_ARM_ERRATA_430973
324 teq r5, #0x00100000 @ only present in r1p*
325 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
326 orreq r10, r10, #(1 << 6) @ set IBE to 1
327 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
328#endif
329#ifdef CONFIG_ARM_ERRATA_458693
330 teq r6, #0x20 @ only present in r2p0
331 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
332 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
333 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
334 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
335#endif
336#ifdef CONFIG_ARM_ERRATA_460075
337 teq r6, #0x20 @ only present in r2p0
338 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
339 tsteq r10, #1 << 22
340 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
341 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
342#endif
343 b 3f
344
345 /* Cortex-A9 Errata */
3462: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
347 teq r0, r10
348 bne 3f
349#ifdef CONFIG_ARM_ERRATA_742230
350 cmp r6, #0x22 @ only present up to r2p2
351 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
352 orrle r10, r10, #1 << 4 @ set bit #4
353 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
354#endif
355#ifdef CONFIG_ARM_ERRATA_742231
356 teq r6, #0x20 @ present in r2p0
357 teqne r6, #0x21 @ present in r2p1
358 teqne r6, #0x22 @ present in r2p2
359 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
360 orreq r10, r10, #1 << 12 @ set bit #12
361 orreq r10, r10, #1 << 22 @ set bit #22
362 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
363#endif
364#ifdef CONFIG_ARM_ERRATA_743622
365 teq r6, #0x20 @ present in r2p0
366 teqne r6, #0x21 @ present in r2p1
367 teqne r6, #0x22 @ present in r2p2
368 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
369 orreq r10, r10, #1 << 6 @ set bit #6
370 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
371#endif
372#ifdef CONFIG_ARM_ERRATA_751472
373 cmp r6, #0x30 @ present prior to r3p0
374 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
375 orrlt r10, r10, #1 << 11 @ set bit #11
376 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
377#endif
378
3793: mov r10, #0
380#ifdef HARVARD_CACHE
381 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
382#endif
383 dsb
384#ifdef CONFIG_MMU
385 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
386 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
387 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
388 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
389 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
390 ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
391 mcr p15, 0, r8, c2, c0, 1 @ load TTB1
392 ldr r5, =PRRR @ PRRR
393 ldr r6, =NMRR @ NMRR
394 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
395 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
396#endif
397 adr r5, v7_crval
398 ldmia r5, {r5, r6}
399#ifdef CONFIG_CPU_ENDIAN_BE8
400 orr r6, r6, #1 << 25 @ big-endian page tables
401#endif
402#ifdef CONFIG_SWP_EMULATE
403 orr r5, r5, #(1 << 10) @ set SW bit in "clear"
404 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
405#endif
406 mrc p15, 0, r0, c1, c0, 0 @ read control register
407 bic r0, r0, r5 @ clear bits them
408 orr r0, r0, r6 @ set them
409 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
410 mov pc, lr @ return to head.S:__ret
411ENDPROC(__v7_setup)
412
413 /* AT
414 * TFR EV X F I D LR S
415 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
416 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
417 * 1 0 110 0011 1100 .111 1101 < we want
418 */
419 .type v7_crval, #object
420v7_crval:
421 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
422
423__v7_setup_stack:
424 .space 4 * 11 @ 11 registers
425
426 __INITDATA
427
428 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
429 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
430
431 .section ".rodata"
432
433 string cpu_arch_name, "armv7"
434 string cpu_elf_name, "v7"
435 .align
436
437 .section ".proc.info.init", #alloc, #execinstr
438
439 /*
440 * Standard v7 proc info content
441 */
442.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
443 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
444 PMD_FLAGS_SMP | \mm_mmuflags)
445 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
446 PMD_FLAGS_UP | \mm_mmuflags)
447 .long PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | \
448 PMD_SECT_AP_READ | \io_mmuflags
449 W(b) \initfunc
450 .long cpu_arch_name
451 .long cpu_elf_name
452 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
453 HWCAP_EDSP | HWCAP_TLS | \hwcaps
454 .long cpu_v7_name
455 .long v7_processor_functions
456 .long v7wbi_tlb_fns
457 .long v6_user_fns
458 .long v7_cache_fns
459.endm
460
461 /*
462 * ARM Ltd. Cortex A5 processor.
463 */
464 .type __v7_ca5mp_proc_info, #object
465__v7_ca5mp_proc_info:
466 .long 0x410fc050
467 .long 0xff0ffff0
468 __v7_proc __v7_ca5mp_setup
469 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
470
471 /*
472 * ARM Ltd. Cortex A9 processor.
473 */
474 .type __v7_ca9mp_proc_info, #object
475__v7_ca9mp_proc_info:
476 .long 0x410fc090
477 .long 0xff0ffff0
478 __v7_proc __v7_ca9mp_setup
479 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
480
481 /*
482 * ARM Ltd. Cortex A15 processor.
483 */
484 .type __v7_ca15mp_proc_info, #object
485__v7_ca15mp_proc_info:
486 .long 0x410fc0f0
487 .long 0xff0ffff0
488 __v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
489 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
490
491 /*
492 * Match any ARMv7 processor core.
493 */
494 .type __v7_proc_info, #object
495__v7_proc_info:
496 .long 0x000f0000 @ Required ID value
497 .long 0x000f0000 @ Mask for ID
498 __v7_proc __v7_setup
499 .size __v7_proc_info, . - __v7_proc_info
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/mm/proc-v7.S
4 *
5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 *
7 * This is the "shell" of the ARMv7 processor support.
8 */
9#include <linux/arm-smccc.h>
10#include <linux/init.h>
11#include <linux/linkage.h>
12#include <linux/pgtable.h>
13#include <asm/assembler.h>
14#include <asm/asm-offsets.h>
15#include <asm/hwcap.h>
16#include <asm/pgtable-hwdef.h>
17#include <asm/memory.h>
18
19#include "proc-macros.S"
20
21#ifdef CONFIG_ARM_LPAE
22#include "proc-v7-3level.S"
23#else
24#include "proc-v7-2level.S"
25#endif
26
27ENTRY(cpu_v7_proc_init)
28 ret lr
29ENDPROC(cpu_v7_proc_init)
30
31ENTRY(cpu_v7_proc_fin)
32 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
33 bic r0, r0, #0x1000 @ ...i............
34 bic r0, r0, #0x0006 @ .............ca.
35 mcr p15, 0, r0, c1, c0, 0 @ disable caches
36 ret lr
37ENDPROC(cpu_v7_proc_fin)
38
39/*
40 * cpu_v7_reset(loc, hyp)
41 *
42 * Perform a soft reset of the system. Put the CPU into the
43 * same state as it would be if it had been reset, and branch
44 * to what would be the reset vector.
45 *
46 * - loc - location to jump to for soft reset
47 * - hyp - indicate if restart occurs in HYP mode
48 *
49 * This code must be executed using a flat identity mapping with
50 * caches disabled.
51 */
52 .align 5
53 .pushsection .idmap.text, "ax"
54ENTRY(cpu_v7_reset)
55 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
56 bic r2, r2, #0x1 @ ...............m
57 THUMB( bic r2, r2, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
58 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
59 isb
60#ifdef CONFIG_ARM_VIRT_EXT
61 teq r1, #0
62 bne __hyp_soft_restart
63#endif
64 bx r0
65ENDPROC(cpu_v7_reset)
66 .popsection
67
68/*
69 * cpu_v7_do_idle()
70 *
71 * Idle the processor (eg, wait for interrupt).
72 *
73 * IRQs are already disabled.
74 */
75ENTRY(cpu_v7_do_idle)
76 dsb @ WFI may enter a low-power mode
77 wfi
78 ret lr
79ENDPROC(cpu_v7_do_idle)
80
81ENTRY(cpu_v7_dcache_clean_area)
82 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
83 ALT_UP_B(1f)
84 ret lr
851: dcache_line_size r2, r3
862: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
87 add r0, r0, r2
88 subs r1, r1, r2
89 bhi 2b
90 dsb ishst
91 ret lr
92ENDPROC(cpu_v7_dcache_clean_area)
93
94#ifdef CONFIG_ARM_PSCI
95 .arch_extension sec
96ENTRY(cpu_v7_smc_switch_mm)
97 stmfd sp!, {r0 - r3}
98 movw r0, #:lower16:ARM_SMCCC_ARCH_WORKAROUND_1
99 movt r0, #:upper16:ARM_SMCCC_ARCH_WORKAROUND_1
100 smc #0
101 ldmfd sp!, {r0 - r3}
102 b cpu_v7_switch_mm
103ENDPROC(cpu_v7_smc_switch_mm)
104 .arch_extension virt
105ENTRY(cpu_v7_hvc_switch_mm)
106 stmfd sp!, {r0 - r3}
107 movw r0, #:lower16:ARM_SMCCC_ARCH_WORKAROUND_1
108 movt r0, #:upper16:ARM_SMCCC_ARCH_WORKAROUND_1
109 hvc #0
110 ldmfd sp!, {r0 - r3}
111 b cpu_v7_switch_mm
112ENDPROC(cpu_v7_hvc_switch_mm)
113#endif
114ENTRY(cpu_v7_iciallu_switch_mm)
115 mov r3, #0
116 mcr p15, 0, r3, c7, c5, 0 @ ICIALLU
117 b cpu_v7_switch_mm
118ENDPROC(cpu_v7_iciallu_switch_mm)
119ENTRY(cpu_v7_bpiall_switch_mm)
120 mov r3, #0
121 mcr p15, 0, r3, c7, c5, 6 @ flush BTAC/BTB
122 b cpu_v7_switch_mm
123ENDPROC(cpu_v7_bpiall_switch_mm)
124
125 string cpu_v7_name, "ARMv7 Processor"
126 .align
127
128/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
129.globl cpu_v7_suspend_size
130.equ cpu_v7_suspend_size, 4 * 9
131#ifdef CONFIG_ARM_CPU_SUSPEND
132ENTRY(cpu_v7_do_suspend)
133 stmfd sp!, {r4 - r11, lr}
134 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
135 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
136 stmia r0!, {r4 - r5}
137#ifdef CONFIG_MMU
138 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
139#ifdef CONFIG_ARM_LPAE
140 mrrc p15, 1, r5, r7, c2 @ TTB 1
141#else
142 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
143#endif
144 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
145#endif
146 mrc p15, 0, r8, c1, c0, 0 @ Control register
147 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
148 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
149 stmia r0, {r5 - r11}
150 ldmfd sp!, {r4 - r11, pc}
151ENDPROC(cpu_v7_do_suspend)
152
153ENTRY(cpu_v7_do_resume)
154 mov ip, #0
155 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
156 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
157 ldmia r0!, {r4 - r5}
158 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
159 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
160 ldmia r0, {r5 - r11}
161#ifdef CONFIG_MMU
162 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
163 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
164#ifdef CONFIG_ARM_LPAE
165 mcrr p15, 0, r1, ip, c2 @ TTB 0
166 mcrr p15, 1, r5, r7, c2 @ TTB 1
167#else
168 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
169 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
170 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
171 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
172#endif
173 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
174 ldr r4, =PRRR @ PRRR
175 ldr r5, =NMRR @ NMRR
176 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
177 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
178#endif /* CONFIG_MMU */
179 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
180 teq r4, r9 @ Is it already set?
181 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
182 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
183 isb
184 dsb
185 mov r0, r8 @ control register
186 b cpu_resume_mmu
187ENDPROC(cpu_v7_do_resume)
188#endif
189
190.globl cpu_ca9mp_suspend_size
191.equ cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
192#ifdef CONFIG_ARM_CPU_SUSPEND
193ENTRY(cpu_ca9mp_do_suspend)
194 stmfd sp!, {r4 - r5}
195 mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register
196 mrc p15, 0, r5, c15, c0, 0 @ Power register
197 stmia r0!, {r4 - r5}
198 ldmfd sp!, {r4 - r5}
199 b cpu_v7_do_suspend
200ENDPROC(cpu_ca9mp_do_suspend)
201
202ENTRY(cpu_ca9mp_do_resume)
203 ldmia r0!, {r4 - r5}
204 mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register
205 teq r4, r10 @ Already restored?
206 mcrne p15, 0, r4, c15, c0, 1 @ No, so restore it
207 mrc p15, 0, r10, c15, c0, 0 @ Read Power register
208 teq r5, r10 @ Already restored?
209 mcrne p15, 0, r5, c15, c0, 0 @ No, so restore it
210 b cpu_v7_do_resume
211ENDPROC(cpu_ca9mp_do_resume)
212#endif
213
214#ifdef CONFIG_CPU_PJ4B
215 globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
216 globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
217 globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init
218 globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin
219 globl_equ cpu_pj4b_reset, cpu_v7_reset
220#ifdef CONFIG_PJ4B_ERRATA_4742
221ENTRY(cpu_pj4b_do_idle)
222 dsb @ WFI may enter a low-power mode
223 wfi
224 dsb @barrier
225 ret lr
226ENDPROC(cpu_pj4b_do_idle)
227#else
228 globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
229#endif
230 globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
231#ifdef CONFIG_ARM_CPU_SUSPEND
232ENTRY(cpu_pj4b_do_suspend)
233 stmfd sp!, {r6 - r10}
234 mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features
235 mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0
236 mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
237 mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1
238 mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC
239 stmia r0!, {r6 - r10}
240 ldmfd sp!, {r6 - r10}
241 b cpu_v7_do_suspend
242ENDPROC(cpu_pj4b_do_suspend)
243
244ENTRY(cpu_pj4b_do_resume)
245 ldmia r0!, {r6 - r10}
246 mcr p15, 1, r6, c15, c1, 0 @ restore CP15 - extra features
247 mcr p15, 1, r7, c15, c2, 0 @ restore CP15 - Aux Func Modes Ctrl 0
248 mcr p15, 1, r8, c15, c1, 2 @ restore CP15 - Aux Debug Modes Ctrl 2
249 mcr p15, 1, r9, c15, c1, 1 @ restore CP15 - Aux Debug Modes Ctrl 1
250 mcr p15, 0, r10, c9, c14, 0 @ restore CP15 - PMC
251 b cpu_v7_do_resume
252ENDPROC(cpu_pj4b_do_resume)
253#endif
254.globl cpu_pj4b_suspend_size
255.equ cpu_pj4b_suspend_size, cpu_v7_suspend_size + 4 * 5
256
257#endif
258
259 @
260 @ Invoke the v7_invalidate_l1() function, which adheres to the AAPCS
261 @ rules, and so it may corrupt registers that we need to preserve.
262 @
263 .macro do_invalidate_l1
264 mov r6, r1
265 mov r7, r2
266 mov r10, lr
267 bl v7_invalidate_l1 @ corrupts {r0-r3, ip, lr}
268 mov r1, r6
269 mov r2, r7
270 mov lr, r10
271 .endm
272
273/*
274 * __v7_setup
275 *
276 * Initialise TLB, Caches, and MMU state ready to switch the MMU
277 * on. Return in r0 the new CP15 C1 control register setting.
278 *
279 * r1, r2, r4, r5, r9, r13 must be preserved - r13 is not a stack
280 * r4: TTBR0 (low word)
281 * r5: TTBR0 (high word if LPAE)
282 * r8: TTBR1
283 * r9: Main ID register
284 *
285 * This should be able to cover all ARMv7 cores.
286 *
287 * It is assumed that:
288 * - cache type register is implemented
289 */
290__v7_ca5mp_setup:
291__v7_ca9mp_setup:
292__v7_cr7mp_setup:
293__v7_cr8mp_setup:
294 do_invalidate_l1
295 mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
296 b 1f
297__v7_ca7mp_setup:
298__v7_ca12mp_setup:
299__v7_ca15mp_setup:
300__v7_b15mp_setup:
301__v7_ca17mp_setup:
302 do_invalidate_l1
303 mov r10, #0
3041:
305#ifdef CONFIG_SMP
306 orr r10, r10, #(1 << 6) @ Enable SMP/nAMP mode
307 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
308 ALT_UP(mov r0, r10) @ fake it for UP
309 orr r10, r10, r0 @ Set required bits
310 teq r10, r0 @ Were they already set?
311 mcrne p15, 0, r10, c1, c0, 1 @ No, update register
312#endif
313 b __v7_setup_cont
314
315/*
316 * Errata:
317 * r0, r10 available for use
318 * r1, r2, r4, r5, r9, r13: must be preserved
319 * r3: contains MIDR rX number in bits 23-20
320 * r6: contains MIDR rXpY as 8-bit XY number
321 * r9: MIDR
322 */
323__ca8_errata:
324#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
325 teq r3, #0x00100000 @ only present in r1p*
326 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
327 orreq r0, r0, #(1 << 6) @ set IBE to 1
328 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
329#endif
330#ifdef CONFIG_ARM_ERRATA_458693
331 teq r6, #0x20 @ only present in r2p0
332 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
333 orreq r0, r0, #(1 << 5) @ set L1NEON to 1
334 orreq r0, r0, #(1 << 9) @ set PLDNOP to 1
335 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
336#endif
337#ifdef CONFIG_ARM_ERRATA_460075
338 teq r6, #0x20 @ only present in r2p0
339 mrceq p15, 1, r0, c9, c0, 2 @ read L2 cache aux ctrl register
340 tsteq r0, #1 << 22
341 orreq r0, r0, #(1 << 22) @ set the Write Allocate disable bit
342 mcreq p15, 1, r0, c9, c0, 2 @ write the L2 cache aux ctrl register
343#endif
344 b __errata_finish
345
346__ca9_errata:
347#ifdef CONFIG_ARM_ERRATA_742230
348 cmp r6, #0x22 @ only present up to r2p2
349 mrcle p15, 0, r0, c15, c0, 1 @ read diagnostic register
350 orrle r0, r0, #1 << 4 @ set bit #4
351 mcrle p15, 0, r0, c15, c0, 1 @ write diagnostic register
352#endif
353#ifdef CONFIG_ARM_ERRATA_742231
354 teq r6, #0x20 @ present in r2p0
355 teqne r6, #0x21 @ present in r2p1
356 teqne r6, #0x22 @ present in r2p2
357 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
358 orreq r0, r0, #1 << 12 @ set bit #12
359 orreq r0, r0, #1 << 22 @ set bit #22
360 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
361#endif
362#ifdef CONFIG_ARM_ERRATA_743622
363 teq r3, #0x00200000 @ only present in r2p*
364 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
365 orreq r0, r0, #1 << 6 @ set bit #6
366 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
367#endif
368#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
369 ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
370 ALT_UP_B(1f)
371 mrclt p15, 0, r0, c15, c0, 1 @ read diagnostic register
372 orrlt r0, r0, #1 << 11 @ set bit #11
373 mcrlt p15, 0, r0, c15, c0, 1 @ write diagnostic register
3741:
375#endif
376 b __errata_finish
377
378__ca15_errata:
379#ifdef CONFIG_ARM_ERRATA_773022
380 cmp r6, #0x4 @ only present up to r0p4
381 mrcle p15, 0, r0, c1, c0, 1 @ read aux control register
382 orrle r0, r0, #1 << 1 @ disable loop buffer
383 mcrle p15, 0, r0, c1, c0, 1 @ write aux control register
384#endif
385 b __errata_finish
386
387__ca12_errata:
388#ifdef CONFIG_ARM_ERRATA_818325_852422
389 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
390 orr r10, r10, #1 << 12 @ set bit #12
391 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
392#endif
393#ifdef CONFIG_ARM_ERRATA_821420
394 mrc p15, 0, r10, c15, c0, 2 @ read internal feature reg
395 orr r10, r10, #1 << 1 @ set bit #1
396 mcr p15, 0, r10, c15, c0, 2 @ write internal feature reg
397#endif
398#ifdef CONFIG_ARM_ERRATA_825619
399 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
400 orr r10, r10, #1 << 24 @ set bit #24
401 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
402#endif
403#ifdef CONFIG_ARM_ERRATA_857271
404 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
405 orr r10, r10, #3 << 10 @ set bits #10 and #11
406 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
407#endif
408 b __errata_finish
409
410__ca17_errata:
411#ifdef CONFIG_ARM_ERRATA_852421
412 cmp r6, #0x12 @ only present up to r1p2
413 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
414 orrle r10, r10, #1 << 24 @ set bit #24
415 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
416#endif
417#ifdef CONFIG_ARM_ERRATA_852423
418 cmp r6, #0x12 @ only present up to r1p2
419 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
420 orrle r10, r10, #1 << 12 @ set bit #12
421 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
422#endif
423#ifdef CONFIG_ARM_ERRATA_857272
424 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
425 orr r10, r10, #3 << 10 @ set bits #10 and #11
426 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
427#endif
428 b __errata_finish
429
430__v7_pj4b_setup:
431#ifdef CONFIG_CPU_PJ4B
432
433/* Auxiliary Debug Modes Control 1 Register */
434#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
435#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
436#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
437
438/* Auxiliary Debug Modes Control 2 Register */
439#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
440#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
441#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
442#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
443#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
444#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
445 PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
446
447/* Auxiliary Functional Modes Control Register 0 */
448#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
449#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
450#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
451
452/* Auxiliary Debug Modes Control 0 Register */
453#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
454
455 /* Auxiliary Debug Modes Control 1 Register */
456 mrc p15, 1, r0, c15, c1, 1
457 orr r0, r0, #PJ4B_CLEAN_LINE
458 orr r0, r0, #PJ4B_INTER_PARITY
459 bic r0, r0, #PJ4B_STATIC_BP
460 mcr p15, 1, r0, c15, c1, 1
461
462 /* Auxiliary Debug Modes Control 2 Register */
463 mrc p15, 1, r0, c15, c1, 2
464 bic r0, r0, #PJ4B_FAST_LDR
465 orr r0, r0, #PJ4B_AUX_DBG_CTRL2
466 mcr p15, 1, r0, c15, c1, 2
467
468 /* Auxiliary Functional Modes Control Register 0 */
469 mrc p15, 1, r0, c15, c2, 0
470#ifdef CONFIG_SMP
471 orr r0, r0, #PJ4B_SMP_CFB
472#endif
473 orr r0, r0, #PJ4B_L1_PAR_CHK
474 orr r0, r0, #PJ4B_BROADCAST_CACHE
475 mcr p15, 1, r0, c15, c2, 0
476
477 /* Auxiliary Debug Modes Control 0 Register */
478 mrc p15, 1, r0, c15, c1, 0
479 orr r0, r0, #PJ4B_WFI_WFE
480 mcr p15, 1, r0, c15, c1, 0
481
482#endif /* CONFIG_CPU_PJ4B */
483
484__v7_setup:
485 do_invalidate_l1
486
487__v7_setup_cont:
488 and r0, r9, #0xff000000 @ ARM?
489 teq r0, #0x41000000
490 bne __errata_finish
491 and r3, r9, #0x00f00000 @ variant
492 and r6, r9, #0x0000000f @ revision
493 orr r6, r6, r3, lsr #20-4 @ combine variant and revision
494 ubfx r0, r9, #4, #12 @ primary part number
495
496 /* Cortex-A8 Errata */
497 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
498 teq r0, r10
499 beq __ca8_errata
500
501 /* Cortex-A9 Errata */
502 ldr r10, =0x00000c09 @ Cortex-A9 primary part number
503 teq r0, r10
504 beq __ca9_errata
505
506 /* Cortex-A12 Errata */
507 ldr r10, =0x00000c0d @ Cortex-A12 primary part number
508 teq r0, r10
509 beq __ca12_errata
510
511 /* Cortex-A17 Errata */
512 ldr r10, =0x00000c0e @ Cortex-A17 primary part number
513 teq r0, r10
514 beq __ca17_errata
515
516 /* Cortex-A15 Errata */
517 ldr r10, =0x00000c0f @ Cortex-A15 primary part number
518 teq r0, r10
519 beq __ca15_errata
520
521__errata_finish:
522 mov r10, #0
523 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
524#ifdef CONFIG_MMU
525 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
526 v7_ttb_setup r10, r4, r5, r8, r3 @ TTBCR, TTBRx setup
527 ldr r3, =PRRR @ PRRR
528 ldr r6, =NMRR @ NMRR
529 mcr p15, 0, r3, c10, c2, 0 @ write PRRR
530 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
531#endif
532 dsb @ Complete invalidations
533#ifndef CONFIG_ARM_THUMBEE
534 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
535 and r0, r0, #(0xf << 12) @ ThumbEE enabled field
536 teq r0, #(1 << 12) @ check if ThumbEE is present
537 bne 1f
538 mov r3, #0
539 mcr p14, 6, r3, c1, c0, 0 @ Initialize TEEHBR to 0
540 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
541 orr r0, r0, #1 @ set the 1st bit in order to
542 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
5431:
544#endif
545 adr r3, v7_crval
546 ldmia r3, {r3, r6}
547 ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
548#ifdef CONFIG_SWP_EMULATE
549 orr r3, r3, #(1 << 10) @ set SW bit in "clear"
550 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
551#endif
552 mrc p15, 0, r0, c1, c0, 0 @ read control register
553 bic r0, r0, r3 @ clear bits them
554 orr r0, r0, r6 @ set them
555 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
556 ret lr @ return to head.S:__ret
557ENDPROC(__v7_setup)
558
559 __INITDATA
560
561 .weak cpu_v7_bugs_init
562
563 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
564 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
565
566#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
567 @ generic v7 bpiall on context switch
568 globl_equ cpu_v7_bpiall_proc_init, cpu_v7_proc_init
569 globl_equ cpu_v7_bpiall_proc_fin, cpu_v7_proc_fin
570 globl_equ cpu_v7_bpiall_reset, cpu_v7_reset
571 globl_equ cpu_v7_bpiall_do_idle, cpu_v7_do_idle
572 globl_equ cpu_v7_bpiall_dcache_clean_area, cpu_v7_dcache_clean_area
573 globl_equ cpu_v7_bpiall_set_pte_ext, cpu_v7_set_pte_ext
574 globl_equ cpu_v7_bpiall_suspend_size, cpu_v7_suspend_size
575#ifdef CONFIG_ARM_CPU_SUSPEND
576 globl_equ cpu_v7_bpiall_do_suspend, cpu_v7_do_suspend
577 globl_equ cpu_v7_bpiall_do_resume, cpu_v7_do_resume
578#endif
579 define_processor_functions v7_bpiall, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
580
581#define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_bpiall_processor_functions
582#else
583#define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_processor_functions
584#endif
585
586#ifndef CONFIG_ARM_LPAE
587 @ Cortex-A8 - always needs bpiall switch_mm implementation
588 globl_equ cpu_ca8_proc_init, cpu_v7_proc_init
589 globl_equ cpu_ca8_proc_fin, cpu_v7_proc_fin
590 globl_equ cpu_ca8_reset, cpu_v7_reset
591 globl_equ cpu_ca8_do_idle, cpu_v7_do_idle
592 globl_equ cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area
593 globl_equ cpu_ca8_set_pte_ext, cpu_v7_set_pte_ext
594 globl_equ cpu_ca8_switch_mm, cpu_v7_bpiall_switch_mm
595 globl_equ cpu_ca8_suspend_size, cpu_v7_suspend_size
596#ifdef CONFIG_ARM_CPU_SUSPEND
597 globl_equ cpu_ca8_do_suspend, cpu_v7_do_suspend
598 globl_equ cpu_ca8_do_resume, cpu_v7_do_resume
599#endif
600 define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca8_ibe
601
602 @ Cortex-A9 - needs more registers preserved across suspend/resume
603 @ and bpiall switch_mm for hardening
604 globl_equ cpu_ca9mp_proc_init, cpu_v7_proc_init
605 globl_equ cpu_ca9mp_proc_fin, cpu_v7_proc_fin
606 globl_equ cpu_ca9mp_reset, cpu_v7_reset
607 globl_equ cpu_ca9mp_do_idle, cpu_v7_do_idle
608 globl_equ cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area
609#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
610 globl_equ cpu_ca9mp_switch_mm, cpu_v7_bpiall_switch_mm
611#else
612 globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm
613#endif
614 globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext
615 define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
616#endif
617
618 @ Cortex-A15 - needs iciallu switch_mm for hardening
619 globl_equ cpu_ca15_proc_init, cpu_v7_proc_init
620 globl_equ cpu_ca15_proc_fin, cpu_v7_proc_fin
621 globl_equ cpu_ca15_reset, cpu_v7_reset
622 globl_equ cpu_ca15_do_idle, cpu_v7_do_idle
623 globl_equ cpu_ca15_dcache_clean_area, cpu_v7_dcache_clean_area
624#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
625 globl_equ cpu_ca15_switch_mm, cpu_v7_iciallu_switch_mm
626#else
627 globl_equ cpu_ca15_switch_mm, cpu_v7_switch_mm
628#endif
629 globl_equ cpu_ca15_set_pte_ext, cpu_v7_set_pte_ext
630 globl_equ cpu_ca15_suspend_size, cpu_v7_suspend_size
631 globl_equ cpu_ca15_do_suspend, cpu_v7_do_suspend
632 globl_equ cpu_ca15_do_resume, cpu_v7_do_resume
633 define_processor_functions ca15, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca15_ibe
634#ifdef CONFIG_CPU_PJ4B
635 define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
636#endif
637
638 .section ".rodata"
639
640 string cpu_arch_name, "armv7"
641 string cpu_elf_name, "v7"
642 .align
643
644 .section ".proc.info.init", "a"
645
646 /*
647 * Standard v7 proc info content
648 */
649.macro __v7_proc name, initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions, cache_fns = v7_cache_fns
650 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
651 PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
652 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
653 PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
654 .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
655 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
656 initfn \initfunc, \name
657 .long cpu_arch_name
658 .long cpu_elf_name
659 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
660 HWCAP_EDSP | HWCAP_TLS | \hwcaps
661 .long cpu_v7_name
662 .long \proc_fns
663 .long v7wbi_tlb_fns
664 .long v6_user_fns
665 .long \cache_fns
666.endm
667
668#ifndef CONFIG_ARM_LPAE
669 /*
670 * ARM Ltd. Cortex A5 processor.
671 */
672 .type __v7_ca5mp_proc_info, #object
673__v7_ca5mp_proc_info:
674 .long 0x410fc050
675 .long 0xff0ffff0
676 __v7_proc __v7_ca5mp_proc_info, __v7_ca5mp_setup
677 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
678
679 /*
680 * ARM Ltd. Cortex A9 processor.
681 */
682 .type __v7_ca9mp_proc_info, #object
683__v7_ca9mp_proc_info:
684 .long 0x410fc090
685 .long 0xff0ffff0
686 __v7_proc __v7_ca9mp_proc_info, __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions
687 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
688
689 /*
690 * ARM Ltd. Cortex A8 processor.
691 */
692 .type __v7_ca8_proc_info, #object
693__v7_ca8_proc_info:
694 .long 0x410fc080
695 .long 0xff0ffff0
696 __v7_proc __v7_ca8_proc_info, __v7_setup, proc_fns = ca8_processor_functions
697 .size __v7_ca8_proc_info, . - __v7_ca8_proc_info
698
699#endif /* CONFIG_ARM_LPAE */
700
701 /*
702 * Marvell PJ4B processor.
703 */
704#ifdef CONFIG_CPU_PJ4B
705 .type __v7_pj4b_proc_info, #object
706__v7_pj4b_proc_info:
707 .long 0x560f5800
708 .long 0xff0fff00
709 __v7_proc __v7_pj4b_proc_info, __v7_pj4b_setup, proc_fns = pj4b_processor_functions
710 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
711#endif
712
713 /*
714 * ARM Ltd. Cortex R7 processor.
715 */
716 .type __v7_cr7mp_proc_info, #object
717__v7_cr7mp_proc_info:
718 .long 0x410fc170
719 .long 0xff0ffff0
720 __v7_proc __v7_cr7mp_proc_info, __v7_cr7mp_setup
721 .size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
722
723 /*
724 * ARM Ltd. Cortex R8 processor.
725 */
726 .type __v7_cr8mp_proc_info, #object
727__v7_cr8mp_proc_info:
728 .long 0x410fc180
729 .long 0xff0ffff0
730 __v7_proc __v7_cr8mp_proc_info, __v7_cr8mp_setup
731 .size __v7_cr8mp_proc_info, . - __v7_cr8mp_proc_info
732
733 /*
734 * ARM Ltd. Cortex A7 processor.
735 */
736 .type __v7_ca7mp_proc_info, #object
737__v7_ca7mp_proc_info:
738 .long 0x410fc070
739 .long 0xff0ffff0
740 __v7_proc __v7_ca7mp_proc_info, __v7_ca7mp_setup
741 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
742
743 /*
744 * ARM Ltd. Cortex A12 processor.
745 */
746 .type __v7_ca12mp_proc_info, #object
747__v7_ca12mp_proc_info:
748 .long 0x410fc0d0
749 .long 0xff0ffff0
750 __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
751 .size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
752
753 /*
754 * ARM Ltd. Cortex A15 processor.
755 */
756 .type __v7_ca15mp_proc_info, #object
757__v7_ca15mp_proc_info:
758 .long 0x410fc0f0
759 .long 0xff0ffff0
760 __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup, proc_fns = ca15_processor_functions
761 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
762
763 /*
764 * Broadcom Corporation Brahma-B15 processor.
765 */
766 .type __v7_b15mp_proc_info, #object
767__v7_b15mp_proc_info:
768 .long 0x420f00f0
769 .long 0xff0ffff0
770 __v7_proc __v7_b15mp_proc_info, __v7_b15mp_setup, proc_fns = ca15_processor_functions, cache_fns = b15_cache_fns
771 .size __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
772
773 /*
774 * ARM Ltd. Cortex A17 processor.
775 */
776 .type __v7_ca17mp_proc_info, #object
777__v7_ca17mp_proc_info:
778 .long 0x410fc0e0
779 .long 0xff0ffff0
780 __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
781 .size __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
782
783 /* ARM Ltd. Cortex A73 processor */
784 .type __v7_ca73_proc_info, #object
785__v7_ca73_proc_info:
786 .long 0x410fd090
787 .long 0xff0ffff0
788 __v7_proc __v7_ca73_proc_info, __v7_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
789 .size __v7_ca73_proc_info, . - __v7_ca73_proc_info
790
791 /* ARM Ltd. Cortex A75 processor */
792 .type __v7_ca75_proc_info, #object
793__v7_ca75_proc_info:
794 .long 0x410fd0a0
795 .long 0xff0ffff0
796 __v7_proc __v7_ca75_proc_info, __v7_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
797 .size __v7_ca75_proc_info, . - __v7_ca75_proc_info
798
799 /*
800 * Qualcomm Inc. Krait processors.
801 */
802 .type __krait_proc_info, #object
803__krait_proc_info:
804 .long 0x510f0400 @ Required ID value
805 .long 0xff0ffc00 @ Mask for ID
806 /*
807 * Some Krait processors don't indicate support for SDIV and UDIV
808 * instructions in the ARM instruction set, even though they actually
809 * do support them. They also don't indicate support for fused multiply
810 * instructions even though they actually do support them.
811 */
812 __v7_proc __krait_proc_info, __v7_setup, hwcaps = HWCAP_IDIV | HWCAP_VFPv4
813 .size __krait_proc_info, . - __krait_proc_info
814
815 /*
816 * Match any ARMv7 processor core.
817 */
818 .type __v7_proc_info, #object
819__v7_proc_info:
820 .long 0x000f0000 @ Required ID value
821 .long 0x000f0000 @ Mask for ID
822 __v7_proc __v7_proc_info, __v7_setup
823 .size __v7_proc_info, . - __v7_proc_info