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1/*
2 * linux/arch/arm/mm/proc-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is the "shell" of the ARMv7 processor support.
11 */
12#include <linux/init.h>
13#include <linux/linkage.h>
14#include <asm/assembler.h>
15#include <asm/asm-offsets.h>
16#include <asm/hwcap.h>
17#include <asm/pgtable-hwdef.h>
18#include <asm/pgtable.h>
19
20#include "proc-macros.S"
21
22#define TTB_S (1 << 1)
23#define TTB_RGN_NC (0 << 3)
24#define TTB_RGN_OC_WBWA (1 << 3)
25#define TTB_RGN_OC_WT (2 << 3)
26#define TTB_RGN_OC_WB (3 << 3)
27#define TTB_NOS (1 << 5)
28#define TTB_IRGN_NC ((0 << 0) | (0 << 6))
29#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
30#define TTB_IRGN_WT ((1 << 0) | (0 << 6))
31#define TTB_IRGN_WB ((1 << 0) | (1 << 6))
32
33/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
34#define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB
35#define PMD_FLAGS_UP PMD_SECT_WB
36
37/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
38#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
39#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
40
41ENTRY(cpu_v7_proc_init)
42 mov pc, lr
43ENDPROC(cpu_v7_proc_init)
44
45ENTRY(cpu_v7_proc_fin)
46 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
47 bic r0, r0, #0x1000 @ ...i............
48 bic r0, r0, #0x0006 @ .............ca.
49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
50 mov pc, lr
51ENDPROC(cpu_v7_proc_fin)
52
53/*
54 * cpu_v7_reset(loc)
55 *
56 * Perform a soft reset of the system. Put the CPU into the
57 * same state as it would be if it had been reset, and branch
58 * to what would be the reset vector.
59 *
60 * - loc - location to jump to for soft reset
61 *
62 * This code must be executed using a flat identity mapping with
63 * caches disabled.
64 */
65 .align 5
66ENTRY(cpu_v7_reset)
67 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
68 bic r1, r1, #0x1 @ ...............m
69 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
70 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
71 isb
72 mov pc, r0
73ENDPROC(cpu_v7_reset)
74
75/*
76 * cpu_v7_do_idle()
77 *
78 * Idle the processor (eg, wait for interrupt).
79 *
80 * IRQs are already disabled.
81 */
82ENTRY(cpu_v7_do_idle)
83 dsb @ WFI may enter a low-power mode
84 wfi
85 mov pc, lr
86ENDPROC(cpu_v7_do_idle)
87
88ENTRY(cpu_v7_dcache_clean_area)
89#ifndef TLB_CAN_READ_FROM_L1_CACHE
90 dcache_line_size r2, r3
911: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
92 add r0, r0, r2
93 subs r1, r1, r2
94 bhi 1b
95 dsb
96#endif
97 mov pc, lr
98ENDPROC(cpu_v7_dcache_clean_area)
99
100/*
101 * cpu_v7_switch_mm(pgd_phys, tsk)
102 *
103 * Set the translation table base pointer to be pgd_phys
104 *
105 * - pgd_phys - physical address of new TTB
106 *
107 * It is assumed that:
108 * - we are not using split page tables
109 */
110ENTRY(cpu_v7_switch_mm)
111#ifdef CONFIG_MMU
112 mov r2, #0
113 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
114 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
115 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
116#ifdef CONFIG_ARM_ERRATA_430973
117 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
118#endif
119#ifdef CONFIG_ARM_ERRATA_754322
120 dsb
121#endif
122 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
123 isb
1241: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
125 isb
126#ifdef CONFIG_ARM_ERRATA_754322
127 dsb
128#endif
129 mcr p15, 0, r1, c13, c0, 1 @ set context ID
130 isb
131#endif
132 mov pc, lr
133ENDPROC(cpu_v7_switch_mm)
134
135/*
136 * cpu_v7_set_pte_ext(ptep, pte)
137 *
138 * Set a level 2 translation table entry.
139 *
140 * - ptep - pointer to level 2 translation table entry
141 * (hardware version is stored at +2048 bytes)
142 * - pte - PTE value to store
143 * - ext - value for extended PTE bits
144 */
145ENTRY(cpu_v7_set_pte_ext)
146#ifdef CONFIG_MMU
147 str r1, [r0] @ linux version
148
149 bic r3, r1, #0x000003f0
150 bic r3, r3, #PTE_TYPE_MASK
151 orr r3, r3, r2
152 orr r3, r3, #PTE_EXT_AP0 | 2
153
154 tst r1, #1 << 4
155 orrne r3, r3, #PTE_EXT_TEX(1)
156
157 eor r1, r1, #L_PTE_DIRTY
158 tst r1, #L_PTE_RDONLY | L_PTE_DIRTY
159 orrne r3, r3, #PTE_EXT_APX
160
161 tst r1, #L_PTE_USER
162 orrne r3, r3, #PTE_EXT_AP1
163#ifdef CONFIG_CPU_USE_DOMAINS
164 @ allow kernel read/write access to read-only user pages
165 tstne r3, #PTE_EXT_APX
166 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
167#endif
168
169 tst r1, #L_PTE_XN
170 orrne r3, r3, #PTE_EXT_XN
171
172 tst r1, #L_PTE_YOUNG
173 tstne r1, #L_PTE_PRESENT
174 moveq r3, #0
175
176 ARM( str r3, [r0, #2048]! )
177 THUMB( add r0, r0, #2048 )
178 THUMB( str r3, [r0] )
179 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
180#endif
181 mov pc, lr
182ENDPROC(cpu_v7_set_pte_ext)
183
184 string cpu_v7_name, "ARMv7 Processor"
185 .align
186
187 /*
188 * Memory region attributes with SCTLR.TRE=1
189 *
190 * n = TEX[0],C,B
191 * TR = PRRR[2n+1:2n] - memory type
192 * IR = NMRR[2n+1:2n] - inner cacheable property
193 * OR = NMRR[2n+17:2n+16] - outer cacheable property
194 *
195 * n TR IR OR
196 * UNCACHED 000 00
197 * BUFFERABLE 001 10 00 00
198 * WRITETHROUGH 010 10 10 10
199 * WRITEBACK 011 10 11 11
200 * reserved 110
201 * WRITEALLOC 111 10 01 01
202 * DEV_SHARED 100 01
203 * DEV_NONSHARED 100 01
204 * DEV_WC 001 10
205 * DEV_CACHED 011 10
206 *
207 * Other attributes:
208 *
209 * DS0 = PRRR[16] = 0 - device shareable property
210 * DS1 = PRRR[17] = 1 - device shareable property
211 * NS0 = PRRR[18] = 0 - normal shareable property
212 * NS1 = PRRR[19] = 1 - normal shareable property
213 * NOS = PRRR[24+n] = 1 - not outer shareable
214 */
215.equ PRRR, 0xff0a81a8
216.equ NMRR, 0x40e040e0
217
218/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
219.globl cpu_v7_suspend_size
220.equ cpu_v7_suspend_size, 4 * 9
221#ifdef CONFIG_PM_SLEEP
222ENTRY(cpu_v7_do_suspend)
223 stmfd sp!, {r4 - r11, lr}
224 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
225 mrc p15, 0, r5, c13, c0, 1 @ Context ID
226 mrc p15, 0, r6, c13, c0, 3 @ User r/o thread ID
227 stmia r0!, {r4 - r6}
228 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
229 mrc p15, 0, r7, c2, c0, 0 @ TTB 0
230 mrc p15, 0, r8, c2, c0, 1 @ TTB 1
231 mrc p15, 0, r9, c1, c0, 0 @ Control register
232 mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
233 mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control
234 stmia r0, {r6 - r11}
235 ldmfd sp!, {r4 - r11, pc}
236ENDPROC(cpu_v7_do_suspend)
237
238ENTRY(cpu_v7_do_resume)
239 mov ip, #0
240 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
241 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
242 ldmia r0!, {r4 - r6}
243 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
244 mcr p15, 0, r5, c13, c0, 1 @ Context ID
245 mcr p15, 0, r6, c13, c0, 3 @ User r/o thread ID
246 ldmia r0, {r6 - r11}
247 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
248 mcr p15, 0, r7, c2, c0, 0 @ TTB 0
249 mcr p15, 0, r8, c2, c0, 1 @ TTB 1
250 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
251 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
252 teq r4, r10 @ Is it already set?
253 mcrne p15, 0, r10, c1, c0, 1 @ No, so write it
254 mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control
255 ldr r4, =PRRR @ PRRR
256 ldr r5, =NMRR @ NMRR
257 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
258 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
259 isb
260 dsb
261 mov r0, r9 @ control register
262 mov r2, r7, lsr #14 @ get TTB0 base
263 mov r2, r2, lsl #14
264 ldr r3, cpu_resume_l1_flags
265 b cpu_resume_mmu
266ENDPROC(cpu_v7_do_resume)
267cpu_resume_l1_flags:
268 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
269 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
270#endif
271
272 __CPUINIT
273
274/*
275 * __v7_setup
276 *
277 * Initialise TLB, Caches, and MMU state ready to switch the MMU
278 * on. Return in r0 the new CP15 C1 control register setting.
279 *
280 * We automatically detect if we have a Harvard cache, and use the
281 * Harvard cache control instructions insead of the unified cache
282 * control instructions.
283 *
284 * This should be able to cover all ARMv7 cores.
285 *
286 * It is assumed that:
287 * - cache type register is implemented
288 */
289__v7_ca5mp_setup:
290__v7_ca9mp_setup:
291 mov r10, #(1 << 0) @ TLB ops broadcasting
292 b 1f
293__v7_ca15mp_setup:
294 mov r10, #0
2951:
296#ifdef CONFIG_SMP
297 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
298 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
299 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
300 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
301 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
302 mcreq p15, 0, r0, c1, c0, 1
303#endif
304__v7_setup:
305 adr r12, __v7_setup_stack @ the local stack
306 stmia r12, {r0-r5, r7, r9, r11, lr}
307 bl v7_flush_dcache_all
308 ldmia r12, {r0-r5, r7, r9, r11, lr}
309
310 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
311 and r10, r0, #0xff000000 @ ARM?
312 teq r10, #0x41000000
313 bne 3f
314 and r5, r0, #0x00f00000 @ variant
315 and r6, r0, #0x0000000f @ revision
316 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
317 ubfx r0, r0, #4, #12 @ primary part number
318
319 /* Cortex-A8 Errata */
320 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
321 teq r0, r10
322 bne 2f
323#ifdef CONFIG_ARM_ERRATA_430973
324 teq r5, #0x00100000 @ only present in r1p*
325 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
326 orreq r10, r10, #(1 << 6) @ set IBE to 1
327 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
328#endif
329#ifdef CONFIG_ARM_ERRATA_458693
330 teq r6, #0x20 @ only present in r2p0
331 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
332 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
333 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
334 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
335#endif
336#ifdef CONFIG_ARM_ERRATA_460075
337 teq r6, #0x20 @ only present in r2p0
338 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
339 tsteq r10, #1 << 22
340 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
341 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
342#endif
343 b 3f
344
345 /* Cortex-A9 Errata */
3462: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
347 teq r0, r10
348 bne 3f
349#ifdef CONFIG_ARM_ERRATA_742230
350 cmp r6, #0x22 @ only present up to r2p2
351 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
352 orrle r10, r10, #1 << 4 @ set bit #4
353 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
354#endif
355#ifdef CONFIG_ARM_ERRATA_742231
356 teq r6, #0x20 @ present in r2p0
357 teqne r6, #0x21 @ present in r2p1
358 teqne r6, #0x22 @ present in r2p2
359 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
360 orreq r10, r10, #1 << 12 @ set bit #12
361 orreq r10, r10, #1 << 22 @ set bit #22
362 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
363#endif
364#ifdef CONFIG_ARM_ERRATA_743622
365 teq r6, #0x20 @ present in r2p0
366 teqne r6, #0x21 @ present in r2p1
367 teqne r6, #0x22 @ present in r2p2
368 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
369 orreq r10, r10, #1 << 6 @ set bit #6
370 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
371#endif
372#ifdef CONFIG_ARM_ERRATA_751472
373 cmp r6, #0x30 @ present prior to r3p0
374 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
375 orrlt r10, r10, #1 << 11 @ set bit #11
376 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
377#endif
378
3793: mov r10, #0
380#ifdef HARVARD_CACHE
381 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
382#endif
383 dsb
384#ifdef CONFIG_MMU
385 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
386 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
387 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
388 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
389 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
390 ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
391 mcr p15, 0, r8, c2, c0, 1 @ load TTB1
392 ldr r5, =PRRR @ PRRR
393 ldr r6, =NMRR @ NMRR
394 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
395 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
396#endif
397 adr r5, v7_crval
398 ldmia r5, {r5, r6}
399#ifdef CONFIG_CPU_ENDIAN_BE8
400 orr r6, r6, #1 << 25 @ big-endian page tables
401#endif
402#ifdef CONFIG_SWP_EMULATE
403 orr r5, r5, #(1 << 10) @ set SW bit in "clear"
404 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
405#endif
406 mrc p15, 0, r0, c1, c0, 0 @ read control register
407 bic r0, r0, r5 @ clear bits them
408 orr r0, r0, r6 @ set them
409 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
410 mov pc, lr @ return to head.S:__ret
411ENDPROC(__v7_setup)
412
413 /* AT
414 * TFR EV X F I D LR S
415 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
416 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
417 * 1 0 110 0011 1100 .111 1101 < we want
418 */
419 .type v7_crval, #object
420v7_crval:
421 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
422
423__v7_setup_stack:
424 .space 4 * 11 @ 11 registers
425
426 __INITDATA
427
428 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
429 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
430
431 .section ".rodata"
432
433 string cpu_arch_name, "armv7"
434 string cpu_elf_name, "v7"
435 .align
436
437 .section ".proc.info.init", #alloc, #execinstr
438
439 /*
440 * Standard v7 proc info content
441 */
442.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
443 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
444 PMD_FLAGS_SMP | \mm_mmuflags)
445 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
446 PMD_FLAGS_UP | \mm_mmuflags)
447 .long PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | \
448 PMD_SECT_AP_READ | \io_mmuflags
449 W(b) \initfunc
450 .long cpu_arch_name
451 .long cpu_elf_name
452 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
453 HWCAP_EDSP | HWCAP_TLS | \hwcaps
454 .long cpu_v7_name
455 .long v7_processor_functions
456 .long v7wbi_tlb_fns
457 .long v6_user_fns
458 .long v7_cache_fns
459.endm
460
461 /*
462 * ARM Ltd. Cortex A5 processor.
463 */
464 .type __v7_ca5mp_proc_info, #object
465__v7_ca5mp_proc_info:
466 .long 0x410fc050
467 .long 0xff0ffff0
468 __v7_proc __v7_ca5mp_setup
469 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
470
471 /*
472 * ARM Ltd. Cortex A9 processor.
473 */
474 .type __v7_ca9mp_proc_info, #object
475__v7_ca9mp_proc_info:
476 .long 0x410fc090
477 .long 0xff0ffff0
478 __v7_proc __v7_ca9mp_setup
479 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
480
481 /*
482 * ARM Ltd. Cortex A15 processor.
483 */
484 .type __v7_ca15mp_proc_info, #object
485__v7_ca15mp_proc_info:
486 .long 0x410fc0f0
487 .long 0xff0ffff0
488 __v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
489 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
490
491 /*
492 * Match any ARMv7 processor core.
493 */
494 .type __v7_proc_info, #object
495__v7_proc_info:
496 .long 0x000f0000 @ Required ID value
497 .long 0x000f0000 @ Mask for ID
498 __v7_proc __v7_setup
499 .size __v7_proc_info, . - __v7_proc_info
1/*
2 * linux/arch/arm/mm/proc-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is the "shell" of the ARMv7 processor support.
11 */
12#include <linux/init.h>
13#include <linux/linkage.h>
14#include <asm/assembler.h>
15#include <asm/asm-offsets.h>
16#include <asm/hwcap.h>
17#include <asm/pgtable-hwdef.h>
18#include <asm/pgtable.h>
19#include <asm/memory.h>
20
21#include "proc-macros.S"
22
23#ifdef CONFIG_ARM_LPAE
24#include "proc-v7-3level.S"
25#else
26#include "proc-v7-2level.S"
27#endif
28
29ENTRY(cpu_v7_proc_init)
30 ret lr
31ENDPROC(cpu_v7_proc_init)
32
33ENTRY(cpu_v7_proc_fin)
34 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
35 bic r0, r0, #0x1000 @ ...i............
36 bic r0, r0, #0x0006 @ .............ca.
37 mcr p15, 0, r0, c1, c0, 0 @ disable caches
38 ret lr
39ENDPROC(cpu_v7_proc_fin)
40
41/*
42 * cpu_v7_reset(loc, hyp)
43 *
44 * Perform a soft reset of the system. Put the CPU into the
45 * same state as it would be if it had been reset, and branch
46 * to what would be the reset vector.
47 *
48 * - loc - location to jump to for soft reset
49 * - hyp - indicate if restart occurs in HYP mode
50 *
51 * This code must be executed using a flat identity mapping with
52 * caches disabled.
53 */
54 .align 5
55 .pushsection .idmap.text, "ax"
56ENTRY(cpu_v7_reset)
57 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
58 bic r2, r2, #0x1 @ ...............m
59 THUMB( bic r2, r2, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
60 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
61 isb
62#ifdef CONFIG_ARM_VIRT_EXT
63 teq r1, #0
64 bne __hyp_soft_restart
65#endif
66 bx r0
67ENDPROC(cpu_v7_reset)
68 .popsection
69
70/*
71 * cpu_v7_do_idle()
72 *
73 * Idle the processor (eg, wait for interrupt).
74 *
75 * IRQs are already disabled.
76 */
77ENTRY(cpu_v7_do_idle)
78 dsb @ WFI may enter a low-power mode
79 wfi
80 ret lr
81ENDPROC(cpu_v7_do_idle)
82
83ENTRY(cpu_v7_dcache_clean_area)
84 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
85 ALT_UP_B(1f)
86 ret lr
871: dcache_line_size r2, r3
882: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
89 add r0, r0, r2
90 subs r1, r1, r2
91 bhi 2b
92 dsb ishst
93 ret lr
94ENDPROC(cpu_v7_dcache_clean_area)
95
96 string cpu_v7_name, "ARMv7 Processor"
97 .align
98
99/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
100.globl cpu_v7_suspend_size
101.equ cpu_v7_suspend_size, 4 * 9
102#ifdef CONFIG_ARM_CPU_SUSPEND
103ENTRY(cpu_v7_do_suspend)
104 stmfd sp!, {r4 - r11, lr}
105 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
106 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
107 stmia r0!, {r4 - r5}
108#ifdef CONFIG_MMU
109 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
110#ifdef CONFIG_ARM_LPAE
111 mrrc p15, 1, r5, r7, c2 @ TTB 1
112#else
113 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
114#endif
115 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
116#endif
117 mrc p15, 0, r8, c1, c0, 0 @ Control register
118 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
119 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
120 stmia r0, {r5 - r11}
121 ldmfd sp!, {r4 - r11, pc}
122ENDPROC(cpu_v7_do_suspend)
123
124ENTRY(cpu_v7_do_resume)
125 mov ip, #0
126 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
127 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
128 ldmia r0!, {r4 - r5}
129 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
130 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
131 ldmia r0, {r5 - r11}
132#ifdef CONFIG_MMU
133 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
134 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
135#ifdef CONFIG_ARM_LPAE
136 mcrr p15, 0, r1, ip, c2 @ TTB 0
137 mcrr p15, 1, r5, r7, c2 @ TTB 1
138#else
139 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
140 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
141 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
142 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
143#endif
144 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
145 ldr r4, =PRRR @ PRRR
146 ldr r5, =NMRR @ NMRR
147 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
148 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
149#endif /* CONFIG_MMU */
150 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
151 teq r4, r9 @ Is it already set?
152 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
153 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
154 isb
155 dsb
156 mov r0, r8 @ control register
157 b cpu_resume_mmu
158ENDPROC(cpu_v7_do_resume)
159#endif
160
161/*
162 * Cortex-A8
163 */
164 globl_equ cpu_ca8_proc_init, cpu_v7_proc_init
165 globl_equ cpu_ca8_proc_fin, cpu_v7_proc_fin
166 globl_equ cpu_ca8_reset, cpu_v7_reset
167 globl_equ cpu_ca8_do_idle, cpu_v7_do_idle
168 globl_equ cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area
169 globl_equ cpu_ca8_set_pte_ext, cpu_v7_set_pte_ext
170 globl_equ cpu_ca8_suspend_size, cpu_v7_suspend_size
171#ifdef CONFIG_ARM_CPU_SUSPEND
172 globl_equ cpu_ca8_do_suspend, cpu_v7_do_suspend
173 globl_equ cpu_ca8_do_resume, cpu_v7_do_resume
174#endif
175
176/*
177 * Cortex-A9 processor functions
178 */
179 globl_equ cpu_ca9mp_proc_init, cpu_v7_proc_init
180 globl_equ cpu_ca9mp_proc_fin, cpu_v7_proc_fin
181 globl_equ cpu_ca9mp_reset, cpu_v7_reset
182 globl_equ cpu_ca9mp_do_idle, cpu_v7_do_idle
183 globl_equ cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area
184 globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm
185 globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext
186.globl cpu_ca9mp_suspend_size
187.equ cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
188#ifdef CONFIG_ARM_CPU_SUSPEND
189ENTRY(cpu_ca9mp_do_suspend)
190 stmfd sp!, {r4 - r5}
191 mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register
192 mrc p15, 0, r5, c15, c0, 0 @ Power register
193 stmia r0!, {r4 - r5}
194 ldmfd sp!, {r4 - r5}
195 b cpu_v7_do_suspend
196ENDPROC(cpu_ca9mp_do_suspend)
197
198ENTRY(cpu_ca9mp_do_resume)
199 ldmia r0!, {r4 - r5}
200 mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register
201 teq r4, r10 @ Already restored?
202 mcrne p15, 0, r4, c15, c0, 1 @ No, so restore it
203 mrc p15, 0, r10, c15, c0, 0 @ Read Power register
204 teq r5, r10 @ Already restored?
205 mcrne p15, 0, r5, c15, c0, 0 @ No, so restore it
206 b cpu_v7_do_resume
207ENDPROC(cpu_ca9mp_do_resume)
208#endif
209
210#ifdef CONFIG_CPU_PJ4B
211 globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
212 globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
213 globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init
214 globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin
215 globl_equ cpu_pj4b_reset, cpu_v7_reset
216#ifdef CONFIG_PJ4B_ERRATA_4742
217ENTRY(cpu_pj4b_do_idle)
218 dsb @ WFI may enter a low-power mode
219 wfi
220 dsb @barrier
221 ret lr
222ENDPROC(cpu_pj4b_do_idle)
223#else
224 globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
225#endif
226 globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
227#ifdef CONFIG_ARM_CPU_SUSPEND
228ENTRY(cpu_pj4b_do_suspend)
229 stmfd sp!, {r6 - r10}
230 mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features
231 mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0
232 mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
233 mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1
234 mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC
235 stmia r0!, {r6 - r10}
236 ldmfd sp!, {r6 - r10}
237 b cpu_v7_do_suspend
238ENDPROC(cpu_pj4b_do_suspend)
239
240ENTRY(cpu_pj4b_do_resume)
241 ldmia r0!, {r6 - r10}
242 mcr p15, 1, r6, c15, c1, 0 @ restore CP15 - extra features
243 mcr p15, 1, r7, c15, c2, 0 @ restore CP15 - Aux Func Modes Ctrl 0
244 mcr p15, 1, r8, c15, c1, 2 @ restore CP15 - Aux Debug Modes Ctrl 2
245 mcr p15, 1, r9, c15, c1, 1 @ restore CP15 - Aux Debug Modes Ctrl 1
246 mcr p15, 0, r10, c9, c14, 0 @ restore CP15 - PMC
247 b cpu_v7_do_resume
248ENDPROC(cpu_pj4b_do_resume)
249#endif
250.globl cpu_pj4b_suspend_size
251.equ cpu_pj4b_suspend_size, cpu_v7_suspend_size + 4 * 5
252
253#endif
254
255/*
256 * __v7_setup
257 *
258 * Initialise TLB, Caches, and MMU state ready to switch the MMU
259 * on. Return in r0 the new CP15 C1 control register setting.
260 *
261 * r1, r2, r4, r5, r9, r13 must be preserved - r13 is not a stack
262 * r4: TTBR0 (low word)
263 * r5: TTBR0 (high word if LPAE)
264 * r8: TTBR1
265 * r9: Main ID register
266 *
267 * This should be able to cover all ARMv7 cores.
268 *
269 * It is assumed that:
270 * - cache type register is implemented
271 */
272__v7_ca5mp_setup:
273__v7_ca9mp_setup:
274__v7_cr7mp_setup:
275__v7_cr8mp_setup:
276 mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
277 b 1f
278__v7_ca7mp_setup:
279__v7_ca12mp_setup:
280__v7_ca15mp_setup:
281__v7_b15mp_setup:
282__v7_ca17mp_setup:
283 mov r10, #0
2841: adr r0, __v7_setup_stack_ptr
285 ldr r12, [r0]
286 add r12, r12, r0 @ the local stack
287 stmia r12, {r1-r6, lr} @ v7_invalidate_l1 touches r0-r6
288 bl v7_invalidate_l1
289 ldmia r12, {r1-r6, lr}
290#ifdef CONFIG_SMP
291 orr r10, r10, #(1 << 6) @ Enable SMP/nAMP mode
292 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
293 ALT_UP(mov r0, r10) @ fake it for UP
294 orr r10, r10, r0 @ Set required bits
295 teq r10, r0 @ Were they already set?
296 mcrne p15, 0, r10, c1, c0, 1 @ No, update register
297#endif
298 b __v7_setup_cont
299
300/*
301 * Errata:
302 * r0, r10 available for use
303 * r1, r2, r4, r5, r9, r13: must be preserved
304 * r3: contains MIDR rX number in bits 23-20
305 * r6: contains MIDR rXpY as 8-bit XY number
306 * r9: MIDR
307 */
308__ca8_errata:
309#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
310 teq r3, #0x00100000 @ only present in r1p*
311 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
312 orreq r0, r0, #(1 << 6) @ set IBE to 1
313 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
314#endif
315#ifdef CONFIG_ARM_ERRATA_458693
316 teq r6, #0x20 @ only present in r2p0
317 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
318 orreq r0, r0, #(1 << 5) @ set L1NEON to 1
319 orreq r0, r0, #(1 << 9) @ set PLDNOP to 1
320 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
321#endif
322#ifdef CONFIG_ARM_ERRATA_460075
323 teq r6, #0x20 @ only present in r2p0
324 mrceq p15, 1, r0, c9, c0, 2 @ read L2 cache aux ctrl register
325 tsteq r0, #1 << 22
326 orreq r0, r0, #(1 << 22) @ set the Write Allocate disable bit
327 mcreq p15, 1, r0, c9, c0, 2 @ write the L2 cache aux ctrl register
328#endif
329 b __errata_finish
330
331__ca9_errata:
332#ifdef CONFIG_ARM_ERRATA_742230
333 cmp r6, #0x22 @ only present up to r2p2
334 mrcle p15, 0, r0, c15, c0, 1 @ read diagnostic register
335 orrle r0, r0, #1 << 4 @ set bit #4
336 mcrle p15, 0, r0, c15, c0, 1 @ write diagnostic register
337#endif
338#ifdef CONFIG_ARM_ERRATA_742231
339 teq r6, #0x20 @ present in r2p0
340 teqne r6, #0x21 @ present in r2p1
341 teqne r6, #0x22 @ present in r2p2
342 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
343 orreq r0, r0, #1 << 12 @ set bit #12
344 orreq r0, r0, #1 << 22 @ set bit #22
345 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
346#endif
347#ifdef CONFIG_ARM_ERRATA_743622
348 teq r3, #0x00200000 @ only present in r2p*
349 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
350 orreq r0, r0, #1 << 6 @ set bit #6
351 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
352#endif
353#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
354 ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
355 ALT_UP_B(1f)
356 mrclt p15, 0, r0, c15, c0, 1 @ read diagnostic register
357 orrlt r0, r0, #1 << 11 @ set bit #11
358 mcrlt p15, 0, r0, c15, c0, 1 @ write diagnostic register
3591:
360#endif
361 b __errata_finish
362
363__ca15_errata:
364#ifdef CONFIG_ARM_ERRATA_773022
365 cmp r6, #0x4 @ only present up to r0p4
366 mrcle p15, 0, r0, c1, c0, 1 @ read aux control register
367 orrle r0, r0, #1 << 1 @ disable loop buffer
368 mcrle p15, 0, r0, c1, c0, 1 @ write aux control register
369#endif
370 b __errata_finish
371
372__ca12_errata:
373#ifdef CONFIG_ARM_ERRATA_818325_852422
374 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
375 orr r10, r10, #1 << 12 @ set bit #12
376 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
377#endif
378#ifdef CONFIG_ARM_ERRATA_821420
379 mrc p15, 0, r10, c15, c0, 2 @ read internal feature reg
380 orr r10, r10, #1 << 1 @ set bit #1
381 mcr p15, 0, r10, c15, c0, 2 @ write internal feature reg
382#endif
383#ifdef CONFIG_ARM_ERRATA_825619
384 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
385 orr r10, r10, #1 << 24 @ set bit #24
386 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
387#endif
388 b __errata_finish
389
390__ca17_errata:
391#ifdef CONFIG_ARM_ERRATA_852421
392 cmp r6, #0x12 @ only present up to r1p2
393 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
394 orrle r10, r10, #1 << 24 @ set bit #24
395 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
396#endif
397#ifdef CONFIG_ARM_ERRATA_852423
398 cmp r6, #0x12 @ only present up to r1p2
399 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
400 orrle r10, r10, #1 << 12 @ set bit #12
401 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
402#endif
403 b __errata_finish
404
405__v7_pj4b_setup:
406#ifdef CONFIG_CPU_PJ4B
407
408/* Auxiliary Debug Modes Control 1 Register */
409#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
410#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
411#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
412
413/* Auxiliary Debug Modes Control 2 Register */
414#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
415#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
416#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
417#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
418#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
419#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
420 PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
421
422/* Auxiliary Functional Modes Control Register 0 */
423#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
424#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
425#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
426
427/* Auxiliary Debug Modes Control 0 Register */
428#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
429
430 /* Auxiliary Debug Modes Control 1 Register */
431 mrc p15, 1, r0, c15, c1, 1
432 orr r0, r0, #PJ4B_CLEAN_LINE
433 orr r0, r0, #PJ4B_INTER_PARITY
434 bic r0, r0, #PJ4B_STATIC_BP
435 mcr p15, 1, r0, c15, c1, 1
436
437 /* Auxiliary Debug Modes Control 2 Register */
438 mrc p15, 1, r0, c15, c1, 2
439 bic r0, r0, #PJ4B_FAST_LDR
440 orr r0, r0, #PJ4B_AUX_DBG_CTRL2
441 mcr p15, 1, r0, c15, c1, 2
442
443 /* Auxiliary Functional Modes Control Register 0 */
444 mrc p15, 1, r0, c15, c2, 0
445#ifdef CONFIG_SMP
446 orr r0, r0, #PJ4B_SMP_CFB
447#endif
448 orr r0, r0, #PJ4B_L1_PAR_CHK
449 orr r0, r0, #PJ4B_BROADCAST_CACHE
450 mcr p15, 1, r0, c15, c2, 0
451
452 /* Auxiliary Debug Modes Control 0 Register */
453 mrc p15, 1, r0, c15, c1, 0
454 orr r0, r0, #PJ4B_WFI_WFE
455 mcr p15, 1, r0, c15, c1, 0
456
457#endif /* CONFIG_CPU_PJ4B */
458
459__v7_setup:
460 adr r0, __v7_setup_stack_ptr
461 ldr r12, [r0]
462 add r12, r12, r0 @ the local stack
463 stmia r12, {r1-r6, lr} @ v7_invalidate_l1 touches r0-r6
464 bl v7_invalidate_l1
465 ldmia r12, {r1-r6, lr}
466
467__v7_setup_cont:
468 and r0, r9, #0xff000000 @ ARM?
469 teq r0, #0x41000000
470 bne __errata_finish
471 and r3, r9, #0x00f00000 @ variant
472 and r6, r9, #0x0000000f @ revision
473 orr r6, r6, r3, lsr #20-4 @ combine variant and revision
474 ubfx r0, r9, #4, #12 @ primary part number
475
476 /* Cortex-A8 Errata */
477 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
478 teq r0, r10
479 beq __ca8_errata
480
481 /* Cortex-A9 Errata */
482 ldr r10, =0x00000c09 @ Cortex-A9 primary part number
483 teq r0, r10
484 beq __ca9_errata
485
486 /* Cortex-A12 Errata */
487 ldr r10, =0x00000c0d @ Cortex-A12 primary part number
488 teq r0, r10
489 beq __ca12_errata
490
491 /* Cortex-A17 Errata */
492 ldr r10, =0x00000c0e @ Cortex-A17 primary part number
493 teq r0, r10
494 beq __ca17_errata
495
496 /* Cortex-A15 Errata */
497 ldr r10, =0x00000c0f @ Cortex-A15 primary part number
498 teq r0, r10
499 beq __ca15_errata
500
501__errata_finish:
502 mov r10, #0
503 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
504#ifdef CONFIG_MMU
505 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
506 v7_ttb_setup r10, r4, r5, r8, r3 @ TTBCR, TTBRx setup
507 ldr r3, =PRRR @ PRRR
508 ldr r6, =NMRR @ NMRR
509 mcr p15, 0, r3, c10, c2, 0 @ write PRRR
510 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
511#endif
512 dsb @ Complete invalidations
513#ifndef CONFIG_ARM_THUMBEE
514 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
515 and r0, r0, #(0xf << 12) @ ThumbEE enabled field
516 teq r0, #(1 << 12) @ check if ThumbEE is present
517 bne 1f
518 mov r3, #0
519 mcr p14, 6, r3, c1, c0, 0 @ Initialize TEEHBR to 0
520 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
521 orr r0, r0, #1 @ set the 1st bit in order to
522 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
5231:
524#endif
525 adr r3, v7_crval
526 ldmia r3, {r3, r6}
527 ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
528#ifdef CONFIG_SWP_EMULATE
529 orr r3, r3, #(1 << 10) @ set SW bit in "clear"
530 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
531#endif
532 mrc p15, 0, r0, c1, c0, 0 @ read control register
533 bic r0, r0, r3 @ clear bits them
534 orr r0, r0, r6 @ set them
535 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
536 ret lr @ return to head.S:__ret
537
538 .align 2
539__v7_setup_stack_ptr:
540 .word PHYS_RELATIVE(__v7_setup_stack, .)
541ENDPROC(__v7_setup)
542
543 .bss
544 .align 2
545__v7_setup_stack:
546 .space 4 * 7 @ 7 registers
547
548 __INITDATA
549
550 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
551 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
552#ifndef CONFIG_ARM_LPAE
553 define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
554 define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
555#endif
556#ifdef CONFIG_CPU_PJ4B
557 define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
558#endif
559
560 .section ".rodata"
561
562 string cpu_arch_name, "armv7"
563 string cpu_elf_name, "v7"
564 .align
565
566 .section ".proc.info.init", #alloc
567
568 /*
569 * Standard v7 proc info content
570 */
571.macro __v7_proc name, initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions, cache_fns = v7_cache_fns
572 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
573 PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
574 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
575 PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
576 .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
577 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
578 initfn \initfunc, \name
579 .long cpu_arch_name
580 .long cpu_elf_name
581 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
582 HWCAP_EDSP | HWCAP_TLS | \hwcaps
583 .long cpu_v7_name
584 .long \proc_fns
585 .long v7wbi_tlb_fns
586 .long v6_user_fns
587 .long \cache_fns
588.endm
589
590#ifndef CONFIG_ARM_LPAE
591 /*
592 * ARM Ltd. Cortex A5 processor.
593 */
594 .type __v7_ca5mp_proc_info, #object
595__v7_ca5mp_proc_info:
596 .long 0x410fc050
597 .long 0xff0ffff0
598 __v7_proc __v7_ca5mp_proc_info, __v7_ca5mp_setup
599 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
600
601 /*
602 * ARM Ltd. Cortex A9 processor.
603 */
604 .type __v7_ca9mp_proc_info, #object
605__v7_ca9mp_proc_info:
606 .long 0x410fc090
607 .long 0xff0ffff0
608 __v7_proc __v7_ca9mp_proc_info, __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions
609 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
610
611 /*
612 * ARM Ltd. Cortex A8 processor.
613 */
614 .type __v7_ca8_proc_info, #object
615__v7_ca8_proc_info:
616 .long 0x410fc080
617 .long 0xff0ffff0
618 __v7_proc __v7_ca8_proc_info, __v7_setup, proc_fns = ca8_processor_functions
619 .size __v7_ca8_proc_info, . - __v7_ca8_proc_info
620
621#endif /* CONFIG_ARM_LPAE */
622
623 /*
624 * Marvell PJ4B processor.
625 */
626#ifdef CONFIG_CPU_PJ4B
627 .type __v7_pj4b_proc_info, #object
628__v7_pj4b_proc_info:
629 .long 0x560f5800
630 .long 0xff0fff00
631 __v7_proc __v7_pj4b_proc_info, __v7_pj4b_setup, proc_fns = pj4b_processor_functions
632 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
633#endif
634
635 /*
636 * ARM Ltd. Cortex R7 processor.
637 */
638 .type __v7_cr7mp_proc_info, #object
639__v7_cr7mp_proc_info:
640 .long 0x410fc170
641 .long 0xff0ffff0
642 __v7_proc __v7_cr7mp_proc_info, __v7_cr7mp_setup
643 .size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
644
645 /*
646 * ARM Ltd. Cortex R8 processor.
647 */
648 .type __v7_cr8mp_proc_info, #object
649__v7_cr8mp_proc_info:
650 .long 0x410fc180
651 .long 0xff0ffff0
652 __v7_proc __v7_cr8mp_proc_info, __v7_cr8mp_setup
653 .size __v7_cr8mp_proc_info, . - __v7_cr8mp_proc_info
654
655 /*
656 * ARM Ltd. Cortex A7 processor.
657 */
658 .type __v7_ca7mp_proc_info, #object
659__v7_ca7mp_proc_info:
660 .long 0x410fc070
661 .long 0xff0ffff0
662 __v7_proc __v7_ca7mp_proc_info, __v7_ca7mp_setup
663 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
664
665 /*
666 * ARM Ltd. Cortex A12 processor.
667 */
668 .type __v7_ca12mp_proc_info, #object
669__v7_ca12mp_proc_info:
670 .long 0x410fc0d0
671 .long 0xff0ffff0
672 __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup
673 .size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
674
675 /*
676 * ARM Ltd. Cortex A15 processor.
677 */
678 .type __v7_ca15mp_proc_info, #object
679__v7_ca15mp_proc_info:
680 .long 0x410fc0f0
681 .long 0xff0ffff0
682 __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup
683 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
684
685 /*
686 * Broadcom Corporation Brahma-B15 processor.
687 */
688 .type __v7_b15mp_proc_info, #object
689__v7_b15mp_proc_info:
690 .long 0x420f00f0
691 .long 0xff0ffff0
692 __v7_proc __v7_b15mp_proc_info, __v7_b15mp_setup, cache_fns = b15_cache_fns
693 .size __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
694
695 /*
696 * ARM Ltd. Cortex A17 processor.
697 */
698 .type __v7_ca17mp_proc_info, #object
699__v7_ca17mp_proc_info:
700 .long 0x410fc0e0
701 .long 0xff0ffff0
702 __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup
703 .size __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
704
705 /*
706 * Qualcomm Inc. Krait processors.
707 */
708 .type __krait_proc_info, #object
709__krait_proc_info:
710 .long 0x510f0400 @ Required ID value
711 .long 0xff0ffc00 @ Mask for ID
712 /*
713 * Some Krait processors don't indicate support for SDIV and UDIV
714 * instructions in the ARM instruction set, even though they actually
715 * do support them. They also don't indicate support for fused multiply
716 * instructions even though they actually do support them.
717 */
718 __v7_proc __krait_proc_info, __v7_setup, hwcaps = HWCAP_IDIV | HWCAP_VFPv4
719 .size __krait_proc_info, . - __krait_proc_info
720
721 /*
722 * Match any ARMv7 processor core.
723 */
724 .type __v7_proc_info, #object
725__v7_proc_info:
726 .long 0x000f0000 @ Required ID value
727 .long 0x000f0000 @ Mask for ID
728 __v7_proc __v7_proc_info, __v7_setup
729 .size __v7_proc_info, . - __v7_proc_info