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1/*
2 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver
3 *
4 * Copyright (C) 2012-2014 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
7 * Based on max3110.c, by Feng Tang <feng.tang@intel.com>
8 * Based on max3107.c, by Aavamobile
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#include <linux/bitops.h>
17#include <linux/clk.h>
18#include <linux/delay.h>
19#include <linux/device.h>
20#include <linux/gpio.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/regmap.h>
25#include <linux/serial_core.h>
26#include <linux/serial.h>
27#include <linux/tty.h>
28#include <linux/tty_flip.h>
29#include <linux/spi/spi.h>
30#include <linux/uaccess.h>
31
32#define MAX310X_NAME "max310x"
33#define MAX310X_MAJOR 204
34#define MAX310X_MINOR 209
35
36/* MAX310X register definitions */
37#define MAX310X_RHR_REG (0x00) /* RX FIFO */
38#define MAX310X_THR_REG (0x00) /* TX FIFO */
39#define MAX310X_IRQEN_REG (0x01) /* IRQ enable */
40#define MAX310X_IRQSTS_REG (0x02) /* IRQ status */
41#define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */
42#define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */
43#define MAX310X_REG_05 (0x05)
44#define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */
45#define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */
46#define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */
47#define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */
48#define MAX310X_MODE1_REG (0x09) /* MODE1 */
49#define MAX310X_MODE2_REG (0x0a) /* MODE2 */
50#define MAX310X_LCR_REG (0x0b) /* LCR */
51#define MAX310X_RXTO_REG (0x0c) /* RX timeout */
52#define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
53#define MAX310X_IRDA_REG (0x0e) /* IRDA settings */
54#define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */
55#define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */
56#define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */
57#define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */
58#define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */
59#define MAX310X_XON1_REG (0x14) /* XON1 character */
60#define MAX310X_XON2_REG (0x15) /* XON2 character */
61#define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */
62#define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */
63#define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */
64#define MAX310X_GPIODATA_REG (0x19) /* GPIO data */
65#define MAX310X_PLLCFG_REG (0x1a) /* PLL config */
66#define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
67#define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
68#define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
69#define MAX310X_CLKSRC_REG (0x1e) /* Clock source */
70#define MAX310X_REG_1F (0x1f)
71
72#define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */
73
74#define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */
75#define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */
76
77/* Extended registers */
78#define MAX310X_REVID_EXTREG MAX310X_REG_05 /* Revision ID */
79
80/* IRQ register bits */
81#define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
82#define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
83#define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */
84#define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
85#define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
86#define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
87#define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
88#define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
89
90/* LSR register bits */
91#define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */
92#define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
93#define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
94#define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */
95#define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */
96#define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
97#define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */
98
99/* Special character register bits */
100#define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
101#define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
102#define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
103#define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
104#define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */
105#define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
106
107/* Status register bits */
108#define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
109#define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
110#define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
111#define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
112#define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
113#define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
114
115/* MODE1 register bits */
116#define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
117#define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
118#define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
119#define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
120#define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
121#define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
122#define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
123#define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
124
125/* MODE2 register bits */
126#define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */
127#define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
128#define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
129#define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
130#define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
131#define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
132#define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
133#define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
134
135/* LCR register bits */
136#define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
137#define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
138 *
139 * Word length bits table:
140 * 00 -> 5 bit words
141 * 01 -> 6 bit words
142 * 10 -> 7 bit words
143 * 11 -> 8 bit words
144 */
145#define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
146 *
147 * STOP length bit table:
148 * 0 -> 1 stop bit
149 * 1 -> 1-1.5 stop bits if
150 * word length is 5,
151 * 2 stop bits otherwise
152 */
153#define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
154#define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
155#define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
156#define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
157#define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */
158#define MAX310X_LCR_WORD_LEN_5 (0x00)
159#define MAX310X_LCR_WORD_LEN_6 (0x01)
160#define MAX310X_LCR_WORD_LEN_7 (0x02)
161#define MAX310X_LCR_WORD_LEN_8 (0x03)
162
163/* IRDA register bits */
164#define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
165#define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
166
167/* Flow control trigger level register masks */
168#define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
169#define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
170#define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
171#define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)
172
173/* FIFO interrupt trigger level register masks */
174#define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */
175#define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */
176#define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f)
177#define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4)
178
179/* Flow control register bits */
180#define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
181#define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
182#define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
183 * are used in conjunction with
184 * XOFF2 for definition of
185 * special character */
186#define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
187#define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
188#define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
189 *
190 * SWFLOW bits 1 & 0 table:
191 * 00 -> no transmitter flow
192 * control
193 * 01 -> receiver compares
194 * XON2 and XOFF2
195 * and controls
196 * transmitter
197 * 10 -> receiver compares
198 * XON1 and XOFF1
199 * and controls
200 * transmitter
201 * 11 -> receiver compares
202 * XON1, XON2, XOFF1 and
203 * XOFF2 and controls
204 * transmitter
205 */
206#define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
207#define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
208 *
209 * SWFLOW bits 3 & 2 table:
210 * 00 -> no received flow
211 * control
212 * 01 -> transmitter generates
213 * XON2 and XOFF2
214 * 10 -> transmitter generates
215 * XON1 and XOFF1
216 * 11 -> transmitter generates
217 * XON1, XON2, XOFF1 and
218 * XOFF2
219 */
220
221/* PLL configuration register masks */
222#define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */
223#define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */
224
225/* Baud rate generator configuration register bits */
226#define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
227#define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
228
229/* Clock source register bits */
230#define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
231#define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
232#define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
233#define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
234#define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
235
236/* Global commands */
237#define MAX310X_EXTREG_ENBL (0xce)
238#define MAX310X_EXTREG_DSBL (0xcd)
239
240/* Misc definitions */
241#define MAX310X_FIFO_SIZE (128)
242#define MAX310x_REV_MASK (0xfc)
243
244/* MAX3107 specific */
245#define MAX3107_REV_ID (0xa0)
246
247/* MAX3109 specific */
248#define MAX3109_REV_ID (0xc0)
249
250/* MAX14830 specific */
251#define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */
252#define MAX14830_REV_ID (0xb0)
253
254struct max310x_devtype {
255 char name[9];
256 int nr;
257 int (*detect)(struct device *);
258 void (*power)(struct uart_port *, int);
259};
260
261struct max310x_one {
262 struct uart_port port;
263 struct work_struct tx_work;
264 struct work_struct md_work;
265};
266
267struct max310x_port {
268 struct uart_driver uart;
269 struct max310x_devtype *devtype;
270 struct regmap *regmap;
271 struct mutex mutex;
272 struct clk *clk;
273#ifdef CONFIG_GPIOLIB
274 struct gpio_chip gpio;
275#endif
276 struct max310x_one p[0];
277};
278
279static u8 max310x_port_read(struct uart_port *port, u8 reg)
280{
281 struct max310x_port *s = dev_get_drvdata(port->dev);
282 unsigned int val = 0;
283
284 regmap_read(s->regmap, port->iobase + reg, &val);
285
286 return val;
287}
288
289static void max310x_port_write(struct uart_port *port, u8 reg, u8 val)
290{
291 struct max310x_port *s = dev_get_drvdata(port->dev);
292
293 regmap_write(s->regmap, port->iobase + reg, val);
294}
295
296static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val)
297{
298 struct max310x_port *s = dev_get_drvdata(port->dev);
299
300 regmap_update_bits(s->regmap, port->iobase + reg, mask, val);
301}
302
303static int max3107_detect(struct device *dev)
304{
305 struct max310x_port *s = dev_get_drvdata(dev);
306 unsigned int val = 0;
307 int ret;
308
309 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val);
310 if (ret)
311 return ret;
312
313 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) {
314 dev_err(dev,
315 "%s ID 0x%02x does not match\n", s->devtype->name, val);
316 return -ENODEV;
317 }
318
319 return 0;
320}
321
322static int max3108_detect(struct device *dev)
323{
324 struct max310x_port *s = dev_get_drvdata(dev);
325 unsigned int val = 0;
326 int ret;
327
328 /* MAX3108 have not REV ID register, we just check default value
329 * from clocksource register to make sure everything works.
330 */
331 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
332 if (ret)
333 return ret;
334
335 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) {
336 dev_err(dev, "%s not present\n", s->devtype->name);
337 return -ENODEV;
338 }
339
340 return 0;
341}
342
343static int max3109_detect(struct device *dev)
344{
345 struct max310x_port *s = dev_get_drvdata(dev);
346 unsigned int val = 0;
347 int ret;
348
349 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
350 MAX310X_EXTREG_ENBL);
351 if (ret)
352 return ret;
353
354 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
355 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
356 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) {
357 dev_err(dev,
358 "%s ID 0x%02x does not match\n", s->devtype->name, val);
359 return -ENODEV;
360 }
361
362 return 0;
363}
364
365static void max310x_power(struct uart_port *port, int on)
366{
367 max310x_port_update(port, MAX310X_MODE1_REG,
368 MAX310X_MODE1_FORCESLEEP_BIT,
369 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT);
370 if (on)
371 msleep(50);
372}
373
374static int max14830_detect(struct device *dev)
375{
376 struct max310x_port *s = dev_get_drvdata(dev);
377 unsigned int val = 0;
378 int ret;
379
380 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
381 MAX310X_EXTREG_ENBL);
382 if (ret)
383 return ret;
384
385 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
386 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
387 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) {
388 dev_err(dev,
389 "%s ID 0x%02x does not match\n", s->devtype->name, val);
390 return -ENODEV;
391 }
392
393 return 0;
394}
395
396static void max14830_power(struct uart_port *port, int on)
397{
398 max310x_port_update(port, MAX310X_BRGCFG_REG,
399 MAX14830_BRGCFG_CLKDIS_BIT,
400 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT);
401 if (on)
402 msleep(50);
403}
404
405static const struct max310x_devtype max3107_devtype = {
406 .name = "MAX3107",
407 .nr = 1,
408 .detect = max3107_detect,
409 .power = max310x_power,
410};
411
412static const struct max310x_devtype max3108_devtype = {
413 .name = "MAX3108",
414 .nr = 1,
415 .detect = max3108_detect,
416 .power = max310x_power,
417};
418
419static const struct max310x_devtype max3109_devtype = {
420 .name = "MAX3109",
421 .nr = 2,
422 .detect = max3109_detect,
423 .power = max310x_power,
424};
425
426static const struct max310x_devtype max14830_devtype = {
427 .name = "MAX14830",
428 .nr = 4,
429 .detect = max14830_detect,
430 .power = max14830_power,
431};
432
433static bool max310x_reg_writeable(struct device *dev, unsigned int reg)
434{
435 switch (reg & 0x1f) {
436 case MAX310X_IRQSTS_REG:
437 case MAX310X_LSR_IRQSTS_REG:
438 case MAX310X_SPCHR_IRQSTS_REG:
439 case MAX310X_STS_IRQSTS_REG:
440 case MAX310X_TXFIFOLVL_REG:
441 case MAX310X_RXFIFOLVL_REG:
442 return false;
443 default:
444 break;
445 }
446
447 return true;
448}
449
450static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
451{
452 switch (reg & 0x1f) {
453 case MAX310X_RHR_REG:
454 case MAX310X_IRQSTS_REG:
455 case MAX310X_LSR_IRQSTS_REG:
456 case MAX310X_SPCHR_IRQSTS_REG:
457 case MAX310X_STS_IRQSTS_REG:
458 case MAX310X_TXFIFOLVL_REG:
459 case MAX310X_RXFIFOLVL_REG:
460 case MAX310X_GPIODATA_REG:
461 case MAX310X_BRGDIVLSB_REG:
462 case MAX310X_REG_05:
463 case MAX310X_REG_1F:
464 return true;
465 default:
466 break;
467 }
468
469 return false;
470}
471
472static bool max310x_reg_precious(struct device *dev, unsigned int reg)
473{
474 switch (reg & 0x1f) {
475 case MAX310X_RHR_REG:
476 case MAX310X_IRQSTS_REG:
477 case MAX310X_SPCHR_IRQSTS_REG:
478 case MAX310X_STS_IRQSTS_REG:
479 return true;
480 default:
481 break;
482 }
483
484 return false;
485}
486
487static int max310x_set_baud(struct uart_port *port, int baud)
488{
489 unsigned int mode = 0, clk = port->uartclk, div = clk / baud;
490
491 /* Check for minimal value for divider */
492 if (div < 16)
493 div = 16;
494
495 if (clk % baud && (div / 16) < 0x8000) {
496 /* Mode x2 */
497 mode = MAX310X_BRGCFG_2XMODE_BIT;
498 clk = port->uartclk * 2;
499 div = clk / baud;
500
501 if (clk % baud && (div / 16) < 0x8000) {
502 /* Mode x4 */
503 mode = MAX310X_BRGCFG_4XMODE_BIT;
504 clk = port->uartclk * 4;
505 div = clk / baud;
506 }
507 }
508
509 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, (div / 16) >> 8);
510 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div / 16);
511 max310x_port_write(port, MAX310X_BRGCFG_REG, (div % 16) | mode);
512
513 return DIV_ROUND_CLOSEST(clk, div);
514}
515
516static int max310x_update_best_err(unsigned long f, long *besterr)
517{
518 /* Use baudrate 115200 for calculate error */
519 long err = f % (115200 * 16);
520
521 if ((*besterr < 0) || (*besterr > err)) {
522 *besterr = err;
523 return 0;
524 }
525
526 return 1;
527}
528
529static int max310x_set_ref_clk(struct max310x_port *s, unsigned long freq,
530 bool xtal)
531{
532 unsigned int div, clksrc, pllcfg = 0;
533 long besterr = -1;
534 unsigned long fdiv, fmul, bestfreq = freq;
535
536 /* First, update error without PLL */
537 max310x_update_best_err(freq, &besterr);
538
539 /* Try all possible PLL dividers */
540 for (div = 1; (div <= 63) && besterr; div++) {
541 fdiv = DIV_ROUND_CLOSEST(freq, div);
542
543 /* Try multiplier 6 */
544 fmul = fdiv * 6;
545 if ((fdiv >= 500000) && (fdiv <= 800000))
546 if (!max310x_update_best_err(fmul, &besterr)) {
547 pllcfg = (0 << 6) | div;
548 bestfreq = fmul;
549 }
550 /* Try multiplier 48 */
551 fmul = fdiv * 48;
552 if ((fdiv >= 850000) && (fdiv <= 1200000))
553 if (!max310x_update_best_err(fmul, &besterr)) {
554 pllcfg = (1 << 6) | div;
555 bestfreq = fmul;
556 }
557 /* Try multiplier 96 */
558 fmul = fdiv * 96;
559 if ((fdiv >= 425000) && (fdiv <= 1000000))
560 if (!max310x_update_best_err(fmul, &besterr)) {
561 pllcfg = (2 << 6) | div;
562 bestfreq = fmul;
563 }
564 /* Try multiplier 144 */
565 fmul = fdiv * 144;
566 if ((fdiv >= 390000) && (fdiv <= 667000))
567 if (!max310x_update_best_err(fmul, &besterr)) {
568 pllcfg = (3 << 6) | div;
569 bestfreq = fmul;
570 }
571 }
572
573 /* Configure clock source */
574 clksrc = xtal ? MAX310X_CLKSRC_CRYST_BIT : MAX310X_CLKSRC_EXTCLK_BIT;
575
576 /* Configure PLL */
577 if (pllcfg) {
578 clksrc |= MAX310X_CLKSRC_PLL_BIT;
579 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg);
580 } else
581 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
582
583 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
584
585 /* Wait for crystal */
586 if (pllcfg && xtal)
587 msleep(10);
588
589 return (int)bestfreq;
590}
591
592static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)
593{
594 unsigned int sts, ch, flag;
595
596 if (unlikely(rxlen >= port->fifosize)) {
597 dev_warn_ratelimited(port->dev,
598 "Port %i: Possible RX FIFO overrun\n",
599 port->line);
600 port->icount.buf_overrun++;
601 /* Ensure sanity of RX level */
602 rxlen = port->fifosize;
603 }
604
605 while (rxlen--) {
606 ch = max310x_port_read(port, MAX310X_RHR_REG);
607 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
608
609 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
610 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
611
612 port->icount.rx++;
613 flag = TTY_NORMAL;
614
615 if (unlikely(sts)) {
616 if (sts & MAX310X_LSR_RXBRK_BIT) {
617 port->icount.brk++;
618 if (uart_handle_break(port))
619 continue;
620 } else if (sts & MAX310X_LSR_RXPAR_BIT)
621 port->icount.parity++;
622 else if (sts & MAX310X_LSR_FRERR_BIT)
623 port->icount.frame++;
624 else if (sts & MAX310X_LSR_RXOVR_BIT)
625 port->icount.overrun++;
626
627 sts &= port->read_status_mask;
628 if (sts & MAX310X_LSR_RXBRK_BIT)
629 flag = TTY_BREAK;
630 else if (sts & MAX310X_LSR_RXPAR_BIT)
631 flag = TTY_PARITY;
632 else if (sts & MAX310X_LSR_FRERR_BIT)
633 flag = TTY_FRAME;
634 else if (sts & MAX310X_LSR_RXOVR_BIT)
635 flag = TTY_OVERRUN;
636 }
637
638 if (uart_handle_sysrq_char(port, ch))
639 continue;
640
641 if (sts & port->ignore_status_mask)
642 continue;
643
644 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag);
645 }
646
647 tty_flip_buffer_push(&port->state->port);
648}
649
650static void max310x_handle_tx(struct uart_port *port)
651{
652 struct circ_buf *xmit = &port->state->xmit;
653 unsigned int txlen, to_send;
654
655 if (unlikely(port->x_char)) {
656 max310x_port_write(port, MAX310X_THR_REG, port->x_char);
657 port->icount.tx++;
658 port->x_char = 0;
659 return;
660 }
661
662 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
663 return;
664
665 /* Get length of data pending in circular buffer */
666 to_send = uart_circ_chars_pending(xmit);
667 if (likely(to_send)) {
668 /* Limit to size of TX FIFO */
669 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
670 txlen = port->fifosize - txlen;
671 to_send = (to_send > txlen) ? txlen : to_send;
672
673 /* Add data to send */
674 port->icount.tx += to_send;
675 while (to_send--) {
676 max310x_port_write(port, MAX310X_THR_REG,
677 xmit->buf[xmit->tail]);
678 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
679 }
680 }
681
682 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
683 uart_write_wakeup(port);
684}
685
686static void max310x_port_irq(struct max310x_port *s, int portno)
687{
688 struct uart_port *port = &s->p[portno].port;
689
690 do {
691 unsigned int ists, lsr, rxlen;
692
693 /* Read IRQ status & RX FIFO level */
694 ists = max310x_port_read(port, MAX310X_IRQSTS_REG);
695 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG);
696 if (!ists && !rxlen)
697 break;
698
699 if (ists & MAX310X_IRQ_CTS_BIT) {
700 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
701 uart_handle_cts_change(port,
702 !!(lsr & MAX310X_LSR_CTS_BIT));
703 }
704 if (rxlen)
705 max310x_handle_rx(port, rxlen);
706 if (ists & MAX310X_IRQ_TXEMPTY_BIT) {
707 mutex_lock(&s->mutex);
708 max310x_handle_tx(port);
709 mutex_unlock(&s->mutex);
710 }
711 } while (1);
712}
713
714static irqreturn_t max310x_ist(int irq, void *dev_id)
715{
716 struct max310x_port *s = (struct max310x_port *)dev_id;
717
718 if (s->uart.nr > 1) {
719 do {
720 unsigned int val = ~0;
721
722 WARN_ON_ONCE(regmap_read(s->regmap,
723 MAX310X_GLOBALIRQ_REG, &val));
724 val = ((1 << s->uart.nr) - 1) & ~val;
725 if (!val)
726 break;
727 max310x_port_irq(s, fls(val) - 1);
728 } while (1);
729 } else
730 max310x_port_irq(s, 0);
731
732 return IRQ_HANDLED;
733}
734
735static void max310x_wq_proc(struct work_struct *ws)
736{
737 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work);
738 struct max310x_port *s = dev_get_drvdata(one->port.dev);
739
740 mutex_lock(&s->mutex);
741 max310x_handle_tx(&one->port);
742 mutex_unlock(&s->mutex);
743}
744
745static void max310x_start_tx(struct uart_port *port)
746{
747 struct max310x_one *one = container_of(port, struct max310x_one, port);
748
749 if (!work_pending(&one->tx_work))
750 schedule_work(&one->tx_work);
751}
752
753static unsigned int max310x_tx_empty(struct uart_port *port)
754{
755 unsigned int lvl, sts;
756
757 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
758 sts = max310x_port_read(port, MAX310X_IRQSTS_REG);
759
760 return ((sts & MAX310X_IRQ_TXEMPTY_BIT) && !lvl) ? TIOCSER_TEMT : 0;
761}
762
763static unsigned int max310x_get_mctrl(struct uart_port *port)
764{
765 /* DCD and DSR are not wired and CTS/RTS is handled automatically
766 * so just indicate DSR and CAR asserted
767 */
768 return TIOCM_DSR | TIOCM_CAR;
769}
770
771static void max310x_md_proc(struct work_struct *ws)
772{
773 struct max310x_one *one = container_of(ws, struct max310x_one, md_work);
774
775 max310x_port_update(&one->port, MAX310X_MODE2_REG,
776 MAX310X_MODE2_LOOPBACK_BIT,
777 (one->port.mctrl & TIOCM_LOOP) ?
778 MAX310X_MODE2_LOOPBACK_BIT : 0);
779}
780
781static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
782{
783 struct max310x_one *one = container_of(port, struct max310x_one, port);
784
785 schedule_work(&one->md_work);
786}
787
788static void max310x_break_ctl(struct uart_port *port, int break_state)
789{
790 max310x_port_update(port, MAX310X_LCR_REG,
791 MAX310X_LCR_TXBREAK_BIT,
792 break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
793}
794
795static void max310x_set_termios(struct uart_port *port,
796 struct ktermios *termios,
797 struct ktermios *old)
798{
799 unsigned int lcr, flow = 0;
800 int baud;
801
802 /* Mask termios capabilities we don't support */
803 termios->c_cflag &= ~CMSPAR;
804
805 /* Word size */
806 switch (termios->c_cflag & CSIZE) {
807 case CS5:
808 lcr = MAX310X_LCR_WORD_LEN_5;
809 break;
810 case CS6:
811 lcr = MAX310X_LCR_WORD_LEN_6;
812 break;
813 case CS7:
814 lcr = MAX310X_LCR_WORD_LEN_7;
815 break;
816 case CS8:
817 default:
818 lcr = MAX310X_LCR_WORD_LEN_8;
819 break;
820 }
821
822 /* Parity */
823 if (termios->c_cflag & PARENB) {
824 lcr |= MAX310X_LCR_PARITY_BIT;
825 if (!(termios->c_cflag & PARODD))
826 lcr |= MAX310X_LCR_EVENPARITY_BIT;
827 }
828
829 /* Stop bits */
830 if (termios->c_cflag & CSTOPB)
831 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */
832
833 /* Update LCR register */
834 max310x_port_write(port, MAX310X_LCR_REG, lcr);
835
836 /* Set read status mask */
837 port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
838 if (termios->c_iflag & INPCK)
839 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
840 MAX310X_LSR_FRERR_BIT;
841 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
842 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
843
844 /* Set status ignore mask */
845 port->ignore_status_mask = 0;
846 if (termios->c_iflag & IGNBRK)
847 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
848 if (!(termios->c_cflag & CREAD))
849 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
850 MAX310X_LSR_RXOVR_BIT |
851 MAX310X_LSR_FRERR_BIT |
852 MAX310X_LSR_RXBRK_BIT;
853
854 /* Configure flow control */
855 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
856 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
857 if (termios->c_cflag & CRTSCTS)
858 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
859 MAX310X_FLOWCTRL_AUTORTS_BIT;
860 if (termios->c_iflag & IXON)
861 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
862 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
863 if (termios->c_iflag & IXOFF)
864 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
865 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
866 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);
867
868 /* Get baud rate generator configuration */
869 baud = uart_get_baud_rate(port, termios, old,
870 port->uartclk / 16 / 0xffff,
871 port->uartclk / 4);
872
873 /* Setup baudrate generator */
874 baud = max310x_set_baud(port, baud);
875
876 /* Update timeout according to new baud rate */
877 uart_update_timeout(port, termios->c_cflag, baud);
878}
879
880static int max310x_rs485_config(struct uart_port *port,
881 struct serial_rs485 *rs485)
882{
883 unsigned int val;
884
885 if (rs485->delay_rts_before_send > 0x0f ||
886 rs485->delay_rts_after_send > 0x0f)
887 return -ERANGE;
888
889 val = (rs485->delay_rts_before_send << 4) |
890 rs485->delay_rts_after_send;
891 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val);
892 if (rs485->flags & SER_RS485_ENABLED) {
893 max310x_port_update(port, MAX310X_MODE1_REG,
894 MAX310X_MODE1_TRNSCVCTRL_BIT,
895 MAX310X_MODE1_TRNSCVCTRL_BIT);
896 max310x_port_update(port, MAX310X_MODE2_REG,
897 MAX310X_MODE2_ECHOSUPR_BIT,
898 MAX310X_MODE2_ECHOSUPR_BIT);
899 } else {
900 max310x_port_update(port, MAX310X_MODE1_REG,
901 MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
902 max310x_port_update(port, MAX310X_MODE2_REG,
903 MAX310X_MODE2_ECHOSUPR_BIT, 0);
904 }
905
906 rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_ENABLED;
907 memset(rs485->padding, 0, sizeof(rs485->padding));
908 port->rs485 = *rs485;
909
910 return 0;
911}
912
913static int max310x_startup(struct uart_port *port)
914{
915 struct max310x_port *s = dev_get_drvdata(port->dev);
916 unsigned int val;
917
918 s->devtype->power(port, 1);
919
920 /* Configure MODE1 register */
921 max310x_port_update(port, MAX310X_MODE1_REG,
922 MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
923
924 /* Configure MODE2 register & Reset FIFOs*/
925 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT;
926 max310x_port_write(port, MAX310X_MODE2_REG, val);
927 max310x_port_update(port, MAX310X_MODE2_REG,
928 MAX310X_MODE2_FIFORST_BIT, 0);
929
930 /* Configure flow control levels */
931 /* Flow control halt level 96, resume level 48 */
932 max310x_port_write(port, MAX310X_FLOWLVL_REG,
933 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96));
934
935 /* Clear IRQ status register */
936 max310x_port_read(port, MAX310X_IRQSTS_REG);
937
938 /* Enable RX, TX, CTS change interrupts */
939 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT;
940 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);
941
942 return 0;
943}
944
945static void max310x_shutdown(struct uart_port *port)
946{
947 struct max310x_port *s = dev_get_drvdata(port->dev);
948
949 /* Disable all interrupts */
950 max310x_port_write(port, MAX310X_IRQEN_REG, 0);
951
952 s->devtype->power(port, 0);
953}
954
955static const char *max310x_type(struct uart_port *port)
956{
957 struct max310x_port *s = dev_get_drvdata(port->dev);
958
959 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL;
960}
961
962static int max310x_request_port(struct uart_port *port)
963{
964 /* Do nothing */
965 return 0;
966}
967
968static void max310x_config_port(struct uart_port *port, int flags)
969{
970 if (flags & UART_CONFIG_TYPE)
971 port->type = PORT_MAX310X;
972}
973
974static int max310x_verify_port(struct uart_port *port, struct serial_struct *s)
975{
976 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X))
977 return -EINVAL;
978 if (s->irq != port->irq)
979 return -EINVAL;
980
981 return 0;
982}
983
984static void max310x_null_void(struct uart_port *port)
985{
986 /* Do nothing */
987}
988
989static const struct uart_ops max310x_ops = {
990 .tx_empty = max310x_tx_empty,
991 .set_mctrl = max310x_set_mctrl,
992 .get_mctrl = max310x_get_mctrl,
993 .stop_tx = max310x_null_void,
994 .start_tx = max310x_start_tx,
995 .stop_rx = max310x_null_void,
996 .break_ctl = max310x_break_ctl,
997 .startup = max310x_startup,
998 .shutdown = max310x_shutdown,
999 .set_termios = max310x_set_termios,
1000 .type = max310x_type,
1001 .request_port = max310x_request_port,
1002 .release_port = max310x_null_void,
1003 .config_port = max310x_config_port,
1004 .verify_port = max310x_verify_port,
1005};
1006
1007static int __maybe_unused max310x_suspend(struct device *dev)
1008{
1009 struct max310x_port *s = dev_get_drvdata(dev);
1010 int i;
1011
1012 for (i = 0; i < s->uart.nr; i++) {
1013 uart_suspend_port(&s->uart, &s->p[i].port);
1014 s->devtype->power(&s->p[i].port, 0);
1015 }
1016
1017 return 0;
1018}
1019
1020static int __maybe_unused max310x_resume(struct device *dev)
1021{
1022 struct max310x_port *s = dev_get_drvdata(dev);
1023 int i;
1024
1025 for (i = 0; i < s->uart.nr; i++) {
1026 s->devtype->power(&s->p[i].port, 1);
1027 uart_resume_port(&s->uart, &s->p[i].port);
1028 }
1029
1030 return 0;
1031}
1032
1033static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume);
1034
1035#ifdef CONFIG_GPIOLIB
1036static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset)
1037{
1038 unsigned int val;
1039 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
1040 struct uart_port *port = &s->p[offset / 4].port;
1041
1042 val = max310x_port_read(port, MAX310X_GPIODATA_REG);
1043
1044 return !!((val >> 4) & (1 << (offset % 4)));
1045}
1046
1047static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1048{
1049 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
1050 struct uart_port *port = &s->p[offset / 4].port;
1051
1052 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1053 value ? 1 << (offset % 4) : 0);
1054}
1055
1056static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1057{
1058 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
1059 struct uart_port *port = &s->p[offset / 4].port;
1060
1061 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0);
1062
1063 return 0;
1064}
1065
1066static int max310x_gpio_direction_output(struct gpio_chip *chip,
1067 unsigned offset, int value)
1068{
1069 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
1070 struct uart_port *port = &s->p[offset / 4].port;
1071
1072 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1073 value ? 1 << (offset % 4) : 0);
1074 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4),
1075 1 << (offset % 4));
1076
1077 return 0;
1078}
1079#endif
1080
1081static int max310x_probe(struct device *dev, struct max310x_devtype *devtype,
1082 struct regmap *regmap, int irq, unsigned long flags)
1083{
1084 int i, ret, fmin, fmax, freq, uartclk;
1085 struct clk *clk_osc, *clk_xtal;
1086 struct max310x_port *s;
1087 bool xtal = false;
1088
1089 if (IS_ERR(regmap))
1090 return PTR_ERR(regmap);
1091
1092 /* Alloc port structure */
1093 s = devm_kzalloc(dev, sizeof(*s) +
1094 sizeof(struct max310x_one) * devtype->nr, GFP_KERNEL);
1095 if (!s) {
1096 dev_err(dev, "Error allocating port structure\n");
1097 return -ENOMEM;
1098 }
1099
1100 clk_osc = devm_clk_get(dev, "osc");
1101 clk_xtal = devm_clk_get(dev, "xtal");
1102 if (!IS_ERR(clk_osc)) {
1103 s->clk = clk_osc;
1104 fmin = 500000;
1105 fmax = 35000000;
1106 } else if (!IS_ERR(clk_xtal)) {
1107 s->clk = clk_xtal;
1108 fmin = 1000000;
1109 fmax = 4000000;
1110 xtal = true;
1111 } else if (PTR_ERR(clk_osc) == -EPROBE_DEFER ||
1112 PTR_ERR(clk_xtal) == -EPROBE_DEFER) {
1113 return -EPROBE_DEFER;
1114 } else {
1115 dev_err(dev, "Cannot get clock\n");
1116 return -EINVAL;
1117 }
1118
1119 ret = clk_prepare_enable(s->clk);
1120 if (ret)
1121 return ret;
1122
1123 freq = clk_get_rate(s->clk);
1124 /* Check frequency limits */
1125 if (freq < fmin || freq > fmax) {
1126 ret = -ERANGE;
1127 goto out_clk;
1128 }
1129
1130 s->regmap = regmap;
1131 s->devtype = devtype;
1132 dev_set_drvdata(dev, s);
1133
1134 /* Check device to ensure we are talking to what we expect */
1135 ret = devtype->detect(dev);
1136 if (ret)
1137 goto out_clk;
1138
1139 for (i = 0; i < devtype->nr; i++) {
1140 unsigned int offs = i << 5;
1141
1142 /* Reset port */
1143 regmap_write(s->regmap, MAX310X_MODE2_REG + offs,
1144 MAX310X_MODE2_RST_BIT);
1145 /* Clear port reset */
1146 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0);
1147
1148 /* Wait for port startup */
1149 do {
1150 regmap_read(s->regmap,
1151 MAX310X_BRGDIVLSB_REG + offs, &ret);
1152 } while (ret != 0x01);
1153
1154 regmap_update_bits(s->regmap, MAX310X_MODE1_REG + offs,
1155 MAX310X_MODE1_AUTOSLEEP_BIT,
1156 MAX310X_MODE1_AUTOSLEEP_BIT);
1157 }
1158
1159 uartclk = max310x_set_ref_clk(s, freq, xtal);
1160 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
1161
1162 /* Register UART driver */
1163 s->uart.owner = THIS_MODULE;
1164 s->uart.dev_name = "ttyMAX";
1165 s->uart.major = MAX310X_MAJOR;
1166 s->uart.minor = MAX310X_MINOR;
1167 s->uart.nr = devtype->nr;
1168 ret = uart_register_driver(&s->uart);
1169 if (ret) {
1170 dev_err(dev, "Registering UART driver failed\n");
1171 goto out_clk;
1172 }
1173
1174#ifdef CONFIG_GPIOLIB
1175 /* Setup GPIO cotroller */
1176 s->gpio.owner = THIS_MODULE;
1177 s->gpio.parent = dev;
1178 s->gpio.label = dev_name(dev);
1179 s->gpio.direction_input = max310x_gpio_direction_input;
1180 s->gpio.get = max310x_gpio_get;
1181 s->gpio.direction_output= max310x_gpio_direction_output;
1182 s->gpio.set = max310x_gpio_set;
1183 s->gpio.base = -1;
1184 s->gpio.ngpio = devtype->nr * 4;
1185 s->gpio.can_sleep = 1;
1186 ret = gpiochip_add(&s->gpio);
1187 if (ret)
1188 goto out_uart;
1189#endif
1190
1191 mutex_init(&s->mutex);
1192
1193 for (i = 0; i < devtype->nr; i++) {
1194 /* Initialize port data */
1195 s->p[i].port.line = i;
1196 s->p[i].port.dev = dev;
1197 s->p[i].port.irq = irq;
1198 s->p[i].port.type = PORT_MAX310X;
1199 s->p[i].port.fifosize = MAX310X_FIFO_SIZE;
1200 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1201 s->p[i].port.iotype = UPIO_PORT;
1202 s->p[i].port.iobase = i * 0x20;
1203 s->p[i].port.membase = (void __iomem *)~0;
1204 s->p[i].port.uartclk = uartclk;
1205 s->p[i].port.rs485_config = max310x_rs485_config;
1206 s->p[i].port.ops = &max310x_ops;
1207 /* Disable all interrupts */
1208 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
1209 /* Clear IRQ status register */
1210 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
1211 /* Enable IRQ pin */
1212 max310x_port_update(&s->p[i].port, MAX310X_MODE1_REG,
1213 MAX310X_MODE1_IRQSEL_BIT,
1214 MAX310X_MODE1_IRQSEL_BIT);
1215 /* Initialize queue for start TX */
1216 INIT_WORK(&s->p[i].tx_work, max310x_wq_proc);
1217 /* Initialize queue for changing mode */
1218 INIT_WORK(&s->p[i].md_work, max310x_md_proc);
1219 /* Register port */
1220 uart_add_one_port(&s->uart, &s->p[i].port);
1221 /* Go to suspend mode */
1222 devtype->power(&s->p[i].port, 0);
1223 }
1224
1225 /* Setup interrupt */
1226 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist,
1227 IRQF_ONESHOT | flags, dev_name(dev), s);
1228 if (!ret)
1229 return 0;
1230
1231 dev_err(dev, "Unable to reguest IRQ %i\n", irq);
1232
1233 mutex_destroy(&s->mutex);
1234
1235#ifdef CONFIG_GPIOLIB
1236 gpiochip_remove(&s->gpio);
1237
1238out_uart:
1239#endif
1240 uart_unregister_driver(&s->uart);
1241
1242out_clk:
1243 clk_disable_unprepare(s->clk);
1244
1245 return ret;
1246}
1247
1248static int max310x_remove(struct device *dev)
1249{
1250 struct max310x_port *s = dev_get_drvdata(dev);
1251 int i;
1252
1253#ifdef CONFIG_GPIOLIB
1254 gpiochip_remove(&s->gpio);
1255#endif
1256
1257 for (i = 0; i < s->uart.nr; i++) {
1258 cancel_work_sync(&s->p[i].tx_work);
1259 cancel_work_sync(&s->p[i].md_work);
1260 uart_remove_one_port(&s->uart, &s->p[i].port);
1261 s->devtype->power(&s->p[i].port, 0);
1262 }
1263
1264 mutex_destroy(&s->mutex);
1265 uart_unregister_driver(&s->uart);
1266 clk_disable_unprepare(s->clk);
1267
1268 return 0;
1269}
1270
1271static const struct of_device_id __maybe_unused max310x_dt_ids[] = {
1272 { .compatible = "maxim,max3107", .data = &max3107_devtype, },
1273 { .compatible = "maxim,max3108", .data = &max3108_devtype, },
1274 { .compatible = "maxim,max3109", .data = &max3109_devtype, },
1275 { .compatible = "maxim,max14830", .data = &max14830_devtype },
1276 { }
1277};
1278MODULE_DEVICE_TABLE(of, max310x_dt_ids);
1279
1280static struct regmap_config regcfg = {
1281 .reg_bits = 8,
1282 .val_bits = 8,
1283 .write_flag_mask = 0x80,
1284 .cache_type = REGCACHE_RBTREE,
1285 .writeable_reg = max310x_reg_writeable,
1286 .volatile_reg = max310x_reg_volatile,
1287 .precious_reg = max310x_reg_precious,
1288};
1289
1290#ifdef CONFIG_SPI_MASTER
1291static int max310x_spi_probe(struct spi_device *spi)
1292{
1293 struct max310x_devtype *devtype;
1294 unsigned long flags = 0;
1295 struct regmap *regmap;
1296 int ret;
1297
1298 /* Setup SPI bus */
1299 spi->bits_per_word = 8;
1300 spi->mode = spi->mode ? : SPI_MODE_0;
1301 spi->max_speed_hz = spi->max_speed_hz ? : 26000000;
1302 ret = spi_setup(spi);
1303 if (ret)
1304 return ret;
1305
1306 if (spi->dev.of_node) {
1307 const struct of_device_id *of_id =
1308 of_match_device(max310x_dt_ids, &spi->dev);
1309
1310 devtype = (struct max310x_devtype *)of_id->data;
1311 } else {
1312 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1313
1314 devtype = (struct max310x_devtype *)id_entry->driver_data;
1315 flags = IRQF_TRIGGER_FALLING;
1316 }
1317
1318 regcfg.max_register = devtype->nr * 0x20 - 1;
1319 regmap = devm_regmap_init_spi(spi, ®cfg);
1320
1321 return max310x_probe(&spi->dev, devtype, regmap, spi->irq, flags);
1322}
1323
1324static int max310x_spi_remove(struct spi_device *spi)
1325{
1326 return max310x_remove(&spi->dev);
1327}
1328
1329static const struct spi_device_id max310x_id_table[] = {
1330 { "max3107", (kernel_ulong_t)&max3107_devtype, },
1331 { "max3108", (kernel_ulong_t)&max3108_devtype, },
1332 { "max3109", (kernel_ulong_t)&max3109_devtype, },
1333 { "max14830", (kernel_ulong_t)&max14830_devtype, },
1334 { }
1335};
1336MODULE_DEVICE_TABLE(spi, max310x_id_table);
1337
1338static struct spi_driver max310x_uart_driver = {
1339 .driver = {
1340 .name = MAX310X_NAME,
1341 .of_match_table = of_match_ptr(max310x_dt_ids),
1342 .pm = &max310x_pm_ops,
1343 },
1344 .probe = max310x_spi_probe,
1345 .remove = max310x_spi_remove,
1346 .id_table = max310x_id_table,
1347};
1348module_spi_driver(max310x_uart_driver);
1349#endif
1350
1351MODULE_LICENSE("GPL");
1352MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1353MODULE_DESCRIPTION("MAX310X serial driver");