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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver
4 *
5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru>
6 *
7 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
8 * Based on max3110.c, by Feng Tang <feng.tang@intel.com>
9 * Based on max3107.c, by Aavamobile
10 */
11
12#include <linux/bitops.h>
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/device.h>
16#include <linux/gpio/driver.h>
17#include <linux/i2c.h>
18#include <linux/module.h>
19#include <linux/mod_devicetable.h>
20#include <linux/property.h>
21#include <linux/regmap.h>
22#include <linux/serial_core.h>
23#include <linux/serial.h>
24#include <linux/tty.h>
25#include <linux/tty_flip.h>
26#include <linux/spi/spi.h>
27#include <linux/uaccess.h>
28
29#define MAX310X_NAME "max310x"
30#define MAX310X_MAJOR 204
31#define MAX310X_MINOR 209
32#define MAX310X_UART_NRMAX 16
33
34/* MAX310X register definitions */
35#define MAX310X_RHR_REG (0x00) /* RX FIFO */
36#define MAX310X_THR_REG (0x00) /* TX FIFO */
37#define MAX310X_IRQEN_REG (0x01) /* IRQ enable */
38#define MAX310X_IRQSTS_REG (0x02) /* IRQ status */
39#define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */
40#define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */
41#define MAX310X_REG_05 (0x05)
42#define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */
43#define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */
44#define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */
45#define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */
46#define MAX310X_MODE1_REG (0x09) /* MODE1 */
47#define MAX310X_MODE2_REG (0x0a) /* MODE2 */
48#define MAX310X_LCR_REG (0x0b) /* LCR */
49#define MAX310X_RXTO_REG (0x0c) /* RX timeout */
50#define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
51#define MAX310X_IRDA_REG (0x0e) /* IRDA settings */
52#define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */
53#define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */
54#define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */
55#define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */
56#define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */
57#define MAX310X_XON1_REG (0x14) /* XON1 character */
58#define MAX310X_XON2_REG (0x15) /* XON2 character */
59#define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */
60#define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */
61#define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */
62#define MAX310X_GPIODATA_REG (0x19) /* GPIO data */
63#define MAX310X_PLLCFG_REG (0x1a) /* PLL config */
64#define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
65#define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
66#define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
67#define MAX310X_CLKSRC_REG (0x1e) /* Clock source */
68#define MAX310X_REG_1F (0x1f)
69
70#define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */
71
72#define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */
73#define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */
74
75/* Extended registers */
76#define MAX310X_SPI_REVID_EXTREG MAX310X_REG_05 /* Revision ID */
77#define MAX310X_I2C_REVID_EXTREG (0x25) /* Revision ID */
78
79/* IRQ register bits */
80#define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
81#define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
82#define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */
83#define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
84#define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
85#define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
86#define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
87#define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
88
89/* LSR register bits */
90#define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */
91#define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
92#define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
93#define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */
94#define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */
95#define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
96#define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */
97
98/* Special character register bits */
99#define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
100#define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
101#define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
102#define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
103#define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */
104#define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
105
106/* Status register bits */
107#define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
108#define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
109#define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
110#define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
111#define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
112#define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
113
114/* MODE1 register bits */
115#define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
116#define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
117#define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
118#define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
119#define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
120#define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
121#define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
122#define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
123
124/* MODE2 register bits */
125#define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */
126#define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
127#define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
128#define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
129#define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
130#define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
131#define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
132#define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
133
134/* LCR register bits */
135#define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
136#define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
137 *
138 * Word length bits table:
139 * 00 -> 5 bit words
140 * 01 -> 6 bit words
141 * 10 -> 7 bit words
142 * 11 -> 8 bit words
143 */
144#define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
145 *
146 * STOP length bit table:
147 * 0 -> 1 stop bit
148 * 1 -> 1-1.5 stop bits if
149 * word length is 5,
150 * 2 stop bits otherwise
151 */
152#define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
153#define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
154#define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
155#define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
156#define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */
157
158/* IRDA register bits */
159#define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
160#define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
161
162/* Flow control trigger level register masks */
163#define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
164#define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
165#define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
166#define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)
167
168/* FIFO interrupt trigger level register masks */
169#define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */
170#define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */
171#define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f)
172#define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4)
173
174/* Flow control register bits */
175#define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
176#define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
177#define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
178 * are used in conjunction with
179 * XOFF2 for definition of
180 * special character */
181#define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
182#define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
183#define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
184 *
185 * SWFLOW bits 1 & 0 table:
186 * 00 -> no transmitter flow
187 * control
188 * 01 -> receiver compares
189 * XON2 and XOFF2
190 * and controls
191 * transmitter
192 * 10 -> receiver compares
193 * XON1 and XOFF1
194 * and controls
195 * transmitter
196 * 11 -> receiver compares
197 * XON1, XON2, XOFF1 and
198 * XOFF2 and controls
199 * transmitter
200 */
201#define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
202#define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
203 *
204 * SWFLOW bits 3 & 2 table:
205 * 00 -> no received flow
206 * control
207 * 01 -> transmitter generates
208 * XON2 and XOFF2
209 * 10 -> transmitter generates
210 * XON1 and XOFF1
211 * 11 -> transmitter generates
212 * XON1, XON2, XOFF1 and
213 * XOFF2
214 */
215
216/* PLL configuration register masks */
217#define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */
218#define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */
219
220/* Baud rate generator configuration register bits */
221#define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
222#define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
223
224/* Clock source register bits */
225#define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
226#define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
227#define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
228#define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
229#define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
230
231/* Global commands */
232#define MAX310X_EXTREG_ENBL (0xce)
233#define MAX310X_EXTREG_DSBL (0xcd)
234
235/* Misc definitions */
236#define MAX310X_FIFO_SIZE (128)
237#define MAX310x_REV_MASK (0xf8)
238#define MAX310X_WRITE_BIT 0x80
239
240/* MAX3107 specific */
241#define MAX3107_REV_ID (0xa0)
242
243/* MAX3109 specific */
244#define MAX3109_REV_ID (0xc0)
245
246/* MAX14830 specific */
247#define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */
248#define MAX14830_REV_ID (0xb0)
249
250struct max310x_if_cfg {
251 int (*extended_reg_enable)(struct device *dev, bool enable);
252
253 unsigned int rev_id_reg;
254};
255
256struct max310x_devtype {
257 struct {
258 unsigned short min;
259 unsigned short max;
260 } slave_addr;
261 char name[9];
262 int nr;
263 u8 mode1;
264 int (*detect)(struct device *);
265 void (*power)(struct uart_port *, int);
266};
267
268struct max310x_one {
269 struct uart_port port;
270 struct work_struct tx_work;
271 struct work_struct md_work;
272 struct work_struct rs_work;
273 struct regmap *regmap;
274
275 u8 rx_buf[MAX310X_FIFO_SIZE];
276};
277#define to_max310x_port(_port) \
278 container_of(_port, struct max310x_one, port)
279
280struct max310x_port {
281 const struct max310x_devtype *devtype;
282 const struct max310x_if_cfg *if_cfg;
283 struct regmap *regmap;
284 struct clk *clk;
285#ifdef CONFIG_GPIOLIB
286 struct gpio_chip gpio;
287#endif
288 struct max310x_one p[];
289};
290
291static struct uart_driver max310x_uart = {
292 .owner = THIS_MODULE,
293 .driver_name = MAX310X_NAME,
294 .dev_name = "ttyMAX",
295 .major = MAX310X_MAJOR,
296 .minor = MAX310X_MINOR,
297 .nr = MAX310X_UART_NRMAX,
298};
299
300static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX);
301
302static u8 max310x_port_read(struct uart_port *port, u8 reg)
303{
304 struct max310x_one *one = to_max310x_port(port);
305 unsigned int val = 0;
306
307 regmap_read(one->regmap, reg, &val);
308
309 return val;
310}
311
312static void max310x_port_write(struct uart_port *port, u8 reg, u8 val)
313{
314 struct max310x_one *one = to_max310x_port(port);
315
316 regmap_write(one->regmap, reg, val);
317}
318
319static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val)
320{
321 struct max310x_one *one = to_max310x_port(port);
322
323 regmap_update_bits(one->regmap, reg, mask, val);
324}
325
326static int max3107_detect(struct device *dev)
327{
328 struct max310x_port *s = dev_get_drvdata(dev);
329 unsigned int val = 0;
330 int ret;
331
332 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val);
333 if (ret)
334 return ret;
335
336 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) {
337 dev_err(dev,
338 "%s ID 0x%02x does not match\n", s->devtype->name, val);
339 return -ENODEV;
340 }
341
342 return 0;
343}
344
345static int max3108_detect(struct device *dev)
346{
347 struct max310x_port *s = dev_get_drvdata(dev);
348 unsigned int val = 0;
349 int ret;
350
351 /* MAX3108 have not REV ID register, we just check default value
352 * from clocksource register to make sure everything works.
353 */
354 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
355 if (ret)
356 return ret;
357
358 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) {
359 dev_err(dev, "%s not present\n", s->devtype->name);
360 return -ENODEV;
361 }
362
363 return 0;
364}
365
366static int max3109_detect(struct device *dev)
367{
368 struct max310x_port *s = dev_get_drvdata(dev);
369 unsigned int val = 0;
370 int ret;
371
372 ret = s->if_cfg->extended_reg_enable(dev, true);
373 if (ret)
374 return ret;
375
376 regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val);
377 s->if_cfg->extended_reg_enable(dev, false);
378 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) {
379 dev_err(dev,
380 "%s ID 0x%02x does not match\n", s->devtype->name, val);
381 return -ENODEV;
382 }
383
384 return 0;
385}
386
387static void max310x_power(struct uart_port *port, int on)
388{
389 max310x_port_update(port, MAX310X_MODE1_REG,
390 MAX310X_MODE1_FORCESLEEP_BIT,
391 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT);
392 if (on)
393 msleep(50);
394}
395
396static int max14830_detect(struct device *dev)
397{
398 struct max310x_port *s = dev_get_drvdata(dev);
399 unsigned int val = 0;
400 int ret;
401
402 ret = s->if_cfg->extended_reg_enable(dev, true);
403 if (ret)
404 return ret;
405
406 regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val);
407 s->if_cfg->extended_reg_enable(dev, false);
408 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) {
409 dev_err(dev,
410 "%s ID 0x%02x does not match\n", s->devtype->name, val);
411 return -ENODEV;
412 }
413
414 return 0;
415}
416
417static void max14830_power(struct uart_port *port, int on)
418{
419 max310x_port_update(port, MAX310X_BRGCFG_REG,
420 MAX14830_BRGCFG_CLKDIS_BIT,
421 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT);
422 if (on)
423 msleep(50);
424}
425
426static const struct max310x_devtype max3107_devtype = {
427 .name = "MAX3107",
428 .nr = 1,
429 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT,
430 .detect = max3107_detect,
431 .power = max310x_power,
432 .slave_addr = {
433 .min = 0x2c,
434 .max = 0x2f,
435 },
436};
437
438static const struct max310x_devtype max3108_devtype = {
439 .name = "MAX3108",
440 .nr = 1,
441 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT,
442 .detect = max3108_detect,
443 .power = max310x_power,
444 .slave_addr = {
445 .min = 0x60,
446 .max = 0x6f,
447 },
448};
449
450static const struct max310x_devtype max3109_devtype = {
451 .name = "MAX3109",
452 .nr = 2,
453 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT,
454 .detect = max3109_detect,
455 .power = max310x_power,
456 .slave_addr = {
457 .min = 0x60,
458 .max = 0x6f,
459 },
460};
461
462static const struct max310x_devtype max14830_devtype = {
463 .name = "MAX14830",
464 .nr = 4,
465 .mode1 = MAX310X_MODE1_IRQSEL_BIT,
466 .detect = max14830_detect,
467 .power = max14830_power,
468 .slave_addr = {
469 .min = 0x60,
470 .max = 0x6f,
471 },
472};
473
474static bool max310x_reg_writeable(struct device *dev, unsigned int reg)
475{
476 switch (reg) {
477 case MAX310X_IRQSTS_REG:
478 case MAX310X_LSR_IRQSTS_REG:
479 case MAX310X_SPCHR_IRQSTS_REG:
480 case MAX310X_STS_IRQSTS_REG:
481 case MAX310X_TXFIFOLVL_REG:
482 case MAX310X_RXFIFOLVL_REG:
483 return false;
484 default:
485 break;
486 }
487
488 return true;
489}
490
491static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
492{
493 switch (reg) {
494 case MAX310X_RHR_REG:
495 case MAX310X_IRQSTS_REG:
496 case MAX310X_LSR_IRQSTS_REG:
497 case MAX310X_SPCHR_IRQSTS_REG:
498 case MAX310X_STS_IRQSTS_REG:
499 case MAX310X_TXFIFOLVL_REG:
500 case MAX310X_RXFIFOLVL_REG:
501 case MAX310X_GPIODATA_REG:
502 case MAX310X_BRGDIVLSB_REG:
503 case MAX310X_REG_05:
504 case MAX310X_REG_1F:
505 return true;
506 default:
507 break;
508 }
509
510 return false;
511}
512
513static bool max310x_reg_precious(struct device *dev, unsigned int reg)
514{
515 switch (reg) {
516 case MAX310X_RHR_REG:
517 case MAX310X_IRQSTS_REG:
518 case MAX310X_SPCHR_IRQSTS_REG:
519 case MAX310X_STS_IRQSTS_REG:
520 return true;
521 default:
522 break;
523 }
524
525 return false;
526}
527
528static int max310x_set_baud(struct uart_port *port, int baud)
529{
530 unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0;
531
532 /*
533 * Calculate the integer divisor first. Select a proper mode
534 * in case if the requested baud is too high for the pre-defined
535 * clocks frequency.
536 */
537 div = port->uartclk / baud;
538 if (div < 8) {
539 /* Mode x4 */
540 c = 4;
541 mode = MAX310X_BRGCFG_4XMODE_BIT;
542 } else if (div < 16) {
543 /* Mode x2 */
544 c = 8;
545 mode = MAX310X_BRGCFG_2XMODE_BIT;
546 } else {
547 c = 16;
548 }
549
550 /* Calculate the divisor in accordance with the fraction coefficient */
551 div /= c;
552 F = c*baud;
553
554 /* Calculate the baud rate fraction */
555 if (div > 0)
556 frac = (16*(port->uartclk % F)) / F;
557 else
558 div = 1;
559
560 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8);
561 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div);
562 max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode);
563
564 /* Return the actual baud rate we just programmed */
565 return (16*port->uartclk) / (c*(16*div + frac));
566}
567
568static int max310x_update_best_err(unsigned long f, long *besterr)
569{
570 /* Use baudrate 115200 for calculate error */
571 long err = f % (460800 * 16);
572
573 if ((*besterr < 0) || (*besterr > err)) {
574 *besterr = err;
575 return 0;
576 }
577
578 return 1;
579}
580
581static u32 max310x_set_ref_clk(struct device *dev, struct max310x_port *s,
582 unsigned long freq, bool xtal)
583{
584 unsigned int div, clksrc, pllcfg = 0;
585 long besterr = -1;
586 unsigned long fdiv, fmul, bestfreq = freq;
587
588 /* First, update error without PLL */
589 max310x_update_best_err(freq, &besterr);
590
591 /* Try all possible PLL dividers */
592 for (div = 1; (div <= 63) && besterr; div++) {
593 fdiv = DIV_ROUND_CLOSEST(freq, div);
594
595 /* Try multiplier 6 */
596 fmul = fdiv * 6;
597 if ((fdiv >= 500000) && (fdiv <= 800000))
598 if (!max310x_update_best_err(fmul, &besterr)) {
599 pllcfg = (0 << 6) | div;
600 bestfreq = fmul;
601 }
602 /* Try multiplier 48 */
603 fmul = fdiv * 48;
604 if ((fdiv >= 850000) && (fdiv <= 1200000))
605 if (!max310x_update_best_err(fmul, &besterr)) {
606 pllcfg = (1 << 6) | div;
607 bestfreq = fmul;
608 }
609 /* Try multiplier 96 */
610 fmul = fdiv * 96;
611 if ((fdiv >= 425000) && (fdiv <= 1000000))
612 if (!max310x_update_best_err(fmul, &besterr)) {
613 pllcfg = (2 << 6) | div;
614 bestfreq = fmul;
615 }
616 /* Try multiplier 144 */
617 fmul = fdiv * 144;
618 if ((fdiv >= 390000) && (fdiv <= 667000))
619 if (!max310x_update_best_err(fmul, &besterr)) {
620 pllcfg = (3 << 6) | div;
621 bestfreq = fmul;
622 }
623 }
624
625 /* Configure clock source */
626 clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0);
627
628 /* Configure PLL */
629 if (pllcfg) {
630 clksrc |= MAX310X_CLKSRC_PLL_BIT;
631 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg);
632 } else
633 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
634
635 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
636
637 /* Wait for crystal */
638 if (xtal) {
639 unsigned int val;
640 msleep(10);
641 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val);
642 if (!(val & MAX310X_STS_CLKREADY_BIT)) {
643 dev_warn(dev, "clock is not stable yet\n");
644 }
645 }
646
647 return bestfreq;
648}
649
650static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len)
651{
652 struct max310x_one *one = to_max310x_port(port);
653
654 regmap_raw_write(one->regmap, MAX310X_THR_REG, txbuf, len);
655}
656
657static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len)
658{
659 struct max310x_one *one = to_max310x_port(port);
660
661 regmap_raw_read(one->regmap, MAX310X_RHR_REG, rxbuf, len);
662}
663
664static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)
665{
666 struct max310x_one *one = to_max310x_port(port);
667 unsigned int sts, ch, flag, i;
668
669 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) {
670 /* We are just reading, happily ignoring any error conditions.
671 * Break condition, parity checking, framing errors -- they
672 * are all ignored. That means that we can do a batch-read.
673 *
674 * There is a small opportunity for race if the RX FIFO
675 * overruns while we're reading the buffer; the datasheets says
676 * that the LSR register applies to the "current" character.
677 * That's also the reason why we cannot do batched reads when
678 * asked to check the individual statuses.
679 * */
680
681 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
682 max310x_batch_read(port, one->rx_buf, rxlen);
683
684 port->icount.rx += rxlen;
685 flag = TTY_NORMAL;
686 sts &= port->read_status_mask;
687
688 if (sts & MAX310X_LSR_RXOVR_BIT) {
689 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n");
690 port->icount.overrun++;
691 }
692
693 for (i = 0; i < (rxlen - 1); ++i)
694 uart_insert_char(port, sts, 0, one->rx_buf[i], flag);
695
696 /*
697 * Handle the overrun case for the last character only, since
698 * the RxFIFO overflow happens after it is pushed to the FIFO
699 * tail.
700 */
701 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT,
702 one->rx_buf[rxlen-1], flag);
703
704 } else {
705 if (unlikely(rxlen >= port->fifosize)) {
706 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n");
707 port->icount.buf_overrun++;
708 /* Ensure sanity of RX level */
709 rxlen = port->fifosize;
710 }
711
712 while (rxlen--) {
713 ch = max310x_port_read(port, MAX310X_RHR_REG);
714 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
715
716 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
717 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
718
719 port->icount.rx++;
720 flag = TTY_NORMAL;
721
722 if (unlikely(sts)) {
723 if (sts & MAX310X_LSR_RXBRK_BIT) {
724 port->icount.brk++;
725 if (uart_handle_break(port))
726 continue;
727 } else if (sts & MAX310X_LSR_RXPAR_BIT)
728 port->icount.parity++;
729 else if (sts & MAX310X_LSR_FRERR_BIT)
730 port->icount.frame++;
731 else if (sts & MAX310X_LSR_RXOVR_BIT)
732 port->icount.overrun++;
733
734 sts &= port->read_status_mask;
735 if (sts & MAX310X_LSR_RXBRK_BIT)
736 flag = TTY_BREAK;
737 else if (sts & MAX310X_LSR_RXPAR_BIT)
738 flag = TTY_PARITY;
739 else if (sts & MAX310X_LSR_FRERR_BIT)
740 flag = TTY_FRAME;
741 else if (sts & MAX310X_LSR_RXOVR_BIT)
742 flag = TTY_OVERRUN;
743 }
744
745 if (uart_handle_sysrq_char(port, ch))
746 continue;
747
748 if (sts & port->ignore_status_mask)
749 continue;
750
751 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag);
752 }
753 }
754
755 tty_flip_buffer_push(&port->state->port);
756}
757
758static void max310x_handle_tx(struct uart_port *port)
759{
760 struct circ_buf *xmit = &port->state->xmit;
761 unsigned int txlen, to_send, until_end;
762
763 if (unlikely(port->x_char)) {
764 max310x_port_write(port, MAX310X_THR_REG, port->x_char);
765 port->icount.tx++;
766 port->x_char = 0;
767 return;
768 }
769
770 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
771 return;
772
773 /* Get length of data pending in circular buffer */
774 to_send = uart_circ_chars_pending(xmit);
775 until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
776 if (likely(to_send)) {
777 /* Limit to size of TX FIFO */
778 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
779 txlen = port->fifosize - txlen;
780 to_send = (to_send > txlen) ? txlen : to_send;
781
782 if (until_end < to_send) {
783 /* It's a circ buffer -- wrap around.
784 * We could do that in one SPI transaction, but meh. */
785 max310x_batch_write(port, xmit->buf + xmit->tail, until_end);
786 max310x_batch_write(port, xmit->buf, to_send - until_end);
787 } else {
788 max310x_batch_write(port, xmit->buf + xmit->tail, to_send);
789 }
790 uart_xmit_advance(port, to_send);
791 }
792
793 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
794 uart_write_wakeup(port);
795}
796
797static void max310x_start_tx(struct uart_port *port)
798{
799 struct max310x_one *one = to_max310x_port(port);
800
801 schedule_work(&one->tx_work);
802}
803
804static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno)
805{
806 struct uart_port *port = &s->p[portno].port;
807 irqreturn_t res = IRQ_NONE;
808
809 do {
810 unsigned int ists, lsr, rxlen;
811
812 /* Read IRQ status & RX FIFO level */
813 ists = max310x_port_read(port, MAX310X_IRQSTS_REG);
814 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG);
815 if (!ists && !rxlen)
816 break;
817
818 res = IRQ_HANDLED;
819
820 if (ists & MAX310X_IRQ_CTS_BIT) {
821 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
822 uart_handle_cts_change(port,
823 !!(lsr & MAX310X_LSR_CTS_BIT));
824 }
825 if (rxlen)
826 max310x_handle_rx(port, rxlen);
827 if (ists & MAX310X_IRQ_TXEMPTY_BIT)
828 max310x_start_tx(port);
829 } while (1);
830 return res;
831}
832
833static irqreturn_t max310x_ist(int irq, void *dev_id)
834{
835 struct max310x_port *s = (struct max310x_port *)dev_id;
836 bool handled = false;
837
838 if (s->devtype->nr > 1) {
839 do {
840 unsigned int val = ~0;
841
842 WARN_ON_ONCE(regmap_read(s->regmap,
843 MAX310X_GLOBALIRQ_REG, &val));
844 val = ((1 << s->devtype->nr) - 1) & ~val;
845 if (!val)
846 break;
847 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED)
848 handled = true;
849 } while (1);
850 } else {
851 if (max310x_port_irq(s, 0) == IRQ_HANDLED)
852 handled = true;
853 }
854
855 return IRQ_RETVAL(handled);
856}
857
858static void max310x_tx_proc(struct work_struct *ws)
859{
860 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work);
861
862 max310x_handle_tx(&one->port);
863}
864
865static unsigned int max310x_tx_empty(struct uart_port *port)
866{
867 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
868
869 return lvl ? 0 : TIOCSER_TEMT;
870}
871
872static unsigned int max310x_get_mctrl(struct uart_port *port)
873{
874 /* DCD and DSR are not wired and CTS/RTS is handled automatically
875 * so just indicate DSR and CAR asserted
876 */
877 return TIOCM_DSR | TIOCM_CAR;
878}
879
880static void max310x_md_proc(struct work_struct *ws)
881{
882 struct max310x_one *one = container_of(ws, struct max310x_one, md_work);
883
884 max310x_port_update(&one->port, MAX310X_MODE2_REG,
885 MAX310X_MODE2_LOOPBACK_BIT,
886 (one->port.mctrl & TIOCM_LOOP) ?
887 MAX310X_MODE2_LOOPBACK_BIT : 0);
888}
889
890static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
891{
892 struct max310x_one *one = to_max310x_port(port);
893
894 schedule_work(&one->md_work);
895}
896
897static void max310x_break_ctl(struct uart_port *port, int break_state)
898{
899 max310x_port_update(port, MAX310X_LCR_REG,
900 MAX310X_LCR_TXBREAK_BIT,
901 break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
902}
903
904static void max310x_set_termios(struct uart_port *port,
905 struct ktermios *termios,
906 const struct ktermios *old)
907{
908 unsigned int lcr = 0, flow = 0;
909 int baud;
910
911 /* Mask termios capabilities we don't support */
912 termios->c_cflag &= ~CMSPAR;
913
914 /* Word size */
915 switch (termios->c_cflag & CSIZE) {
916 case CS5:
917 break;
918 case CS6:
919 lcr = MAX310X_LCR_LENGTH0_BIT;
920 break;
921 case CS7:
922 lcr = MAX310X_LCR_LENGTH1_BIT;
923 break;
924 case CS8:
925 default:
926 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT;
927 break;
928 }
929
930 /* Parity */
931 if (termios->c_cflag & PARENB) {
932 lcr |= MAX310X_LCR_PARITY_BIT;
933 if (!(termios->c_cflag & PARODD))
934 lcr |= MAX310X_LCR_EVENPARITY_BIT;
935 }
936
937 /* Stop bits */
938 if (termios->c_cflag & CSTOPB)
939 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */
940
941 /* Update LCR register */
942 max310x_port_write(port, MAX310X_LCR_REG, lcr);
943
944 /* Set read status mask */
945 port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
946 if (termios->c_iflag & INPCK)
947 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
948 MAX310X_LSR_FRERR_BIT;
949 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
950 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
951
952 /* Set status ignore mask */
953 port->ignore_status_mask = 0;
954 if (termios->c_iflag & IGNBRK)
955 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
956 if (!(termios->c_cflag & CREAD))
957 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
958 MAX310X_LSR_RXOVR_BIT |
959 MAX310X_LSR_FRERR_BIT |
960 MAX310X_LSR_RXBRK_BIT;
961
962 /* Configure flow control */
963 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
964 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
965
966 /* Disable transmitter before enabling AutoCTS or auto transmitter
967 * flow control
968 */
969 if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) {
970 max310x_port_update(port, MAX310X_MODE1_REG,
971 MAX310X_MODE1_TXDIS_BIT,
972 MAX310X_MODE1_TXDIS_BIT);
973 }
974
975 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
976
977 if (termios->c_cflag & CRTSCTS) {
978 /* Enable AUTORTS and AUTOCTS */
979 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
980 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
981 MAX310X_FLOWCTRL_AUTORTS_BIT;
982 }
983 if (termios->c_iflag & IXON)
984 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
985 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
986 if (termios->c_iflag & IXOFF) {
987 port->status |= UPSTAT_AUTOXOFF;
988 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
989 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
990 }
991 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);
992
993 /* Enable transmitter after disabling AutoCTS and auto transmitter
994 * flow control
995 */
996 if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) {
997 max310x_port_update(port, MAX310X_MODE1_REG,
998 MAX310X_MODE1_TXDIS_BIT,
999 0);
1000 }
1001
1002 /* Get baud rate generator configuration */
1003 baud = uart_get_baud_rate(port, termios, old,
1004 port->uartclk / 16 / 0xffff,
1005 port->uartclk / 4);
1006
1007 /* Setup baudrate generator */
1008 baud = max310x_set_baud(port, baud);
1009
1010 /* Update timeout according to new baud rate */
1011 uart_update_timeout(port, termios->c_cflag, baud);
1012}
1013
1014static void max310x_rs_proc(struct work_struct *ws)
1015{
1016 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work);
1017 unsigned int delay, mode1 = 0, mode2 = 0;
1018
1019 delay = (one->port.rs485.delay_rts_before_send << 4) |
1020 one->port.rs485.delay_rts_after_send;
1021 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay);
1022
1023 if (one->port.rs485.flags & SER_RS485_ENABLED) {
1024 mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT;
1025
1026 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX))
1027 mode2 = MAX310X_MODE2_ECHOSUPR_BIT;
1028 }
1029
1030 max310x_port_update(&one->port, MAX310X_MODE1_REG,
1031 MAX310X_MODE1_TRNSCVCTRL_BIT, mode1);
1032 max310x_port_update(&one->port, MAX310X_MODE2_REG,
1033 MAX310X_MODE2_ECHOSUPR_BIT, mode2);
1034}
1035
1036static int max310x_rs485_config(struct uart_port *port, struct ktermios *termios,
1037 struct serial_rs485 *rs485)
1038{
1039 struct max310x_one *one = to_max310x_port(port);
1040
1041 if ((rs485->delay_rts_before_send > 0x0f) ||
1042 (rs485->delay_rts_after_send > 0x0f))
1043 return -ERANGE;
1044
1045 port->rs485 = *rs485;
1046
1047 schedule_work(&one->rs_work);
1048
1049 return 0;
1050}
1051
1052static int max310x_startup(struct uart_port *port)
1053{
1054 struct max310x_port *s = dev_get_drvdata(port->dev);
1055 unsigned int val;
1056
1057 s->devtype->power(port, 1);
1058
1059 /* Configure MODE1 register */
1060 max310x_port_update(port, MAX310X_MODE1_REG,
1061 MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
1062
1063 /* Configure MODE2 register & Reset FIFOs*/
1064 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT;
1065 max310x_port_write(port, MAX310X_MODE2_REG, val);
1066 max310x_port_update(port, MAX310X_MODE2_REG,
1067 MAX310X_MODE2_FIFORST_BIT, 0);
1068
1069 /* Configure mode1/mode2 to have rs485/rs232 enabled at startup */
1070 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) |
1071 clamp(port->rs485.delay_rts_after_send, 0U, 15U);
1072 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val);
1073
1074 if (port->rs485.flags & SER_RS485_ENABLED) {
1075 max310x_port_update(port, MAX310X_MODE1_REG,
1076 MAX310X_MODE1_TRNSCVCTRL_BIT,
1077 MAX310X_MODE1_TRNSCVCTRL_BIT);
1078
1079 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
1080 max310x_port_update(port, MAX310X_MODE2_REG,
1081 MAX310X_MODE2_ECHOSUPR_BIT,
1082 MAX310X_MODE2_ECHOSUPR_BIT);
1083 }
1084
1085 /* Configure flow control levels */
1086 /* Flow control halt level 96, resume level 48 */
1087 max310x_port_write(port, MAX310X_FLOWLVL_REG,
1088 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96));
1089
1090 /* Clear IRQ status register */
1091 max310x_port_read(port, MAX310X_IRQSTS_REG);
1092
1093 /* Enable RX, TX, CTS change interrupts */
1094 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT;
1095 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);
1096
1097 return 0;
1098}
1099
1100static void max310x_shutdown(struct uart_port *port)
1101{
1102 struct max310x_port *s = dev_get_drvdata(port->dev);
1103
1104 /* Disable all interrupts */
1105 max310x_port_write(port, MAX310X_IRQEN_REG, 0);
1106
1107 s->devtype->power(port, 0);
1108}
1109
1110static const char *max310x_type(struct uart_port *port)
1111{
1112 struct max310x_port *s = dev_get_drvdata(port->dev);
1113
1114 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL;
1115}
1116
1117static int max310x_request_port(struct uart_port *port)
1118{
1119 /* Do nothing */
1120 return 0;
1121}
1122
1123static void max310x_config_port(struct uart_port *port, int flags)
1124{
1125 if (flags & UART_CONFIG_TYPE)
1126 port->type = PORT_MAX310X;
1127}
1128
1129static int max310x_verify_port(struct uart_port *port, struct serial_struct *s)
1130{
1131 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X))
1132 return -EINVAL;
1133 if (s->irq != port->irq)
1134 return -EINVAL;
1135
1136 return 0;
1137}
1138
1139static void max310x_null_void(struct uart_port *port)
1140{
1141 /* Do nothing */
1142}
1143
1144static const struct uart_ops max310x_ops = {
1145 .tx_empty = max310x_tx_empty,
1146 .set_mctrl = max310x_set_mctrl,
1147 .get_mctrl = max310x_get_mctrl,
1148 .stop_tx = max310x_null_void,
1149 .start_tx = max310x_start_tx,
1150 .stop_rx = max310x_null_void,
1151 .break_ctl = max310x_break_ctl,
1152 .startup = max310x_startup,
1153 .shutdown = max310x_shutdown,
1154 .set_termios = max310x_set_termios,
1155 .type = max310x_type,
1156 .request_port = max310x_request_port,
1157 .release_port = max310x_null_void,
1158 .config_port = max310x_config_port,
1159 .verify_port = max310x_verify_port,
1160};
1161
1162static int __maybe_unused max310x_suspend(struct device *dev)
1163{
1164 struct max310x_port *s = dev_get_drvdata(dev);
1165 int i;
1166
1167 for (i = 0; i < s->devtype->nr; i++) {
1168 uart_suspend_port(&max310x_uart, &s->p[i].port);
1169 s->devtype->power(&s->p[i].port, 0);
1170 }
1171
1172 return 0;
1173}
1174
1175static int __maybe_unused max310x_resume(struct device *dev)
1176{
1177 struct max310x_port *s = dev_get_drvdata(dev);
1178 int i;
1179
1180 for (i = 0; i < s->devtype->nr; i++) {
1181 s->devtype->power(&s->p[i].port, 1);
1182 uart_resume_port(&max310x_uart, &s->p[i].port);
1183 }
1184
1185 return 0;
1186}
1187
1188static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume);
1189
1190#ifdef CONFIG_GPIOLIB
1191static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset)
1192{
1193 unsigned int val;
1194 struct max310x_port *s = gpiochip_get_data(chip);
1195 struct uart_port *port = &s->p[offset / 4].port;
1196
1197 val = max310x_port_read(port, MAX310X_GPIODATA_REG);
1198
1199 return !!((val >> 4) & (1 << (offset % 4)));
1200}
1201
1202static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1203{
1204 struct max310x_port *s = gpiochip_get_data(chip);
1205 struct uart_port *port = &s->p[offset / 4].port;
1206
1207 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1208 value ? 1 << (offset % 4) : 0);
1209}
1210
1211static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1212{
1213 struct max310x_port *s = gpiochip_get_data(chip);
1214 struct uart_port *port = &s->p[offset / 4].port;
1215
1216 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0);
1217
1218 return 0;
1219}
1220
1221static int max310x_gpio_direction_output(struct gpio_chip *chip,
1222 unsigned offset, int value)
1223{
1224 struct max310x_port *s = gpiochip_get_data(chip);
1225 struct uart_port *port = &s->p[offset / 4].port;
1226
1227 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1228 value ? 1 << (offset % 4) : 0);
1229 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4),
1230 1 << (offset % 4));
1231
1232 return 0;
1233}
1234
1235static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
1236 unsigned long config)
1237{
1238 struct max310x_port *s = gpiochip_get_data(chip);
1239 struct uart_port *port = &s->p[offset / 4].port;
1240
1241 switch (pinconf_to_config_param(config)) {
1242 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1243 max310x_port_update(port, MAX310X_GPIOCFG_REG,
1244 1 << ((offset % 4) + 4),
1245 1 << ((offset % 4) + 4));
1246 return 0;
1247 case PIN_CONFIG_DRIVE_PUSH_PULL:
1248 max310x_port_update(port, MAX310X_GPIOCFG_REG,
1249 1 << ((offset % 4) + 4), 0);
1250 return 0;
1251 default:
1252 return -ENOTSUPP;
1253 }
1254}
1255#endif
1256
1257static const struct serial_rs485 max310x_rs485_supported = {
1258 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX,
1259 .delay_rts_before_send = 1,
1260 .delay_rts_after_send = 1,
1261};
1262
1263static int max310x_probe(struct device *dev, const struct max310x_devtype *devtype,
1264 const struct max310x_if_cfg *if_cfg,
1265 struct regmap *regmaps[], int irq)
1266{
1267 int i, ret, fmin, fmax, freq;
1268 struct max310x_port *s;
1269 u32 uartclk = 0;
1270 bool xtal;
1271
1272 for (i = 0; i < devtype->nr; i++)
1273 if (IS_ERR(regmaps[i]))
1274 return PTR_ERR(regmaps[i]);
1275
1276 /* Alloc port structure */
1277 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL);
1278 if (!s) {
1279 dev_err(dev, "Error allocating port structure\n");
1280 return -ENOMEM;
1281 }
1282
1283 /* Always ask for fixed clock rate from a property. */
1284 device_property_read_u32(dev, "clock-frequency", &uartclk);
1285
1286 xtal = device_property_match_string(dev, "clock-names", "osc") < 0;
1287 if (xtal)
1288 s->clk = devm_clk_get_optional(dev, "xtal");
1289 else
1290 s->clk = devm_clk_get_optional(dev, "osc");
1291 if (IS_ERR(s->clk))
1292 return PTR_ERR(s->clk);
1293
1294 ret = clk_prepare_enable(s->clk);
1295 if (ret)
1296 return ret;
1297
1298 freq = clk_get_rate(s->clk);
1299 if (freq == 0)
1300 freq = uartclk;
1301 if (freq == 0) {
1302 dev_err(dev, "Cannot get clock rate\n");
1303 ret = -EINVAL;
1304 goto out_clk;
1305 }
1306
1307 if (xtal) {
1308 fmin = 1000000;
1309 fmax = 4000000;
1310 } else {
1311 fmin = 500000;
1312 fmax = 35000000;
1313 }
1314
1315 /* Check frequency limits */
1316 if (freq < fmin || freq > fmax) {
1317 ret = -ERANGE;
1318 goto out_clk;
1319 }
1320
1321 s->regmap = regmaps[0];
1322 s->devtype = devtype;
1323 s->if_cfg = if_cfg;
1324 dev_set_drvdata(dev, s);
1325
1326 /* Check device to ensure we are talking to what we expect */
1327 ret = devtype->detect(dev);
1328 if (ret)
1329 goto out_clk;
1330
1331 for (i = 0; i < devtype->nr; i++) {
1332 /* Reset port */
1333 regmap_write(regmaps[i], MAX310X_MODE2_REG,
1334 MAX310X_MODE2_RST_BIT);
1335 /* Clear port reset */
1336 regmap_write(regmaps[i], MAX310X_MODE2_REG, 0);
1337
1338 /* Wait for port startup */
1339 do {
1340 regmap_read(regmaps[i], MAX310X_BRGDIVLSB_REG, &ret);
1341 } while (ret != 0x01);
1342
1343 regmap_write(regmaps[i], MAX310X_MODE1_REG, devtype->mode1);
1344 }
1345
1346 uartclk = max310x_set_ref_clk(dev, s, freq, xtal);
1347 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
1348
1349 for (i = 0; i < devtype->nr; i++) {
1350 unsigned int line;
1351
1352 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX);
1353 if (line == MAX310X_UART_NRMAX) {
1354 ret = -ERANGE;
1355 goto out_uart;
1356 }
1357
1358 /* Initialize port data */
1359 s->p[i].port.line = line;
1360 s->p[i].port.dev = dev;
1361 s->p[i].port.irq = irq;
1362 s->p[i].port.type = PORT_MAX310X;
1363 s->p[i].port.fifosize = MAX310X_FIFO_SIZE;
1364 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1365 s->p[i].port.iotype = UPIO_PORT;
1366 s->p[i].port.iobase = i;
1367 s->p[i].port.membase = (void __iomem *)~0;
1368 s->p[i].port.uartclk = uartclk;
1369 s->p[i].port.rs485_config = max310x_rs485_config;
1370 s->p[i].port.rs485_supported = max310x_rs485_supported;
1371 s->p[i].port.ops = &max310x_ops;
1372 s->p[i].regmap = regmaps[i];
1373
1374 /* Disable all interrupts */
1375 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
1376 /* Clear IRQ status register */
1377 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
1378 /* Initialize queue for start TX */
1379 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc);
1380 /* Initialize queue for changing LOOPBACK mode */
1381 INIT_WORK(&s->p[i].md_work, max310x_md_proc);
1382 /* Initialize queue for changing RS485 mode */
1383 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc);
1384
1385 /* Register port */
1386 ret = uart_add_one_port(&max310x_uart, &s->p[i].port);
1387 if (ret) {
1388 s->p[i].port.dev = NULL;
1389 goto out_uart;
1390 }
1391 set_bit(line, max310x_lines);
1392
1393 /* Go to suspend mode */
1394 devtype->power(&s->p[i].port, 0);
1395 }
1396
1397#ifdef CONFIG_GPIOLIB
1398 /* Setup GPIO cotroller */
1399 s->gpio.owner = THIS_MODULE;
1400 s->gpio.parent = dev;
1401 s->gpio.label = devtype->name;
1402 s->gpio.direction_input = max310x_gpio_direction_input;
1403 s->gpio.get = max310x_gpio_get;
1404 s->gpio.direction_output= max310x_gpio_direction_output;
1405 s->gpio.set = max310x_gpio_set;
1406 s->gpio.set_config = max310x_gpio_set_config;
1407 s->gpio.base = -1;
1408 s->gpio.ngpio = devtype->nr * 4;
1409 s->gpio.can_sleep = 1;
1410 ret = devm_gpiochip_add_data(dev, &s->gpio, s);
1411 if (ret)
1412 goto out_uart;
1413#endif
1414
1415 /* Setup interrupt */
1416 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist,
1417 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s);
1418 if (!ret)
1419 return 0;
1420
1421 dev_err(dev, "Unable to reguest IRQ %i\n", irq);
1422
1423out_uart:
1424 for (i = 0; i < devtype->nr; i++) {
1425 if (s->p[i].port.dev) {
1426 uart_remove_one_port(&max310x_uart, &s->p[i].port);
1427 clear_bit(s->p[i].port.line, max310x_lines);
1428 }
1429 }
1430
1431out_clk:
1432 clk_disable_unprepare(s->clk);
1433
1434 return ret;
1435}
1436
1437static void max310x_remove(struct device *dev)
1438{
1439 struct max310x_port *s = dev_get_drvdata(dev);
1440 int i;
1441
1442 for (i = 0; i < s->devtype->nr; i++) {
1443 cancel_work_sync(&s->p[i].tx_work);
1444 cancel_work_sync(&s->p[i].md_work);
1445 cancel_work_sync(&s->p[i].rs_work);
1446 uart_remove_one_port(&max310x_uart, &s->p[i].port);
1447 clear_bit(s->p[i].port.line, max310x_lines);
1448 s->devtype->power(&s->p[i].port, 0);
1449 }
1450
1451 clk_disable_unprepare(s->clk);
1452}
1453
1454static const struct of_device_id __maybe_unused max310x_dt_ids[] = {
1455 { .compatible = "maxim,max3107", .data = &max3107_devtype, },
1456 { .compatible = "maxim,max3108", .data = &max3108_devtype, },
1457 { .compatible = "maxim,max3109", .data = &max3109_devtype, },
1458 { .compatible = "maxim,max14830", .data = &max14830_devtype },
1459 { }
1460};
1461MODULE_DEVICE_TABLE(of, max310x_dt_ids);
1462
1463static struct regmap_config regcfg = {
1464 .reg_bits = 8,
1465 .val_bits = 8,
1466 .write_flag_mask = MAX310X_WRITE_BIT,
1467 .cache_type = REGCACHE_RBTREE,
1468 .max_register = MAX310X_REG_1F,
1469 .writeable_reg = max310x_reg_writeable,
1470 .volatile_reg = max310x_reg_volatile,
1471 .precious_reg = max310x_reg_precious,
1472};
1473
1474#ifdef CONFIG_SPI_MASTER
1475static int max310x_spi_extended_reg_enable(struct device *dev, bool enable)
1476{
1477 struct max310x_port *s = dev_get_drvdata(dev);
1478
1479 return regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
1480 enable ? MAX310X_EXTREG_ENBL : MAX310X_EXTREG_DSBL);
1481}
1482
1483static const struct max310x_if_cfg __maybe_unused max310x_spi_if_cfg = {
1484 .extended_reg_enable = max310x_spi_extended_reg_enable,
1485 .rev_id_reg = MAX310X_SPI_REVID_EXTREG,
1486};
1487
1488static int max310x_spi_probe(struct spi_device *spi)
1489{
1490 const struct max310x_devtype *devtype;
1491 struct regmap *regmaps[4];
1492 unsigned int i;
1493 int ret;
1494
1495 /* Setup SPI bus */
1496 spi->bits_per_word = 8;
1497 spi->mode = spi->mode ? : SPI_MODE_0;
1498 spi->max_speed_hz = spi->max_speed_hz ? : 26000000;
1499 ret = spi_setup(spi);
1500 if (ret)
1501 return ret;
1502
1503 devtype = device_get_match_data(&spi->dev);
1504 if (!devtype)
1505 devtype = (struct max310x_devtype *)spi_get_device_id(spi)->driver_data;
1506
1507 for (i = 0; i < devtype->nr; i++) {
1508 u8 port_mask = i * 0x20;
1509 regcfg.read_flag_mask = port_mask;
1510 regcfg.write_flag_mask = port_mask | MAX310X_WRITE_BIT;
1511 regmaps[i] = devm_regmap_init_spi(spi, ®cfg);
1512 }
1513
1514 return max310x_probe(&spi->dev, devtype, &max310x_spi_if_cfg, regmaps, spi->irq);
1515}
1516
1517static void max310x_spi_remove(struct spi_device *spi)
1518{
1519 max310x_remove(&spi->dev);
1520}
1521
1522static const struct spi_device_id max310x_id_table[] = {
1523 { "max3107", (kernel_ulong_t)&max3107_devtype, },
1524 { "max3108", (kernel_ulong_t)&max3108_devtype, },
1525 { "max3109", (kernel_ulong_t)&max3109_devtype, },
1526 { "max14830", (kernel_ulong_t)&max14830_devtype, },
1527 { }
1528};
1529MODULE_DEVICE_TABLE(spi, max310x_id_table);
1530
1531static struct spi_driver max310x_spi_driver = {
1532 .driver = {
1533 .name = MAX310X_NAME,
1534 .of_match_table = max310x_dt_ids,
1535 .pm = &max310x_pm_ops,
1536 },
1537 .probe = max310x_spi_probe,
1538 .remove = max310x_spi_remove,
1539 .id_table = max310x_id_table,
1540};
1541#endif
1542
1543#ifdef CONFIG_I2C
1544static int max310x_i2c_extended_reg_enable(struct device *dev, bool enable)
1545{
1546 return 0;
1547}
1548
1549static struct regmap_config regcfg_i2c = {
1550 .reg_bits = 8,
1551 .val_bits = 8,
1552 .cache_type = REGCACHE_RBTREE,
1553 .writeable_reg = max310x_reg_writeable,
1554 .volatile_reg = max310x_reg_volatile,
1555 .precious_reg = max310x_reg_precious,
1556 .max_register = MAX310X_I2C_REVID_EXTREG,
1557};
1558
1559static const struct max310x_if_cfg max310x_i2c_if_cfg = {
1560 .extended_reg_enable = max310x_i2c_extended_reg_enable,
1561 .rev_id_reg = MAX310X_I2C_REVID_EXTREG,
1562};
1563
1564static unsigned short max310x_i2c_slave_addr(unsigned short addr,
1565 unsigned int nr)
1566{
1567 /*
1568 * For MAX14830 and MAX3109, the slave address depends on what the
1569 * A0 and A1 pins are tied to.
1570 * See Table I2C Address Map of the datasheet.
1571 * Based on that table, the following formulas were determined.
1572 * UART1 - UART0 = 0x10
1573 * UART2 - UART1 = 0x20 + 0x10
1574 * UART3 - UART2 = 0x10
1575 */
1576
1577 addr -= nr * 0x10;
1578
1579 if (nr >= 2)
1580 addr -= 0x20;
1581
1582 return addr;
1583}
1584
1585static int max310x_i2c_probe(struct i2c_client *client)
1586{
1587 const struct max310x_devtype *devtype =
1588 device_get_match_data(&client->dev);
1589 struct i2c_client *port_client;
1590 struct regmap *regmaps[4];
1591 unsigned int i;
1592 u8 port_addr;
1593
1594 if (client->addr < devtype->slave_addr.min ||
1595 client->addr > devtype->slave_addr.max)
1596 return dev_err_probe(&client->dev, -EINVAL,
1597 "Slave addr 0x%x outside of range [0x%x, 0x%x]\n",
1598 client->addr, devtype->slave_addr.min,
1599 devtype->slave_addr.max);
1600
1601 regmaps[0] = devm_regmap_init_i2c(client, ®cfg_i2c);
1602
1603 for (i = 1; i < devtype->nr; i++) {
1604 port_addr = max310x_i2c_slave_addr(client->addr, i);
1605 port_client = devm_i2c_new_dummy_device(&client->dev,
1606 client->adapter,
1607 port_addr);
1608
1609 regmaps[i] = devm_regmap_init_i2c(port_client, ®cfg_i2c);
1610 }
1611
1612 return max310x_probe(&client->dev, devtype, &max310x_i2c_if_cfg,
1613 regmaps, client->irq);
1614}
1615
1616static void max310x_i2c_remove(struct i2c_client *client)
1617{
1618 max310x_remove(&client->dev);
1619}
1620
1621static struct i2c_driver max310x_i2c_driver = {
1622 .driver = {
1623 .name = MAX310X_NAME,
1624 .of_match_table = max310x_dt_ids,
1625 .pm = &max310x_pm_ops,
1626 },
1627 .probe_new = max310x_i2c_probe,
1628 .remove = max310x_i2c_remove,
1629};
1630#endif
1631
1632static int __init max310x_uart_init(void)
1633{
1634 int ret;
1635
1636 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX);
1637
1638 ret = uart_register_driver(&max310x_uart);
1639 if (ret)
1640 return ret;
1641
1642#ifdef CONFIG_SPI_MASTER
1643 ret = spi_register_driver(&max310x_spi_driver);
1644 if (ret)
1645 goto err_spi_register;
1646#endif
1647
1648#ifdef CONFIG_I2C
1649 ret = i2c_add_driver(&max310x_i2c_driver);
1650 if (ret)
1651 goto err_i2c_register;
1652#endif
1653
1654 return 0;
1655
1656#ifdef CONFIG_I2C
1657err_i2c_register:
1658 spi_unregister_driver(&max310x_spi_driver);
1659#endif
1660
1661err_spi_register:
1662 uart_unregister_driver(&max310x_uart);
1663
1664 return ret;
1665}
1666module_init(max310x_uart_init);
1667
1668static void __exit max310x_uart_exit(void)
1669{
1670#ifdef CONFIG_I2C
1671 i2c_del_driver(&max310x_i2c_driver);
1672#endif
1673
1674#ifdef CONFIG_SPI_MASTER
1675 spi_unregister_driver(&max310x_spi_driver);
1676#endif
1677
1678 uart_unregister_driver(&max310x_uart);
1679}
1680module_exit(max310x_uart_exit);
1681
1682MODULE_LICENSE("GPL");
1683MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1684MODULE_DESCRIPTION("MAX310X serial driver");