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1/*
2 * Copyright (c) 2011 Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * All enquiries to support@picochip.com
9 */
10#include <linux/gpio/driver.h>
11/* FIXME: for gpio_get_value(), replace this with direct register read */
12#include <linux/gpio.h>
13#include <linux/err.h>
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/ioport.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
24#include <linux/platform_device.h>
25#include <linux/spinlock.h>
26#include <linux/platform_data/gpio-dwapb.h>
27#include <linux/slab.h>
28
29#define GPIO_SWPORTA_DR 0x00
30#define GPIO_SWPORTA_DDR 0x04
31#define GPIO_SWPORTB_DR 0x0c
32#define GPIO_SWPORTB_DDR 0x10
33#define GPIO_SWPORTC_DR 0x18
34#define GPIO_SWPORTC_DDR 0x1c
35#define GPIO_SWPORTD_DR 0x24
36#define GPIO_SWPORTD_DDR 0x28
37#define GPIO_INTEN 0x30
38#define GPIO_INTMASK 0x34
39#define GPIO_INTTYPE_LEVEL 0x38
40#define GPIO_INT_POLARITY 0x3c
41#define GPIO_INTSTATUS 0x40
42#define GPIO_PORTA_DEBOUNCE 0x48
43#define GPIO_PORTA_EOI 0x4c
44#define GPIO_EXT_PORTA 0x50
45#define GPIO_EXT_PORTB 0x54
46#define GPIO_EXT_PORTC 0x58
47#define GPIO_EXT_PORTD 0x5c
48
49#define DWAPB_MAX_PORTS 4
50#define GPIO_EXT_PORT_SIZE (GPIO_EXT_PORTB - GPIO_EXT_PORTA)
51#define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
52#define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)
53
54struct dwapb_gpio;
55
56#ifdef CONFIG_PM_SLEEP
57/* Store GPIO context across system-wide suspend/resume transitions */
58struct dwapb_context {
59 u32 data;
60 u32 dir;
61 u32 ext;
62 u32 int_en;
63 u32 int_mask;
64 u32 int_type;
65 u32 int_pol;
66 u32 int_deb;
67};
68#endif
69
70struct dwapb_gpio_port {
71 struct gpio_chip gc;
72 bool is_registered;
73 struct dwapb_gpio *gpio;
74#ifdef CONFIG_PM_SLEEP
75 struct dwapb_context *ctx;
76#endif
77 unsigned int idx;
78};
79
80struct dwapb_gpio {
81 struct device *dev;
82 void __iomem *regs;
83 struct dwapb_gpio_port *ports;
84 unsigned int nr_ports;
85 struct irq_domain *domain;
86};
87
88static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
89{
90 struct gpio_chip *gc = &gpio->ports[0].gc;
91 void __iomem *reg_base = gpio->regs;
92
93 return gc->read_reg(reg_base + offset);
94}
95
96static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
97 u32 val)
98{
99 struct gpio_chip *gc = &gpio->ports[0].gc;
100 void __iomem *reg_base = gpio->regs;
101
102 gc->write_reg(reg_base + offset, val);
103}
104
105static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
106{
107 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
108 struct dwapb_gpio *gpio = port->gpio;
109
110 return irq_find_mapping(gpio->domain, offset);
111}
112
113static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
114{
115 u32 v = dwapb_read(gpio, GPIO_INT_POLARITY);
116
117 if (gpio_get_value(gpio->ports[0].gc.base + offs))
118 v &= ~BIT(offs);
119 else
120 v |= BIT(offs);
121
122 dwapb_write(gpio, GPIO_INT_POLARITY, v);
123}
124
125static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
126{
127 u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS);
128 u32 ret = irq_status;
129
130 while (irq_status) {
131 int hwirq = fls(irq_status) - 1;
132 int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
133
134 generic_handle_irq(gpio_irq);
135 irq_status &= ~BIT(hwirq);
136
137 if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
138 == IRQ_TYPE_EDGE_BOTH)
139 dwapb_toggle_trigger(gpio, hwirq);
140 }
141
142 return ret;
143}
144
145static void dwapb_irq_handler(struct irq_desc *desc)
146{
147 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
148 struct irq_chip *chip = irq_desc_get_chip(desc);
149
150 dwapb_do_irq(gpio);
151
152 if (chip->irq_eoi)
153 chip->irq_eoi(irq_desc_get_irq_data(desc));
154}
155
156static void dwapb_irq_enable(struct irq_data *d)
157{
158 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
159 struct dwapb_gpio *gpio = igc->private;
160 struct gpio_chip *gc = &gpio->ports[0].gc;
161 unsigned long flags;
162 u32 val;
163
164 spin_lock_irqsave(&gc->bgpio_lock, flags);
165 val = dwapb_read(gpio, GPIO_INTEN);
166 val |= BIT(d->hwirq);
167 dwapb_write(gpio, GPIO_INTEN, val);
168 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
169}
170
171static void dwapb_irq_disable(struct irq_data *d)
172{
173 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
174 struct dwapb_gpio *gpio = igc->private;
175 struct gpio_chip *gc = &gpio->ports[0].gc;
176 unsigned long flags;
177 u32 val;
178
179 spin_lock_irqsave(&gc->bgpio_lock, flags);
180 val = dwapb_read(gpio, GPIO_INTEN);
181 val &= ~BIT(d->hwirq);
182 dwapb_write(gpio, GPIO_INTEN, val);
183 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
184}
185
186static int dwapb_irq_reqres(struct irq_data *d)
187{
188 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
189 struct dwapb_gpio *gpio = igc->private;
190 struct gpio_chip *gc = &gpio->ports[0].gc;
191
192 if (gpiochip_lock_as_irq(gc, irqd_to_hwirq(d))) {
193 dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
194 irqd_to_hwirq(d));
195 return -EINVAL;
196 }
197 return 0;
198}
199
200static void dwapb_irq_relres(struct irq_data *d)
201{
202 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
203 struct dwapb_gpio *gpio = igc->private;
204 struct gpio_chip *gc = &gpio->ports[0].gc;
205
206 gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d));
207}
208
209static int dwapb_irq_set_type(struct irq_data *d, u32 type)
210{
211 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
212 struct dwapb_gpio *gpio = igc->private;
213 struct gpio_chip *gc = &gpio->ports[0].gc;
214 int bit = d->hwirq;
215 unsigned long level, polarity, flags;
216
217 if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
218 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
219 return -EINVAL;
220
221 spin_lock_irqsave(&gc->bgpio_lock, flags);
222 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
223 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
224
225 switch (type) {
226 case IRQ_TYPE_EDGE_BOTH:
227 level |= BIT(bit);
228 dwapb_toggle_trigger(gpio, bit);
229 break;
230 case IRQ_TYPE_EDGE_RISING:
231 level |= BIT(bit);
232 polarity |= BIT(bit);
233 break;
234 case IRQ_TYPE_EDGE_FALLING:
235 level |= BIT(bit);
236 polarity &= ~BIT(bit);
237 break;
238 case IRQ_TYPE_LEVEL_HIGH:
239 level &= ~BIT(bit);
240 polarity |= BIT(bit);
241 break;
242 case IRQ_TYPE_LEVEL_LOW:
243 level &= ~BIT(bit);
244 polarity &= ~BIT(bit);
245 break;
246 }
247
248 irq_setup_alt_chip(d, type);
249
250 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
251 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
252 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
253
254 return 0;
255}
256
257static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
258 unsigned offset, unsigned debounce)
259{
260 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
261 struct dwapb_gpio *gpio = port->gpio;
262 unsigned long flags, val_deb;
263 unsigned long mask = gc->pin2mask(gc, offset);
264
265 spin_lock_irqsave(&gc->bgpio_lock, flags);
266
267 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
268 if (debounce)
269 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask);
270 else
271 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
272
273 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
274
275 return 0;
276}
277
278static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
279{
280 u32 worked;
281 struct dwapb_gpio *gpio = dev_id;
282
283 worked = dwapb_do_irq(gpio);
284
285 return worked ? IRQ_HANDLED : IRQ_NONE;
286}
287
288static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
289 struct dwapb_gpio_port *port,
290 struct dwapb_port_property *pp)
291{
292 struct gpio_chip *gc = &port->gc;
293 struct device_node *node = pp->node;
294 struct irq_chip_generic *irq_gc = NULL;
295 unsigned int hwirq, ngpio = gc->ngpio;
296 struct irq_chip_type *ct;
297 int err, i;
298
299 gpio->domain = irq_domain_add_linear(node, ngpio,
300 &irq_generic_chip_ops, gpio);
301 if (!gpio->domain)
302 return;
303
304 err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
305 "gpio-dwapb", handle_level_irq,
306 IRQ_NOREQUEST, 0,
307 IRQ_GC_INIT_NESTED_LOCK);
308 if (err) {
309 dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
310 irq_domain_remove(gpio->domain);
311 gpio->domain = NULL;
312 return;
313 }
314
315 irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
316 if (!irq_gc) {
317 irq_domain_remove(gpio->domain);
318 gpio->domain = NULL;
319 return;
320 }
321
322 irq_gc->reg_base = gpio->regs;
323 irq_gc->private = gpio;
324
325 for (i = 0; i < 2; i++) {
326 ct = &irq_gc->chip_types[i];
327 ct->chip.irq_ack = irq_gc_ack_set_bit;
328 ct->chip.irq_mask = irq_gc_mask_set_bit;
329 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
330 ct->chip.irq_set_type = dwapb_irq_set_type;
331 ct->chip.irq_enable = dwapb_irq_enable;
332 ct->chip.irq_disable = dwapb_irq_disable;
333 ct->chip.irq_request_resources = dwapb_irq_reqres;
334 ct->chip.irq_release_resources = dwapb_irq_relres;
335 ct->regs.ack = GPIO_PORTA_EOI;
336 ct->regs.mask = GPIO_INTMASK;
337 ct->type = IRQ_TYPE_LEVEL_MASK;
338 }
339
340 irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
341 irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
342 irq_gc->chip_types[1].handler = handle_edge_irq;
343
344 if (!pp->irq_shared) {
345 irq_set_chained_handler_and_data(pp->irq, dwapb_irq_handler,
346 gpio);
347 } else {
348 /*
349 * Request a shared IRQ since where MFD would have devices
350 * using the same irq pin
351 */
352 err = devm_request_irq(gpio->dev, pp->irq,
353 dwapb_irq_handler_mfd,
354 IRQF_SHARED, "gpio-dwapb-mfd", gpio);
355 if (err) {
356 dev_err(gpio->dev, "error requesting IRQ\n");
357 irq_domain_remove(gpio->domain);
358 gpio->domain = NULL;
359 return;
360 }
361 }
362
363 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
364 irq_create_mapping(gpio->domain, hwirq);
365
366 port->gc.to_irq = dwapb_gpio_to_irq;
367}
368
369static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
370{
371 struct dwapb_gpio_port *port = &gpio->ports[0];
372 struct gpio_chip *gc = &port->gc;
373 unsigned int ngpio = gc->ngpio;
374 irq_hw_number_t hwirq;
375
376 if (!gpio->domain)
377 return;
378
379 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
380 irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
381
382 irq_domain_remove(gpio->domain);
383 gpio->domain = NULL;
384}
385
386static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
387 struct dwapb_port_property *pp,
388 unsigned int offs)
389{
390 struct dwapb_gpio_port *port;
391 void __iomem *dat, *set, *dirout;
392 int err;
393
394 port = &gpio->ports[offs];
395 port->gpio = gpio;
396 port->idx = pp->idx;
397
398#ifdef CONFIG_PM_SLEEP
399 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
400 if (!port->ctx)
401 return -ENOMEM;
402#endif
403
404 dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_SIZE);
405 set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_SIZE);
406 dirout = gpio->regs + GPIO_SWPORTA_DDR +
407 (pp->idx * GPIO_SWPORT_DDR_SIZE);
408
409 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
410 NULL, false);
411 if (err) {
412 dev_err(gpio->dev, "failed to init gpio chip for %s\n",
413 pp->name);
414 return err;
415 }
416
417#ifdef CONFIG_OF_GPIO
418 port->gc.of_node = pp->node;
419#endif
420 port->gc.ngpio = pp->ngpio;
421 port->gc.base = pp->gpio_base;
422
423 /* Only port A support debounce */
424 if (pp->idx == 0)
425 port->gc.set_debounce = dwapb_gpio_set_debounce;
426
427 if (pp->irq)
428 dwapb_configure_irqs(gpio, port, pp);
429
430 err = gpiochip_add_data(&port->gc, port);
431 if (err)
432 dev_err(gpio->dev, "failed to register gpiochip for %s\n",
433 pp->name);
434 else
435 port->is_registered = true;
436
437 return err;
438}
439
440static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
441{
442 unsigned int m;
443
444 for (m = 0; m < gpio->nr_ports; ++m)
445 if (gpio->ports[m].is_registered)
446 gpiochip_remove(&gpio->ports[m].gc);
447}
448
449static struct dwapb_platform_data *
450dwapb_gpio_get_pdata_of(struct device *dev)
451{
452 struct device_node *node, *port_np;
453 struct dwapb_platform_data *pdata;
454 struct dwapb_port_property *pp;
455 int nports;
456 int i;
457
458 node = dev->of_node;
459 if (!IS_ENABLED(CONFIG_OF_GPIO) || !node)
460 return ERR_PTR(-ENODEV);
461
462 nports = of_get_child_count(node);
463 if (nports == 0)
464 return ERR_PTR(-ENODEV);
465
466 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
467 if (!pdata)
468 return ERR_PTR(-ENOMEM);
469
470 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
471 if (!pdata->properties)
472 return ERR_PTR(-ENOMEM);
473
474 pdata->nports = nports;
475
476 i = 0;
477 for_each_child_of_node(node, port_np) {
478 pp = &pdata->properties[i++];
479 pp->node = port_np;
480
481 if (of_property_read_u32(port_np, "reg", &pp->idx) ||
482 pp->idx >= DWAPB_MAX_PORTS) {
483 dev_err(dev, "missing/invalid port index for %s\n",
484 port_np->full_name);
485 return ERR_PTR(-EINVAL);
486 }
487
488 if (of_property_read_u32(port_np, "snps,nr-gpios",
489 &pp->ngpio)) {
490 dev_info(dev, "failed to get number of gpios for %s\n",
491 port_np->full_name);
492 pp->ngpio = 32;
493 }
494
495 /*
496 * Only port A can provide interrupts in all configurations of
497 * the IP.
498 */
499 if (pp->idx == 0 &&
500 of_property_read_bool(port_np, "interrupt-controller")) {
501 pp->irq = irq_of_parse_and_map(port_np, 0);
502 if (!pp->irq) {
503 dev_warn(dev, "no irq for bank %s\n",
504 port_np->full_name);
505 }
506 }
507
508 pp->irq_shared = false;
509 pp->gpio_base = -1;
510 pp->name = port_np->full_name;
511 }
512
513 return pdata;
514}
515
516static int dwapb_gpio_probe(struct platform_device *pdev)
517{
518 unsigned int i;
519 struct resource *res;
520 struct dwapb_gpio *gpio;
521 int err;
522 struct device *dev = &pdev->dev;
523 struct dwapb_platform_data *pdata = dev_get_platdata(dev);
524
525 if (!pdata) {
526 pdata = dwapb_gpio_get_pdata_of(dev);
527 if (IS_ERR(pdata))
528 return PTR_ERR(pdata);
529 }
530
531 if (!pdata->nports)
532 return -ENODEV;
533
534 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
535 if (!gpio)
536 return -ENOMEM;
537
538 gpio->dev = &pdev->dev;
539 gpio->nr_ports = pdata->nports;
540
541 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
542 sizeof(*gpio->ports), GFP_KERNEL);
543 if (!gpio->ports)
544 return -ENOMEM;
545
546 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
547 gpio->regs = devm_ioremap_resource(&pdev->dev, res);
548 if (IS_ERR(gpio->regs))
549 return PTR_ERR(gpio->regs);
550
551 for (i = 0; i < gpio->nr_ports; i++) {
552 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
553 if (err)
554 goto out_unregister;
555 }
556 platform_set_drvdata(pdev, gpio);
557
558 return 0;
559
560out_unregister:
561 dwapb_gpio_unregister(gpio);
562 dwapb_irq_teardown(gpio);
563
564 return err;
565}
566
567static int dwapb_gpio_remove(struct platform_device *pdev)
568{
569 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
570
571 dwapb_gpio_unregister(gpio);
572 dwapb_irq_teardown(gpio);
573
574 return 0;
575}
576
577static const struct of_device_id dwapb_of_match[] = {
578 { .compatible = "snps,dw-apb-gpio" },
579 { /* Sentinel */ }
580};
581MODULE_DEVICE_TABLE(of, dwapb_of_match);
582
583#ifdef CONFIG_PM_SLEEP
584static int dwapb_gpio_suspend(struct device *dev)
585{
586 struct platform_device *pdev = to_platform_device(dev);
587 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
588 struct gpio_chip *gc = &gpio->ports[0].gc;
589 unsigned long flags;
590 int i;
591
592 spin_lock_irqsave(&gc->bgpio_lock, flags);
593 for (i = 0; i < gpio->nr_ports; i++) {
594 unsigned int offset;
595 unsigned int idx = gpio->ports[i].idx;
596 struct dwapb_context *ctx = gpio->ports[i].ctx;
597
598 BUG_ON(!ctx);
599
600 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
601 ctx->dir = dwapb_read(gpio, offset);
602
603 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
604 ctx->data = dwapb_read(gpio, offset);
605
606 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
607 ctx->ext = dwapb_read(gpio, offset);
608
609 /* Only port A can provide interrupts */
610 if (idx == 0) {
611 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
612 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
613 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
614 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
615 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
616
617 /* Mask out interrupts */
618 dwapb_write(gpio, GPIO_INTMASK, 0xffffffff);
619 }
620 }
621 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
622
623 return 0;
624}
625
626static int dwapb_gpio_resume(struct device *dev)
627{
628 struct platform_device *pdev = to_platform_device(dev);
629 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
630 struct gpio_chip *gc = &gpio->ports[0].gc;
631 unsigned long flags;
632 int i;
633
634 spin_lock_irqsave(&gc->bgpio_lock, flags);
635 for (i = 0; i < gpio->nr_ports; i++) {
636 unsigned int offset;
637 unsigned int idx = gpio->ports[i].idx;
638 struct dwapb_context *ctx = gpio->ports[i].ctx;
639
640 BUG_ON(!ctx);
641
642 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
643 dwapb_write(gpio, offset, ctx->data);
644
645 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
646 dwapb_write(gpio, offset, ctx->dir);
647
648 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
649 dwapb_write(gpio, offset, ctx->ext);
650
651 /* Only port A can provide interrupts */
652 if (idx == 0) {
653 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
654 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
655 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
656 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
657 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
658
659 /* Clear out spurious interrupts */
660 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
661 }
662 }
663 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
664
665 return 0;
666}
667#endif
668
669static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
670 dwapb_gpio_resume);
671
672static struct platform_driver dwapb_gpio_driver = {
673 .driver = {
674 .name = "gpio-dwapb",
675 .pm = &dwapb_gpio_pm_ops,
676 .of_match_table = of_match_ptr(dwapb_of_match),
677 },
678 .probe = dwapb_gpio_probe,
679 .remove = dwapb_gpio_remove,
680};
681
682module_platform_driver(dwapb_gpio_driver);
683
684MODULE_LICENSE("GPL");
685MODULE_AUTHOR("Jamie Iles");
686MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");