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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2011 Jamie Iles
4 *
5 * All enquiries to support@picochip.com
6 */
7#include <linux/acpi.h>
8#include <linux/clk.h>
9#include <linux/err.h>
10#include <linux/gpio/driver.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/ioport.h>
15#include <linux/irq.h>
16#include <linux/irqdomain.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_device.h>
21#include <linux/of_irq.h>
22#include <linux/platform_device.h>
23#include <linux/property.h>
24#include <linux/reset.h>
25#include <linux/spinlock.h>
26#include <linux/platform_data/gpio-dwapb.h>
27#include <linux/slab.h>
28
29#include "gpiolib.h"
30#include "gpiolib-acpi.h"
31
32#define GPIO_SWPORTA_DR 0x00
33#define GPIO_SWPORTA_DDR 0x04
34#define GPIO_SWPORTB_DR 0x0c
35#define GPIO_SWPORTB_DDR 0x10
36#define GPIO_SWPORTC_DR 0x18
37#define GPIO_SWPORTC_DDR 0x1c
38#define GPIO_SWPORTD_DR 0x24
39#define GPIO_SWPORTD_DDR 0x28
40#define GPIO_INTEN 0x30
41#define GPIO_INTMASK 0x34
42#define GPIO_INTTYPE_LEVEL 0x38
43#define GPIO_INT_POLARITY 0x3c
44#define GPIO_INTSTATUS 0x40
45#define GPIO_PORTA_DEBOUNCE 0x48
46#define GPIO_PORTA_EOI 0x4c
47#define GPIO_EXT_PORTA 0x50
48#define GPIO_EXT_PORTB 0x54
49#define GPIO_EXT_PORTC 0x58
50#define GPIO_EXT_PORTD 0x5c
51
52#define DWAPB_MAX_PORTS 4
53#define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */
54#define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */
55#define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */
56
57#define GPIO_REG_OFFSET_V2 1
58
59#define GPIO_INTMASK_V2 0x44
60#define GPIO_INTTYPE_LEVEL_V2 0x34
61#define GPIO_INT_POLARITY_V2 0x38
62#define GPIO_INTSTATUS_V2 0x3c
63#define GPIO_PORTA_EOI_V2 0x40
64
65struct dwapb_gpio;
66
67#ifdef CONFIG_PM_SLEEP
68/* Store GPIO context across system-wide suspend/resume transitions */
69struct dwapb_context {
70 u32 data;
71 u32 dir;
72 u32 ext;
73 u32 int_en;
74 u32 int_mask;
75 u32 int_type;
76 u32 int_pol;
77 u32 int_deb;
78 u32 wake_en;
79};
80#endif
81
82struct dwapb_gpio_port {
83 struct gpio_chip gc;
84 bool is_registered;
85 struct dwapb_gpio *gpio;
86#ifdef CONFIG_PM_SLEEP
87 struct dwapb_context *ctx;
88#endif
89 unsigned int idx;
90};
91
92struct dwapb_gpio {
93 struct device *dev;
94 void __iomem *regs;
95 struct dwapb_gpio_port *ports;
96 unsigned int nr_ports;
97 struct irq_domain *domain;
98 unsigned int flags;
99 struct reset_control *rst;
100 struct clk *clk;
101};
102
103static inline u32 gpio_reg_v2_convert(unsigned int offset)
104{
105 switch (offset) {
106 case GPIO_INTMASK:
107 return GPIO_INTMASK_V2;
108 case GPIO_INTTYPE_LEVEL:
109 return GPIO_INTTYPE_LEVEL_V2;
110 case GPIO_INT_POLARITY:
111 return GPIO_INT_POLARITY_V2;
112 case GPIO_INTSTATUS:
113 return GPIO_INTSTATUS_V2;
114 case GPIO_PORTA_EOI:
115 return GPIO_PORTA_EOI_V2;
116 }
117
118 return offset;
119}
120
121static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
122{
123 if (gpio->flags & GPIO_REG_OFFSET_V2)
124 return gpio_reg_v2_convert(offset);
125
126 return offset;
127}
128
129static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
130{
131 struct gpio_chip *gc = &gpio->ports[0].gc;
132 void __iomem *reg_base = gpio->regs;
133
134 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
135}
136
137static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
138 u32 val)
139{
140 struct gpio_chip *gc = &gpio->ports[0].gc;
141 void __iomem *reg_base = gpio->regs;
142
143 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
144}
145
146static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
147{
148 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
149 struct dwapb_gpio *gpio = port->gpio;
150
151 return irq_find_mapping(gpio->domain, offset);
152}
153
154static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
155{
156 struct dwapb_gpio_port *port;
157 int i;
158
159 for (i = 0; i < gpio->nr_ports; i++) {
160 port = &gpio->ports[i];
161 if (port->idx == offs / 32)
162 return port;
163 }
164
165 return NULL;
166}
167
168static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
169{
170 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
171 struct gpio_chip *gc;
172 u32 pol;
173 int val;
174
175 if (!port)
176 return;
177 gc = &port->gc;
178
179 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
180 /* Just read the current value right out of the data register */
181 val = gc->get(gc, offs % 32);
182 if (val)
183 pol &= ~BIT(offs);
184 else
185 pol |= BIT(offs);
186
187 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
188}
189
190static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
191{
192 u32 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
193 u32 ret = irq_status;
194
195 while (irq_status) {
196 int hwirq = fls(irq_status) - 1;
197 int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
198
199 generic_handle_irq(gpio_irq);
200 irq_status &= ~BIT(hwirq);
201
202 if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
203 == IRQ_TYPE_EDGE_BOTH)
204 dwapb_toggle_trigger(gpio, hwirq);
205 }
206
207 return ret;
208}
209
210static void dwapb_irq_handler(struct irq_desc *desc)
211{
212 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
213 struct irq_chip *chip = irq_desc_get_chip(desc);
214
215 dwapb_do_irq(gpio);
216
217 if (chip->irq_eoi)
218 chip->irq_eoi(irq_desc_get_irq_data(desc));
219}
220
221static void dwapb_irq_enable(struct irq_data *d)
222{
223 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
224 struct dwapb_gpio *gpio = igc->private;
225 struct gpio_chip *gc = &gpio->ports[0].gc;
226 unsigned long flags;
227 u32 val;
228
229 spin_lock_irqsave(&gc->bgpio_lock, flags);
230 val = dwapb_read(gpio, GPIO_INTEN);
231 val |= BIT(d->hwirq);
232 dwapb_write(gpio, GPIO_INTEN, val);
233 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
234}
235
236static void dwapb_irq_disable(struct irq_data *d)
237{
238 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
239 struct dwapb_gpio *gpio = igc->private;
240 struct gpio_chip *gc = &gpio->ports[0].gc;
241 unsigned long flags;
242 u32 val;
243
244 spin_lock_irqsave(&gc->bgpio_lock, flags);
245 val = dwapb_read(gpio, GPIO_INTEN);
246 val &= ~BIT(d->hwirq);
247 dwapb_write(gpio, GPIO_INTEN, val);
248 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
249}
250
251static int dwapb_irq_reqres(struct irq_data *d)
252{
253 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
254 struct dwapb_gpio *gpio = igc->private;
255 struct gpio_chip *gc = &gpio->ports[0].gc;
256 int ret;
257
258 ret = gpiochip_lock_as_irq(gc, irqd_to_hwirq(d));
259 if (ret) {
260 dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
261 irqd_to_hwirq(d));
262 return ret;
263 }
264 return 0;
265}
266
267static void dwapb_irq_relres(struct irq_data *d)
268{
269 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
270 struct dwapb_gpio *gpio = igc->private;
271 struct gpio_chip *gc = &gpio->ports[0].gc;
272
273 gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d));
274}
275
276static int dwapb_irq_set_type(struct irq_data *d, u32 type)
277{
278 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
279 struct dwapb_gpio *gpio = igc->private;
280 struct gpio_chip *gc = &gpio->ports[0].gc;
281 int bit = d->hwirq;
282 unsigned long level, polarity, flags;
283
284 if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
285 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
286 return -EINVAL;
287
288 spin_lock_irqsave(&gc->bgpio_lock, flags);
289 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
290 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
291
292 switch (type) {
293 case IRQ_TYPE_EDGE_BOTH:
294 level |= BIT(bit);
295 dwapb_toggle_trigger(gpio, bit);
296 break;
297 case IRQ_TYPE_EDGE_RISING:
298 level |= BIT(bit);
299 polarity |= BIT(bit);
300 break;
301 case IRQ_TYPE_EDGE_FALLING:
302 level |= BIT(bit);
303 polarity &= ~BIT(bit);
304 break;
305 case IRQ_TYPE_LEVEL_HIGH:
306 level &= ~BIT(bit);
307 polarity |= BIT(bit);
308 break;
309 case IRQ_TYPE_LEVEL_LOW:
310 level &= ~BIT(bit);
311 polarity &= ~BIT(bit);
312 break;
313 }
314
315 irq_setup_alt_chip(d, type);
316
317 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
318 if (type != IRQ_TYPE_EDGE_BOTH)
319 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
320 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
321
322 return 0;
323}
324
325#ifdef CONFIG_PM_SLEEP
326static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
327{
328 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
329 struct dwapb_gpio *gpio = igc->private;
330 struct dwapb_context *ctx = gpio->ports[0].ctx;
331
332 if (enable)
333 ctx->wake_en |= BIT(d->hwirq);
334 else
335 ctx->wake_en &= ~BIT(d->hwirq);
336
337 return 0;
338}
339#endif
340
341static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
342 unsigned offset, unsigned debounce)
343{
344 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
345 struct dwapb_gpio *gpio = port->gpio;
346 unsigned long flags, val_deb;
347 unsigned long mask = BIT(offset);
348
349 spin_lock_irqsave(&gc->bgpio_lock, flags);
350
351 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
352 if (debounce)
353 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask);
354 else
355 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
356
357 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
358
359 return 0;
360}
361
362static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
363 unsigned long config)
364{
365 u32 debounce;
366
367 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
368 return -ENOTSUPP;
369
370 debounce = pinconf_to_config_argument(config);
371 return dwapb_gpio_set_debounce(gc, offset, debounce);
372}
373
374static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
375{
376 u32 worked;
377 struct dwapb_gpio *gpio = dev_id;
378
379 worked = dwapb_do_irq(gpio);
380
381 return worked ? IRQ_HANDLED : IRQ_NONE;
382}
383
384static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
385 struct dwapb_gpio_port *port,
386 struct dwapb_port_property *pp)
387{
388 struct gpio_chip *gc = &port->gc;
389 struct fwnode_handle *fwnode = pp->fwnode;
390 struct irq_chip_generic *irq_gc = NULL;
391 unsigned int hwirq, ngpio = gc->ngpio;
392 struct irq_chip_type *ct;
393 int err, i;
394
395 gpio->domain = irq_domain_create_linear(fwnode, ngpio,
396 &irq_generic_chip_ops, gpio);
397 if (!gpio->domain)
398 return;
399
400 err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
401 "gpio-dwapb", handle_level_irq,
402 IRQ_NOREQUEST, 0,
403 IRQ_GC_INIT_NESTED_LOCK);
404 if (err) {
405 dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
406 irq_domain_remove(gpio->domain);
407 gpio->domain = NULL;
408 return;
409 }
410
411 irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
412 if (!irq_gc) {
413 irq_domain_remove(gpio->domain);
414 gpio->domain = NULL;
415 return;
416 }
417
418 irq_gc->reg_base = gpio->regs;
419 irq_gc->private = gpio;
420
421 for (i = 0; i < 2; i++) {
422 ct = &irq_gc->chip_types[i];
423 ct->chip.irq_ack = irq_gc_ack_set_bit;
424 ct->chip.irq_mask = irq_gc_mask_set_bit;
425 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
426 ct->chip.irq_set_type = dwapb_irq_set_type;
427 ct->chip.irq_enable = dwapb_irq_enable;
428 ct->chip.irq_disable = dwapb_irq_disable;
429 ct->chip.irq_request_resources = dwapb_irq_reqres;
430 ct->chip.irq_release_resources = dwapb_irq_relres;
431#ifdef CONFIG_PM_SLEEP
432 ct->chip.irq_set_wake = dwapb_irq_set_wake;
433#endif
434 ct->regs.ack = gpio_reg_convert(gpio, GPIO_PORTA_EOI);
435 ct->regs.mask = gpio_reg_convert(gpio, GPIO_INTMASK);
436 ct->type = IRQ_TYPE_LEVEL_MASK;
437 }
438
439 irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
440 irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
441 irq_gc->chip_types[1].handler = handle_edge_irq;
442
443 if (!pp->irq_shared) {
444 int i;
445
446 for (i = 0; i < pp->ngpio; i++) {
447 if (pp->irq[i] >= 0)
448 irq_set_chained_handler_and_data(pp->irq[i],
449 dwapb_irq_handler, gpio);
450 }
451 } else {
452 /*
453 * Request a shared IRQ since where MFD would have devices
454 * using the same irq pin
455 */
456 err = devm_request_irq(gpio->dev, pp->irq[0],
457 dwapb_irq_handler_mfd,
458 IRQF_SHARED, "gpio-dwapb-mfd", gpio);
459 if (err) {
460 dev_err(gpio->dev, "error requesting IRQ\n");
461 irq_domain_remove(gpio->domain);
462 gpio->domain = NULL;
463 return;
464 }
465 }
466
467 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
468 irq_create_mapping(gpio->domain, hwirq);
469
470 port->gc.to_irq = dwapb_gpio_to_irq;
471}
472
473static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
474{
475 struct dwapb_gpio_port *port = &gpio->ports[0];
476 struct gpio_chip *gc = &port->gc;
477 unsigned int ngpio = gc->ngpio;
478 irq_hw_number_t hwirq;
479
480 if (!gpio->domain)
481 return;
482
483 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
484 irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
485
486 irq_domain_remove(gpio->domain);
487 gpio->domain = NULL;
488}
489
490static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
491 struct dwapb_port_property *pp,
492 unsigned int offs)
493{
494 struct dwapb_gpio_port *port;
495 void __iomem *dat, *set, *dirout;
496 int err;
497
498 port = &gpio->ports[offs];
499 port->gpio = gpio;
500 port->idx = pp->idx;
501
502#ifdef CONFIG_PM_SLEEP
503 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
504 if (!port->ctx)
505 return -ENOMEM;
506#endif
507
508 dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_STRIDE);
509 set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_STRIDE);
510 dirout = gpio->regs + GPIO_SWPORTA_DDR +
511 (pp->idx * GPIO_SWPORT_DDR_STRIDE);
512
513 /* This registers 32 GPIO lines per port */
514 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
515 NULL, 0);
516 if (err) {
517 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
518 port->idx);
519 return err;
520 }
521
522#ifdef CONFIG_OF_GPIO
523 port->gc.of_node = to_of_node(pp->fwnode);
524#endif
525 port->gc.ngpio = pp->ngpio;
526 port->gc.base = pp->gpio_base;
527
528 /* Only port A support debounce */
529 if (pp->idx == 0)
530 port->gc.set_config = dwapb_gpio_set_config;
531
532 if (pp->has_irq)
533 dwapb_configure_irqs(gpio, port, pp);
534
535 err = gpiochip_add_data(&port->gc, port);
536 if (err)
537 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
538 port->idx);
539 else
540 port->is_registered = true;
541
542 /* Add GPIO-signaled ACPI event support */
543 if (pp->has_irq)
544 acpi_gpiochip_request_interrupts(&port->gc);
545
546 return err;
547}
548
549static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
550{
551 unsigned int m;
552
553 for (m = 0; m < gpio->nr_ports; ++m)
554 if (gpio->ports[m].is_registered)
555 gpiochip_remove(&gpio->ports[m].gc);
556}
557
558static struct dwapb_platform_data *
559dwapb_gpio_get_pdata(struct device *dev)
560{
561 struct fwnode_handle *fwnode;
562 struct dwapb_platform_data *pdata;
563 struct dwapb_port_property *pp;
564 int nports;
565 int i, j;
566
567 nports = device_get_child_node_count(dev);
568 if (nports == 0)
569 return ERR_PTR(-ENODEV);
570
571 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
572 if (!pdata)
573 return ERR_PTR(-ENOMEM);
574
575 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
576 if (!pdata->properties)
577 return ERR_PTR(-ENOMEM);
578
579 pdata->nports = nports;
580
581 i = 0;
582 device_for_each_child_node(dev, fwnode) {
583 struct device_node *np = NULL;
584
585 pp = &pdata->properties[i++];
586 pp->fwnode = fwnode;
587
588 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
589 pp->idx >= DWAPB_MAX_PORTS) {
590 dev_err(dev,
591 "missing/invalid port index for port%d\n", i);
592 fwnode_handle_put(fwnode);
593 return ERR_PTR(-EINVAL);
594 }
595
596 if (fwnode_property_read_u32(fwnode, "snps,nr-gpios",
597 &pp->ngpio)) {
598 dev_info(dev,
599 "failed to get number of gpios for port%d\n",
600 i);
601 pp->ngpio = 32;
602 }
603
604 pp->irq_shared = false;
605 pp->gpio_base = -1;
606
607 /*
608 * Only port A can provide interrupts in all configurations of
609 * the IP.
610 */
611 if (pp->idx != 0)
612 continue;
613
614 if (dev->of_node && fwnode_property_read_bool(fwnode,
615 "interrupt-controller")) {
616 np = to_of_node(fwnode);
617 }
618
619 for (j = 0; j < pp->ngpio; j++) {
620 pp->irq[j] = -ENXIO;
621
622 if (np)
623 pp->irq[j] = of_irq_get(np, j);
624 else if (has_acpi_companion(dev))
625 pp->irq[j] = platform_get_irq(to_platform_device(dev), j);
626
627 if (pp->irq[j] >= 0)
628 pp->has_irq = true;
629 }
630
631 if (!pp->has_irq)
632 dev_warn(dev, "no irq for port%d\n", pp->idx);
633 }
634
635 return pdata;
636}
637
638static const struct of_device_id dwapb_of_match[] = {
639 { .compatible = "snps,dw-apb-gpio", .data = (void *)0},
640 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
641 { /* Sentinel */ }
642};
643MODULE_DEVICE_TABLE(of, dwapb_of_match);
644
645static const struct acpi_device_id dwapb_acpi_match[] = {
646 {"HISI0181", 0},
647 {"APMC0D07", 0},
648 {"APMC0D81", GPIO_REG_OFFSET_V2},
649 { }
650};
651MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
652
653static int dwapb_gpio_probe(struct platform_device *pdev)
654{
655 unsigned int i;
656 struct dwapb_gpio *gpio;
657 int err;
658 struct device *dev = &pdev->dev;
659 struct dwapb_platform_data *pdata = dev_get_platdata(dev);
660
661 if (!pdata) {
662 pdata = dwapb_gpio_get_pdata(dev);
663 if (IS_ERR(pdata))
664 return PTR_ERR(pdata);
665 }
666
667 if (!pdata->nports)
668 return -ENODEV;
669
670 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
671 if (!gpio)
672 return -ENOMEM;
673
674 gpio->dev = &pdev->dev;
675 gpio->nr_ports = pdata->nports;
676
677 gpio->rst = devm_reset_control_get_optional_shared(dev, NULL);
678 if (IS_ERR(gpio->rst))
679 return PTR_ERR(gpio->rst);
680
681 reset_control_deassert(gpio->rst);
682
683 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
684 sizeof(*gpio->ports), GFP_KERNEL);
685 if (!gpio->ports)
686 return -ENOMEM;
687
688 gpio->regs = devm_platform_ioremap_resource(pdev, 0);
689 if (IS_ERR(gpio->regs))
690 return PTR_ERR(gpio->regs);
691
692 /* Optional bus clock */
693 gpio->clk = devm_clk_get(&pdev->dev, "bus");
694 if (!IS_ERR(gpio->clk)) {
695 err = clk_prepare_enable(gpio->clk);
696 if (err) {
697 dev_info(&pdev->dev, "Cannot enable clock\n");
698 return err;
699 }
700 }
701
702 gpio->flags = 0;
703 if (dev->of_node) {
704 gpio->flags = (uintptr_t)of_device_get_match_data(dev);
705 } else if (has_acpi_companion(dev)) {
706 const struct acpi_device_id *acpi_id;
707
708 acpi_id = acpi_match_device(dwapb_acpi_match, dev);
709 if (acpi_id) {
710 if (acpi_id->driver_data)
711 gpio->flags = acpi_id->driver_data;
712 }
713 }
714
715 for (i = 0; i < gpio->nr_ports; i++) {
716 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
717 if (err)
718 goto out_unregister;
719 }
720 platform_set_drvdata(pdev, gpio);
721
722 return 0;
723
724out_unregister:
725 dwapb_gpio_unregister(gpio);
726 dwapb_irq_teardown(gpio);
727 clk_disable_unprepare(gpio->clk);
728
729 return err;
730}
731
732static int dwapb_gpio_remove(struct platform_device *pdev)
733{
734 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
735
736 dwapb_gpio_unregister(gpio);
737 dwapb_irq_teardown(gpio);
738 reset_control_assert(gpio->rst);
739 clk_disable_unprepare(gpio->clk);
740
741 return 0;
742}
743
744#ifdef CONFIG_PM_SLEEP
745static int dwapb_gpio_suspend(struct device *dev)
746{
747 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
748 struct gpio_chip *gc = &gpio->ports[0].gc;
749 unsigned long flags;
750 int i;
751
752 spin_lock_irqsave(&gc->bgpio_lock, flags);
753 for (i = 0; i < gpio->nr_ports; i++) {
754 unsigned int offset;
755 unsigned int idx = gpio->ports[i].idx;
756 struct dwapb_context *ctx = gpio->ports[i].ctx;
757
758 BUG_ON(!ctx);
759
760 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
761 ctx->dir = dwapb_read(gpio, offset);
762
763 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
764 ctx->data = dwapb_read(gpio, offset);
765
766 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
767 ctx->ext = dwapb_read(gpio, offset);
768
769 /* Only port A can provide interrupts */
770 if (idx == 0) {
771 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
772 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
773 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
774 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
775 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
776
777 /* Mask out interrupts */
778 dwapb_write(gpio, GPIO_INTMASK,
779 0xffffffff & ~ctx->wake_en);
780 }
781 }
782 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
783
784 clk_disable_unprepare(gpio->clk);
785
786 return 0;
787}
788
789static int dwapb_gpio_resume(struct device *dev)
790{
791 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
792 struct gpio_chip *gc = &gpio->ports[0].gc;
793 unsigned long flags;
794 int i;
795
796 if (!IS_ERR(gpio->clk))
797 clk_prepare_enable(gpio->clk);
798
799 spin_lock_irqsave(&gc->bgpio_lock, flags);
800 for (i = 0; i < gpio->nr_ports; i++) {
801 unsigned int offset;
802 unsigned int idx = gpio->ports[i].idx;
803 struct dwapb_context *ctx = gpio->ports[i].ctx;
804
805 BUG_ON(!ctx);
806
807 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
808 dwapb_write(gpio, offset, ctx->data);
809
810 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
811 dwapb_write(gpio, offset, ctx->dir);
812
813 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
814 dwapb_write(gpio, offset, ctx->ext);
815
816 /* Only port A can provide interrupts */
817 if (idx == 0) {
818 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
819 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
820 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
821 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
822 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
823
824 /* Clear out spurious interrupts */
825 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
826 }
827 }
828 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
829
830 return 0;
831}
832#endif
833
834static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
835 dwapb_gpio_resume);
836
837static struct platform_driver dwapb_gpio_driver = {
838 .driver = {
839 .name = "gpio-dwapb",
840 .pm = &dwapb_gpio_pm_ops,
841 .of_match_table = of_match_ptr(dwapb_of_match),
842 .acpi_match_table = ACPI_PTR(dwapb_acpi_match),
843 },
844 .probe = dwapb_gpio_probe,
845 .remove = dwapb_gpio_remove,
846};
847
848module_platform_driver(dwapb_gpio_driver);
849
850MODULE_LICENSE("GPL");
851MODULE_AUTHOR("Jamie Iles");
852MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");