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1/*
2 * libata-sff.c - helper library for PCI IDE BMDMA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2006 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/gfp.h>
37#include <linux/pci.h>
38#include <linux/libata.h>
39#include <linux/highmem.h>
40
41#include "libata.h"
42
43static struct workqueue_struct *ata_sff_wq;
44
45const struct ata_port_operations ata_sff_port_ops = {
46 .inherits = &ata_base_port_ops,
47
48 .qc_prep = ata_noop_qc_prep,
49 .qc_issue = ata_sff_qc_issue,
50 .qc_fill_rtf = ata_sff_qc_fill_rtf,
51
52 .freeze = ata_sff_freeze,
53 .thaw = ata_sff_thaw,
54 .prereset = ata_sff_prereset,
55 .softreset = ata_sff_softreset,
56 .hardreset = sata_sff_hardreset,
57 .postreset = ata_sff_postreset,
58 .error_handler = ata_sff_error_handler,
59
60 .sff_dev_select = ata_sff_dev_select,
61 .sff_check_status = ata_sff_check_status,
62 .sff_tf_load = ata_sff_tf_load,
63 .sff_tf_read = ata_sff_tf_read,
64 .sff_exec_command = ata_sff_exec_command,
65 .sff_data_xfer = ata_sff_data_xfer,
66 .sff_drain_fifo = ata_sff_drain_fifo,
67
68 .lost_interrupt = ata_sff_lost_interrupt,
69};
70EXPORT_SYMBOL_GPL(ata_sff_port_ops);
71
72/**
73 * ata_sff_check_status - Read device status reg & clear interrupt
74 * @ap: port where the device is
75 *
76 * Reads ATA taskfile status register for currently-selected device
77 * and return its value. This also clears pending interrupts
78 * from this device
79 *
80 * LOCKING:
81 * Inherited from caller.
82 */
83u8 ata_sff_check_status(struct ata_port *ap)
84{
85 return ioread8(ap->ioaddr.status_addr);
86}
87EXPORT_SYMBOL_GPL(ata_sff_check_status);
88
89/**
90 * ata_sff_altstatus - Read device alternate status reg
91 * @ap: port where the device is
92 *
93 * Reads ATA taskfile alternate status register for
94 * currently-selected device and return its value.
95 *
96 * Note: may NOT be used as the check_altstatus() entry in
97 * ata_port_operations.
98 *
99 * LOCKING:
100 * Inherited from caller.
101 */
102static u8 ata_sff_altstatus(struct ata_port *ap)
103{
104 if (ap->ops->sff_check_altstatus)
105 return ap->ops->sff_check_altstatus(ap);
106
107 return ioread8(ap->ioaddr.altstatus_addr);
108}
109
110/**
111 * ata_sff_irq_status - Check if the device is busy
112 * @ap: port where the device is
113 *
114 * Determine if the port is currently busy. Uses altstatus
115 * if available in order to avoid clearing shared IRQ status
116 * when finding an IRQ source. Non ctl capable devices don't
117 * share interrupt lines fortunately for us.
118 *
119 * LOCKING:
120 * Inherited from caller.
121 */
122static u8 ata_sff_irq_status(struct ata_port *ap)
123{
124 u8 status;
125
126 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
127 status = ata_sff_altstatus(ap);
128 /* Not us: We are busy */
129 if (status & ATA_BUSY)
130 return status;
131 }
132 /* Clear INTRQ latch */
133 status = ap->ops->sff_check_status(ap);
134 return status;
135}
136
137/**
138 * ata_sff_sync - Flush writes
139 * @ap: Port to wait for.
140 *
141 * CAUTION:
142 * If we have an mmio device with no ctl and no altstatus
143 * method this will fail. No such devices are known to exist.
144 *
145 * LOCKING:
146 * Inherited from caller.
147 */
148
149static void ata_sff_sync(struct ata_port *ap)
150{
151 if (ap->ops->sff_check_altstatus)
152 ap->ops->sff_check_altstatus(ap);
153 else if (ap->ioaddr.altstatus_addr)
154 ioread8(ap->ioaddr.altstatus_addr);
155}
156
157/**
158 * ata_sff_pause - Flush writes and wait 400nS
159 * @ap: Port to pause for.
160 *
161 * CAUTION:
162 * If we have an mmio device with no ctl and no altstatus
163 * method this will fail. No such devices are known to exist.
164 *
165 * LOCKING:
166 * Inherited from caller.
167 */
168
169void ata_sff_pause(struct ata_port *ap)
170{
171 ata_sff_sync(ap);
172 ndelay(400);
173}
174EXPORT_SYMBOL_GPL(ata_sff_pause);
175
176/**
177 * ata_sff_dma_pause - Pause before commencing DMA
178 * @ap: Port to pause for.
179 *
180 * Perform I/O fencing and ensure sufficient cycle delays occur
181 * for the HDMA1:0 transition
182 */
183
184void ata_sff_dma_pause(struct ata_port *ap)
185{
186 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
187 /* An altstatus read will cause the needed delay without
188 messing up the IRQ status */
189 ata_sff_altstatus(ap);
190 return;
191 }
192 /* There are no DMA controllers without ctl. BUG here to ensure
193 we never violate the HDMA1:0 transition timing and risk
194 corruption. */
195 BUG();
196}
197EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
198
199/**
200 * ata_sff_busy_sleep - sleep until BSY clears, or timeout
201 * @ap: port containing status register to be polled
202 * @tmout_pat: impatience timeout in msecs
203 * @tmout: overall timeout in msecs
204 *
205 * Sleep until ATA Status register bit BSY clears,
206 * or a timeout occurs.
207 *
208 * LOCKING:
209 * Kernel thread context (may sleep).
210 *
211 * RETURNS:
212 * 0 on success, -errno otherwise.
213 */
214int ata_sff_busy_sleep(struct ata_port *ap,
215 unsigned long tmout_pat, unsigned long tmout)
216{
217 unsigned long timer_start, timeout;
218 u8 status;
219
220 status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
221 timer_start = jiffies;
222 timeout = ata_deadline(timer_start, tmout_pat);
223 while (status != 0xff && (status & ATA_BUSY) &&
224 time_before(jiffies, timeout)) {
225 ata_msleep(ap, 50);
226 status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
227 }
228
229 if (status != 0xff && (status & ATA_BUSY))
230 ata_port_warn(ap,
231 "port is slow to respond, please be patient (Status 0x%x)\n",
232 status);
233
234 timeout = ata_deadline(timer_start, tmout);
235 while (status != 0xff && (status & ATA_BUSY) &&
236 time_before(jiffies, timeout)) {
237 ata_msleep(ap, 50);
238 status = ap->ops->sff_check_status(ap);
239 }
240
241 if (status == 0xff)
242 return -ENODEV;
243
244 if (status & ATA_BUSY) {
245 ata_port_err(ap,
246 "port failed to respond (%lu secs, Status 0x%x)\n",
247 DIV_ROUND_UP(tmout, 1000), status);
248 return -EBUSY;
249 }
250
251 return 0;
252}
253EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
254
255static int ata_sff_check_ready(struct ata_link *link)
256{
257 u8 status = link->ap->ops->sff_check_status(link->ap);
258
259 return ata_check_ready(status);
260}
261
262/**
263 * ata_sff_wait_ready - sleep until BSY clears, or timeout
264 * @link: SFF link to wait ready status for
265 * @deadline: deadline jiffies for the operation
266 *
267 * Sleep until ATA Status register bit BSY clears, or timeout
268 * occurs.
269 *
270 * LOCKING:
271 * Kernel thread context (may sleep).
272 *
273 * RETURNS:
274 * 0 on success, -errno otherwise.
275 */
276int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
277{
278 return ata_wait_ready(link, deadline, ata_sff_check_ready);
279}
280EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
281
282/**
283 * ata_sff_set_devctl - Write device control reg
284 * @ap: port where the device is
285 * @ctl: value to write
286 *
287 * Writes ATA taskfile device control register.
288 *
289 * Note: may NOT be used as the sff_set_devctl() entry in
290 * ata_port_operations.
291 *
292 * LOCKING:
293 * Inherited from caller.
294 */
295static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl)
296{
297 if (ap->ops->sff_set_devctl)
298 ap->ops->sff_set_devctl(ap, ctl);
299 else
300 iowrite8(ctl, ap->ioaddr.ctl_addr);
301}
302
303/**
304 * ata_sff_dev_select - Select device 0/1 on ATA bus
305 * @ap: ATA channel to manipulate
306 * @device: ATA device (numbered from zero) to select
307 *
308 * Use the method defined in the ATA specification to
309 * make either device 0, or device 1, active on the
310 * ATA channel. Works with both PIO and MMIO.
311 *
312 * May be used as the dev_select() entry in ata_port_operations.
313 *
314 * LOCKING:
315 * caller.
316 */
317void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
318{
319 u8 tmp;
320
321 if (device == 0)
322 tmp = ATA_DEVICE_OBS;
323 else
324 tmp = ATA_DEVICE_OBS | ATA_DEV1;
325
326 iowrite8(tmp, ap->ioaddr.device_addr);
327 ata_sff_pause(ap); /* needed; also flushes, for mmio */
328}
329EXPORT_SYMBOL_GPL(ata_sff_dev_select);
330
331/**
332 * ata_dev_select - Select device 0/1 on ATA bus
333 * @ap: ATA channel to manipulate
334 * @device: ATA device (numbered from zero) to select
335 * @wait: non-zero to wait for Status register BSY bit to clear
336 * @can_sleep: non-zero if context allows sleeping
337 *
338 * Use the method defined in the ATA specification to
339 * make either device 0, or device 1, active on the
340 * ATA channel.
341 *
342 * This is a high-level version of ata_sff_dev_select(), which
343 * additionally provides the services of inserting the proper
344 * pauses and status polling, where needed.
345 *
346 * LOCKING:
347 * caller.
348 */
349static void ata_dev_select(struct ata_port *ap, unsigned int device,
350 unsigned int wait, unsigned int can_sleep)
351{
352 if (ata_msg_probe(ap))
353 ata_port_info(ap, "ata_dev_select: ENTER, device %u, wait %u\n",
354 device, wait);
355
356 if (wait)
357 ata_wait_idle(ap);
358
359 ap->ops->sff_dev_select(ap, device);
360
361 if (wait) {
362 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
363 ata_msleep(ap, 150);
364 ata_wait_idle(ap);
365 }
366}
367
368/**
369 * ata_sff_irq_on - Enable interrupts on a port.
370 * @ap: Port on which interrupts are enabled.
371 *
372 * Enable interrupts on a legacy IDE device using MMIO or PIO,
373 * wait for idle, clear any pending interrupts.
374 *
375 * Note: may NOT be used as the sff_irq_on() entry in
376 * ata_port_operations.
377 *
378 * LOCKING:
379 * Inherited from caller.
380 */
381void ata_sff_irq_on(struct ata_port *ap)
382{
383 struct ata_ioports *ioaddr = &ap->ioaddr;
384
385 if (ap->ops->sff_irq_on) {
386 ap->ops->sff_irq_on(ap);
387 return;
388 }
389
390 ap->ctl &= ~ATA_NIEN;
391 ap->last_ctl = ap->ctl;
392
393 if (ap->ops->sff_set_devctl || ioaddr->ctl_addr)
394 ata_sff_set_devctl(ap, ap->ctl);
395 ata_wait_idle(ap);
396
397 if (ap->ops->sff_irq_clear)
398 ap->ops->sff_irq_clear(ap);
399}
400EXPORT_SYMBOL_GPL(ata_sff_irq_on);
401
402/**
403 * ata_sff_tf_load - send taskfile registers to host controller
404 * @ap: Port to which output is sent
405 * @tf: ATA taskfile register set
406 *
407 * Outputs ATA taskfile to standard ATA host controller.
408 *
409 * LOCKING:
410 * Inherited from caller.
411 */
412void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
413{
414 struct ata_ioports *ioaddr = &ap->ioaddr;
415 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
416
417 if (tf->ctl != ap->last_ctl) {
418 if (ioaddr->ctl_addr)
419 iowrite8(tf->ctl, ioaddr->ctl_addr);
420 ap->last_ctl = tf->ctl;
421 ata_wait_idle(ap);
422 }
423
424 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
425 WARN_ON_ONCE(!ioaddr->ctl_addr);
426 iowrite8(tf->hob_feature, ioaddr->feature_addr);
427 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
428 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
429 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
430 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
431 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
432 tf->hob_feature,
433 tf->hob_nsect,
434 tf->hob_lbal,
435 tf->hob_lbam,
436 tf->hob_lbah);
437 }
438
439 if (is_addr) {
440 iowrite8(tf->feature, ioaddr->feature_addr);
441 iowrite8(tf->nsect, ioaddr->nsect_addr);
442 iowrite8(tf->lbal, ioaddr->lbal_addr);
443 iowrite8(tf->lbam, ioaddr->lbam_addr);
444 iowrite8(tf->lbah, ioaddr->lbah_addr);
445 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
446 tf->feature,
447 tf->nsect,
448 tf->lbal,
449 tf->lbam,
450 tf->lbah);
451 }
452
453 if (tf->flags & ATA_TFLAG_DEVICE) {
454 iowrite8(tf->device, ioaddr->device_addr);
455 VPRINTK("device 0x%X\n", tf->device);
456 }
457
458 ata_wait_idle(ap);
459}
460EXPORT_SYMBOL_GPL(ata_sff_tf_load);
461
462/**
463 * ata_sff_tf_read - input device's ATA taskfile shadow registers
464 * @ap: Port from which input is read
465 * @tf: ATA taskfile register set for storing input
466 *
467 * Reads ATA taskfile registers for currently-selected device
468 * into @tf. Assumes the device has a fully SFF compliant task file
469 * layout and behaviour. If you device does not (eg has a different
470 * status method) then you will need to provide a replacement tf_read
471 *
472 * LOCKING:
473 * Inherited from caller.
474 */
475void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
476{
477 struct ata_ioports *ioaddr = &ap->ioaddr;
478
479 tf->command = ata_sff_check_status(ap);
480 tf->feature = ioread8(ioaddr->error_addr);
481 tf->nsect = ioread8(ioaddr->nsect_addr);
482 tf->lbal = ioread8(ioaddr->lbal_addr);
483 tf->lbam = ioread8(ioaddr->lbam_addr);
484 tf->lbah = ioread8(ioaddr->lbah_addr);
485 tf->device = ioread8(ioaddr->device_addr);
486
487 if (tf->flags & ATA_TFLAG_LBA48) {
488 if (likely(ioaddr->ctl_addr)) {
489 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
490 tf->hob_feature = ioread8(ioaddr->error_addr);
491 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
492 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
493 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
494 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
495 iowrite8(tf->ctl, ioaddr->ctl_addr);
496 ap->last_ctl = tf->ctl;
497 } else
498 WARN_ON_ONCE(1);
499 }
500}
501EXPORT_SYMBOL_GPL(ata_sff_tf_read);
502
503/**
504 * ata_sff_exec_command - issue ATA command to host controller
505 * @ap: port to which command is being issued
506 * @tf: ATA taskfile register set
507 *
508 * Issues ATA command, with proper synchronization with interrupt
509 * handler / other threads.
510 *
511 * LOCKING:
512 * spin_lock_irqsave(host lock)
513 */
514void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
515{
516 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
517
518 iowrite8(tf->command, ap->ioaddr.command_addr);
519 ata_sff_pause(ap);
520}
521EXPORT_SYMBOL_GPL(ata_sff_exec_command);
522
523/**
524 * ata_tf_to_host - issue ATA taskfile to host controller
525 * @ap: port to which command is being issued
526 * @tf: ATA taskfile register set
527 *
528 * Issues ATA taskfile register set to ATA host controller,
529 * with proper synchronization with interrupt handler and
530 * other threads.
531 *
532 * LOCKING:
533 * spin_lock_irqsave(host lock)
534 */
535static inline void ata_tf_to_host(struct ata_port *ap,
536 const struct ata_taskfile *tf)
537{
538 ap->ops->sff_tf_load(ap, tf);
539 ap->ops->sff_exec_command(ap, tf);
540}
541
542/**
543 * ata_sff_data_xfer - Transfer data by PIO
544 * @dev: device to target
545 * @buf: data buffer
546 * @buflen: buffer length
547 * @rw: read/write
548 *
549 * Transfer data from/to the device data register by PIO.
550 *
551 * LOCKING:
552 * Inherited from caller.
553 *
554 * RETURNS:
555 * Bytes consumed.
556 */
557unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf,
558 unsigned int buflen, int rw)
559{
560 struct ata_port *ap = dev->link->ap;
561 void __iomem *data_addr = ap->ioaddr.data_addr;
562 unsigned int words = buflen >> 1;
563
564 /* Transfer multiple of 2 bytes */
565 if (rw == READ)
566 ioread16_rep(data_addr, buf, words);
567 else
568 iowrite16_rep(data_addr, buf, words);
569
570 /* Transfer trailing byte, if any. */
571 if (unlikely(buflen & 0x01)) {
572 unsigned char pad[2];
573
574 /* Point buf to the tail of buffer */
575 buf += buflen - 1;
576
577 /*
578 * Use io*16_rep() accessors here as well to avoid pointlessly
579 * swapping bytes to and from on the big endian machines...
580 */
581 if (rw == READ) {
582 ioread16_rep(data_addr, pad, 1);
583 *buf = pad[0];
584 } else {
585 pad[0] = *buf;
586 iowrite16_rep(data_addr, pad, 1);
587 }
588 words++;
589 }
590
591 return words << 1;
592}
593EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
594
595/**
596 * ata_sff_data_xfer32 - Transfer data by PIO
597 * @dev: device to target
598 * @buf: data buffer
599 * @buflen: buffer length
600 * @rw: read/write
601 *
602 * Transfer data from/to the device data register by PIO using 32bit
603 * I/O operations.
604 *
605 * LOCKING:
606 * Inherited from caller.
607 *
608 * RETURNS:
609 * Bytes consumed.
610 */
611
612unsigned int ata_sff_data_xfer32(struct ata_device *dev, unsigned char *buf,
613 unsigned int buflen, int rw)
614{
615 struct ata_port *ap = dev->link->ap;
616 void __iomem *data_addr = ap->ioaddr.data_addr;
617 unsigned int words = buflen >> 2;
618 int slop = buflen & 3;
619
620 if (!(ap->pflags & ATA_PFLAG_PIO32))
621 return ata_sff_data_xfer(dev, buf, buflen, rw);
622
623 /* Transfer multiple of 4 bytes */
624 if (rw == READ)
625 ioread32_rep(data_addr, buf, words);
626 else
627 iowrite32_rep(data_addr, buf, words);
628
629 /* Transfer trailing bytes, if any */
630 if (unlikely(slop)) {
631 unsigned char pad[4];
632
633 /* Point buf to the tail of buffer */
634 buf += buflen - slop;
635
636 /*
637 * Use io*_rep() accessors here as well to avoid pointlessly
638 * swapping bytes to and from on the big endian machines...
639 */
640 if (rw == READ) {
641 if (slop < 3)
642 ioread16_rep(data_addr, pad, 1);
643 else
644 ioread32_rep(data_addr, pad, 1);
645 memcpy(buf, pad, slop);
646 } else {
647 memcpy(pad, buf, slop);
648 if (slop < 3)
649 iowrite16_rep(data_addr, pad, 1);
650 else
651 iowrite32_rep(data_addr, pad, 1);
652 }
653 }
654 return (buflen + 1) & ~1;
655}
656EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
657
658/**
659 * ata_sff_data_xfer_noirq - Transfer data by PIO
660 * @dev: device to target
661 * @buf: data buffer
662 * @buflen: buffer length
663 * @rw: read/write
664 *
665 * Transfer data from/to the device data register by PIO. Do the
666 * transfer with interrupts disabled.
667 *
668 * LOCKING:
669 * Inherited from caller.
670 *
671 * RETURNS:
672 * Bytes consumed.
673 */
674unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
675 unsigned int buflen, int rw)
676{
677 unsigned long flags;
678 unsigned int consumed;
679
680 local_irq_save(flags);
681 consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
682 local_irq_restore(flags);
683
684 return consumed;
685}
686EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq);
687
688/**
689 * ata_pio_sector - Transfer a sector of data.
690 * @qc: Command on going
691 *
692 * Transfer qc->sect_size bytes of data from/to the ATA device.
693 *
694 * LOCKING:
695 * Inherited from caller.
696 */
697static void ata_pio_sector(struct ata_queued_cmd *qc)
698{
699 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
700 struct ata_port *ap = qc->ap;
701 struct page *page;
702 unsigned int offset;
703 unsigned char *buf;
704
705 if (qc->curbytes == qc->nbytes - qc->sect_size)
706 ap->hsm_task_state = HSM_ST_LAST;
707
708 page = sg_page(qc->cursg);
709 offset = qc->cursg->offset + qc->cursg_ofs;
710
711 /* get the current page and offset */
712 page = nth_page(page, (offset >> PAGE_SHIFT));
713 offset %= PAGE_SIZE;
714
715 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
716
717 if (PageHighMem(page)) {
718 unsigned long flags;
719
720 /* FIXME: use a bounce buffer */
721 local_irq_save(flags);
722 buf = kmap_atomic(page, KM_IRQ0);
723
724 /* do the actual data transfer */
725 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
726 do_write);
727
728 kunmap_atomic(buf, KM_IRQ0);
729 local_irq_restore(flags);
730 } else {
731 buf = page_address(page);
732 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
733 do_write);
734 }
735
736 if (!do_write && !PageSlab(page))
737 flush_dcache_page(page);
738
739 qc->curbytes += qc->sect_size;
740 qc->cursg_ofs += qc->sect_size;
741
742 if (qc->cursg_ofs == qc->cursg->length) {
743 qc->cursg = sg_next(qc->cursg);
744 qc->cursg_ofs = 0;
745 }
746}
747
748/**
749 * ata_pio_sectors - Transfer one or many sectors.
750 * @qc: Command on going
751 *
752 * Transfer one or many sectors of data from/to the
753 * ATA device for the DRQ request.
754 *
755 * LOCKING:
756 * Inherited from caller.
757 */
758static void ata_pio_sectors(struct ata_queued_cmd *qc)
759{
760 if (is_multi_taskfile(&qc->tf)) {
761 /* READ/WRITE MULTIPLE */
762 unsigned int nsect;
763
764 WARN_ON_ONCE(qc->dev->multi_count == 0);
765
766 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
767 qc->dev->multi_count);
768 while (nsect--)
769 ata_pio_sector(qc);
770 } else
771 ata_pio_sector(qc);
772
773 ata_sff_sync(qc->ap); /* flush */
774}
775
776/**
777 * atapi_send_cdb - Write CDB bytes to hardware
778 * @ap: Port to which ATAPI device is attached.
779 * @qc: Taskfile currently active
780 *
781 * When device has indicated its readiness to accept
782 * a CDB, this function is called. Send the CDB.
783 *
784 * LOCKING:
785 * caller.
786 */
787static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
788{
789 /* send SCSI cdb */
790 DPRINTK("send cdb\n");
791 WARN_ON_ONCE(qc->dev->cdb_len < 12);
792
793 ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
794 ata_sff_sync(ap);
795 /* FIXME: If the CDB is for DMA do we need to do the transition delay
796 or is bmdma_start guaranteed to do it ? */
797 switch (qc->tf.protocol) {
798 case ATAPI_PROT_PIO:
799 ap->hsm_task_state = HSM_ST;
800 break;
801 case ATAPI_PROT_NODATA:
802 ap->hsm_task_state = HSM_ST_LAST;
803 break;
804#ifdef CONFIG_ATA_BMDMA
805 case ATAPI_PROT_DMA:
806 ap->hsm_task_state = HSM_ST_LAST;
807 /* initiate bmdma */
808 ap->ops->bmdma_start(qc);
809 break;
810#endif /* CONFIG_ATA_BMDMA */
811 default:
812 BUG();
813 }
814}
815
816/**
817 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
818 * @qc: Command on going
819 * @bytes: number of bytes
820 *
821 * Transfer Transfer data from/to the ATAPI device.
822 *
823 * LOCKING:
824 * Inherited from caller.
825 *
826 */
827static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
828{
829 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
830 struct ata_port *ap = qc->ap;
831 struct ata_device *dev = qc->dev;
832 struct ata_eh_info *ehi = &dev->link->eh_info;
833 struct scatterlist *sg;
834 struct page *page;
835 unsigned char *buf;
836 unsigned int offset, count, consumed;
837
838next_sg:
839 sg = qc->cursg;
840 if (unlikely(!sg)) {
841 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
842 "buf=%u cur=%u bytes=%u",
843 qc->nbytes, qc->curbytes, bytes);
844 return -1;
845 }
846
847 page = sg_page(sg);
848 offset = sg->offset + qc->cursg_ofs;
849
850 /* get the current page and offset */
851 page = nth_page(page, (offset >> PAGE_SHIFT));
852 offset %= PAGE_SIZE;
853
854 /* don't overrun current sg */
855 count = min(sg->length - qc->cursg_ofs, bytes);
856
857 /* don't cross page boundaries */
858 count = min(count, (unsigned int)PAGE_SIZE - offset);
859
860 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
861
862 if (PageHighMem(page)) {
863 unsigned long flags;
864
865 /* FIXME: use bounce buffer */
866 local_irq_save(flags);
867 buf = kmap_atomic(page, KM_IRQ0);
868
869 /* do the actual data transfer */
870 consumed = ap->ops->sff_data_xfer(dev, buf + offset,
871 count, rw);
872
873 kunmap_atomic(buf, KM_IRQ0);
874 local_irq_restore(flags);
875 } else {
876 buf = page_address(page);
877 consumed = ap->ops->sff_data_xfer(dev, buf + offset,
878 count, rw);
879 }
880
881 bytes -= min(bytes, consumed);
882 qc->curbytes += count;
883 qc->cursg_ofs += count;
884
885 if (qc->cursg_ofs == sg->length) {
886 qc->cursg = sg_next(qc->cursg);
887 qc->cursg_ofs = 0;
888 }
889
890 /*
891 * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed);
892 * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
893 * check correctly as it doesn't know if it is the last request being
894 * made. Somebody should implement a proper sanity check.
895 */
896 if (bytes)
897 goto next_sg;
898 return 0;
899}
900
901/**
902 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
903 * @qc: Command on going
904 *
905 * Transfer Transfer data from/to the ATAPI device.
906 *
907 * LOCKING:
908 * Inherited from caller.
909 */
910static void atapi_pio_bytes(struct ata_queued_cmd *qc)
911{
912 struct ata_port *ap = qc->ap;
913 struct ata_device *dev = qc->dev;
914 struct ata_eh_info *ehi = &dev->link->eh_info;
915 unsigned int ireason, bc_lo, bc_hi, bytes;
916 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
917
918 /* Abuse qc->result_tf for temp storage of intermediate TF
919 * here to save some kernel stack usage.
920 * For normal completion, qc->result_tf is not relevant. For
921 * error, qc->result_tf is later overwritten by ata_qc_complete().
922 * So, the correctness of qc->result_tf is not affected.
923 */
924 ap->ops->sff_tf_read(ap, &qc->result_tf);
925 ireason = qc->result_tf.nsect;
926 bc_lo = qc->result_tf.lbam;
927 bc_hi = qc->result_tf.lbah;
928 bytes = (bc_hi << 8) | bc_lo;
929
930 /* shall be cleared to zero, indicating xfer of data */
931 if (unlikely(ireason & (1 << 0)))
932 goto atapi_check;
933
934 /* make sure transfer direction matches expected */
935 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
936 if (unlikely(do_write != i_write))
937 goto atapi_check;
938
939 if (unlikely(!bytes))
940 goto atapi_check;
941
942 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
943
944 if (unlikely(__atapi_pio_bytes(qc, bytes)))
945 goto err_out;
946 ata_sff_sync(ap); /* flush */
947
948 return;
949
950 atapi_check:
951 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
952 ireason, bytes);
953 err_out:
954 qc->err_mask |= AC_ERR_HSM;
955 ap->hsm_task_state = HSM_ST_ERR;
956}
957
958/**
959 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
960 * @ap: the target ata_port
961 * @qc: qc on going
962 *
963 * RETURNS:
964 * 1 if ok in workqueue, 0 otherwise.
965 */
966static inline int ata_hsm_ok_in_wq(struct ata_port *ap,
967 struct ata_queued_cmd *qc)
968{
969 if (qc->tf.flags & ATA_TFLAG_POLLING)
970 return 1;
971
972 if (ap->hsm_task_state == HSM_ST_FIRST) {
973 if (qc->tf.protocol == ATA_PROT_PIO &&
974 (qc->tf.flags & ATA_TFLAG_WRITE))
975 return 1;
976
977 if (ata_is_atapi(qc->tf.protocol) &&
978 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
979 return 1;
980 }
981
982 return 0;
983}
984
985/**
986 * ata_hsm_qc_complete - finish a qc running on standard HSM
987 * @qc: Command to complete
988 * @in_wq: 1 if called from workqueue, 0 otherwise
989 *
990 * Finish @qc which is running on standard HSM.
991 *
992 * LOCKING:
993 * If @in_wq is zero, spin_lock_irqsave(host lock).
994 * Otherwise, none on entry and grabs host lock.
995 */
996static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
997{
998 struct ata_port *ap = qc->ap;
999 unsigned long flags;
1000
1001 if (ap->ops->error_handler) {
1002 if (in_wq) {
1003 spin_lock_irqsave(ap->lock, flags);
1004
1005 /* EH might have kicked in while host lock is
1006 * released.
1007 */
1008 qc = ata_qc_from_tag(ap, qc->tag);
1009 if (qc) {
1010 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
1011 ata_sff_irq_on(ap);
1012 ata_qc_complete(qc);
1013 } else
1014 ata_port_freeze(ap);
1015 }
1016
1017 spin_unlock_irqrestore(ap->lock, flags);
1018 } else {
1019 if (likely(!(qc->err_mask & AC_ERR_HSM)))
1020 ata_qc_complete(qc);
1021 else
1022 ata_port_freeze(ap);
1023 }
1024 } else {
1025 if (in_wq) {
1026 spin_lock_irqsave(ap->lock, flags);
1027 ata_sff_irq_on(ap);
1028 ata_qc_complete(qc);
1029 spin_unlock_irqrestore(ap->lock, flags);
1030 } else
1031 ata_qc_complete(qc);
1032 }
1033}
1034
1035/**
1036 * ata_sff_hsm_move - move the HSM to the next state.
1037 * @ap: the target ata_port
1038 * @qc: qc on going
1039 * @status: current device status
1040 * @in_wq: 1 if called from workqueue, 0 otherwise
1041 *
1042 * RETURNS:
1043 * 1 when poll next status needed, 0 otherwise.
1044 */
1045int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1046 u8 status, int in_wq)
1047{
1048 struct ata_link *link = qc->dev->link;
1049 struct ata_eh_info *ehi = &link->eh_info;
1050 unsigned long flags = 0;
1051 int poll_next;
1052
1053 WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
1054
1055 /* Make sure ata_sff_qc_issue() does not throw things
1056 * like DMA polling into the workqueue. Notice that
1057 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1058 */
1059 WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc));
1060
1061fsm_start:
1062 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1063 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1064
1065 switch (ap->hsm_task_state) {
1066 case HSM_ST_FIRST:
1067 /* Send first data block or PACKET CDB */
1068
1069 /* If polling, we will stay in the work queue after
1070 * sending the data. Otherwise, interrupt handler
1071 * takes over after sending the data.
1072 */
1073 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1074
1075 /* check device status */
1076 if (unlikely((status & ATA_DRQ) == 0)) {
1077 /* handle BSY=0, DRQ=0 as error */
1078 if (likely(status & (ATA_ERR | ATA_DF)))
1079 /* device stops HSM for abort/error */
1080 qc->err_mask |= AC_ERR_DEV;
1081 else {
1082 /* HSM violation. Let EH handle this */
1083 ata_ehi_push_desc(ehi,
1084 "ST_FIRST: !(DRQ|ERR|DF)");
1085 qc->err_mask |= AC_ERR_HSM;
1086 }
1087
1088 ap->hsm_task_state = HSM_ST_ERR;
1089 goto fsm_start;
1090 }
1091
1092 /* Device should not ask for data transfer (DRQ=1)
1093 * when it finds something wrong.
1094 * We ignore DRQ here and stop the HSM by
1095 * changing hsm_task_state to HSM_ST_ERR and
1096 * let the EH abort the command or reset the device.
1097 */
1098 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1099 /* Some ATAPI tape drives forget to clear the ERR bit
1100 * when doing the next command (mostly request sense).
1101 * We ignore ERR here to workaround and proceed sending
1102 * the CDB.
1103 */
1104 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1105 ata_ehi_push_desc(ehi, "ST_FIRST: "
1106 "DRQ=1 with device error, "
1107 "dev_stat 0x%X", status);
1108 qc->err_mask |= AC_ERR_HSM;
1109 ap->hsm_task_state = HSM_ST_ERR;
1110 goto fsm_start;
1111 }
1112 }
1113
1114 /* Send the CDB (atapi) or the first data block (ata pio out).
1115 * During the state transition, interrupt handler shouldn't
1116 * be invoked before the data transfer is complete and
1117 * hsm_task_state is changed. Hence, the following locking.
1118 */
1119 if (in_wq)
1120 spin_lock_irqsave(ap->lock, flags);
1121
1122 if (qc->tf.protocol == ATA_PROT_PIO) {
1123 /* PIO data out protocol.
1124 * send first data block.
1125 */
1126
1127 /* ata_pio_sectors() might change the state
1128 * to HSM_ST_LAST. so, the state is changed here
1129 * before ata_pio_sectors().
1130 */
1131 ap->hsm_task_state = HSM_ST;
1132 ata_pio_sectors(qc);
1133 } else
1134 /* send CDB */
1135 atapi_send_cdb(ap, qc);
1136
1137 if (in_wq)
1138 spin_unlock_irqrestore(ap->lock, flags);
1139
1140 /* if polling, ata_sff_pio_task() handles the rest.
1141 * otherwise, interrupt handler takes over from here.
1142 */
1143 break;
1144
1145 case HSM_ST:
1146 /* complete command or read/write the data register */
1147 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1148 /* ATAPI PIO protocol */
1149 if ((status & ATA_DRQ) == 0) {
1150 /* No more data to transfer or device error.
1151 * Device error will be tagged in HSM_ST_LAST.
1152 */
1153 ap->hsm_task_state = HSM_ST_LAST;
1154 goto fsm_start;
1155 }
1156
1157 /* Device should not ask for data transfer (DRQ=1)
1158 * when it finds something wrong.
1159 * We ignore DRQ here and stop the HSM by
1160 * changing hsm_task_state to HSM_ST_ERR and
1161 * let the EH abort the command or reset the device.
1162 */
1163 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1164 ata_ehi_push_desc(ehi, "ST-ATAPI: "
1165 "DRQ=1 with device error, "
1166 "dev_stat 0x%X", status);
1167 qc->err_mask |= AC_ERR_HSM;
1168 ap->hsm_task_state = HSM_ST_ERR;
1169 goto fsm_start;
1170 }
1171
1172 atapi_pio_bytes(qc);
1173
1174 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1175 /* bad ireason reported by device */
1176 goto fsm_start;
1177
1178 } else {
1179 /* ATA PIO protocol */
1180 if (unlikely((status & ATA_DRQ) == 0)) {
1181 /* handle BSY=0, DRQ=0 as error */
1182 if (likely(status & (ATA_ERR | ATA_DF))) {
1183 /* device stops HSM for abort/error */
1184 qc->err_mask |= AC_ERR_DEV;
1185
1186 /* If diagnostic failed and this is
1187 * IDENTIFY, it's likely a phantom
1188 * device. Mark hint.
1189 */
1190 if (qc->dev->horkage &
1191 ATA_HORKAGE_DIAGNOSTIC)
1192 qc->err_mask |=
1193 AC_ERR_NODEV_HINT;
1194 } else {
1195 /* HSM violation. Let EH handle this.
1196 * Phantom devices also trigger this
1197 * condition. Mark hint.
1198 */
1199 ata_ehi_push_desc(ehi, "ST-ATA: "
1200 "DRQ=0 without device error, "
1201 "dev_stat 0x%X", status);
1202 qc->err_mask |= AC_ERR_HSM |
1203 AC_ERR_NODEV_HINT;
1204 }
1205
1206 ap->hsm_task_state = HSM_ST_ERR;
1207 goto fsm_start;
1208 }
1209
1210 /* For PIO reads, some devices may ask for
1211 * data transfer (DRQ=1) alone with ERR=1.
1212 * We respect DRQ here and transfer one
1213 * block of junk data before changing the
1214 * hsm_task_state to HSM_ST_ERR.
1215 *
1216 * For PIO writes, ERR=1 DRQ=1 doesn't make
1217 * sense since the data block has been
1218 * transferred to the device.
1219 */
1220 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1221 /* data might be corrputed */
1222 qc->err_mask |= AC_ERR_DEV;
1223
1224 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1225 ata_pio_sectors(qc);
1226 status = ata_wait_idle(ap);
1227 }
1228
1229 if (status & (ATA_BUSY | ATA_DRQ)) {
1230 ata_ehi_push_desc(ehi, "ST-ATA: "
1231 "BUSY|DRQ persists on ERR|DF, "
1232 "dev_stat 0x%X", status);
1233 qc->err_mask |= AC_ERR_HSM;
1234 }
1235
1236 /* There are oddball controllers with
1237 * status register stuck at 0x7f and
1238 * lbal/m/h at zero which makes it
1239 * pass all other presence detection
1240 * mechanisms we have. Set NODEV_HINT
1241 * for it. Kernel bz#7241.
1242 */
1243 if (status == 0x7f)
1244 qc->err_mask |= AC_ERR_NODEV_HINT;
1245
1246 /* ata_pio_sectors() might change the
1247 * state to HSM_ST_LAST. so, the state
1248 * is changed after ata_pio_sectors().
1249 */
1250 ap->hsm_task_state = HSM_ST_ERR;
1251 goto fsm_start;
1252 }
1253
1254 ata_pio_sectors(qc);
1255
1256 if (ap->hsm_task_state == HSM_ST_LAST &&
1257 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1258 /* all data read */
1259 status = ata_wait_idle(ap);
1260 goto fsm_start;
1261 }
1262 }
1263
1264 poll_next = 1;
1265 break;
1266
1267 case HSM_ST_LAST:
1268 if (unlikely(!ata_ok(status))) {
1269 qc->err_mask |= __ac_err_mask(status);
1270 ap->hsm_task_state = HSM_ST_ERR;
1271 goto fsm_start;
1272 }
1273
1274 /* no more data to transfer */
1275 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1276 ap->print_id, qc->dev->devno, status);
1277
1278 WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
1279
1280 ap->hsm_task_state = HSM_ST_IDLE;
1281
1282 /* complete taskfile transaction */
1283 ata_hsm_qc_complete(qc, in_wq);
1284
1285 poll_next = 0;
1286 break;
1287
1288 case HSM_ST_ERR:
1289 ap->hsm_task_state = HSM_ST_IDLE;
1290
1291 /* complete taskfile transaction */
1292 ata_hsm_qc_complete(qc, in_wq);
1293
1294 poll_next = 0;
1295 break;
1296 default:
1297 poll_next = 0;
1298 BUG();
1299 }
1300
1301 return poll_next;
1302}
1303EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
1304
1305void ata_sff_queue_work(struct work_struct *work)
1306{
1307 queue_work(ata_sff_wq, work);
1308}
1309EXPORT_SYMBOL_GPL(ata_sff_queue_work);
1310
1311void ata_sff_queue_delayed_work(struct delayed_work *dwork, unsigned long delay)
1312{
1313 queue_delayed_work(ata_sff_wq, dwork, delay);
1314}
1315EXPORT_SYMBOL_GPL(ata_sff_queue_delayed_work);
1316
1317void ata_sff_queue_pio_task(struct ata_link *link, unsigned long delay)
1318{
1319 struct ata_port *ap = link->ap;
1320
1321 WARN_ON((ap->sff_pio_task_link != NULL) &&
1322 (ap->sff_pio_task_link != link));
1323 ap->sff_pio_task_link = link;
1324
1325 /* may fail if ata_sff_flush_pio_task() in progress */
1326 ata_sff_queue_delayed_work(&ap->sff_pio_task, msecs_to_jiffies(delay));
1327}
1328EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task);
1329
1330void ata_sff_flush_pio_task(struct ata_port *ap)
1331{
1332 DPRINTK("ENTER\n");
1333
1334 cancel_delayed_work_sync(&ap->sff_pio_task);
1335 ap->hsm_task_state = HSM_ST_IDLE;
1336 ap->sff_pio_task_link = NULL;
1337
1338 if (ata_msg_ctl(ap))
1339 ata_port_dbg(ap, "%s: EXIT\n", __func__);
1340}
1341
1342static void ata_sff_pio_task(struct work_struct *work)
1343{
1344 struct ata_port *ap =
1345 container_of(work, struct ata_port, sff_pio_task.work);
1346 struct ata_link *link = ap->sff_pio_task_link;
1347 struct ata_queued_cmd *qc;
1348 u8 status;
1349 int poll_next;
1350
1351 BUG_ON(ap->sff_pio_task_link == NULL);
1352 /* qc can be NULL if timeout occurred */
1353 qc = ata_qc_from_tag(ap, link->active_tag);
1354 if (!qc) {
1355 ap->sff_pio_task_link = NULL;
1356 return;
1357 }
1358
1359fsm_start:
1360 WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE);
1361
1362 /*
1363 * This is purely heuristic. This is a fast path.
1364 * Sometimes when we enter, BSY will be cleared in
1365 * a chk-status or two. If not, the drive is probably seeking
1366 * or something. Snooze for a couple msecs, then
1367 * chk-status again. If still busy, queue delayed work.
1368 */
1369 status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
1370 if (status & ATA_BUSY) {
1371 ata_msleep(ap, 2);
1372 status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
1373 if (status & ATA_BUSY) {
1374 ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE);
1375 return;
1376 }
1377 }
1378
1379 /*
1380 * hsm_move() may trigger another command to be processed.
1381 * clean the link beforehand.
1382 */
1383 ap->sff_pio_task_link = NULL;
1384 /* move the HSM */
1385 poll_next = ata_sff_hsm_move(ap, qc, status, 1);
1386
1387 /* another command or interrupt handler
1388 * may be running at this point.
1389 */
1390 if (poll_next)
1391 goto fsm_start;
1392}
1393
1394/**
1395 * ata_sff_qc_issue - issue taskfile to a SFF controller
1396 * @qc: command to issue to device
1397 *
1398 * This function issues a PIO or NODATA command to a SFF
1399 * controller.
1400 *
1401 * LOCKING:
1402 * spin_lock_irqsave(host lock)
1403 *
1404 * RETURNS:
1405 * Zero on success, AC_ERR_* mask on failure
1406 */
1407unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
1408{
1409 struct ata_port *ap = qc->ap;
1410 struct ata_link *link = qc->dev->link;
1411
1412 /* Use polling pio if the LLD doesn't handle
1413 * interrupt driven pio and atapi CDB interrupt.
1414 */
1415 if (ap->flags & ATA_FLAG_PIO_POLLING)
1416 qc->tf.flags |= ATA_TFLAG_POLLING;
1417
1418 /* select the device */
1419 ata_dev_select(ap, qc->dev->devno, 1, 0);
1420
1421 /* start the command */
1422 switch (qc->tf.protocol) {
1423 case ATA_PROT_NODATA:
1424 if (qc->tf.flags & ATA_TFLAG_POLLING)
1425 ata_qc_set_polling(qc);
1426
1427 ata_tf_to_host(ap, &qc->tf);
1428 ap->hsm_task_state = HSM_ST_LAST;
1429
1430 if (qc->tf.flags & ATA_TFLAG_POLLING)
1431 ata_sff_queue_pio_task(link, 0);
1432
1433 break;
1434
1435 case ATA_PROT_PIO:
1436 if (qc->tf.flags & ATA_TFLAG_POLLING)
1437 ata_qc_set_polling(qc);
1438
1439 ata_tf_to_host(ap, &qc->tf);
1440
1441 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1442 /* PIO data out protocol */
1443 ap->hsm_task_state = HSM_ST_FIRST;
1444 ata_sff_queue_pio_task(link, 0);
1445
1446 /* always send first data block using the
1447 * ata_sff_pio_task() codepath.
1448 */
1449 } else {
1450 /* PIO data in protocol */
1451 ap->hsm_task_state = HSM_ST;
1452
1453 if (qc->tf.flags & ATA_TFLAG_POLLING)
1454 ata_sff_queue_pio_task(link, 0);
1455
1456 /* if polling, ata_sff_pio_task() handles the
1457 * rest. otherwise, interrupt handler takes
1458 * over from here.
1459 */
1460 }
1461
1462 break;
1463
1464 case ATAPI_PROT_PIO:
1465 case ATAPI_PROT_NODATA:
1466 if (qc->tf.flags & ATA_TFLAG_POLLING)
1467 ata_qc_set_polling(qc);
1468
1469 ata_tf_to_host(ap, &qc->tf);
1470
1471 ap->hsm_task_state = HSM_ST_FIRST;
1472
1473 /* send cdb by polling if no cdb interrupt */
1474 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1475 (qc->tf.flags & ATA_TFLAG_POLLING))
1476 ata_sff_queue_pio_task(link, 0);
1477 break;
1478
1479 default:
1480 WARN_ON_ONCE(1);
1481 return AC_ERR_SYSTEM;
1482 }
1483
1484 return 0;
1485}
1486EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
1487
1488/**
1489 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
1490 * @qc: qc to fill result TF for
1491 *
1492 * @qc is finished and result TF needs to be filled. Fill it
1493 * using ->sff_tf_read.
1494 *
1495 * LOCKING:
1496 * spin_lock_irqsave(host lock)
1497 *
1498 * RETURNS:
1499 * true indicating that result TF is successfully filled.
1500 */
1501bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
1502{
1503 qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
1504 return true;
1505}
1506EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
1507
1508static unsigned int ata_sff_idle_irq(struct ata_port *ap)
1509{
1510 ap->stats.idle_irq++;
1511
1512#ifdef ATA_IRQ_TRAP
1513 if ((ap->stats.idle_irq % 1000) == 0) {
1514 ap->ops->sff_check_status(ap);
1515 if (ap->ops->sff_irq_clear)
1516 ap->ops->sff_irq_clear(ap);
1517 ata_port_warn(ap, "irq trap\n");
1518 return 1;
1519 }
1520#endif
1521 return 0; /* irq not handled */
1522}
1523
1524static unsigned int __ata_sff_port_intr(struct ata_port *ap,
1525 struct ata_queued_cmd *qc,
1526 bool hsmv_on_idle)
1527{
1528 u8 status;
1529
1530 VPRINTK("ata%u: protocol %d task_state %d\n",
1531 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1532
1533 /* Check whether we are expecting interrupt in this state */
1534 switch (ap->hsm_task_state) {
1535 case HSM_ST_FIRST:
1536 /* Some pre-ATAPI-4 devices assert INTRQ
1537 * at this state when ready to receive CDB.
1538 */
1539
1540 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1541 * The flag was turned on only for atapi devices. No
1542 * need to check ata_is_atapi(qc->tf.protocol) again.
1543 */
1544 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1545 return ata_sff_idle_irq(ap);
1546 break;
1547 case HSM_ST_IDLE:
1548 return ata_sff_idle_irq(ap);
1549 default:
1550 break;
1551 }
1552
1553 /* check main status, clearing INTRQ if needed */
1554 status = ata_sff_irq_status(ap);
1555 if (status & ATA_BUSY) {
1556 if (hsmv_on_idle) {
1557 /* BMDMA engine is already stopped, we're screwed */
1558 qc->err_mask |= AC_ERR_HSM;
1559 ap->hsm_task_state = HSM_ST_ERR;
1560 } else
1561 return ata_sff_idle_irq(ap);
1562 }
1563
1564 /* clear irq events */
1565 if (ap->ops->sff_irq_clear)
1566 ap->ops->sff_irq_clear(ap);
1567
1568 ata_sff_hsm_move(ap, qc, status, 0);
1569
1570 return 1; /* irq handled */
1571}
1572
1573/**
1574 * ata_sff_port_intr - Handle SFF port interrupt
1575 * @ap: Port on which interrupt arrived (possibly...)
1576 * @qc: Taskfile currently active in engine
1577 *
1578 * Handle port interrupt for given queued command.
1579 *
1580 * LOCKING:
1581 * spin_lock_irqsave(host lock)
1582 *
1583 * RETURNS:
1584 * One if interrupt was handled, zero if not (shared irq).
1585 */
1586unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
1587{
1588 return __ata_sff_port_intr(ap, qc, false);
1589}
1590EXPORT_SYMBOL_GPL(ata_sff_port_intr);
1591
1592static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance,
1593 unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *))
1594{
1595 struct ata_host *host = dev_instance;
1596 bool retried = false;
1597 unsigned int i;
1598 unsigned int handled, idle, polling;
1599 unsigned long flags;
1600
1601 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1602 spin_lock_irqsave(&host->lock, flags);
1603
1604retry:
1605 handled = idle = polling = 0;
1606 for (i = 0; i < host->n_ports; i++) {
1607 struct ata_port *ap = host->ports[i];
1608 struct ata_queued_cmd *qc;
1609
1610 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1611 if (qc) {
1612 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
1613 handled |= port_intr(ap, qc);
1614 else
1615 polling |= 1 << i;
1616 } else
1617 idle |= 1 << i;
1618 }
1619
1620 /*
1621 * If no port was expecting IRQ but the controller is actually
1622 * asserting IRQ line, nobody cared will ensue. Check IRQ
1623 * pending status if available and clear spurious IRQ.
1624 */
1625 if (!handled && !retried) {
1626 bool retry = false;
1627
1628 for (i = 0; i < host->n_ports; i++) {
1629 struct ata_port *ap = host->ports[i];
1630
1631 if (polling & (1 << i))
1632 continue;
1633
1634 if (!ap->ops->sff_irq_check ||
1635 !ap->ops->sff_irq_check(ap))
1636 continue;
1637
1638 if (idle & (1 << i)) {
1639 ap->ops->sff_check_status(ap);
1640 if (ap->ops->sff_irq_clear)
1641 ap->ops->sff_irq_clear(ap);
1642 } else {
1643 /* clear INTRQ and check if BUSY cleared */
1644 if (!(ap->ops->sff_check_status(ap) & ATA_BUSY))
1645 retry |= true;
1646 /*
1647 * With command in flight, we can't do
1648 * sff_irq_clear() w/o racing with completion.
1649 */
1650 }
1651 }
1652
1653 if (retry) {
1654 retried = true;
1655 goto retry;
1656 }
1657 }
1658
1659 spin_unlock_irqrestore(&host->lock, flags);
1660
1661 return IRQ_RETVAL(handled);
1662}
1663
1664/**
1665 * ata_sff_interrupt - Default SFF ATA host interrupt handler
1666 * @irq: irq line (unused)
1667 * @dev_instance: pointer to our ata_host information structure
1668 *
1669 * Default interrupt handler for PCI IDE devices. Calls
1670 * ata_sff_port_intr() for each port that is not disabled.
1671 *
1672 * LOCKING:
1673 * Obtains host lock during operation.
1674 *
1675 * RETURNS:
1676 * IRQ_NONE or IRQ_HANDLED.
1677 */
1678irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
1679{
1680 return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr);
1681}
1682EXPORT_SYMBOL_GPL(ata_sff_interrupt);
1683
1684/**
1685 * ata_sff_lost_interrupt - Check for an apparent lost interrupt
1686 * @ap: port that appears to have timed out
1687 *
1688 * Called from the libata error handlers when the core code suspects
1689 * an interrupt has been lost. If it has complete anything we can and
1690 * then return. Interface must support altstatus for this faster
1691 * recovery to occur.
1692 *
1693 * Locking:
1694 * Caller holds host lock
1695 */
1696
1697void ata_sff_lost_interrupt(struct ata_port *ap)
1698{
1699 u8 status;
1700 struct ata_queued_cmd *qc;
1701
1702 /* Only one outstanding command per SFF channel */
1703 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1704 /* We cannot lose an interrupt on a non-existent or polled command */
1705 if (!qc || qc->tf.flags & ATA_TFLAG_POLLING)
1706 return;
1707 /* See if the controller thinks it is still busy - if so the command
1708 isn't a lost IRQ but is still in progress */
1709 status = ata_sff_altstatus(ap);
1710 if (status & ATA_BUSY)
1711 return;
1712
1713 /* There was a command running, we are no longer busy and we have
1714 no interrupt. */
1715 ata_port_warn(ap, "lost interrupt (Status 0x%x)\n",
1716 status);
1717 /* Run the host interrupt logic as if the interrupt had not been
1718 lost */
1719 ata_sff_port_intr(ap, qc);
1720}
1721EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
1722
1723/**
1724 * ata_sff_freeze - Freeze SFF controller port
1725 * @ap: port to freeze
1726 *
1727 * Freeze SFF controller port.
1728 *
1729 * LOCKING:
1730 * Inherited from caller.
1731 */
1732void ata_sff_freeze(struct ata_port *ap)
1733{
1734 ap->ctl |= ATA_NIEN;
1735 ap->last_ctl = ap->ctl;
1736
1737 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr)
1738 ata_sff_set_devctl(ap, ap->ctl);
1739
1740 /* Under certain circumstances, some controllers raise IRQ on
1741 * ATA_NIEN manipulation. Also, many controllers fail to mask
1742 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1743 */
1744 ap->ops->sff_check_status(ap);
1745
1746 if (ap->ops->sff_irq_clear)
1747 ap->ops->sff_irq_clear(ap);
1748}
1749EXPORT_SYMBOL_GPL(ata_sff_freeze);
1750
1751/**
1752 * ata_sff_thaw - Thaw SFF controller port
1753 * @ap: port to thaw
1754 *
1755 * Thaw SFF controller port.
1756 *
1757 * LOCKING:
1758 * Inherited from caller.
1759 */
1760void ata_sff_thaw(struct ata_port *ap)
1761{
1762 /* clear & re-enable interrupts */
1763 ap->ops->sff_check_status(ap);
1764 if (ap->ops->sff_irq_clear)
1765 ap->ops->sff_irq_clear(ap);
1766 ata_sff_irq_on(ap);
1767}
1768EXPORT_SYMBOL_GPL(ata_sff_thaw);
1769
1770/**
1771 * ata_sff_prereset - prepare SFF link for reset
1772 * @link: SFF link to be reset
1773 * @deadline: deadline jiffies for the operation
1774 *
1775 * SFF link @link is about to be reset. Initialize it. It first
1776 * calls ata_std_prereset() and wait for !BSY if the port is
1777 * being softreset.
1778 *
1779 * LOCKING:
1780 * Kernel thread context (may sleep)
1781 *
1782 * RETURNS:
1783 * 0 on success, -errno otherwise.
1784 */
1785int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
1786{
1787 struct ata_eh_context *ehc = &link->eh_context;
1788 int rc;
1789
1790 rc = ata_std_prereset(link, deadline);
1791 if (rc)
1792 return rc;
1793
1794 /* if we're about to do hardreset, nothing more to do */
1795 if (ehc->i.action & ATA_EH_HARDRESET)
1796 return 0;
1797
1798 /* wait for !BSY if we don't know that no device is attached */
1799 if (!ata_link_offline(link)) {
1800 rc = ata_sff_wait_ready(link, deadline);
1801 if (rc && rc != -ENODEV) {
1802 ata_link_warn(link,
1803 "device not ready (errno=%d), forcing hardreset\n",
1804 rc);
1805 ehc->i.action |= ATA_EH_HARDRESET;
1806 }
1807 }
1808
1809 return 0;
1810}
1811EXPORT_SYMBOL_GPL(ata_sff_prereset);
1812
1813/**
1814 * ata_devchk - PATA device presence detection
1815 * @ap: ATA channel to examine
1816 * @device: Device to examine (starting at zero)
1817 *
1818 * This technique was originally described in
1819 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1820 * later found its way into the ATA/ATAPI spec.
1821 *
1822 * Write a pattern to the ATA shadow registers,
1823 * and if a device is present, it will respond by
1824 * correctly storing and echoing back the
1825 * ATA shadow register contents.
1826 *
1827 * LOCKING:
1828 * caller.
1829 */
1830static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
1831{
1832 struct ata_ioports *ioaddr = &ap->ioaddr;
1833 u8 nsect, lbal;
1834
1835 ap->ops->sff_dev_select(ap, device);
1836
1837 iowrite8(0x55, ioaddr->nsect_addr);
1838 iowrite8(0xaa, ioaddr->lbal_addr);
1839
1840 iowrite8(0xaa, ioaddr->nsect_addr);
1841 iowrite8(0x55, ioaddr->lbal_addr);
1842
1843 iowrite8(0x55, ioaddr->nsect_addr);
1844 iowrite8(0xaa, ioaddr->lbal_addr);
1845
1846 nsect = ioread8(ioaddr->nsect_addr);
1847 lbal = ioread8(ioaddr->lbal_addr);
1848
1849 if ((nsect == 0x55) && (lbal == 0xaa))
1850 return 1; /* we found a device */
1851
1852 return 0; /* nothing found */
1853}
1854
1855/**
1856 * ata_sff_dev_classify - Parse returned ATA device signature
1857 * @dev: ATA device to classify (starting at zero)
1858 * @present: device seems present
1859 * @r_err: Value of error register on completion
1860 *
1861 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1862 * an ATA/ATAPI-defined set of values is placed in the ATA
1863 * shadow registers, indicating the results of device detection
1864 * and diagnostics.
1865 *
1866 * Select the ATA device, and read the values from the ATA shadow
1867 * registers. Then parse according to the Error register value,
1868 * and the spec-defined values examined by ata_dev_classify().
1869 *
1870 * LOCKING:
1871 * caller.
1872 *
1873 * RETURNS:
1874 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1875 */
1876unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
1877 u8 *r_err)
1878{
1879 struct ata_port *ap = dev->link->ap;
1880 struct ata_taskfile tf;
1881 unsigned int class;
1882 u8 err;
1883
1884 ap->ops->sff_dev_select(ap, dev->devno);
1885
1886 memset(&tf, 0, sizeof(tf));
1887
1888 ap->ops->sff_tf_read(ap, &tf);
1889 err = tf.feature;
1890 if (r_err)
1891 *r_err = err;
1892
1893 /* see if device passed diags: continue and warn later */
1894 if (err == 0)
1895 /* diagnostic fail : do nothing _YET_ */
1896 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1897 else if (err == 1)
1898 /* do nothing */ ;
1899 else if ((dev->devno == 0) && (err == 0x81))
1900 /* do nothing */ ;
1901 else
1902 return ATA_DEV_NONE;
1903
1904 /* determine if device is ATA or ATAPI */
1905 class = ata_dev_classify(&tf);
1906
1907 if (class == ATA_DEV_UNKNOWN) {
1908 /* If the device failed diagnostic, it's likely to
1909 * have reported incorrect device signature too.
1910 * Assume ATA device if the device seems present but
1911 * device signature is invalid with diagnostic
1912 * failure.
1913 */
1914 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1915 class = ATA_DEV_ATA;
1916 else
1917 class = ATA_DEV_NONE;
1918 } else if ((class == ATA_DEV_ATA) &&
1919 (ap->ops->sff_check_status(ap) == 0))
1920 class = ATA_DEV_NONE;
1921
1922 return class;
1923}
1924EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
1925
1926/**
1927 * ata_sff_wait_after_reset - wait for devices to become ready after reset
1928 * @link: SFF link which is just reset
1929 * @devmask: mask of present devices
1930 * @deadline: deadline jiffies for the operation
1931 *
1932 * Wait devices attached to SFF @link to become ready after
1933 * reset. It contains preceding 150ms wait to avoid accessing TF
1934 * status register too early.
1935 *
1936 * LOCKING:
1937 * Kernel thread context (may sleep).
1938 *
1939 * RETURNS:
1940 * 0 on success, -ENODEV if some or all of devices in @devmask
1941 * don't seem to exist. -errno on other errors.
1942 */
1943int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
1944 unsigned long deadline)
1945{
1946 struct ata_port *ap = link->ap;
1947 struct ata_ioports *ioaddr = &ap->ioaddr;
1948 unsigned int dev0 = devmask & (1 << 0);
1949 unsigned int dev1 = devmask & (1 << 1);
1950 int rc, ret = 0;
1951
1952 ata_msleep(ap, ATA_WAIT_AFTER_RESET);
1953
1954 /* always check readiness of the master device */
1955 rc = ata_sff_wait_ready(link, deadline);
1956 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
1957 * and TF status is 0xff, bail out on it too.
1958 */
1959 if (rc)
1960 return rc;
1961
1962 /* if device 1 was found in ata_devchk, wait for register
1963 * access briefly, then wait for BSY to clear.
1964 */
1965 if (dev1) {
1966 int i;
1967
1968 ap->ops->sff_dev_select(ap, 1);
1969
1970 /* Wait for register access. Some ATAPI devices fail
1971 * to set nsect/lbal after reset, so don't waste too
1972 * much time on it. We're gonna wait for !BSY anyway.
1973 */
1974 for (i = 0; i < 2; i++) {
1975 u8 nsect, lbal;
1976
1977 nsect = ioread8(ioaddr->nsect_addr);
1978 lbal = ioread8(ioaddr->lbal_addr);
1979 if ((nsect == 1) && (lbal == 1))
1980 break;
1981 ata_msleep(ap, 50); /* give drive a breather */
1982 }
1983
1984 rc = ata_sff_wait_ready(link, deadline);
1985 if (rc) {
1986 if (rc != -ENODEV)
1987 return rc;
1988 ret = rc;
1989 }
1990 }
1991
1992 /* is all this really necessary? */
1993 ap->ops->sff_dev_select(ap, 0);
1994 if (dev1)
1995 ap->ops->sff_dev_select(ap, 1);
1996 if (dev0)
1997 ap->ops->sff_dev_select(ap, 0);
1998
1999 return ret;
2000}
2001EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
2002
2003static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
2004 unsigned long deadline)
2005{
2006 struct ata_ioports *ioaddr = &ap->ioaddr;
2007
2008 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
2009
2010 /* software reset. causes dev0 to be selected */
2011 iowrite8(ap->ctl, ioaddr->ctl_addr);
2012 udelay(20); /* FIXME: flush */
2013 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
2014 udelay(20); /* FIXME: flush */
2015 iowrite8(ap->ctl, ioaddr->ctl_addr);
2016 ap->last_ctl = ap->ctl;
2017
2018 /* wait the port to become ready */
2019 return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
2020}
2021
2022/**
2023 * ata_sff_softreset - reset host port via ATA SRST
2024 * @link: ATA link to reset
2025 * @classes: resulting classes of attached devices
2026 * @deadline: deadline jiffies for the operation
2027 *
2028 * Reset host port using ATA SRST.
2029 *
2030 * LOCKING:
2031 * Kernel thread context (may sleep)
2032 *
2033 * RETURNS:
2034 * 0 on success, -errno otherwise.
2035 */
2036int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
2037 unsigned long deadline)
2038{
2039 struct ata_port *ap = link->ap;
2040 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2041 unsigned int devmask = 0;
2042 int rc;
2043 u8 err;
2044
2045 DPRINTK("ENTER\n");
2046
2047 /* determine if device 0/1 are present */
2048 if (ata_devchk(ap, 0))
2049 devmask |= (1 << 0);
2050 if (slave_possible && ata_devchk(ap, 1))
2051 devmask |= (1 << 1);
2052
2053 /* select device 0 again */
2054 ap->ops->sff_dev_select(ap, 0);
2055
2056 /* issue bus reset */
2057 DPRINTK("about to softreset, devmask=%x\n", devmask);
2058 rc = ata_bus_softreset(ap, devmask, deadline);
2059 /* if link is occupied, -ENODEV too is an error */
2060 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
2061 ata_link_err(link, "SRST failed (errno=%d)\n", rc);
2062 return rc;
2063 }
2064
2065 /* determine by signature whether we have ATA or ATAPI devices */
2066 classes[0] = ata_sff_dev_classify(&link->device[0],
2067 devmask & (1 << 0), &err);
2068 if (slave_possible && err != 0x81)
2069 classes[1] = ata_sff_dev_classify(&link->device[1],
2070 devmask & (1 << 1), &err);
2071
2072 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2073 return 0;
2074}
2075EXPORT_SYMBOL_GPL(ata_sff_softreset);
2076
2077/**
2078 * sata_sff_hardreset - reset host port via SATA phy reset
2079 * @link: link to reset
2080 * @class: resulting class of attached device
2081 * @deadline: deadline jiffies for the operation
2082 *
2083 * SATA phy-reset host port using DET bits of SControl register,
2084 * wait for !BSY and classify the attached device.
2085 *
2086 * LOCKING:
2087 * Kernel thread context (may sleep)
2088 *
2089 * RETURNS:
2090 * 0 on success, -errno otherwise.
2091 */
2092int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
2093 unsigned long deadline)
2094{
2095 struct ata_eh_context *ehc = &link->eh_context;
2096 const unsigned long *timing = sata_ehc_deb_timing(ehc);
2097 bool online;
2098 int rc;
2099
2100 rc = sata_link_hardreset(link, timing, deadline, &online,
2101 ata_sff_check_ready);
2102 if (online)
2103 *class = ata_sff_dev_classify(link->device, 1, NULL);
2104
2105 DPRINTK("EXIT, class=%u\n", *class);
2106 return rc;
2107}
2108EXPORT_SYMBOL_GPL(sata_sff_hardreset);
2109
2110/**
2111 * ata_sff_postreset - SFF postreset callback
2112 * @link: the target SFF ata_link
2113 * @classes: classes of attached devices
2114 *
2115 * This function is invoked after a successful reset. It first
2116 * calls ata_std_postreset() and performs SFF specific postreset
2117 * processing.
2118 *
2119 * LOCKING:
2120 * Kernel thread context (may sleep)
2121 */
2122void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
2123{
2124 struct ata_port *ap = link->ap;
2125
2126 ata_std_postreset(link, classes);
2127
2128 /* is double-select really necessary? */
2129 if (classes[0] != ATA_DEV_NONE)
2130 ap->ops->sff_dev_select(ap, 1);
2131 if (classes[1] != ATA_DEV_NONE)
2132 ap->ops->sff_dev_select(ap, 0);
2133
2134 /* bail out if no device is present */
2135 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2136 DPRINTK("EXIT, no device\n");
2137 return;
2138 }
2139
2140 /* set up device control */
2141 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) {
2142 ata_sff_set_devctl(ap, ap->ctl);
2143 ap->last_ctl = ap->ctl;
2144 }
2145}
2146EXPORT_SYMBOL_GPL(ata_sff_postreset);
2147
2148/**
2149 * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers
2150 * @qc: command
2151 *
2152 * Drain the FIFO and device of any stuck data following a command
2153 * failing to complete. In some cases this is necessary before a
2154 * reset will recover the device.
2155 *
2156 */
2157
2158void ata_sff_drain_fifo(struct ata_queued_cmd *qc)
2159{
2160 int count;
2161 struct ata_port *ap;
2162
2163 /* We only need to flush incoming data when a command was running */
2164 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
2165 return;
2166
2167 ap = qc->ap;
2168 /* Drain up to 64K of data before we give up this recovery method */
2169 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
2170 && count < 65536; count += 2)
2171 ioread16(ap->ioaddr.data_addr);
2172
2173 /* Can become DEBUG later */
2174 if (count)
2175 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
2176
2177}
2178EXPORT_SYMBOL_GPL(ata_sff_drain_fifo);
2179
2180/**
2181 * ata_sff_error_handler - Stock error handler for SFF controller
2182 * @ap: port to handle error for
2183 *
2184 * Stock error handler for SFF controller. It can handle both
2185 * PATA and SATA controllers. Many controllers should be able to
2186 * use this EH as-is or with some added handling before and
2187 * after.
2188 *
2189 * LOCKING:
2190 * Kernel thread context (may sleep)
2191 */
2192void ata_sff_error_handler(struct ata_port *ap)
2193{
2194 ata_reset_fn_t softreset = ap->ops->softreset;
2195 ata_reset_fn_t hardreset = ap->ops->hardreset;
2196 struct ata_queued_cmd *qc;
2197 unsigned long flags;
2198
2199 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2200 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2201 qc = NULL;
2202
2203 spin_lock_irqsave(ap->lock, flags);
2204
2205 /*
2206 * We *MUST* do FIFO draining before we issue a reset as
2207 * several devices helpfully clear their internal state and
2208 * will lock solid if we touch the data port post reset. Pass
2209 * qc in case anyone wants to do different PIO/DMA recovery or
2210 * has per command fixups
2211 */
2212 if (ap->ops->sff_drain_fifo)
2213 ap->ops->sff_drain_fifo(qc);
2214
2215 spin_unlock_irqrestore(ap->lock, flags);
2216
2217 /* ignore ata_sff_softreset if ctl isn't accessible */
2218 if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr)
2219 softreset = NULL;
2220
2221 /* ignore built-in hardresets if SCR access is not available */
2222 if ((hardreset == sata_std_hardreset ||
2223 hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link))
2224 hardreset = NULL;
2225
2226 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2227 ap->ops->postreset);
2228}
2229EXPORT_SYMBOL_GPL(ata_sff_error_handler);
2230
2231/**
2232 * ata_sff_std_ports - initialize ioaddr with standard port offsets.
2233 * @ioaddr: IO address structure to be initialized
2234 *
2235 * Utility function which initializes data_addr, error_addr,
2236 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2237 * device_addr, status_addr, and command_addr to standard offsets
2238 * relative to cmd_addr.
2239 *
2240 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2241 */
2242void ata_sff_std_ports(struct ata_ioports *ioaddr)
2243{
2244 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2245 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2246 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2247 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2248 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2249 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2250 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2251 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2252 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2253 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2254}
2255EXPORT_SYMBOL_GPL(ata_sff_std_ports);
2256
2257#ifdef CONFIG_PCI
2258
2259static int ata_resources_present(struct pci_dev *pdev, int port)
2260{
2261 int i;
2262
2263 /* Check the PCI resources for this channel are enabled */
2264 port = port * 2;
2265 for (i = 0; i < 2; i++) {
2266 if (pci_resource_start(pdev, port + i) == 0 ||
2267 pci_resource_len(pdev, port + i) == 0)
2268 return 0;
2269 }
2270 return 1;
2271}
2272
2273/**
2274 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
2275 * @host: target ATA host
2276 *
2277 * Acquire native PCI ATA resources for @host and initialize the
2278 * first two ports of @host accordingly. Ports marked dummy are
2279 * skipped and allocation failure makes the port dummy.
2280 *
2281 * Note that native PCI resources are valid even for legacy hosts
2282 * as we fix up pdev resources array early in boot, so this
2283 * function can be used for both native and legacy SFF hosts.
2284 *
2285 * LOCKING:
2286 * Inherited from calling layer (may sleep).
2287 *
2288 * RETURNS:
2289 * 0 if at least one port is initialized, -ENODEV if no port is
2290 * available.
2291 */
2292int ata_pci_sff_init_host(struct ata_host *host)
2293{
2294 struct device *gdev = host->dev;
2295 struct pci_dev *pdev = to_pci_dev(gdev);
2296 unsigned int mask = 0;
2297 int i, rc;
2298
2299 /* request, iomap BARs and init port addresses accordingly */
2300 for (i = 0; i < 2; i++) {
2301 struct ata_port *ap = host->ports[i];
2302 int base = i * 2;
2303 void __iomem * const *iomap;
2304
2305 if (ata_port_is_dummy(ap))
2306 continue;
2307
2308 /* Discard disabled ports. Some controllers show
2309 * their unused channels this way. Disabled ports are
2310 * made dummy.
2311 */
2312 if (!ata_resources_present(pdev, i)) {
2313 ap->ops = &ata_dummy_port_ops;
2314 continue;
2315 }
2316
2317 rc = pcim_iomap_regions(pdev, 0x3 << base,
2318 dev_driver_string(gdev));
2319 if (rc) {
2320 dev_warn(gdev,
2321 "failed to request/iomap BARs for port %d (errno=%d)\n",
2322 i, rc);
2323 if (rc == -EBUSY)
2324 pcim_pin_device(pdev);
2325 ap->ops = &ata_dummy_port_ops;
2326 continue;
2327 }
2328 host->iomap = iomap = pcim_iomap_table(pdev);
2329
2330 ap->ioaddr.cmd_addr = iomap[base];
2331 ap->ioaddr.altstatus_addr =
2332 ap->ioaddr.ctl_addr = (void __iomem *)
2333 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
2334 ata_sff_std_ports(&ap->ioaddr);
2335
2336 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2337 (unsigned long long)pci_resource_start(pdev, base),
2338 (unsigned long long)pci_resource_start(pdev, base + 1));
2339
2340 mask |= 1 << i;
2341 }
2342
2343 if (!mask) {
2344 dev_err(gdev, "no available native port\n");
2345 return -ENODEV;
2346 }
2347
2348 return 0;
2349}
2350EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
2351
2352/**
2353 * ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host
2354 * @pdev: target PCI device
2355 * @ppi: array of port_info, must be enough for two ports
2356 * @r_host: out argument for the initialized ATA host
2357 *
2358 * Helper to allocate PIO-only SFF ATA host for @pdev, acquire
2359 * all PCI resources and initialize it accordingly in one go.
2360 *
2361 * LOCKING:
2362 * Inherited from calling layer (may sleep).
2363 *
2364 * RETURNS:
2365 * 0 on success, -errno otherwise.
2366 */
2367int ata_pci_sff_prepare_host(struct pci_dev *pdev,
2368 const struct ata_port_info * const *ppi,
2369 struct ata_host **r_host)
2370{
2371 struct ata_host *host;
2372 int rc;
2373
2374 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2375 return -ENOMEM;
2376
2377 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2378 if (!host) {
2379 dev_err(&pdev->dev, "failed to allocate ATA host\n");
2380 rc = -ENOMEM;
2381 goto err_out;
2382 }
2383
2384 rc = ata_pci_sff_init_host(host);
2385 if (rc)
2386 goto err_out;
2387
2388 devres_remove_group(&pdev->dev, NULL);
2389 *r_host = host;
2390 return 0;
2391
2392err_out:
2393 devres_release_group(&pdev->dev, NULL);
2394 return rc;
2395}
2396EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
2397
2398/**
2399 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
2400 * @host: target SFF ATA host
2401 * @irq_handler: irq_handler used when requesting IRQ(s)
2402 * @sht: scsi_host_template to use when registering the host
2403 *
2404 * This is the counterpart of ata_host_activate() for SFF ATA
2405 * hosts. This separate helper is necessary because SFF hosts
2406 * use two separate interrupts in legacy mode.
2407 *
2408 * LOCKING:
2409 * Inherited from calling layer (may sleep).
2410 *
2411 * RETURNS:
2412 * 0 on success, -errno otherwise.
2413 */
2414int ata_pci_sff_activate_host(struct ata_host *host,
2415 irq_handler_t irq_handler,
2416 struct scsi_host_template *sht)
2417{
2418 struct device *dev = host->dev;
2419 struct pci_dev *pdev = to_pci_dev(dev);
2420 const char *drv_name = dev_driver_string(host->dev);
2421 int legacy_mode = 0, rc;
2422
2423 rc = ata_host_start(host);
2424 if (rc)
2425 return rc;
2426
2427 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2428 u8 tmp8, mask;
2429
2430 /* TODO: What if one channel is in native mode ... */
2431 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2432 mask = (1 << 2) | (1 << 0);
2433 if ((tmp8 & mask) != mask)
2434 legacy_mode = 1;
2435#if defined(CONFIG_NO_ATA_LEGACY)
2436 /* Some platforms with PCI limits cannot address compat
2437 port space. In that case we punt if their firmware has
2438 left a device in compatibility mode */
2439 if (legacy_mode) {
2440 printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n");
2441 return -EOPNOTSUPP;
2442 }
2443#endif
2444 }
2445
2446 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2447 return -ENOMEM;
2448
2449 if (!legacy_mode && pdev->irq) {
2450 int i;
2451
2452 rc = devm_request_irq(dev, pdev->irq, irq_handler,
2453 IRQF_SHARED, drv_name, host);
2454 if (rc)
2455 goto out;
2456
2457 for (i = 0; i < 2; i++) {
2458 if (ata_port_is_dummy(host->ports[i]))
2459 continue;
2460 ata_port_desc(host->ports[i], "irq %d", pdev->irq);
2461 }
2462 } else if (legacy_mode) {
2463 if (!ata_port_is_dummy(host->ports[0])) {
2464 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2465 irq_handler, IRQF_SHARED,
2466 drv_name, host);
2467 if (rc)
2468 goto out;
2469
2470 ata_port_desc(host->ports[0], "irq %d",
2471 ATA_PRIMARY_IRQ(pdev));
2472 }
2473
2474 if (!ata_port_is_dummy(host->ports[1])) {
2475 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2476 irq_handler, IRQF_SHARED,
2477 drv_name, host);
2478 if (rc)
2479 goto out;
2480
2481 ata_port_desc(host->ports[1], "irq %d",
2482 ATA_SECONDARY_IRQ(pdev));
2483 }
2484 }
2485
2486 rc = ata_host_register(host, sht);
2487out:
2488 if (rc == 0)
2489 devres_remove_group(dev, NULL);
2490 else
2491 devres_release_group(dev, NULL);
2492
2493 return rc;
2494}
2495EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
2496
2497static const struct ata_port_info *ata_sff_find_valid_pi(
2498 const struct ata_port_info * const *ppi)
2499{
2500 int i;
2501
2502 /* look up the first valid port_info */
2503 for (i = 0; i < 2 && ppi[i]; i++)
2504 if (ppi[i]->port_ops != &ata_dummy_port_ops)
2505 return ppi[i];
2506
2507 return NULL;
2508}
2509
2510/**
2511 * ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller
2512 * @pdev: Controller to be initialized
2513 * @ppi: array of port_info, must be enough for two ports
2514 * @sht: scsi_host_template to use when registering the host
2515 * @host_priv: host private_data
2516 * @hflag: host flags
2517 *
2518 * This is a helper function which can be called from a driver's
2519 * xxx_init_one() probe function if the hardware uses traditional
2520 * IDE taskfile registers and is PIO only.
2521 *
2522 * ASSUMPTION:
2523 * Nobody makes a single channel controller that appears solely as
2524 * the secondary legacy port on PCI.
2525 *
2526 * LOCKING:
2527 * Inherited from PCI layer (may sleep).
2528 *
2529 * RETURNS:
2530 * Zero on success, negative on errno-based value on error.
2531 */
2532int ata_pci_sff_init_one(struct pci_dev *pdev,
2533 const struct ata_port_info * const *ppi,
2534 struct scsi_host_template *sht, void *host_priv, int hflag)
2535{
2536 struct device *dev = &pdev->dev;
2537 const struct ata_port_info *pi;
2538 struct ata_host *host = NULL;
2539 int rc;
2540
2541 DPRINTK("ENTER\n");
2542
2543 pi = ata_sff_find_valid_pi(ppi);
2544 if (!pi) {
2545 dev_err(&pdev->dev, "no valid port_info specified\n");
2546 return -EINVAL;
2547 }
2548
2549 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2550 return -ENOMEM;
2551
2552 rc = pcim_enable_device(pdev);
2553 if (rc)
2554 goto out;
2555
2556 /* prepare and activate SFF host */
2557 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
2558 if (rc)
2559 goto out;
2560 host->private_data = host_priv;
2561 host->flags |= hflag;
2562
2563 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
2564out:
2565 if (rc == 0)
2566 devres_remove_group(&pdev->dev, NULL);
2567 else
2568 devres_release_group(&pdev->dev, NULL);
2569
2570 return rc;
2571}
2572EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
2573
2574#endif /* CONFIG_PCI */
2575
2576/*
2577 * BMDMA support
2578 */
2579
2580#ifdef CONFIG_ATA_BMDMA
2581
2582const struct ata_port_operations ata_bmdma_port_ops = {
2583 .inherits = &ata_sff_port_ops,
2584
2585 .error_handler = ata_bmdma_error_handler,
2586 .post_internal_cmd = ata_bmdma_post_internal_cmd,
2587
2588 .qc_prep = ata_bmdma_qc_prep,
2589 .qc_issue = ata_bmdma_qc_issue,
2590
2591 .sff_irq_clear = ata_bmdma_irq_clear,
2592 .bmdma_setup = ata_bmdma_setup,
2593 .bmdma_start = ata_bmdma_start,
2594 .bmdma_stop = ata_bmdma_stop,
2595 .bmdma_status = ata_bmdma_status,
2596
2597 .port_start = ata_bmdma_port_start,
2598};
2599EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
2600
2601const struct ata_port_operations ata_bmdma32_port_ops = {
2602 .inherits = &ata_bmdma_port_ops,
2603
2604 .sff_data_xfer = ata_sff_data_xfer32,
2605 .port_start = ata_bmdma_port_start32,
2606};
2607EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
2608
2609/**
2610 * ata_bmdma_fill_sg - Fill PCI IDE PRD table
2611 * @qc: Metadata associated with taskfile to be transferred
2612 *
2613 * Fill PCI IDE PRD (scatter-gather) table with segments
2614 * associated with the current disk command.
2615 *
2616 * LOCKING:
2617 * spin_lock_irqsave(host lock)
2618 *
2619 */
2620static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc)
2621{
2622 struct ata_port *ap = qc->ap;
2623 struct ata_bmdma_prd *prd = ap->bmdma_prd;
2624 struct scatterlist *sg;
2625 unsigned int si, pi;
2626
2627 pi = 0;
2628 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2629 u32 addr, offset;
2630 u32 sg_len, len;
2631
2632 /* determine if physical DMA addr spans 64K boundary.
2633 * Note h/w doesn't support 64-bit, so we unconditionally
2634 * truncate dma_addr_t to u32.
2635 */
2636 addr = (u32) sg_dma_address(sg);
2637 sg_len = sg_dma_len(sg);
2638
2639 while (sg_len) {
2640 offset = addr & 0xffff;
2641 len = sg_len;
2642 if ((offset + sg_len) > 0x10000)
2643 len = 0x10000 - offset;
2644
2645 prd[pi].addr = cpu_to_le32(addr);
2646 prd[pi].flags_len = cpu_to_le32(len & 0xffff);
2647 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
2648
2649 pi++;
2650 sg_len -= len;
2651 addr += len;
2652 }
2653 }
2654
2655 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2656}
2657
2658/**
2659 * ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table
2660 * @qc: Metadata associated with taskfile to be transferred
2661 *
2662 * Fill PCI IDE PRD (scatter-gather) table with segments
2663 * associated with the current disk command. Perform the fill
2664 * so that we avoid writing any length 64K records for
2665 * controllers that don't follow the spec.
2666 *
2667 * LOCKING:
2668 * spin_lock_irqsave(host lock)
2669 *
2670 */
2671static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc)
2672{
2673 struct ata_port *ap = qc->ap;
2674 struct ata_bmdma_prd *prd = ap->bmdma_prd;
2675 struct scatterlist *sg;
2676 unsigned int si, pi;
2677
2678 pi = 0;
2679 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2680 u32 addr, offset;
2681 u32 sg_len, len, blen;
2682
2683 /* determine if physical DMA addr spans 64K boundary.
2684 * Note h/w doesn't support 64-bit, so we unconditionally
2685 * truncate dma_addr_t to u32.
2686 */
2687 addr = (u32) sg_dma_address(sg);
2688 sg_len = sg_dma_len(sg);
2689
2690 while (sg_len) {
2691 offset = addr & 0xffff;
2692 len = sg_len;
2693 if ((offset + sg_len) > 0x10000)
2694 len = 0x10000 - offset;
2695
2696 blen = len & 0xffff;
2697 prd[pi].addr = cpu_to_le32(addr);
2698 if (blen == 0) {
2699 /* Some PATA chipsets like the CS5530 can't
2700 cope with 0x0000 meaning 64K as the spec
2701 says */
2702 prd[pi].flags_len = cpu_to_le32(0x8000);
2703 blen = 0x8000;
2704 prd[++pi].addr = cpu_to_le32(addr + 0x8000);
2705 }
2706 prd[pi].flags_len = cpu_to_le32(blen);
2707 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
2708
2709 pi++;
2710 sg_len -= len;
2711 addr += len;
2712 }
2713 }
2714
2715 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2716}
2717
2718/**
2719 * ata_bmdma_qc_prep - Prepare taskfile for submission
2720 * @qc: Metadata associated with taskfile to be prepared
2721 *
2722 * Prepare ATA taskfile for submission.
2723 *
2724 * LOCKING:
2725 * spin_lock_irqsave(host lock)
2726 */
2727void ata_bmdma_qc_prep(struct ata_queued_cmd *qc)
2728{
2729 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2730 return;
2731
2732 ata_bmdma_fill_sg(qc);
2733}
2734EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep);
2735
2736/**
2737 * ata_bmdma_dumb_qc_prep - Prepare taskfile for submission
2738 * @qc: Metadata associated with taskfile to be prepared
2739 *
2740 * Prepare ATA taskfile for submission.
2741 *
2742 * LOCKING:
2743 * spin_lock_irqsave(host lock)
2744 */
2745void ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc)
2746{
2747 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2748 return;
2749
2750 ata_bmdma_fill_sg_dumb(qc);
2751}
2752EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep);
2753
2754/**
2755 * ata_bmdma_qc_issue - issue taskfile to a BMDMA controller
2756 * @qc: command to issue to device
2757 *
2758 * This function issues a PIO, NODATA or DMA command to a
2759 * SFF/BMDMA controller. PIO and NODATA are handled by
2760 * ata_sff_qc_issue().
2761 *
2762 * LOCKING:
2763 * spin_lock_irqsave(host lock)
2764 *
2765 * RETURNS:
2766 * Zero on success, AC_ERR_* mask on failure
2767 */
2768unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc)
2769{
2770 struct ata_port *ap = qc->ap;
2771 struct ata_link *link = qc->dev->link;
2772
2773 /* defer PIO handling to sff_qc_issue */
2774 if (!ata_is_dma(qc->tf.protocol))
2775 return ata_sff_qc_issue(qc);
2776
2777 /* select the device */
2778 ata_dev_select(ap, qc->dev->devno, 1, 0);
2779
2780 /* start the command */
2781 switch (qc->tf.protocol) {
2782 case ATA_PROT_DMA:
2783 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2784
2785 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2786 ap->ops->bmdma_setup(qc); /* set up bmdma */
2787 ap->ops->bmdma_start(qc); /* initiate bmdma */
2788 ap->hsm_task_state = HSM_ST_LAST;
2789 break;
2790
2791 case ATAPI_PROT_DMA:
2792 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2793
2794 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2795 ap->ops->bmdma_setup(qc); /* set up bmdma */
2796 ap->hsm_task_state = HSM_ST_FIRST;
2797
2798 /* send cdb by polling if no cdb interrupt */
2799 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
2800 ata_sff_queue_pio_task(link, 0);
2801 break;
2802
2803 default:
2804 WARN_ON(1);
2805 return AC_ERR_SYSTEM;
2806 }
2807
2808 return 0;
2809}
2810EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue);
2811
2812/**
2813 * ata_bmdma_port_intr - Handle BMDMA port interrupt
2814 * @ap: Port on which interrupt arrived (possibly...)
2815 * @qc: Taskfile currently active in engine
2816 *
2817 * Handle port interrupt for given queued command.
2818 *
2819 * LOCKING:
2820 * spin_lock_irqsave(host lock)
2821 *
2822 * RETURNS:
2823 * One if interrupt was handled, zero if not (shared irq).
2824 */
2825unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
2826{
2827 struct ata_eh_info *ehi = &ap->link.eh_info;
2828 u8 host_stat = 0;
2829 bool bmdma_stopped = false;
2830 unsigned int handled;
2831
2832 if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) {
2833 /* check status of DMA engine */
2834 host_stat = ap->ops->bmdma_status(ap);
2835 VPRINTK("ata%u: host_stat 0x%X\n", ap->print_id, host_stat);
2836
2837 /* if it's not our irq... */
2838 if (!(host_stat & ATA_DMA_INTR))
2839 return ata_sff_idle_irq(ap);
2840
2841 /* before we do anything else, clear DMA-Start bit */
2842 ap->ops->bmdma_stop(qc);
2843 bmdma_stopped = true;
2844
2845 if (unlikely(host_stat & ATA_DMA_ERR)) {
2846 /* error when transferring data to/from memory */
2847 qc->err_mask |= AC_ERR_HOST_BUS;
2848 ap->hsm_task_state = HSM_ST_ERR;
2849 }
2850 }
2851
2852 handled = __ata_sff_port_intr(ap, qc, bmdma_stopped);
2853
2854 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
2855 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
2856
2857 return handled;
2858}
2859EXPORT_SYMBOL_GPL(ata_bmdma_port_intr);
2860
2861/**
2862 * ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler
2863 * @irq: irq line (unused)
2864 * @dev_instance: pointer to our ata_host information structure
2865 *
2866 * Default interrupt handler for PCI IDE devices. Calls
2867 * ata_bmdma_port_intr() for each port that is not disabled.
2868 *
2869 * LOCKING:
2870 * Obtains host lock during operation.
2871 *
2872 * RETURNS:
2873 * IRQ_NONE or IRQ_HANDLED.
2874 */
2875irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance)
2876{
2877 return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr);
2878}
2879EXPORT_SYMBOL_GPL(ata_bmdma_interrupt);
2880
2881/**
2882 * ata_bmdma_error_handler - Stock error handler for BMDMA controller
2883 * @ap: port to handle error for
2884 *
2885 * Stock error handler for BMDMA controller. It can handle both
2886 * PATA and SATA controllers. Most BMDMA controllers should be
2887 * able to use this EH as-is or with some added handling before
2888 * and after.
2889 *
2890 * LOCKING:
2891 * Kernel thread context (may sleep)
2892 */
2893void ata_bmdma_error_handler(struct ata_port *ap)
2894{
2895 struct ata_queued_cmd *qc;
2896 unsigned long flags;
2897 bool thaw = false;
2898
2899 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2900 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2901 qc = NULL;
2902
2903 /* reset PIO HSM and stop DMA engine */
2904 spin_lock_irqsave(ap->lock, flags);
2905
2906 if (qc && ata_is_dma(qc->tf.protocol)) {
2907 u8 host_stat;
2908
2909 host_stat = ap->ops->bmdma_status(ap);
2910
2911 /* BMDMA controllers indicate host bus error by
2912 * setting DMA_ERR bit and timing out. As it wasn't
2913 * really a timeout event, adjust error mask and
2914 * cancel frozen state.
2915 */
2916 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
2917 qc->err_mask = AC_ERR_HOST_BUS;
2918 thaw = true;
2919 }
2920
2921 ap->ops->bmdma_stop(qc);
2922
2923 /* if we're gonna thaw, make sure IRQ is clear */
2924 if (thaw) {
2925 ap->ops->sff_check_status(ap);
2926 if (ap->ops->sff_irq_clear)
2927 ap->ops->sff_irq_clear(ap);
2928 }
2929 }
2930
2931 spin_unlock_irqrestore(ap->lock, flags);
2932
2933 if (thaw)
2934 ata_eh_thaw_port(ap);
2935
2936 ata_sff_error_handler(ap);
2937}
2938EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
2939
2940/**
2941 * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA
2942 * @qc: internal command to clean up
2943 *
2944 * LOCKING:
2945 * Kernel thread context (may sleep)
2946 */
2947void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
2948{
2949 struct ata_port *ap = qc->ap;
2950 unsigned long flags;
2951
2952 if (ata_is_dma(qc->tf.protocol)) {
2953 spin_lock_irqsave(ap->lock, flags);
2954 ap->ops->bmdma_stop(qc);
2955 spin_unlock_irqrestore(ap->lock, flags);
2956 }
2957}
2958EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
2959
2960/**
2961 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
2962 * @ap: Port associated with this ATA transaction.
2963 *
2964 * Clear interrupt and error flags in DMA status register.
2965 *
2966 * May be used as the irq_clear() entry in ata_port_operations.
2967 *
2968 * LOCKING:
2969 * spin_lock_irqsave(host lock)
2970 */
2971void ata_bmdma_irq_clear(struct ata_port *ap)
2972{
2973 void __iomem *mmio = ap->ioaddr.bmdma_addr;
2974
2975 if (!mmio)
2976 return;
2977
2978 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
2979}
2980EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
2981
2982/**
2983 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
2984 * @qc: Info associated with this ATA transaction.
2985 *
2986 * LOCKING:
2987 * spin_lock_irqsave(host lock)
2988 */
2989void ata_bmdma_setup(struct ata_queued_cmd *qc)
2990{
2991 struct ata_port *ap = qc->ap;
2992 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
2993 u8 dmactl;
2994
2995 /* load PRD table addr. */
2996 mb(); /* make sure PRD table writes are visible to controller */
2997 iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2998
2999 /* specify data direction, triple-check start bit is clear */
3000 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3001 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3002 if (!rw)
3003 dmactl |= ATA_DMA_WR;
3004 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3005
3006 /* issue r/w command */
3007 ap->ops->sff_exec_command(ap, &qc->tf);
3008}
3009EXPORT_SYMBOL_GPL(ata_bmdma_setup);
3010
3011/**
3012 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
3013 * @qc: Info associated with this ATA transaction.
3014 *
3015 * LOCKING:
3016 * spin_lock_irqsave(host lock)
3017 */
3018void ata_bmdma_start(struct ata_queued_cmd *qc)
3019{
3020 struct ata_port *ap = qc->ap;
3021 u8 dmactl;
3022
3023 /* start host DMA transaction */
3024 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3025 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3026
3027 /* Strictly, one may wish to issue an ioread8() here, to
3028 * flush the mmio write. However, control also passes
3029 * to the hardware at this point, and it will interrupt
3030 * us when we are to resume control. So, in effect,
3031 * we don't care when the mmio write flushes.
3032 * Further, a read of the DMA status register _immediately_
3033 * following the write may not be what certain flaky hardware
3034 * is expected, so I think it is best to not add a readb()
3035 * without first all the MMIO ATA cards/mobos.
3036 * Or maybe I'm just being paranoid.
3037 *
3038 * FIXME: The posting of this write means I/O starts are
3039 * unnecessarily delayed for MMIO
3040 */
3041}
3042EXPORT_SYMBOL_GPL(ata_bmdma_start);
3043
3044/**
3045 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
3046 * @qc: Command we are ending DMA for
3047 *
3048 * Clears the ATA_DMA_START flag in the dma control register
3049 *
3050 * May be used as the bmdma_stop() entry in ata_port_operations.
3051 *
3052 * LOCKING:
3053 * spin_lock_irqsave(host lock)
3054 */
3055void ata_bmdma_stop(struct ata_queued_cmd *qc)
3056{
3057 struct ata_port *ap = qc->ap;
3058 void __iomem *mmio = ap->ioaddr.bmdma_addr;
3059
3060 /* clear start/stop bit */
3061 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
3062 mmio + ATA_DMA_CMD);
3063
3064 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
3065 ata_sff_dma_pause(ap);
3066}
3067EXPORT_SYMBOL_GPL(ata_bmdma_stop);
3068
3069/**
3070 * ata_bmdma_status - Read PCI IDE BMDMA status
3071 * @ap: Port associated with this ATA transaction.
3072 *
3073 * Read and return BMDMA status register.
3074 *
3075 * May be used as the bmdma_status() entry in ata_port_operations.
3076 *
3077 * LOCKING:
3078 * spin_lock_irqsave(host lock)
3079 */
3080u8 ata_bmdma_status(struct ata_port *ap)
3081{
3082 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
3083}
3084EXPORT_SYMBOL_GPL(ata_bmdma_status);
3085
3086
3087/**
3088 * ata_bmdma_port_start - Set port up for bmdma.
3089 * @ap: Port to initialize
3090 *
3091 * Called just after data structures for each port are
3092 * initialized. Allocates space for PRD table.
3093 *
3094 * May be used as the port_start() entry in ata_port_operations.
3095 *
3096 * LOCKING:
3097 * Inherited from caller.
3098 */
3099int ata_bmdma_port_start(struct ata_port *ap)
3100{
3101 if (ap->mwdma_mask || ap->udma_mask) {
3102 ap->bmdma_prd =
3103 dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ,
3104 &ap->bmdma_prd_dma, GFP_KERNEL);
3105 if (!ap->bmdma_prd)
3106 return -ENOMEM;
3107 }
3108
3109 return 0;
3110}
3111EXPORT_SYMBOL_GPL(ata_bmdma_port_start);
3112
3113/**
3114 * ata_bmdma_port_start32 - Set port up for dma.
3115 * @ap: Port to initialize
3116 *
3117 * Called just after data structures for each port are
3118 * initialized. Enables 32bit PIO and allocates space for PRD
3119 * table.
3120 *
3121 * May be used as the port_start() entry in ata_port_operations for
3122 * devices that are capable of 32bit PIO.
3123 *
3124 * LOCKING:
3125 * Inherited from caller.
3126 */
3127int ata_bmdma_port_start32(struct ata_port *ap)
3128{
3129 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
3130 return ata_bmdma_port_start(ap);
3131}
3132EXPORT_SYMBOL_GPL(ata_bmdma_port_start32);
3133
3134#ifdef CONFIG_PCI
3135
3136/**
3137 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
3138 * @pdev: PCI device
3139 *
3140 * Some PCI ATA devices report simplex mode but in fact can be told to
3141 * enter non simplex mode. This implements the necessary logic to
3142 * perform the task on such devices. Calling it on other devices will
3143 * have -undefined- behaviour.
3144 */
3145int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
3146{
3147 unsigned long bmdma = pci_resource_start(pdev, 4);
3148 u8 simplex;
3149
3150 if (bmdma == 0)
3151 return -ENOENT;
3152
3153 simplex = inb(bmdma + 0x02);
3154 outb(simplex & 0x60, bmdma + 0x02);
3155 simplex = inb(bmdma + 0x02);
3156 if (simplex & 0x80)
3157 return -EOPNOTSUPP;
3158 return 0;
3159}
3160EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
3161
3162static void ata_bmdma_nodma(struct ata_host *host, const char *reason)
3163{
3164 int i;
3165
3166 dev_err(host->dev, "BMDMA: %s, falling back to PIO\n", reason);
3167
3168 for (i = 0; i < 2; i++) {
3169 host->ports[i]->mwdma_mask = 0;
3170 host->ports[i]->udma_mask = 0;
3171 }
3172}
3173
3174/**
3175 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
3176 * @host: target ATA host
3177 *
3178 * Acquire PCI BMDMA resources and initialize @host accordingly.
3179 *
3180 * LOCKING:
3181 * Inherited from calling layer (may sleep).
3182 */
3183void ata_pci_bmdma_init(struct ata_host *host)
3184{
3185 struct device *gdev = host->dev;
3186 struct pci_dev *pdev = to_pci_dev(gdev);
3187 int i, rc;
3188
3189 /* No BAR4 allocation: No DMA */
3190 if (pci_resource_start(pdev, 4) == 0) {
3191 ata_bmdma_nodma(host, "BAR4 is zero");
3192 return;
3193 }
3194
3195 /*
3196 * Some controllers require BMDMA region to be initialized
3197 * even if DMA is not in use to clear IRQ status via
3198 * ->sff_irq_clear method. Try to initialize bmdma_addr
3199 * regardless of dma masks.
3200 */
3201 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
3202 if (rc)
3203 ata_bmdma_nodma(host, "failed to set dma mask");
3204 if (!rc) {
3205 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
3206 if (rc)
3207 ata_bmdma_nodma(host,
3208 "failed to set consistent dma mask");
3209 }
3210
3211 /* request and iomap DMA region */
3212 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
3213 if (rc) {
3214 ata_bmdma_nodma(host, "failed to request/iomap BAR4");
3215 return;
3216 }
3217 host->iomap = pcim_iomap_table(pdev);
3218
3219 for (i = 0; i < 2; i++) {
3220 struct ata_port *ap = host->ports[i];
3221 void __iomem *bmdma = host->iomap[4] + 8 * i;
3222
3223 if (ata_port_is_dummy(ap))
3224 continue;
3225
3226 ap->ioaddr.bmdma_addr = bmdma;
3227 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
3228 (ioread8(bmdma + 2) & 0x80))
3229 host->flags |= ATA_HOST_SIMPLEX;
3230
3231 ata_port_desc(ap, "bmdma 0x%llx",
3232 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
3233 }
3234}
3235EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
3236
3237/**
3238 * ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host
3239 * @pdev: target PCI device
3240 * @ppi: array of port_info, must be enough for two ports
3241 * @r_host: out argument for the initialized ATA host
3242 *
3243 * Helper to allocate BMDMA ATA host for @pdev, acquire all PCI
3244 * resources and initialize it accordingly in one go.
3245 *
3246 * LOCKING:
3247 * Inherited from calling layer (may sleep).
3248 *
3249 * RETURNS:
3250 * 0 on success, -errno otherwise.
3251 */
3252int ata_pci_bmdma_prepare_host(struct pci_dev *pdev,
3253 const struct ata_port_info * const * ppi,
3254 struct ata_host **r_host)
3255{
3256 int rc;
3257
3258 rc = ata_pci_sff_prepare_host(pdev, ppi, r_host);
3259 if (rc)
3260 return rc;
3261
3262 ata_pci_bmdma_init(*r_host);
3263 return 0;
3264}
3265EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host);
3266
3267/**
3268 * ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller
3269 * @pdev: Controller to be initialized
3270 * @ppi: array of port_info, must be enough for two ports
3271 * @sht: scsi_host_template to use when registering the host
3272 * @host_priv: host private_data
3273 * @hflags: host flags
3274 *
3275 * This function is similar to ata_pci_sff_init_one() but also
3276 * takes care of BMDMA initialization.
3277 *
3278 * LOCKING:
3279 * Inherited from PCI layer (may sleep).
3280 *
3281 * RETURNS:
3282 * Zero on success, negative on errno-based value on error.
3283 */
3284int ata_pci_bmdma_init_one(struct pci_dev *pdev,
3285 const struct ata_port_info * const * ppi,
3286 struct scsi_host_template *sht, void *host_priv,
3287 int hflags)
3288{
3289 struct device *dev = &pdev->dev;
3290 const struct ata_port_info *pi;
3291 struct ata_host *host = NULL;
3292 int rc;
3293
3294 DPRINTK("ENTER\n");
3295
3296 pi = ata_sff_find_valid_pi(ppi);
3297 if (!pi) {
3298 dev_err(&pdev->dev, "no valid port_info specified\n");
3299 return -EINVAL;
3300 }
3301
3302 if (!devres_open_group(dev, NULL, GFP_KERNEL))
3303 return -ENOMEM;
3304
3305 rc = pcim_enable_device(pdev);
3306 if (rc)
3307 goto out;
3308
3309 /* prepare and activate BMDMA host */
3310 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
3311 if (rc)
3312 goto out;
3313 host->private_data = host_priv;
3314 host->flags |= hflags;
3315
3316 pci_set_master(pdev);
3317 rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
3318 out:
3319 if (rc == 0)
3320 devres_remove_group(&pdev->dev, NULL);
3321 else
3322 devres_release_group(&pdev->dev, NULL);
3323
3324 return rc;
3325}
3326EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one);
3327
3328#endif /* CONFIG_PCI */
3329#endif /* CONFIG_ATA_BMDMA */
3330
3331/**
3332 * ata_sff_port_init - Initialize SFF/BMDMA ATA port
3333 * @ap: Port to initialize
3334 *
3335 * Called on port allocation to initialize SFF/BMDMA specific
3336 * fields.
3337 *
3338 * LOCKING:
3339 * None.
3340 */
3341void ata_sff_port_init(struct ata_port *ap)
3342{
3343 INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task);
3344 ap->ctl = ATA_DEVCTL_OBS;
3345 ap->last_ctl = 0xFF;
3346}
3347
3348int __init ata_sff_init(void)
3349{
3350 ata_sff_wq = alloc_workqueue("ata_sff", WQ_MEM_RECLAIM, WQ_MAX_ACTIVE);
3351 if (!ata_sff_wq)
3352 return -ENOMEM;
3353
3354 return 0;
3355}
3356
3357void ata_sff_exit(void)
3358{
3359 destroy_workqueue(ata_sff_wq);
3360}
1/*
2 * libata-sff.c - helper library for PCI IDE BMDMA
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2006 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/gfp.h>
37#include <linux/pci.h>
38#include <linux/module.h>
39#include <linux/libata.h>
40#include <linux/highmem.h>
41
42#include "libata.h"
43
44static struct workqueue_struct *ata_sff_wq;
45
46const struct ata_port_operations ata_sff_port_ops = {
47 .inherits = &ata_base_port_ops,
48
49 .qc_prep = ata_noop_qc_prep,
50 .qc_issue = ata_sff_qc_issue,
51 .qc_fill_rtf = ata_sff_qc_fill_rtf,
52
53 .freeze = ata_sff_freeze,
54 .thaw = ata_sff_thaw,
55 .prereset = ata_sff_prereset,
56 .softreset = ata_sff_softreset,
57 .hardreset = sata_sff_hardreset,
58 .postreset = ata_sff_postreset,
59 .error_handler = ata_sff_error_handler,
60
61 .sff_dev_select = ata_sff_dev_select,
62 .sff_check_status = ata_sff_check_status,
63 .sff_tf_load = ata_sff_tf_load,
64 .sff_tf_read = ata_sff_tf_read,
65 .sff_exec_command = ata_sff_exec_command,
66 .sff_data_xfer = ata_sff_data_xfer,
67 .sff_drain_fifo = ata_sff_drain_fifo,
68
69 .lost_interrupt = ata_sff_lost_interrupt,
70};
71EXPORT_SYMBOL_GPL(ata_sff_port_ops);
72
73/**
74 * ata_sff_check_status - Read device status reg & clear interrupt
75 * @ap: port where the device is
76 *
77 * Reads ATA taskfile status register for currently-selected device
78 * and return its value. This also clears pending interrupts
79 * from this device
80 *
81 * LOCKING:
82 * Inherited from caller.
83 */
84u8 ata_sff_check_status(struct ata_port *ap)
85{
86 return ioread8(ap->ioaddr.status_addr);
87}
88EXPORT_SYMBOL_GPL(ata_sff_check_status);
89
90/**
91 * ata_sff_altstatus - Read device alternate status reg
92 * @ap: port where the device is
93 *
94 * Reads ATA taskfile alternate status register for
95 * currently-selected device and return its value.
96 *
97 * Note: may NOT be used as the check_altstatus() entry in
98 * ata_port_operations.
99 *
100 * LOCKING:
101 * Inherited from caller.
102 */
103static u8 ata_sff_altstatus(struct ata_port *ap)
104{
105 if (ap->ops->sff_check_altstatus)
106 return ap->ops->sff_check_altstatus(ap);
107
108 return ioread8(ap->ioaddr.altstatus_addr);
109}
110
111/**
112 * ata_sff_irq_status - Check if the device is busy
113 * @ap: port where the device is
114 *
115 * Determine if the port is currently busy. Uses altstatus
116 * if available in order to avoid clearing shared IRQ status
117 * when finding an IRQ source. Non ctl capable devices don't
118 * share interrupt lines fortunately for us.
119 *
120 * LOCKING:
121 * Inherited from caller.
122 */
123static u8 ata_sff_irq_status(struct ata_port *ap)
124{
125 u8 status;
126
127 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
128 status = ata_sff_altstatus(ap);
129 /* Not us: We are busy */
130 if (status & ATA_BUSY)
131 return status;
132 }
133 /* Clear INTRQ latch */
134 status = ap->ops->sff_check_status(ap);
135 return status;
136}
137
138/**
139 * ata_sff_sync - Flush writes
140 * @ap: Port to wait for.
141 *
142 * CAUTION:
143 * If we have an mmio device with no ctl and no altstatus
144 * method this will fail. No such devices are known to exist.
145 *
146 * LOCKING:
147 * Inherited from caller.
148 */
149
150static void ata_sff_sync(struct ata_port *ap)
151{
152 if (ap->ops->sff_check_altstatus)
153 ap->ops->sff_check_altstatus(ap);
154 else if (ap->ioaddr.altstatus_addr)
155 ioread8(ap->ioaddr.altstatus_addr);
156}
157
158/**
159 * ata_sff_pause - Flush writes and wait 400nS
160 * @ap: Port to pause for.
161 *
162 * CAUTION:
163 * If we have an mmio device with no ctl and no altstatus
164 * method this will fail. No such devices are known to exist.
165 *
166 * LOCKING:
167 * Inherited from caller.
168 */
169
170void ata_sff_pause(struct ata_port *ap)
171{
172 ata_sff_sync(ap);
173 ndelay(400);
174}
175EXPORT_SYMBOL_GPL(ata_sff_pause);
176
177/**
178 * ata_sff_dma_pause - Pause before commencing DMA
179 * @ap: Port to pause for.
180 *
181 * Perform I/O fencing and ensure sufficient cycle delays occur
182 * for the HDMA1:0 transition
183 */
184
185void ata_sff_dma_pause(struct ata_port *ap)
186{
187 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
188 /* An altstatus read will cause the needed delay without
189 messing up the IRQ status */
190 ata_sff_altstatus(ap);
191 return;
192 }
193 /* There are no DMA controllers without ctl. BUG here to ensure
194 we never violate the HDMA1:0 transition timing and risk
195 corruption. */
196 BUG();
197}
198EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
199
200/**
201 * ata_sff_busy_sleep - sleep until BSY clears, or timeout
202 * @ap: port containing status register to be polled
203 * @tmout_pat: impatience timeout in msecs
204 * @tmout: overall timeout in msecs
205 *
206 * Sleep until ATA Status register bit BSY clears,
207 * or a timeout occurs.
208 *
209 * LOCKING:
210 * Kernel thread context (may sleep).
211 *
212 * RETURNS:
213 * 0 on success, -errno otherwise.
214 */
215int ata_sff_busy_sleep(struct ata_port *ap,
216 unsigned long tmout_pat, unsigned long tmout)
217{
218 unsigned long timer_start, timeout;
219 u8 status;
220
221 status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
222 timer_start = jiffies;
223 timeout = ata_deadline(timer_start, tmout_pat);
224 while (status != 0xff && (status & ATA_BUSY) &&
225 time_before(jiffies, timeout)) {
226 ata_msleep(ap, 50);
227 status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
228 }
229
230 if (status != 0xff && (status & ATA_BUSY))
231 ata_port_warn(ap,
232 "port is slow to respond, please be patient (Status 0x%x)\n",
233 status);
234
235 timeout = ata_deadline(timer_start, tmout);
236 while (status != 0xff && (status & ATA_BUSY) &&
237 time_before(jiffies, timeout)) {
238 ata_msleep(ap, 50);
239 status = ap->ops->sff_check_status(ap);
240 }
241
242 if (status == 0xff)
243 return -ENODEV;
244
245 if (status & ATA_BUSY) {
246 ata_port_err(ap,
247 "port failed to respond (%lu secs, Status 0x%x)\n",
248 DIV_ROUND_UP(tmout, 1000), status);
249 return -EBUSY;
250 }
251
252 return 0;
253}
254EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
255
256static int ata_sff_check_ready(struct ata_link *link)
257{
258 u8 status = link->ap->ops->sff_check_status(link->ap);
259
260 return ata_check_ready(status);
261}
262
263/**
264 * ata_sff_wait_ready - sleep until BSY clears, or timeout
265 * @link: SFF link to wait ready status for
266 * @deadline: deadline jiffies for the operation
267 *
268 * Sleep until ATA Status register bit BSY clears, or timeout
269 * occurs.
270 *
271 * LOCKING:
272 * Kernel thread context (may sleep).
273 *
274 * RETURNS:
275 * 0 on success, -errno otherwise.
276 */
277int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
278{
279 return ata_wait_ready(link, deadline, ata_sff_check_ready);
280}
281EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
282
283/**
284 * ata_sff_set_devctl - Write device control reg
285 * @ap: port where the device is
286 * @ctl: value to write
287 *
288 * Writes ATA taskfile device control register.
289 *
290 * Note: may NOT be used as the sff_set_devctl() entry in
291 * ata_port_operations.
292 *
293 * LOCKING:
294 * Inherited from caller.
295 */
296static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl)
297{
298 if (ap->ops->sff_set_devctl)
299 ap->ops->sff_set_devctl(ap, ctl);
300 else
301 iowrite8(ctl, ap->ioaddr.ctl_addr);
302}
303
304/**
305 * ata_sff_dev_select - Select device 0/1 on ATA bus
306 * @ap: ATA channel to manipulate
307 * @device: ATA device (numbered from zero) to select
308 *
309 * Use the method defined in the ATA specification to
310 * make either device 0, or device 1, active on the
311 * ATA channel. Works with both PIO and MMIO.
312 *
313 * May be used as the dev_select() entry in ata_port_operations.
314 *
315 * LOCKING:
316 * caller.
317 */
318void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
319{
320 u8 tmp;
321
322 if (device == 0)
323 tmp = ATA_DEVICE_OBS;
324 else
325 tmp = ATA_DEVICE_OBS | ATA_DEV1;
326
327 iowrite8(tmp, ap->ioaddr.device_addr);
328 ata_sff_pause(ap); /* needed; also flushes, for mmio */
329}
330EXPORT_SYMBOL_GPL(ata_sff_dev_select);
331
332/**
333 * ata_dev_select - Select device 0/1 on ATA bus
334 * @ap: ATA channel to manipulate
335 * @device: ATA device (numbered from zero) to select
336 * @wait: non-zero to wait for Status register BSY bit to clear
337 * @can_sleep: non-zero if context allows sleeping
338 *
339 * Use the method defined in the ATA specification to
340 * make either device 0, or device 1, active on the
341 * ATA channel.
342 *
343 * This is a high-level version of ata_sff_dev_select(), which
344 * additionally provides the services of inserting the proper
345 * pauses and status polling, where needed.
346 *
347 * LOCKING:
348 * caller.
349 */
350static void ata_dev_select(struct ata_port *ap, unsigned int device,
351 unsigned int wait, unsigned int can_sleep)
352{
353 if (ata_msg_probe(ap))
354 ata_port_info(ap, "ata_dev_select: ENTER, device %u, wait %u\n",
355 device, wait);
356
357 if (wait)
358 ata_wait_idle(ap);
359
360 ap->ops->sff_dev_select(ap, device);
361
362 if (wait) {
363 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
364 ata_msleep(ap, 150);
365 ata_wait_idle(ap);
366 }
367}
368
369/**
370 * ata_sff_irq_on - Enable interrupts on a port.
371 * @ap: Port on which interrupts are enabled.
372 *
373 * Enable interrupts on a legacy IDE device using MMIO or PIO,
374 * wait for idle, clear any pending interrupts.
375 *
376 * Note: may NOT be used as the sff_irq_on() entry in
377 * ata_port_operations.
378 *
379 * LOCKING:
380 * Inherited from caller.
381 */
382void ata_sff_irq_on(struct ata_port *ap)
383{
384 struct ata_ioports *ioaddr = &ap->ioaddr;
385
386 if (ap->ops->sff_irq_on) {
387 ap->ops->sff_irq_on(ap);
388 return;
389 }
390
391 ap->ctl &= ~ATA_NIEN;
392 ap->last_ctl = ap->ctl;
393
394 if (ap->ops->sff_set_devctl || ioaddr->ctl_addr)
395 ata_sff_set_devctl(ap, ap->ctl);
396 ata_wait_idle(ap);
397
398 if (ap->ops->sff_irq_clear)
399 ap->ops->sff_irq_clear(ap);
400}
401EXPORT_SYMBOL_GPL(ata_sff_irq_on);
402
403/**
404 * ata_sff_tf_load - send taskfile registers to host controller
405 * @ap: Port to which output is sent
406 * @tf: ATA taskfile register set
407 *
408 * Outputs ATA taskfile to standard ATA host controller.
409 *
410 * LOCKING:
411 * Inherited from caller.
412 */
413void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
414{
415 struct ata_ioports *ioaddr = &ap->ioaddr;
416 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
417
418 if (tf->ctl != ap->last_ctl) {
419 if (ioaddr->ctl_addr)
420 iowrite8(tf->ctl, ioaddr->ctl_addr);
421 ap->last_ctl = tf->ctl;
422 ata_wait_idle(ap);
423 }
424
425 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
426 WARN_ON_ONCE(!ioaddr->ctl_addr);
427 iowrite8(tf->hob_feature, ioaddr->feature_addr);
428 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
429 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
430 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
431 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
432 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
433 tf->hob_feature,
434 tf->hob_nsect,
435 tf->hob_lbal,
436 tf->hob_lbam,
437 tf->hob_lbah);
438 }
439
440 if (is_addr) {
441 iowrite8(tf->feature, ioaddr->feature_addr);
442 iowrite8(tf->nsect, ioaddr->nsect_addr);
443 iowrite8(tf->lbal, ioaddr->lbal_addr);
444 iowrite8(tf->lbam, ioaddr->lbam_addr);
445 iowrite8(tf->lbah, ioaddr->lbah_addr);
446 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
447 tf->feature,
448 tf->nsect,
449 tf->lbal,
450 tf->lbam,
451 tf->lbah);
452 }
453
454 if (tf->flags & ATA_TFLAG_DEVICE) {
455 iowrite8(tf->device, ioaddr->device_addr);
456 VPRINTK("device 0x%X\n", tf->device);
457 }
458
459 ata_wait_idle(ap);
460}
461EXPORT_SYMBOL_GPL(ata_sff_tf_load);
462
463/**
464 * ata_sff_tf_read - input device's ATA taskfile shadow registers
465 * @ap: Port from which input is read
466 * @tf: ATA taskfile register set for storing input
467 *
468 * Reads ATA taskfile registers for currently-selected device
469 * into @tf. Assumes the device has a fully SFF compliant task file
470 * layout and behaviour. If you device does not (eg has a different
471 * status method) then you will need to provide a replacement tf_read
472 *
473 * LOCKING:
474 * Inherited from caller.
475 */
476void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
477{
478 struct ata_ioports *ioaddr = &ap->ioaddr;
479
480 tf->command = ata_sff_check_status(ap);
481 tf->feature = ioread8(ioaddr->error_addr);
482 tf->nsect = ioread8(ioaddr->nsect_addr);
483 tf->lbal = ioread8(ioaddr->lbal_addr);
484 tf->lbam = ioread8(ioaddr->lbam_addr);
485 tf->lbah = ioread8(ioaddr->lbah_addr);
486 tf->device = ioread8(ioaddr->device_addr);
487
488 if (tf->flags & ATA_TFLAG_LBA48) {
489 if (likely(ioaddr->ctl_addr)) {
490 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
491 tf->hob_feature = ioread8(ioaddr->error_addr);
492 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
493 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
494 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
495 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
496 iowrite8(tf->ctl, ioaddr->ctl_addr);
497 ap->last_ctl = tf->ctl;
498 } else
499 WARN_ON_ONCE(1);
500 }
501}
502EXPORT_SYMBOL_GPL(ata_sff_tf_read);
503
504/**
505 * ata_sff_exec_command - issue ATA command to host controller
506 * @ap: port to which command is being issued
507 * @tf: ATA taskfile register set
508 *
509 * Issues ATA command, with proper synchronization with interrupt
510 * handler / other threads.
511 *
512 * LOCKING:
513 * spin_lock_irqsave(host lock)
514 */
515void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
516{
517 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
518
519 iowrite8(tf->command, ap->ioaddr.command_addr);
520 ata_sff_pause(ap);
521}
522EXPORT_SYMBOL_GPL(ata_sff_exec_command);
523
524/**
525 * ata_tf_to_host - issue ATA taskfile to host controller
526 * @ap: port to which command is being issued
527 * @tf: ATA taskfile register set
528 *
529 * Issues ATA taskfile register set to ATA host controller,
530 * with proper synchronization with interrupt handler and
531 * other threads.
532 *
533 * LOCKING:
534 * spin_lock_irqsave(host lock)
535 */
536static inline void ata_tf_to_host(struct ata_port *ap,
537 const struct ata_taskfile *tf)
538{
539 ap->ops->sff_tf_load(ap, tf);
540 ap->ops->sff_exec_command(ap, tf);
541}
542
543/**
544 * ata_sff_data_xfer - Transfer data by PIO
545 * @dev: device to target
546 * @buf: data buffer
547 * @buflen: buffer length
548 * @rw: read/write
549 *
550 * Transfer data from/to the device data register by PIO.
551 *
552 * LOCKING:
553 * Inherited from caller.
554 *
555 * RETURNS:
556 * Bytes consumed.
557 */
558unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf,
559 unsigned int buflen, int rw)
560{
561 struct ata_port *ap = dev->link->ap;
562 void __iomem *data_addr = ap->ioaddr.data_addr;
563 unsigned int words = buflen >> 1;
564
565 /* Transfer multiple of 2 bytes */
566 if (rw == READ)
567 ioread16_rep(data_addr, buf, words);
568 else
569 iowrite16_rep(data_addr, buf, words);
570
571 /* Transfer trailing byte, if any. */
572 if (unlikely(buflen & 0x01)) {
573 unsigned char pad[2] = { };
574
575 /* Point buf to the tail of buffer */
576 buf += buflen - 1;
577
578 /*
579 * Use io*16_rep() accessors here as well to avoid pointlessly
580 * swapping bytes to and from on the big endian machines...
581 */
582 if (rw == READ) {
583 ioread16_rep(data_addr, pad, 1);
584 *buf = pad[0];
585 } else {
586 pad[0] = *buf;
587 iowrite16_rep(data_addr, pad, 1);
588 }
589 words++;
590 }
591
592 return words << 1;
593}
594EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
595
596/**
597 * ata_sff_data_xfer32 - Transfer data by PIO
598 * @dev: device to target
599 * @buf: data buffer
600 * @buflen: buffer length
601 * @rw: read/write
602 *
603 * Transfer data from/to the device data register by PIO using 32bit
604 * I/O operations.
605 *
606 * LOCKING:
607 * Inherited from caller.
608 *
609 * RETURNS:
610 * Bytes consumed.
611 */
612
613unsigned int ata_sff_data_xfer32(struct ata_device *dev, unsigned char *buf,
614 unsigned int buflen, int rw)
615{
616 struct ata_port *ap = dev->link->ap;
617 void __iomem *data_addr = ap->ioaddr.data_addr;
618 unsigned int words = buflen >> 2;
619 int slop = buflen & 3;
620
621 if (!(ap->pflags & ATA_PFLAG_PIO32))
622 return ata_sff_data_xfer(dev, buf, buflen, rw);
623
624 /* Transfer multiple of 4 bytes */
625 if (rw == READ)
626 ioread32_rep(data_addr, buf, words);
627 else
628 iowrite32_rep(data_addr, buf, words);
629
630 /* Transfer trailing bytes, if any */
631 if (unlikely(slop)) {
632 unsigned char pad[4] = { };
633
634 /* Point buf to the tail of buffer */
635 buf += buflen - slop;
636
637 /*
638 * Use io*_rep() accessors here as well to avoid pointlessly
639 * swapping bytes to and from on the big endian machines...
640 */
641 if (rw == READ) {
642 if (slop < 3)
643 ioread16_rep(data_addr, pad, 1);
644 else
645 ioread32_rep(data_addr, pad, 1);
646 memcpy(buf, pad, slop);
647 } else {
648 memcpy(pad, buf, slop);
649 if (slop < 3)
650 iowrite16_rep(data_addr, pad, 1);
651 else
652 iowrite32_rep(data_addr, pad, 1);
653 }
654 }
655 return (buflen + 1) & ~1;
656}
657EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
658
659/**
660 * ata_sff_data_xfer_noirq - Transfer data by PIO
661 * @dev: device to target
662 * @buf: data buffer
663 * @buflen: buffer length
664 * @rw: read/write
665 *
666 * Transfer data from/to the device data register by PIO. Do the
667 * transfer with interrupts disabled.
668 *
669 * LOCKING:
670 * Inherited from caller.
671 *
672 * RETURNS:
673 * Bytes consumed.
674 */
675unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
676 unsigned int buflen, int rw)
677{
678 unsigned long flags;
679 unsigned int consumed;
680
681 local_irq_save(flags);
682 consumed = ata_sff_data_xfer32(dev, buf, buflen, rw);
683 local_irq_restore(flags);
684
685 return consumed;
686}
687EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq);
688
689/**
690 * ata_pio_sector - Transfer a sector of data.
691 * @qc: Command on going
692 *
693 * Transfer qc->sect_size bytes of data from/to the ATA device.
694 *
695 * LOCKING:
696 * Inherited from caller.
697 */
698static void ata_pio_sector(struct ata_queued_cmd *qc)
699{
700 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
701 struct ata_port *ap = qc->ap;
702 struct page *page;
703 unsigned int offset;
704 unsigned char *buf;
705
706 if (qc->curbytes == qc->nbytes - qc->sect_size)
707 ap->hsm_task_state = HSM_ST_LAST;
708
709 page = sg_page(qc->cursg);
710 offset = qc->cursg->offset + qc->cursg_ofs;
711
712 /* get the current page and offset */
713 page = nth_page(page, (offset >> PAGE_SHIFT));
714 offset %= PAGE_SIZE;
715
716 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
717
718 if (PageHighMem(page)) {
719 unsigned long flags;
720
721 /* FIXME: use a bounce buffer */
722 local_irq_save(flags);
723 buf = kmap_atomic(page);
724
725 /* do the actual data transfer */
726 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
727 do_write);
728
729 kunmap_atomic(buf);
730 local_irq_restore(flags);
731 } else {
732 buf = page_address(page);
733 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
734 do_write);
735 }
736
737 if (!do_write && !PageSlab(page))
738 flush_dcache_page(page);
739
740 qc->curbytes += qc->sect_size;
741 qc->cursg_ofs += qc->sect_size;
742
743 if (qc->cursg_ofs == qc->cursg->length) {
744 qc->cursg = sg_next(qc->cursg);
745 qc->cursg_ofs = 0;
746 }
747}
748
749/**
750 * ata_pio_sectors - Transfer one or many sectors.
751 * @qc: Command on going
752 *
753 * Transfer one or many sectors of data from/to the
754 * ATA device for the DRQ request.
755 *
756 * LOCKING:
757 * Inherited from caller.
758 */
759static void ata_pio_sectors(struct ata_queued_cmd *qc)
760{
761 if (is_multi_taskfile(&qc->tf)) {
762 /* READ/WRITE MULTIPLE */
763 unsigned int nsect;
764
765 WARN_ON_ONCE(qc->dev->multi_count == 0);
766
767 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
768 qc->dev->multi_count);
769 while (nsect--)
770 ata_pio_sector(qc);
771 } else
772 ata_pio_sector(qc);
773
774 ata_sff_sync(qc->ap); /* flush */
775}
776
777/**
778 * atapi_send_cdb - Write CDB bytes to hardware
779 * @ap: Port to which ATAPI device is attached.
780 * @qc: Taskfile currently active
781 *
782 * When device has indicated its readiness to accept
783 * a CDB, this function is called. Send the CDB.
784 *
785 * LOCKING:
786 * caller.
787 */
788static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
789{
790 /* send SCSI cdb */
791 DPRINTK("send cdb\n");
792 WARN_ON_ONCE(qc->dev->cdb_len < 12);
793
794 ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
795 ata_sff_sync(ap);
796 /* FIXME: If the CDB is for DMA do we need to do the transition delay
797 or is bmdma_start guaranteed to do it ? */
798 switch (qc->tf.protocol) {
799 case ATAPI_PROT_PIO:
800 ap->hsm_task_state = HSM_ST;
801 break;
802 case ATAPI_PROT_NODATA:
803 ap->hsm_task_state = HSM_ST_LAST;
804 break;
805#ifdef CONFIG_ATA_BMDMA
806 case ATAPI_PROT_DMA:
807 ap->hsm_task_state = HSM_ST_LAST;
808 /* initiate bmdma */
809 ap->ops->bmdma_start(qc);
810 break;
811#endif /* CONFIG_ATA_BMDMA */
812 default:
813 BUG();
814 }
815}
816
817/**
818 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
819 * @qc: Command on going
820 * @bytes: number of bytes
821 *
822 * Transfer Transfer data from/to the ATAPI device.
823 *
824 * LOCKING:
825 * Inherited from caller.
826 *
827 */
828static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
829{
830 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
831 struct ata_port *ap = qc->ap;
832 struct ata_device *dev = qc->dev;
833 struct ata_eh_info *ehi = &dev->link->eh_info;
834 struct scatterlist *sg;
835 struct page *page;
836 unsigned char *buf;
837 unsigned int offset, count, consumed;
838
839next_sg:
840 sg = qc->cursg;
841 if (unlikely(!sg)) {
842 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
843 "buf=%u cur=%u bytes=%u",
844 qc->nbytes, qc->curbytes, bytes);
845 return -1;
846 }
847
848 page = sg_page(sg);
849 offset = sg->offset + qc->cursg_ofs;
850
851 /* get the current page and offset */
852 page = nth_page(page, (offset >> PAGE_SHIFT));
853 offset %= PAGE_SIZE;
854
855 /* don't overrun current sg */
856 count = min(sg->length - qc->cursg_ofs, bytes);
857
858 /* don't cross page boundaries */
859 count = min(count, (unsigned int)PAGE_SIZE - offset);
860
861 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
862
863 if (PageHighMem(page)) {
864 unsigned long flags;
865
866 /* FIXME: use bounce buffer */
867 local_irq_save(flags);
868 buf = kmap_atomic(page);
869
870 /* do the actual data transfer */
871 consumed = ap->ops->sff_data_xfer(dev, buf + offset,
872 count, rw);
873
874 kunmap_atomic(buf);
875 local_irq_restore(flags);
876 } else {
877 buf = page_address(page);
878 consumed = ap->ops->sff_data_xfer(dev, buf + offset,
879 count, rw);
880 }
881
882 bytes -= min(bytes, consumed);
883 qc->curbytes += count;
884 qc->cursg_ofs += count;
885
886 if (qc->cursg_ofs == sg->length) {
887 qc->cursg = sg_next(qc->cursg);
888 qc->cursg_ofs = 0;
889 }
890
891 /*
892 * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed);
893 * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
894 * check correctly as it doesn't know if it is the last request being
895 * made. Somebody should implement a proper sanity check.
896 */
897 if (bytes)
898 goto next_sg;
899 return 0;
900}
901
902/**
903 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
904 * @qc: Command on going
905 *
906 * Transfer Transfer data from/to the ATAPI device.
907 *
908 * LOCKING:
909 * Inherited from caller.
910 */
911static void atapi_pio_bytes(struct ata_queued_cmd *qc)
912{
913 struct ata_port *ap = qc->ap;
914 struct ata_device *dev = qc->dev;
915 struct ata_eh_info *ehi = &dev->link->eh_info;
916 unsigned int ireason, bc_lo, bc_hi, bytes;
917 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
918
919 /* Abuse qc->result_tf for temp storage of intermediate TF
920 * here to save some kernel stack usage.
921 * For normal completion, qc->result_tf is not relevant. For
922 * error, qc->result_tf is later overwritten by ata_qc_complete().
923 * So, the correctness of qc->result_tf is not affected.
924 */
925 ap->ops->sff_tf_read(ap, &qc->result_tf);
926 ireason = qc->result_tf.nsect;
927 bc_lo = qc->result_tf.lbam;
928 bc_hi = qc->result_tf.lbah;
929 bytes = (bc_hi << 8) | bc_lo;
930
931 /* shall be cleared to zero, indicating xfer of data */
932 if (unlikely(ireason & ATAPI_COD))
933 goto atapi_check;
934
935 /* make sure transfer direction matches expected */
936 i_write = ((ireason & ATAPI_IO) == 0) ? 1 : 0;
937 if (unlikely(do_write != i_write))
938 goto atapi_check;
939
940 if (unlikely(!bytes))
941 goto atapi_check;
942
943 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
944
945 if (unlikely(__atapi_pio_bytes(qc, bytes)))
946 goto err_out;
947 ata_sff_sync(ap); /* flush */
948
949 return;
950
951 atapi_check:
952 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
953 ireason, bytes);
954 err_out:
955 qc->err_mask |= AC_ERR_HSM;
956 ap->hsm_task_state = HSM_ST_ERR;
957}
958
959/**
960 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
961 * @ap: the target ata_port
962 * @qc: qc on going
963 *
964 * RETURNS:
965 * 1 if ok in workqueue, 0 otherwise.
966 */
967static inline int ata_hsm_ok_in_wq(struct ata_port *ap,
968 struct ata_queued_cmd *qc)
969{
970 if (qc->tf.flags & ATA_TFLAG_POLLING)
971 return 1;
972
973 if (ap->hsm_task_state == HSM_ST_FIRST) {
974 if (qc->tf.protocol == ATA_PROT_PIO &&
975 (qc->tf.flags & ATA_TFLAG_WRITE))
976 return 1;
977
978 if (ata_is_atapi(qc->tf.protocol) &&
979 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
980 return 1;
981 }
982
983 return 0;
984}
985
986/**
987 * ata_hsm_qc_complete - finish a qc running on standard HSM
988 * @qc: Command to complete
989 * @in_wq: 1 if called from workqueue, 0 otherwise
990 *
991 * Finish @qc which is running on standard HSM.
992 *
993 * LOCKING:
994 * If @in_wq is zero, spin_lock_irqsave(host lock).
995 * Otherwise, none on entry and grabs host lock.
996 */
997static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
998{
999 struct ata_port *ap = qc->ap;
1000
1001 if (ap->ops->error_handler) {
1002 if (in_wq) {
1003 /* EH might have kicked in while host lock is
1004 * released.
1005 */
1006 qc = ata_qc_from_tag(ap, qc->tag);
1007 if (qc) {
1008 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
1009 ata_sff_irq_on(ap);
1010 ata_qc_complete(qc);
1011 } else
1012 ata_port_freeze(ap);
1013 }
1014 } else {
1015 if (likely(!(qc->err_mask & AC_ERR_HSM)))
1016 ata_qc_complete(qc);
1017 else
1018 ata_port_freeze(ap);
1019 }
1020 } else {
1021 if (in_wq) {
1022 ata_sff_irq_on(ap);
1023 ata_qc_complete(qc);
1024 } else
1025 ata_qc_complete(qc);
1026 }
1027}
1028
1029/**
1030 * ata_sff_hsm_move - move the HSM to the next state.
1031 * @ap: the target ata_port
1032 * @qc: qc on going
1033 * @status: current device status
1034 * @in_wq: 1 if called from workqueue, 0 otherwise
1035 *
1036 * RETURNS:
1037 * 1 when poll next status needed, 0 otherwise.
1038 */
1039int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1040 u8 status, int in_wq)
1041{
1042 struct ata_link *link = qc->dev->link;
1043 struct ata_eh_info *ehi = &link->eh_info;
1044 int poll_next;
1045
1046 lockdep_assert_held(ap->lock);
1047
1048 WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
1049
1050 /* Make sure ata_sff_qc_issue() does not throw things
1051 * like DMA polling into the workqueue. Notice that
1052 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1053 */
1054 WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc));
1055
1056fsm_start:
1057 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1058 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1059
1060 switch (ap->hsm_task_state) {
1061 case HSM_ST_FIRST:
1062 /* Send first data block or PACKET CDB */
1063
1064 /* If polling, we will stay in the work queue after
1065 * sending the data. Otherwise, interrupt handler
1066 * takes over after sending the data.
1067 */
1068 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1069
1070 /* check device status */
1071 if (unlikely((status & ATA_DRQ) == 0)) {
1072 /* handle BSY=0, DRQ=0 as error */
1073 if (likely(status & (ATA_ERR | ATA_DF)))
1074 /* device stops HSM for abort/error */
1075 qc->err_mask |= AC_ERR_DEV;
1076 else {
1077 /* HSM violation. Let EH handle this */
1078 ata_ehi_push_desc(ehi,
1079 "ST_FIRST: !(DRQ|ERR|DF)");
1080 qc->err_mask |= AC_ERR_HSM;
1081 }
1082
1083 ap->hsm_task_state = HSM_ST_ERR;
1084 goto fsm_start;
1085 }
1086
1087 /* Device should not ask for data transfer (DRQ=1)
1088 * when it finds something wrong.
1089 * We ignore DRQ here and stop the HSM by
1090 * changing hsm_task_state to HSM_ST_ERR and
1091 * let the EH abort the command or reset the device.
1092 */
1093 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1094 /* Some ATAPI tape drives forget to clear the ERR bit
1095 * when doing the next command (mostly request sense).
1096 * We ignore ERR here to workaround and proceed sending
1097 * the CDB.
1098 */
1099 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1100 ata_ehi_push_desc(ehi, "ST_FIRST: "
1101 "DRQ=1 with device error, "
1102 "dev_stat 0x%X", status);
1103 qc->err_mask |= AC_ERR_HSM;
1104 ap->hsm_task_state = HSM_ST_ERR;
1105 goto fsm_start;
1106 }
1107 }
1108
1109 if (qc->tf.protocol == ATA_PROT_PIO) {
1110 /* PIO data out protocol.
1111 * send first data block.
1112 */
1113
1114 /* ata_pio_sectors() might change the state
1115 * to HSM_ST_LAST. so, the state is changed here
1116 * before ata_pio_sectors().
1117 */
1118 ap->hsm_task_state = HSM_ST;
1119 ata_pio_sectors(qc);
1120 } else
1121 /* send CDB */
1122 atapi_send_cdb(ap, qc);
1123
1124 /* if polling, ata_sff_pio_task() handles the rest.
1125 * otherwise, interrupt handler takes over from here.
1126 */
1127 break;
1128
1129 case HSM_ST:
1130 /* complete command or read/write the data register */
1131 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1132 /* ATAPI PIO protocol */
1133 if ((status & ATA_DRQ) == 0) {
1134 /* No more data to transfer or device error.
1135 * Device error will be tagged in HSM_ST_LAST.
1136 */
1137 ap->hsm_task_state = HSM_ST_LAST;
1138 goto fsm_start;
1139 }
1140
1141 /* Device should not ask for data transfer (DRQ=1)
1142 * when it finds something wrong.
1143 * We ignore DRQ here and stop the HSM by
1144 * changing hsm_task_state to HSM_ST_ERR and
1145 * let the EH abort the command or reset the device.
1146 */
1147 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1148 ata_ehi_push_desc(ehi, "ST-ATAPI: "
1149 "DRQ=1 with device error, "
1150 "dev_stat 0x%X", status);
1151 qc->err_mask |= AC_ERR_HSM;
1152 ap->hsm_task_state = HSM_ST_ERR;
1153 goto fsm_start;
1154 }
1155
1156 atapi_pio_bytes(qc);
1157
1158 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1159 /* bad ireason reported by device */
1160 goto fsm_start;
1161
1162 } else {
1163 /* ATA PIO protocol */
1164 if (unlikely((status & ATA_DRQ) == 0)) {
1165 /* handle BSY=0, DRQ=0 as error */
1166 if (likely(status & (ATA_ERR | ATA_DF))) {
1167 /* device stops HSM for abort/error */
1168 qc->err_mask |= AC_ERR_DEV;
1169
1170 /* If diagnostic failed and this is
1171 * IDENTIFY, it's likely a phantom
1172 * device. Mark hint.
1173 */
1174 if (qc->dev->horkage &
1175 ATA_HORKAGE_DIAGNOSTIC)
1176 qc->err_mask |=
1177 AC_ERR_NODEV_HINT;
1178 } else {
1179 /* HSM violation. Let EH handle this.
1180 * Phantom devices also trigger this
1181 * condition. Mark hint.
1182 */
1183 ata_ehi_push_desc(ehi, "ST-ATA: "
1184 "DRQ=0 without device error, "
1185 "dev_stat 0x%X", status);
1186 qc->err_mask |= AC_ERR_HSM |
1187 AC_ERR_NODEV_HINT;
1188 }
1189
1190 ap->hsm_task_state = HSM_ST_ERR;
1191 goto fsm_start;
1192 }
1193
1194 /* For PIO reads, some devices may ask for
1195 * data transfer (DRQ=1) alone with ERR=1.
1196 * We respect DRQ here and transfer one
1197 * block of junk data before changing the
1198 * hsm_task_state to HSM_ST_ERR.
1199 *
1200 * For PIO writes, ERR=1 DRQ=1 doesn't make
1201 * sense since the data block has been
1202 * transferred to the device.
1203 */
1204 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1205 /* data might be corrputed */
1206 qc->err_mask |= AC_ERR_DEV;
1207
1208 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1209 ata_pio_sectors(qc);
1210 status = ata_wait_idle(ap);
1211 }
1212
1213 if (status & (ATA_BUSY | ATA_DRQ)) {
1214 ata_ehi_push_desc(ehi, "ST-ATA: "
1215 "BUSY|DRQ persists on ERR|DF, "
1216 "dev_stat 0x%X", status);
1217 qc->err_mask |= AC_ERR_HSM;
1218 }
1219
1220 /* There are oddball controllers with
1221 * status register stuck at 0x7f and
1222 * lbal/m/h at zero which makes it
1223 * pass all other presence detection
1224 * mechanisms we have. Set NODEV_HINT
1225 * for it. Kernel bz#7241.
1226 */
1227 if (status == 0x7f)
1228 qc->err_mask |= AC_ERR_NODEV_HINT;
1229
1230 /* ata_pio_sectors() might change the
1231 * state to HSM_ST_LAST. so, the state
1232 * is changed after ata_pio_sectors().
1233 */
1234 ap->hsm_task_state = HSM_ST_ERR;
1235 goto fsm_start;
1236 }
1237
1238 ata_pio_sectors(qc);
1239
1240 if (ap->hsm_task_state == HSM_ST_LAST &&
1241 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1242 /* all data read */
1243 status = ata_wait_idle(ap);
1244 goto fsm_start;
1245 }
1246 }
1247
1248 poll_next = 1;
1249 break;
1250
1251 case HSM_ST_LAST:
1252 if (unlikely(!ata_ok(status))) {
1253 qc->err_mask |= __ac_err_mask(status);
1254 ap->hsm_task_state = HSM_ST_ERR;
1255 goto fsm_start;
1256 }
1257
1258 /* no more data to transfer */
1259 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1260 ap->print_id, qc->dev->devno, status);
1261
1262 WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
1263
1264 ap->hsm_task_state = HSM_ST_IDLE;
1265
1266 /* complete taskfile transaction */
1267 ata_hsm_qc_complete(qc, in_wq);
1268
1269 poll_next = 0;
1270 break;
1271
1272 case HSM_ST_ERR:
1273 ap->hsm_task_state = HSM_ST_IDLE;
1274
1275 /* complete taskfile transaction */
1276 ata_hsm_qc_complete(qc, in_wq);
1277
1278 poll_next = 0;
1279 break;
1280 default:
1281 poll_next = 0;
1282 WARN(true, "ata%d: SFF host state machine in invalid state %d",
1283 ap->print_id, ap->hsm_task_state);
1284 }
1285
1286 return poll_next;
1287}
1288EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
1289
1290void ata_sff_queue_work(struct work_struct *work)
1291{
1292 queue_work(ata_sff_wq, work);
1293}
1294EXPORT_SYMBOL_GPL(ata_sff_queue_work);
1295
1296void ata_sff_queue_delayed_work(struct delayed_work *dwork, unsigned long delay)
1297{
1298 queue_delayed_work(ata_sff_wq, dwork, delay);
1299}
1300EXPORT_SYMBOL_GPL(ata_sff_queue_delayed_work);
1301
1302void ata_sff_queue_pio_task(struct ata_link *link, unsigned long delay)
1303{
1304 struct ata_port *ap = link->ap;
1305
1306 WARN_ON((ap->sff_pio_task_link != NULL) &&
1307 (ap->sff_pio_task_link != link));
1308 ap->sff_pio_task_link = link;
1309
1310 /* may fail if ata_sff_flush_pio_task() in progress */
1311 ata_sff_queue_delayed_work(&ap->sff_pio_task, msecs_to_jiffies(delay));
1312}
1313EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task);
1314
1315void ata_sff_flush_pio_task(struct ata_port *ap)
1316{
1317 DPRINTK("ENTER\n");
1318
1319 cancel_delayed_work_sync(&ap->sff_pio_task);
1320
1321 /*
1322 * We wanna reset the HSM state to IDLE. If we do so without
1323 * grabbing the port lock, critical sections protected by it which
1324 * expect the HSM state to stay stable may get surprised. For
1325 * example, we may set IDLE in between the time
1326 * __ata_sff_port_intr() checks for HSM_ST_IDLE and before it calls
1327 * ata_sff_hsm_move() causing ata_sff_hsm_move() to BUG().
1328 */
1329 spin_lock_irq(ap->lock);
1330 ap->hsm_task_state = HSM_ST_IDLE;
1331 spin_unlock_irq(ap->lock);
1332
1333 ap->sff_pio_task_link = NULL;
1334
1335 if (ata_msg_ctl(ap))
1336 ata_port_dbg(ap, "%s: EXIT\n", __func__);
1337}
1338
1339static void ata_sff_pio_task(struct work_struct *work)
1340{
1341 struct ata_port *ap =
1342 container_of(work, struct ata_port, sff_pio_task.work);
1343 struct ata_link *link = ap->sff_pio_task_link;
1344 struct ata_queued_cmd *qc;
1345 u8 status;
1346 int poll_next;
1347
1348 spin_lock_irq(ap->lock);
1349
1350 BUG_ON(ap->sff_pio_task_link == NULL);
1351 /* qc can be NULL if timeout occurred */
1352 qc = ata_qc_from_tag(ap, link->active_tag);
1353 if (!qc) {
1354 ap->sff_pio_task_link = NULL;
1355 goto out_unlock;
1356 }
1357
1358fsm_start:
1359 WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE);
1360
1361 /*
1362 * This is purely heuristic. This is a fast path.
1363 * Sometimes when we enter, BSY will be cleared in
1364 * a chk-status or two. If not, the drive is probably seeking
1365 * or something. Snooze for a couple msecs, then
1366 * chk-status again. If still busy, queue delayed work.
1367 */
1368 status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
1369 if (status & ATA_BUSY) {
1370 spin_unlock_irq(ap->lock);
1371 ata_msleep(ap, 2);
1372 spin_lock_irq(ap->lock);
1373
1374 status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
1375 if (status & ATA_BUSY) {
1376 ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE);
1377 goto out_unlock;
1378 }
1379 }
1380
1381 /*
1382 * hsm_move() may trigger another command to be processed.
1383 * clean the link beforehand.
1384 */
1385 ap->sff_pio_task_link = NULL;
1386 /* move the HSM */
1387 poll_next = ata_sff_hsm_move(ap, qc, status, 1);
1388
1389 /* another command or interrupt handler
1390 * may be running at this point.
1391 */
1392 if (poll_next)
1393 goto fsm_start;
1394out_unlock:
1395 spin_unlock_irq(ap->lock);
1396}
1397
1398/**
1399 * ata_sff_qc_issue - issue taskfile to a SFF controller
1400 * @qc: command to issue to device
1401 *
1402 * This function issues a PIO or NODATA command to a SFF
1403 * controller.
1404 *
1405 * LOCKING:
1406 * spin_lock_irqsave(host lock)
1407 *
1408 * RETURNS:
1409 * Zero on success, AC_ERR_* mask on failure
1410 */
1411unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
1412{
1413 struct ata_port *ap = qc->ap;
1414 struct ata_link *link = qc->dev->link;
1415
1416 /* Use polling pio if the LLD doesn't handle
1417 * interrupt driven pio and atapi CDB interrupt.
1418 */
1419 if (ap->flags & ATA_FLAG_PIO_POLLING)
1420 qc->tf.flags |= ATA_TFLAG_POLLING;
1421
1422 /* select the device */
1423 ata_dev_select(ap, qc->dev->devno, 1, 0);
1424
1425 /* start the command */
1426 switch (qc->tf.protocol) {
1427 case ATA_PROT_NODATA:
1428 if (qc->tf.flags & ATA_TFLAG_POLLING)
1429 ata_qc_set_polling(qc);
1430
1431 ata_tf_to_host(ap, &qc->tf);
1432 ap->hsm_task_state = HSM_ST_LAST;
1433
1434 if (qc->tf.flags & ATA_TFLAG_POLLING)
1435 ata_sff_queue_pio_task(link, 0);
1436
1437 break;
1438
1439 case ATA_PROT_PIO:
1440 if (qc->tf.flags & ATA_TFLAG_POLLING)
1441 ata_qc_set_polling(qc);
1442
1443 ata_tf_to_host(ap, &qc->tf);
1444
1445 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1446 /* PIO data out protocol */
1447 ap->hsm_task_state = HSM_ST_FIRST;
1448 ata_sff_queue_pio_task(link, 0);
1449
1450 /* always send first data block using the
1451 * ata_sff_pio_task() codepath.
1452 */
1453 } else {
1454 /* PIO data in protocol */
1455 ap->hsm_task_state = HSM_ST;
1456
1457 if (qc->tf.flags & ATA_TFLAG_POLLING)
1458 ata_sff_queue_pio_task(link, 0);
1459
1460 /* if polling, ata_sff_pio_task() handles the
1461 * rest. otherwise, interrupt handler takes
1462 * over from here.
1463 */
1464 }
1465
1466 break;
1467
1468 case ATAPI_PROT_PIO:
1469 case ATAPI_PROT_NODATA:
1470 if (qc->tf.flags & ATA_TFLAG_POLLING)
1471 ata_qc_set_polling(qc);
1472
1473 ata_tf_to_host(ap, &qc->tf);
1474
1475 ap->hsm_task_state = HSM_ST_FIRST;
1476
1477 /* send cdb by polling if no cdb interrupt */
1478 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1479 (qc->tf.flags & ATA_TFLAG_POLLING))
1480 ata_sff_queue_pio_task(link, 0);
1481 break;
1482
1483 default:
1484 WARN_ON_ONCE(1);
1485 return AC_ERR_SYSTEM;
1486 }
1487
1488 return 0;
1489}
1490EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
1491
1492/**
1493 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
1494 * @qc: qc to fill result TF for
1495 *
1496 * @qc is finished and result TF needs to be filled. Fill it
1497 * using ->sff_tf_read.
1498 *
1499 * LOCKING:
1500 * spin_lock_irqsave(host lock)
1501 *
1502 * RETURNS:
1503 * true indicating that result TF is successfully filled.
1504 */
1505bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
1506{
1507 qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
1508 return true;
1509}
1510EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
1511
1512static unsigned int ata_sff_idle_irq(struct ata_port *ap)
1513{
1514 ap->stats.idle_irq++;
1515
1516#ifdef ATA_IRQ_TRAP
1517 if ((ap->stats.idle_irq % 1000) == 0) {
1518 ap->ops->sff_check_status(ap);
1519 if (ap->ops->sff_irq_clear)
1520 ap->ops->sff_irq_clear(ap);
1521 ata_port_warn(ap, "irq trap\n");
1522 return 1;
1523 }
1524#endif
1525 return 0; /* irq not handled */
1526}
1527
1528static unsigned int __ata_sff_port_intr(struct ata_port *ap,
1529 struct ata_queued_cmd *qc,
1530 bool hsmv_on_idle)
1531{
1532 u8 status;
1533
1534 VPRINTK("ata%u: protocol %d task_state %d\n",
1535 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1536
1537 /* Check whether we are expecting interrupt in this state */
1538 switch (ap->hsm_task_state) {
1539 case HSM_ST_FIRST:
1540 /* Some pre-ATAPI-4 devices assert INTRQ
1541 * at this state when ready to receive CDB.
1542 */
1543
1544 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1545 * The flag was turned on only for atapi devices. No
1546 * need to check ata_is_atapi(qc->tf.protocol) again.
1547 */
1548 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1549 return ata_sff_idle_irq(ap);
1550 break;
1551 case HSM_ST_IDLE:
1552 return ata_sff_idle_irq(ap);
1553 default:
1554 break;
1555 }
1556
1557 /* check main status, clearing INTRQ if needed */
1558 status = ata_sff_irq_status(ap);
1559 if (status & ATA_BUSY) {
1560 if (hsmv_on_idle) {
1561 /* BMDMA engine is already stopped, we're screwed */
1562 qc->err_mask |= AC_ERR_HSM;
1563 ap->hsm_task_state = HSM_ST_ERR;
1564 } else
1565 return ata_sff_idle_irq(ap);
1566 }
1567
1568 /* clear irq events */
1569 if (ap->ops->sff_irq_clear)
1570 ap->ops->sff_irq_clear(ap);
1571
1572 ata_sff_hsm_move(ap, qc, status, 0);
1573
1574 return 1; /* irq handled */
1575}
1576
1577/**
1578 * ata_sff_port_intr - Handle SFF port interrupt
1579 * @ap: Port on which interrupt arrived (possibly...)
1580 * @qc: Taskfile currently active in engine
1581 *
1582 * Handle port interrupt for given queued command.
1583 *
1584 * LOCKING:
1585 * spin_lock_irqsave(host lock)
1586 *
1587 * RETURNS:
1588 * One if interrupt was handled, zero if not (shared irq).
1589 */
1590unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
1591{
1592 return __ata_sff_port_intr(ap, qc, false);
1593}
1594EXPORT_SYMBOL_GPL(ata_sff_port_intr);
1595
1596static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance,
1597 unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *))
1598{
1599 struct ata_host *host = dev_instance;
1600 bool retried = false;
1601 unsigned int i;
1602 unsigned int handled, idle, polling;
1603 unsigned long flags;
1604
1605 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1606 spin_lock_irqsave(&host->lock, flags);
1607
1608retry:
1609 handled = idle = polling = 0;
1610 for (i = 0; i < host->n_ports; i++) {
1611 struct ata_port *ap = host->ports[i];
1612 struct ata_queued_cmd *qc;
1613
1614 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1615 if (qc) {
1616 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
1617 handled |= port_intr(ap, qc);
1618 else
1619 polling |= 1 << i;
1620 } else
1621 idle |= 1 << i;
1622 }
1623
1624 /*
1625 * If no port was expecting IRQ but the controller is actually
1626 * asserting IRQ line, nobody cared will ensue. Check IRQ
1627 * pending status if available and clear spurious IRQ.
1628 */
1629 if (!handled && !retried) {
1630 bool retry = false;
1631
1632 for (i = 0; i < host->n_ports; i++) {
1633 struct ata_port *ap = host->ports[i];
1634
1635 if (polling & (1 << i))
1636 continue;
1637
1638 if (!ap->ops->sff_irq_check ||
1639 !ap->ops->sff_irq_check(ap))
1640 continue;
1641
1642 if (idle & (1 << i)) {
1643 ap->ops->sff_check_status(ap);
1644 if (ap->ops->sff_irq_clear)
1645 ap->ops->sff_irq_clear(ap);
1646 } else {
1647 /* clear INTRQ and check if BUSY cleared */
1648 if (!(ap->ops->sff_check_status(ap) & ATA_BUSY))
1649 retry |= true;
1650 /*
1651 * With command in flight, we can't do
1652 * sff_irq_clear() w/o racing with completion.
1653 */
1654 }
1655 }
1656
1657 if (retry) {
1658 retried = true;
1659 goto retry;
1660 }
1661 }
1662
1663 spin_unlock_irqrestore(&host->lock, flags);
1664
1665 return IRQ_RETVAL(handled);
1666}
1667
1668/**
1669 * ata_sff_interrupt - Default SFF ATA host interrupt handler
1670 * @irq: irq line (unused)
1671 * @dev_instance: pointer to our ata_host information structure
1672 *
1673 * Default interrupt handler for PCI IDE devices. Calls
1674 * ata_sff_port_intr() for each port that is not disabled.
1675 *
1676 * LOCKING:
1677 * Obtains host lock during operation.
1678 *
1679 * RETURNS:
1680 * IRQ_NONE or IRQ_HANDLED.
1681 */
1682irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
1683{
1684 return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr);
1685}
1686EXPORT_SYMBOL_GPL(ata_sff_interrupt);
1687
1688/**
1689 * ata_sff_lost_interrupt - Check for an apparent lost interrupt
1690 * @ap: port that appears to have timed out
1691 *
1692 * Called from the libata error handlers when the core code suspects
1693 * an interrupt has been lost. If it has complete anything we can and
1694 * then return. Interface must support altstatus for this faster
1695 * recovery to occur.
1696 *
1697 * Locking:
1698 * Caller holds host lock
1699 */
1700
1701void ata_sff_lost_interrupt(struct ata_port *ap)
1702{
1703 u8 status;
1704 struct ata_queued_cmd *qc;
1705
1706 /* Only one outstanding command per SFF channel */
1707 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1708 /* We cannot lose an interrupt on a non-existent or polled command */
1709 if (!qc || qc->tf.flags & ATA_TFLAG_POLLING)
1710 return;
1711 /* See if the controller thinks it is still busy - if so the command
1712 isn't a lost IRQ but is still in progress */
1713 status = ata_sff_altstatus(ap);
1714 if (status & ATA_BUSY)
1715 return;
1716
1717 /* There was a command running, we are no longer busy and we have
1718 no interrupt. */
1719 ata_port_warn(ap, "lost interrupt (Status 0x%x)\n",
1720 status);
1721 /* Run the host interrupt logic as if the interrupt had not been
1722 lost */
1723 ata_sff_port_intr(ap, qc);
1724}
1725EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
1726
1727/**
1728 * ata_sff_freeze - Freeze SFF controller port
1729 * @ap: port to freeze
1730 *
1731 * Freeze SFF controller port.
1732 *
1733 * LOCKING:
1734 * Inherited from caller.
1735 */
1736void ata_sff_freeze(struct ata_port *ap)
1737{
1738 ap->ctl |= ATA_NIEN;
1739 ap->last_ctl = ap->ctl;
1740
1741 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr)
1742 ata_sff_set_devctl(ap, ap->ctl);
1743
1744 /* Under certain circumstances, some controllers raise IRQ on
1745 * ATA_NIEN manipulation. Also, many controllers fail to mask
1746 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1747 */
1748 ap->ops->sff_check_status(ap);
1749
1750 if (ap->ops->sff_irq_clear)
1751 ap->ops->sff_irq_clear(ap);
1752}
1753EXPORT_SYMBOL_GPL(ata_sff_freeze);
1754
1755/**
1756 * ata_sff_thaw - Thaw SFF controller port
1757 * @ap: port to thaw
1758 *
1759 * Thaw SFF controller port.
1760 *
1761 * LOCKING:
1762 * Inherited from caller.
1763 */
1764void ata_sff_thaw(struct ata_port *ap)
1765{
1766 /* clear & re-enable interrupts */
1767 ap->ops->sff_check_status(ap);
1768 if (ap->ops->sff_irq_clear)
1769 ap->ops->sff_irq_clear(ap);
1770 ata_sff_irq_on(ap);
1771}
1772EXPORT_SYMBOL_GPL(ata_sff_thaw);
1773
1774/**
1775 * ata_sff_prereset - prepare SFF link for reset
1776 * @link: SFF link to be reset
1777 * @deadline: deadline jiffies for the operation
1778 *
1779 * SFF link @link is about to be reset. Initialize it. It first
1780 * calls ata_std_prereset() and wait for !BSY if the port is
1781 * being softreset.
1782 *
1783 * LOCKING:
1784 * Kernel thread context (may sleep)
1785 *
1786 * RETURNS:
1787 * 0 on success, -errno otherwise.
1788 */
1789int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
1790{
1791 struct ata_eh_context *ehc = &link->eh_context;
1792 int rc;
1793
1794 rc = ata_std_prereset(link, deadline);
1795 if (rc)
1796 return rc;
1797
1798 /* if we're about to do hardreset, nothing more to do */
1799 if (ehc->i.action & ATA_EH_HARDRESET)
1800 return 0;
1801
1802 /* wait for !BSY if we don't know that no device is attached */
1803 if (!ata_link_offline(link)) {
1804 rc = ata_sff_wait_ready(link, deadline);
1805 if (rc && rc != -ENODEV) {
1806 ata_link_warn(link,
1807 "device not ready (errno=%d), forcing hardreset\n",
1808 rc);
1809 ehc->i.action |= ATA_EH_HARDRESET;
1810 }
1811 }
1812
1813 return 0;
1814}
1815EXPORT_SYMBOL_GPL(ata_sff_prereset);
1816
1817/**
1818 * ata_devchk - PATA device presence detection
1819 * @ap: ATA channel to examine
1820 * @device: Device to examine (starting at zero)
1821 *
1822 * This technique was originally described in
1823 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1824 * later found its way into the ATA/ATAPI spec.
1825 *
1826 * Write a pattern to the ATA shadow registers,
1827 * and if a device is present, it will respond by
1828 * correctly storing and echoing back the
1829 * ATA shadow register contents.
1830 *
1831 * LOCKING:
1832 * caller.
1833 */
1834static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
1835{
1836 struct ata_ioports *ioaddr = &ap->ioaddr;
1837 u8 nsect, lbal;
1838
1839 ap->ops->sff_dev_select(ap, device);
1840
1841 iowrite8(0x55, ioaddr->nsect_addr);
1842 iowrite8(0xaa, ioaddr->lbal_addr);
1843
1844 iowrite8(0xaa, ioaddr->nsect_addr);
1845 iowrite8(0x55, ioaddr->lbal_addr);
1846
1847 iowrite8(0x55, ioaddr->nsect_addr);
1848 iowrite8(0xaa, ioaddr->lbal_addr);
1849
1850 nsect = ioread8(ioaddr->nsect_addr);
1851 lbal = ioread8(ioaddr->lbal_addr);
1852
1853 if ((nsect == 0x55) && (lbal == 0xaa))
1854 return 1; /* we found a device */
1855
1856 return 0; /* nothing found */
1857}
1858
1859/**
1860 * ata_sff_dev_classify - Parse returned ATA device signature
1861 * @dev: ATA device to classify (starting at zero)
1862 * @present: device seems present
1863 * @r_err: Value of error register on completion
1864 *
1865 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1866 * an ATA/ATAPI-defined set of values is placed in the ATA
1867 * shadow registers, indicating the results of device detection
1868 * and diagnostics.
1869 *
1870 * Select the ATA device, and read the values from the ATA shadow
1871 * registers. Then parse according to the Error register value,
1872 * and the spec-defined values examined by ata_dev_classify().
1873 *
1874 * LOCKING:
1875 * caller.
1876 *
1877 * RETURNS:
1878 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1879 */
1880unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
1881 u8 *r_err)
1882{
1883 struct ata_port *ap = dev->link->ap;
1884 struct ata_taskfile tf;
1885 unsigned int class;
1886 u8 err;
1887
1888 ap->ops->sff_dev_select(ap, dev->devno);
1889
1890 memset(&tf, 0, sizeof(tf));
1891
1892 ap->ops->sff_tf_read(ap, &tf);
1893 err = tf.feature;
1894 if (r_err)
1895 *r_err = err;
1896
1897 /* see if device passed diags: continue and warn later */
1898 if (err == 0)
1899 /* diagnostic fail : do nothing _YET_ */
1900 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1901 else if (err == 1)
1902 /* do nothing */ ;
1903 else if ((dev->devno == 0) && (err == 0x81))
1904 /* do nothing */ ;
1905 else
1906 return ATA_DEV_NONE;
1907
1908 /* determine if device is ATA or ATAPI */
1909 class = ata_dev_classify(&tf);
1910
1911 if (class == ATA_DEV_UNKNOWN) {
1912 /* If the device failed diagnostic, it's likely to
1913 * have reported incorrect device signature too.
1914 * Assume ATA device if the device seems present but
1915 * device signature is invalid with diagnostic
1916 * failure.
1917 */
1918 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1919 class = ATA_DEV_ATA;
1920 else
1921 class = ATA_DEV_NONE;
1922 } else if ((class == ATA_DEV_ATA) &&
1923 (ap->ops->sff_check_status(ap) == 0))
1924 class = ATA_DEV_NONE;
1925
1926 return class;
1927}
1928EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
1929
1930/**
1931 * ata_sff_wait_after_reset - wait for devices to become ready after reset
1932 * @link: SFF link which is just reset
1933 * @devmask: mask of present devices
1934 * @deadline: deadline jiffies for the operation
1935 *
1936 * Wait devices attached to SFF @link to become ready after
1937 * reset. It contains preceding 150ms wait to avoid accessing TF
1938 * status register too early.
1939 *
1940 * LOCKING:
1941 * Kernel thread context (may sleep).
1942 *
1943 * RETURNS:
1944 * 0 on success, -ENODEV if some or all of devices in @devmask
1945 * don't seem to exist. -errno on other errors.
1946 */
1947int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
1948 unsigned long deadline)
1949{
1950 struct ata_port *ap = link->ap;
1951 struct ata_ioports *ioaddr = &ap->ioaddr;
1952 unsigned int dev0 = devmask & (1 << 0);
1953 unsigned int dev1 = devmask & (1 << 1);
1954 int rc, ret = 0;
1955
1956 ata_msleep(ap, ATA_WAIT_AFTER_RESET);
1957
1958 /* always check readiness of the master device */
1959 rc = ata_sff_wait_ready(link, deadline);
1960 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
1961 * and TF status is 0xff, bail out on it too.
1962 */
1963 if (rc)
1964 return rc;
1965
1966 /* if device 1 was found in ata_devchk, wait for register
1967 * access briefly, then wait for BSY to clear.
1968 */
1969 if (dev1) {
1970 int i;
1971
1972 ap->ops->sff_dev_select(ap, 1);
1973
1974 /* Wait for register access. Some ATAPI devices fail
1975 * to set nsect/lbal after reset, so don't waste too
1976 * much time on it. We're gonna wait for !BSY anyway.
1977 */
1978 for (i = 0; i < 2; i++) {
1979 u8 nsect, lbal;
1980
1981 nsect = ioread8(ioaddr->nsect_addr);
1982 lbal = ioread8(ioaddr->lbal_addr);
1983 if ((nsect == 1) && (lbal == 1))
1984 break;
1985 ata_msleep(ap, 50); /* give drive a breather */
1986 }
1987
1988 rc = ata_sff_wait_ready(link, deadline);
1989 if (rc) {
1990 if (rc != -ENODEV)
1991 return rc;
1992 ret = rc;
1993 }
1994 }
1995
1996 /* is all this really necessary? */
1997 ap->ops->sff_dev_select(ap, 0);
1998 if (dev1)
1999 ap->ops->sff_dev_select(ap, 1);
2000 if (dev0)
2001 ap->ops->sff_dev_select(ap, 0);
2002
2003 return ret;
2004}
2005EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
2006
2007static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
2008 unsigned long deadline)
2009{
2010 struct ata_ioports *ioaddr = &ap->ioaddr;
2011
2012 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
2013
2014 if (ap->ioaddr.ctl_addr) {
2015 /* software reset. causes dev0 to be selected */
2016 iowrite8(ap->ctl, ioaddr->ctl_addr);
2017 udelay(20); /* FIXME: flush */
2018 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
2019 udelay(20); /* FIXME: flush */
2020 iowrite8(ap->ctl, ioaddr->ctl_addr);
2021 ap->last_ctl = ap->ctl;
2022 }
2023
2024 /* wait the port to become ready */
2025 return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
2026}
2027
2028/**
2029 * ata_sff_softreset - reset host port via ATA SRST
2030 * @link: ATA link to reset
2031 * @classes: resulting classes of attached devices
2032 * @deadline: deadline jiffies for the operation
2033 *
2034 * Reset host port using ATA SRST.
2035 *
2036 * LOCKING:
2037 * Kernel thread context (may sleep)
2038 *
2039 * RETURNS:
2040 * 0 on success, -errno otherwise.
2041 */
2042int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
2043 unsigned long deadline)
2044{
2045 struct ata_port *ap = link->ap;
2046 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2047 unsigned int devmask = 0;
2048 int rc;
2049 u8 err;
2050
2051 DPRINTK("ENTER\n");
2052
2053 /* determine if device 0/1 are present */
2054 if (ata_devchk(ap, 0))
2055 devmask |= (1 << 0);
2056 if (slave_possible && ata_devchk(ap, 1))
2057 devmask |= (1 << 1);
2058
2059 /* select device 0 again */
2060 ap->ops->sff_dev_select(ap, 0);
2061
2062 /* issue bus reset */
2063 DPRINTK("about to softreset, devmask=%x\n", devmask);
2064 rc = ata_bus_softreset(ap, devmask, deadline);
2065 /* if link is occupied, -ENODEV too is an error */
2066 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
2067 ata_link_err(link, "SRST failed (errno=%d)\n", rc);
2068 return rc;
2069 }
2070
2071 /* determine by signature whether we have ATA or ATAPI devices */
2072 classes[0] = ata_sff_dev_classify(&link->device[0],
2073 devmask & (1 << 0), &err);
2074 if (slave_possible && err != 0x81)
2075 classes[1] = ata_sff_dev_classify(&link->device[1],
2076 devmask & (1 << 1), &err);
2077
2078 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2079 return 0;
2080}
2081EXPORT_SYMBOL_GPL(ata_sff_softreset);
2082
2083/**
2084 * sata_sff_hardreset - reset host port via SATA phy reset
2085 * @link: link to reset
2086 * @class: resulting class of attached device
2087 * @deadline: deadline jiffies for the operation
2088 *
2089 * SATA phy-reset host port using DET bits of SControl register,
2090 * wait for !BSY and classify the attached device.
2091 *
2092 * LOCKING:
2093 * Kernel thread context (may sleep)
2094 *
2095 * RETURNS:
2096 * 0 on success, -errno otherwise.
2097 */
2098int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
2099 unsigned long deadline)
2100{
2101 struct ata_eh_context *ehc = &link->eh_context;
2102 const unsigned long *timing = sata_ehc_deb_timing(ehc);
2103 bool online;
2104 int rc;
2105
2106 rc = sata_link_hardreset(link, timing, deadline, &online,
2107 ata_sff_check_ready);
2108 if (online)
2109 *class = ata_sff_dev_classify(link->device, 1, NULL);
2110
2111 DPRINTK("EXIT, class=%u\n", *class);
2112 return rc;
2113}
2114EXPORT_SYMBOL_GPL(sata_sff_hardreset);
2115
2116/**
2117 * ata_sff_postreset - SFF postreset callback
2118 * @link: the target SFF ata_link
2119 * @classes: classes of attached devices
2120 *
2121 * This function is invoked after a successful reset. It first
2122 * calls ata_std_postreset() and performs SFF specific postreset
2123 * processing.
2124 *
2125 * LOCKING:
2126 * Kernel thread context (may sleep)
2127 */
2128void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
2129{
2130 struct ata_port *ap = link->ap;
2131
2132 ata_std_postreset(link, classes);
2133
2134 /* is double-select really necessary? */
2135 if (classes[0] != ATA_DEV_NONE)
2136 ap->ops->sff_dev_select(ap, 1);
2137 if (classes[1] != ATA_DEV_NONE)
2138 ap->ops->sff_dev_select(ap, 0);
2139
2140 /* bail out if no device is present */
2141 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2142 DPRINTK("EXIT, no device\n");
2143 return;
2144 }
2145
2146 /* set up device control */
2147 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) {
2148 ata_sff_set_devctl(ap, ap->ctl);
2149 ap->last_ctl = ap->ctl;
2150 }
2151}
2152EXPORT_SYMBOL_GPL(ata_sff_postreset);
2153
2154/**
2155 * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers
2156 * @qc: command
2157 *
2158 * Drain the FIFO and device of any stuck data following a command
2159 * failing to complete. In some cases this is necessary before a
2160 * reset will recover the device.
2161 *
2162 */
2163
2164void ata_sff_drain_fifo(struct ata_queued_cmd *qc)
2165{
2166 int count;
2167 struct ata_port *ap;
2168
2169 /* We only need to flush incoming data when a command was running */
2170 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
2171 return;
2172
2173 ap = qc->ap;
2174 /* Drain up to 64K of data before we give up this recovery method */
2175 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
2176 && count < 65536; count += 2)
2177 ioread16(ap->ioaddr.data_addr);
2178
2179 /* Can become DEBUG later */
2180 if (count)
2181 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
2182
2183}
2184EXPORT_SYMBOL_GPL(ata_sff_drain_fifo);
2185
2186/**
2187 * ata_sff_error_handler - Stock error handler for SFF controller
2188 * @ap: port to handle error for
2189 *
2190 * Stock error handler for SFF controller. It can handle both
2191 * PATA and SATA controllers. Many controllers should be able to
2192 * use this EH as-is or with some added handling before and
2193 * after.
2194 *
2195 * LOCKING:
2196 * Kernel thread context (may sleep)
2197 */
2198void ata_sff_error_handler(struct ata_port *ap)
2199{
2200 ata_reset_fn_t softreset = ap->ops->softreset;
2201 ata_reset_fn_t hardreset = ap->ops->hardreset;
2202 struct ata_queued_cmd *qc;
2203 unsigned long flags;
2204
2205 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2206 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2207 qc = NULL;
2208
2209 spin_lock_irqsave(ap->lock, flags);
2210
2211 /*
2212 * We *MUST* do FIFO draining before we issue a reset as
2213 * several devices helpfully clear their internal state and
2214 * will lock solid if we touch the data port post reset. Pass
2215 * qc in case anyone wants to do different PIO/DMA recovery or
2216 * has per command fixups
2217 */
2218 if (ap->ops->sff_drain_fifo)
2219 ap->ops->sff_drain_fifo(qc);
2220
2221 spin_unlock_irqrestore(ap->lock, flags);
2222
2223 /* ignore built-in hardresets if SCR access is not available */
2224 if ((hardreset == sata_std_hardreset ||
2225 hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link))
2226 hardreset = NULL;
2227
2228 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2229 ap->ops->postreset);
2230}
2231EXPORT_SYMBOL_GPL(ata_sff_error_handler);
2232
2233/**
2234 * ata_sff_std_ports - initialize ioaddr with standard port offsets.
2235 * @ioaddr: IO address structure to be initialized
2236 *
2237 * Utility function which initializes data_addr, error_addr,
2238 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2239 * device_addr, status_addr, and command_addr to standard offsets
2240 * relative to cmd_addr.
2241 *
2242 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2243 */
2244void ata_sff_std_ports(struct ata_ioports *ioaddr)
2245{
2246 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2247 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2248 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2249 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2250 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2251 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2252 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2253 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2254 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2255 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2256}
2257EXPORT_SYMBOL_GPL(ata_sff_std_ports);
2258
2259#ifdef CONFIG_PCI
2260
2261static int ata_resources_present(struct pci_dev *pdev, int port)
2262{
2263 int i;
2264
2265 /* Check the PCI resources for this channel are enabled */
2266 port = port * 2;
2267 for (i = 0; i < 2; i++) {
2268 if (pci_resource_start(pdev, port + i) == 0 ||
2269 pci_resource_len(pdev, port + i) == 0)
2270 return 0;
2271 }
2272 return 1;
2273}
2274
2275/**
2276 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
2277 * @host: target ATA host
2278 *
2279 * Acquire native PCI ATA resources for @host and initialize the
2280 * first two ports of @host accordingly. Ports marked dummy are
2281 * skipped and allocation failure makes the port dummy.
2282 *
2283 * Note that native PCI resources are valid even for legacy hosts
2284 * as we fix up pdev resources array early in boot, so this
2285 * function can be used for both native and legacy SFF hosts.
2286 *
2287 * LOCKING:
2288 * Inherited from calling layer (may sleep).
2289 *
2290 * RETURNS:
2291 * 0 if at least one port is initialized, -ENODEV if no port is
2292 * available.
2293 */
2294int ata_pci_sff_init_host(struct ata_host *host)
2295{
2296 struct device *gdev = host->dev;
2297 struct pci_dev *pdev = to_pci_dev(gdev);
2298 unsigned int mask = 0;
2299 int i, rc;
2300
2301 /* request, iomap BARs and init port addresses accordingly */
2302 for (i = 0; i < 2; i++) {
2303 struct ata_port *ap = host->ports[i];
2304 int base = i * 2;
2305 void __iomem * const *iomap;
2306
2307 if (ata_port_is_dummy(ap))
2308 continue;
2309
2310 /* Discard disabled ports. Some controllers show
2311 * their unused channels this way. Disabled ports are
2312 * made dummy.
2313 */
2314 if (!ata_resources_present(pdev, i)) {
2315 ap->ops = &ata_dummy_port_ops;
2316 continue;
2317 }
2318
2319 rc = pcim_iomap_regions(pdev, 0x3 << base,
2320 dev_driver_string(gdev));
2321 if (rc) {
2322 dev_warn(gdev,
2323 "failed to request/iomap BARs for port %d (errno=%d)\n",
2324 i, rc);
2325 if (rc == -EBUSY)
2326 pcim_pin_device(pdev);
2327 ap->ops = &ata_dummy_port_ops;
2328 continue;
2329 }
2330 host->iomap = iomap = pcim_iomap_table(pdev);
2331
2332 ap->ioaddr.cmd_addr = iomap[base];
2333 ap->ioaddr.altstatus_addr =
2334 ap->ioaddr.ctl_addr = (void __iomem *)
2335 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
2336 ata_sff_std_ports(&ap->ioaddr);
2337
2338 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2339 (unsigned long long)pci_resource_start(pdev, base),
2340 (unsigned long long)pci_resource_start(pdev, base + 1));
2341
2342 mask |= 1 << i;
2343 }
2344
2345 if (!mask) {
2346 dev_err(gdev, "no available native port\n");
2347 return -ENODEV;
2348 }
2349
2350 return 0;
2351}
2352EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
2353
2354/**
2355 * ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host
2356 * @pdev: target PCI device
2357 * @ppi: array of port_info, must be enough for two ports
2358 * @r_host: out argument for the initialized ATA host
2359 *
2360 * Helper to allocate PIO-only SFF ATA host for @pdev, acquire
2361 * all PCI resources and initialize it accordingly in one go.
2362 *
2363 * LOCKING:
2364 * Inherited from calling layer (may sleep).
2365 *
2366 * RETURNS:
2367 * 0 on success, -errno otherwise.
2368 */
2369int ata_pci_sff_prepare_host(struct pci_dev *pdev,
2370 const struct ata_port_info * const *ppi,
2371 struct ata_host **r_host)
2372{
2373 struct ata_host *host;
2374 int rc;
2375
2376 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2377 return -ENOMEM;
2378
2379 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2380 if (!host) {
2381 dev_err(&pdev->dev, "failed to allocate ATA host\n");
2382 rc = -ENOMEM;
2383 goto err_out;
2384 }
2385
2386 rc = ata_pci_sff_init_host(host);
2387 if (rc)
2388 goto err_out;
2389
2390 devres_remove_group(&pdev->dev, NULL);
2391 *r_host = host;
2392 return 0;
2393
2394err_out:
2395 devres_release_group(&pdev->dev, NULL);
2396 return rc;
2397}
2398EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
2399
2400/**
2401 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
2402 * @host: target SFF ATA host
2403 * @irq_handler: irq_handler used when requesting IRQ(s)
2404 * @sht: scsi_host_template to use when registering the host
2405 *
2406 * This is the counterpart of ata_host_activate() for SFF ATA
2407 * hosts. This separate helper is necessary because SFF hosts
2408 * use two separate interrupts in legacy mode.
2409 *
2410 * LOCKING:
2411 * Inherited from calling layer (may sleep).
2412 *
2413 * RETURNS:
2414 * 0 on success, -errno otherwise.
2415 */
2416int ata_pci_sff_activate_host(struct ata_host *host,
2417 irq_handler_t irq_handler,
2418 struct scsi_host_template *sht)
2419{
2420 struct device *dev = host->dev;
2421 struct pci_dev *pdev = to_pci_dev(dev);
2422 const char *drv_name = dev_driver_string(host->dev);
2423 int legacy_mode = 0, rc;
2424
2425 rc = ata_host_start(host);
2426 if (rc)
2427 return rc;
2428
2429 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2430 u8 tmp8, mask;
2431
2432 /* TODO: What if one channel is in native mode ... */
2433 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2434 mask = (1 << 2) | (1 << 0);
2435 if ((tmp8 & mask) != mask)
2436 legacy_mode = 1;
2437 }
2438
2439 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2440 return -ENOMEM;
2441
2442 if (!legacy_mode && pdev->irq) {
2443 int i;
2444
2445 rc = devm_request_irq(dev, pdev->irq, irq_handler,
2446 IRQF_SHARED, drv_name, host);
2447 if (rc)
2448 goto out;
2449
2450 for (i = 0; i < 2; i++) {
2451 if (ata_port_is_dummy(host->ports[i]))
2452 continue;
2453 ata_port_desc(host->ports[i], "irq %d", pdev->irq);
2454 }
2455 } else if (legacy_mode) {
2456 if (!ata_port_is_dummy(host->ports[0])) {
2457 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2458 irq_handler, IRQF_SHARED,
2459 drv_name, host);
2460 if (rc)
2461 goto out;
2462
2463 ata_port_desc(host->ports[0], "irq %d",
2464 ATA_PRIMARY_IRQ(pdev));
2465 }
2466
2467 if (!ata_port_is_dummy(host->ports[1])) {
2468 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2469 irq_handler, IRQF_SHARED,
2470 drv_name, host);
2471 if (rc)
2472 goto out;
2473
2474 ata_port_desc(host->ports[1], "irq %d",
2475 ATA_SECONDARY_IRQ(pdev));
2476 }
2477 }
2478
2479 rc = ata_host_register(host, sht);
2480out:
2481 if (rc == 0)
2482 devres_remove_group(dev, NULL);
2483 else
2484 devres_release_group(dev, NULL);
2485
2486 return rc;
2487}
2488EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
2489
2490static const struct ata_port_info *ata_sff_find_valid_pi(
2491 const struct ata_port_info * const *ppi)
2492{
2493 int i;
2494
2495 /* look up the first valid port_info */
2496 for (i = 0; i < 2 && ppi[i]; i++)
2497 if (ppi[i]->port_ops != &ata_dummy_port_ops)
2498 return ppi[i];
2499
2500 return NULL;
2501}
2502
2503static int ata_pci_init_one(struct pci_dev *pdev,
2504 const struct ata_port_info * const *ppi,
2505 struct scsi_host_template *sht, void *host_priv,
2506 int hflags, bool bmdma)
2507{
2508 struct device *dev = &pdev->dev;
2509 const struct ata_port_info *pi;
2510 struct ata_host *host = NULL;
2511 int rc;
2512
2513 DPRINTK("ENTER\n");
2514
2515 pi = ata_sff_find_valid_pi(ppi);
2516 if (!pi) {
2517 dev_err(&pdev->dev, "no valid port_info specified\n");
2518 return -EINVAL;
2519 }
2520
2521 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2522 return -ENOMEM;
2523
2524 rc = pcim_enable_device(pdev);
2525 if (rc)
2526 goto out;
2527
2528#ifdef CONFIG_ATA_BMDMA
2529 if (bmdma)
2530 /* prepare and activate BMDMA host */
2531 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
2532 else
2533#endif
2534 /* prepare and activate SFF host */
2535 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
2536 if (rc)
2537 goto out;
2538 host->private_data = host_priv;
2539 host->flags |= hflags;
2540
2541#ifdef CONFIG_ATA_BMDMA
2542 if (bmdma) {
2543 pci_set_master(pdev);
2544 rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
2545 } else
2546#endif
2547 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
2548out:
2549 if (rc == 0)
2550 devres_remove_group(&pdev->dev, NULL);
2551 else
2552 devres_release_group(&pdev->dev, NULL);
2553
2554 return rc;
2555}
2556
2557/**
2558 * ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller
2559 * @pdev: Controller to be initialized
2560 * @ppi: array of port_info, must be enough for two ports
2561 * @sht: scsi_host_template to use when registering the host
2562 * @host_priv: host private_data
2563 * @hflag: host flags
2564 *
2565 * This is a helper function which can be called from a driver's
2566 * xxx_init_one() probe function if the hardware uses traditional
2567 * IDE taskfile registers and is PIO only.
2568 *
2569 * ASSUMPTION:
2570 * Nobody makes a single channel controller that appears solely as
2571 * the secondary legacy port on PCI.
2572 *
2573 * LOCKING:
2574 * Inherited from PCI layer (may sleep).
2575 *
2576 * RETURNS:
2577 * Zero on success, negative on errno-based value on error.
2578 */
2579int ata_pci_sff_init_one(struct pci_dev *pdev,
2580 const struct ata_port_info * const *ppi,
2581 struct scsi_host_template *sht, void *host_priv, int hflag)
2582{
2583 return ata_pci_init_one(pdev, ppi, sht, host_priv, hflag, 0);
2584}
2585EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
2586
2587#endif /* CONFIG_PCI */
2588
2589/*
2590 * BMDMA support
2591 */
2592
2593#ifdef CONFIG_ATA_BMDMA
2594
2595const struct ata_port_operations ata_bmdma_port_ops = {
2596 .inherits = &ata_sff_port_ops,
2597
2598 .error_handler = ata_bmdma_error_handler,
2599 .post_internal_cmd = ata_bmdma_post_internal_cmd,
2600
2601 .qc_prep = ata_bmdma_qc_prep,
2602 .qc_issue = ata_bmdma_qc_issue,
2603
2604 .sff_irq_clear = ata_bmdma_irq_clear,
2605 .bmdma_setup = ata_bmdma_setup,
2606 .bmdma_start = ata_bmdma_start,
2607 .bmdma_stop = ata_bmdma_stop,
2608 .bmdma_status = ata_bmdma_status,
2609
2610 .port_start = ata_bmdma_port_start,
2611};
2612EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
2613
2614const struct ata_port_operations ata_bmdma32_port_ops = {
2615 .inherits = &ata_bmdma_port_ops,
2616
2617 .sff_data_xfer = ata_sff_data_xfer32,
2618 .port_start = ata_bmdma_port_start32,
2619};
2620EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
2621
2622/**
2623 * ata_bmdma_fill_sg - Fill PCI IDE PRD table
2624 * @qc: Metadata associated with taskfile to be transferred
2625 *
2626 * Fill PCI IDE PRD (scatter-gather) table with segments
2627 * associated with the current disk command.
2628 *
2629 * LOCKING:
2630 * spin_lock_irqsave(host lock)
2631 *
2632 */
2633static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc)
2634{
2635 struct ata_port *ap = qc->ap;
2636 struct ata_bmdma_prd *prd = ap->bmdma_prd;
2637 struct scatterlist *sg;
2638 unsigned int si, pi;
2639
2640 pi = 0;
2641 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2642 u32 addr, offset;
2643 u32 sg_len, len;
2644
2645 /* determine if physical DMA addr spans 64K boundary.
2646 * Note h/w doesn't support 64-bit, so we unconditionally
2647 * truncate dma_addr_t to u32.
2648 */
2649 addr = (u32) sg_dma_address(sg);
2650 sg_len = sg_dma_len(sg);
2651
2652 while (sg_len) {
2653 offset = addr & 0xffff;
2654 len = sg_len;
2655 if ((offset + sg_len) > 0x10000)
2656 len = 0x10000 - offset;
2657
2658 prd[pi].addr = cpu_to_le32(addr);
2659 prd[pi].flags_len = cpu_to_le32(len & 0xffff);
2660 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
2661
2662 pi++;
2663 sg_len -= len;
2664 addr += len;
2665 }
2666 }
2667
2668 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2669}
2670
2671/**
2672 * ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table
2673 * @qc: Metadata associated with taskfile to be transferred
2674 *
2675 * Fill PCI IDE PRD (scatter-gather) table with segments
2676 * associated with the current disk command. Perform the fill
2677 * so that we avoid writing any length 64K records for
2678 * controllers that don't follow the spec.
2679 *
2680 * LOCKING:
2681 * spin_lock_irqsave(host lock)
2682 *
2683 */
2684static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc)
2685{
2686 struct ata_port *ap = qc->ap;
2687 struct ata_bmdma_prd *prd = ap->bmdma_prd;
2688 struct scatterlist *sg;
2689 unsigned int si, pi;
2690
2691 pi = 0;
2692 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2693 u32 addr, offset;
2694 u32 sg_len, len, blen;
2695
2696 /* determine if physical DMA addr spans 64K boundary.
2697 * Note h/w doesn't support 64-bit, so we unconditionally
2698 * truncate dma_addr_t to u32.
2699 */
2700 addr = (u32) sg_dma_address(sg);
2701 sg_len = sg_dma_len(sg);
2702
2703 while (sg_len) {
2704 offset = addr & 0xffff;
2705 len = sg_len;
2706 if ((offset + sg_len) > 0x10000)
2707 len = 0x10000 - offset;
2708
2709 blen = len & 0xffff;
2710 prd[pi].addr = cpu_to_le32(addr);
2711 if (blen == 0) {
2712 /* Some PATA chipsets like the CS5530 can't
2713 cope with 0x0000 meaning 64K as the spec
2714 says */
2715 prd[pi].flags_len = cpu_to_le32(0x8000);
2716 blen = 0x8000;
2717 prd[++pi].addr = cpu_to_le32(addr + 0x8000);
2718 }
2719 prd[pi].flags_len = cpu_to_le32(blen);
2720 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
2721
2722 pi++;
2723 sg_len -= len;
2724 addr += len;
2725 }
2726 }
2727
2728 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2729}
2730
2731/**
2732 * ata_bmdma_qc_prep - Prepare taskfile for submission
2733 * @qc: Metadata associated with taskfile to be prepared
2734 *
2735 * Prepare ATA taskfile for submission.
2736 *
2737 * LOCKING:
2738 * spin_lock_irqsave(host lock)
2739 */
2740void ata_bmdma_qc_prep(struct ata_queued_cmd *qc)
2741{
2742 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2743 return;
2744
2745 ata_bmdma_fill_sg(qc);
2746}
2747EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep);
2748
2749/**
2750 * ata_bmdma_dumb_qc_prep - Prepare taskfile for submission
2751 * @qc: Metadata associated with taskfile to be prepared
2752 *
2753 * Prepare ATA taskfile for submission.
2754 *
2755 * LOCKING:
2756 * spin_lock_irqsave(host lock)
2757 */
2758void ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc)
2759{
2760 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2761 return;
2762
2763 ata_bmdma_fill_sg_dumb(qc);
2764}
2765EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep);
2766
2767/**
2768 * ata_bmdma_qc_issue - issue taskfile to a BMDMA controller
2769 * @qc: command to issue to device
2770 *
2771 * This function issues a PIO, NODATA or DMA command to a
2772 * SFF/BMDMA controller. PIO and NODATA are handled by
2773 * ata_sff_qc_issue().
2774 *
2775 * LOCKING:
2776 * spin_lock_irqsave(host lock)
2777 *
2778 * RETURNS:
2779 * Zero on success, AC_ERR_* mask on failure
2780 */
2781unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc)
2782{
2783 struct ata_port *ap = qc->ap;
2784 struct ata_link *link = qc->dev->link;
2785
2786 /* defer PIO handling to sff_qc_issue */
2787 if (!ata_is_dma(qc->tf.protocol))
2788 return ata_sff_qc_issue(qc);
2789
2790 /* select the device */
2791 ata_dev_select(ap, qc->dev->devno, 1, 0);
2792
2793 /* start the command */
2794 switch (qc->tf.protocol) {
2795 case ATA_PROT_DMA:
2796 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2797
2798 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2799 ap->ops->bmdma_setup(qc); /* set up bmdma */
2800 ap->ops->bmdma_start(qc); /* initiate bmdma */
2801 ap->hsm_task_state = HSM_ST_LAST;
2802 break;
2803
2804 case ATAPI_PROT_DMA:
2805 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2806
2807 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2808 ap->ops->bmdma_setup(qc); /* set up bmdma */
2809 ap->hsm_task_state = HSM_ST_FIRST;
2810
2811 /* send cdb by polling if no cdb interrupt */
2812 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
2813 ata_sff_queue_pio_task(link, 0);
2814 break;
2815
2816 default:
2817 WARN_ON(1);
2818 return AC_ERR_SYSTEM;
2819 }
2820
2821 return 0;
2822}
2823EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue);
2824
2825/**
2826 * ata_bmdma_port_intr - Handle BMDMA port interrupt
2827 * @ap: Port on which interrupt arrived (possibly...)
2828 * @qc: Taskfile currently active in engine
2829 *
2830 * Handle port interrupt for given queued command.
2831 *
2832 * LOCKING:
2833 * spin_lock_irqsave(host lock)
2834 *
2835 * RETURNS:
2836 * One if interrupt was handled, zero if not (shared irq).
2837 */
2838unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
2839{
2840 struct ata_eh_info *ehi = &ap->link.eh_info;
2841 u8 host_stat = 0;
2842 bool bmdma_stopped = false;
2843 unsigned int handled;
2844
2845 if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) {
2846 /* check status of DMA engine */
2847 host_stat = ap->ops->bmdma_status(ap);
2848 VPRINTK("ata%u: host_stat 0x%X\n", ap->print_id, host_stat);
2849
2850 /* if it's not our irq... */
2851 if (!(host_stat & ATA_DMA_INTR))
2852 return ata_sff_idle_irq(ap);
2853
2854 /* before we do anything else, clear DMA-Start bit */
2855 ap->ops->bmdma_stop(qc);
2856 bmdma_stopped = true;
2857
2858 if (unlikely(host_stat & ATA_DMA_ERR)) {
2859 /* error when transferring data to/from memory */
2860 qc->err_mask |= AC_ERR_HOST_BUS;
2861 ap->hsm_task_state = HSM_ST_ERR;
2862 }
2863 }
2864
2865 handled = __ata_sff_port_intr(ap, qc, bmdma_stopped);
2866
2867 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
2868 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
2869
2870 return handled;
2871}
2872EXPORT_SYMBOL_GPL(ata_bmdma_port_intr);
2873
2874/**
2875 * ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler
2876 * @irq: irq line (unused)
2877 * @dev_instance: pointer to our ata_host information structure
2878 *
2879 * Default interrupt handler for PCI IDE devices. Calls
2880 * ata_bmdma_port_intr() for each port that is not disabled.
2881 *
2882 * LOCKING:
2883 * Obtains host lock during operation.
2884 *
2885 * RETURNS:
2886 * IRQ_NONE or IRQ_HANDLED.
2887 */
2888irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance)
2889{
2890 return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr);
2891}
2892EXPORT_SYMBOL_GPL(ata_bmdma_interrupt);
2893
2894/**
2895 * ata_bmdma_error_handler - Stock error handler for BMDMA controller
2896 * @ap: port to handle error for
2897 *
2898 * Stock error handler for BMDMA controller. It can handle both
2899 * PATA and SATA controllers. Most BMDMA controllers should be
2900 * able to use this EH as-is or with some added handling before
2901 * and after.
2902 *
2903 * LOCKING:
2904 * Kernel thread context (may sleep)
2905 */
2906void ata_bmdma_error_handler(struct ata_port *ap)
2907{
2908 struct ata_queued_cmd *qc;
2909 unsigned long flags;
2910 bool thaw = false;
2911
2912 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2913 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2914 qc = NULL;
2915
2916 /* reset PIO HSM and stop DMA engine */
2917 spin_lock_irqsave(ap->lock, flags);
2918
2919 if (qc && ata_is_dma(qc->tf.protocol)) {
2920 u8 host_stat;
2921
2922 host_stat = ap->ops->bmdma_status(ap);
2923
2924 /* BMDMA controllers indicate host bus error by
2925 * setting DMA_ERR bit and timing out. As it wasn't
2926 * really a timeout event, adjust error mask and
2927 * cancel frozen state.
2928 */
2929 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
2930 qc->err_mask = AC_ERR_HOST_BUS;
2931 thaw = true;
2932 }
2933
2934 ap->ops->bmdma_stop(qc);
2935
2936 /* if we're gonna thaw, make sure IRQ is clear */
2937 if (thaw) {
2938 ap->ops->sff_check_status(ap);
2939 if (ap->ops->sff_irq_clear)
2940 ap->ops->sff_irq_clear(ap);
2941 }
2942 }
2943
2944 spin_unlock_irqrestore(ap->lock, flags);
2945
2946 if (thaw)
2947 ata_eh_thaw_port(ap);
2948
2949 ata_sff_error_handler(ap);
2950}
2951EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
2952
2953/**
2954 * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA
2955 * @qc: internal command to clean up
2956 *
2957 * LOCKING:
2958 * Kernel thread context (may sleep)
2959 */
2960void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
2961{
2962 struct ata_port *ap = qc->ap;
2963 unsigned long flags;
2964
2965 if (ata_is_dma(qc->tf.protocol)) {
2966 spin_lock_irqsave(ap->lock, flags);
2967 ap->ops->bmdma_stop(qc);
2968 spin_unlock_irqrestore(ap->lock, flags);
2969 }
2970}
2971EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
2972
2973/**
2974 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
2975 * @ap: Port associated with this ATA transaction.
2976 *
2977 * Clear interrupt and error flags in DMA status register.
2978 *
2979 * May be used as the irq_clear() entry in ata_port_operations.
2980 *
2981 * LOCKING:
2982 * spin_lock_irqsave(host lock)
2983 */
2984void ata_bmdma_irq_clear(struct ata_port *ap)
2985{
2986 void __iomem *mmio = ap->ioaddr.bmdma_addr;
2987
2988 if (!mmio)
2989 return;
2990
2991 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
2992}
2993EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
2994
2995/**
2996 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
2997 * @qc: Info associated with this ATA transaction.
2998 *
2999 * LOCKING:
3000 * spin_lock_irqsave(host lock)
3001 */
3002void ata_bmdma_setup(struct ata_queued_cmd *qc)
3003{
3004 struct ata_port *ap = qc->ap;
3005 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3006 u8 dmactl;
3007
3008 /* load PRD table addr. */
3009 mb(); /* make sure PRD table writes are visible to controller */
3010 iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
3011
3012 /* specify data direction, triple-check start bit is clear */
3013 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3014 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3015 if (!rw)
3016 dmactl |= ATA_DMA_WR;
3017 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3018
3019 /* issue r/w command */
3020 ap->ops->sff_exec_command(ap, &qc->tf);
3021}
3022EXPORT_SYMBOL_GPL(ata_bmdma_setup);
3023
3024/**
3025 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
3026 * @qc: Info associated with this ATA transaction.
3027 *
3028 * LOCKING:
3029 * spin_lock_irqsave(host lock)
3030 */
3031void ata_bmdma_start(struct ata_queued_cmd *qc)
3032{
3033 struct ata_port *ap = qc->ap;
3034 u8 dmactl;
3035
3036 /* start host DMA transaction */
3037 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3038 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3039
3040 /* Strictly, one may wish to issue an ioread8() here, to
3041 * flush the mmio write. However, control also passes
3042 * to the hardware at this point, and it will interrupt
3043 * us when we are to resume control. So, in effect,
3044 * we don't care when the mmio write flushes.
3045 * Further, a read of the DMA status register _immediately_
3046 * following the write may not be what certain flaky hardware
3047 * is expected, so I think it is best to not add a readb()
3048 * without first all the MMIO ATA cards/mobos.
3049 * Or maybe I'm just being paranoid.
3050 *
3051 * FIXME: The posting of this write means I/O starts are
3052 * unnecessarily delayed for MMIO
3053 */
3054}
3055EXPORT_SYMBOL_GPL(ata_bmdma_start);
3056
3057/**
3058 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
3059 * @qc: Command we are ending DMA for
3060 *
3061 * Clears the ATA_DMA_START flag in the dma control register
3062 *
3063 * May be used as the bmdma_stop() entry in ata_port_operations.
3064 *
3065 * LOCKING:
3066 * spin_lock_irqsave(host lock)
3067 */
3068void ata_bmdma_stop(struct ata_queued_cmd *qc)
3069{
3070 struct ata_port *ap = qc->ap;
3071 void __iomem *mmio = ap->ioaddr.bmdma_addr;
3072
3073 /* clear start/stop bit */
3074 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
3075 mmio + ATA_DMA_CMD);
3076
3077 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
3078 ata_sff_dma_pause(ap);
3079}
3080EXPORT_SYMBOL_GPL(ata_bmdma_stop);
3081
3082/**
3083 * ata_bmdma_status - Read PCI IDE BMDMA status
3084 * @ap: Port associated with this ATA transaction.
3085 *
3086 * Read and return BMDMA status register.
3087 *
3088 * May be used as the bmdma_status() entry in ata_port_operations.
3089 *
3090 * LOCKING:
3091 * spin_lock_irqsave(host lock)
3092 */
3093u8 ata_bmdma_status(struct ata_port *ap)
3094{
3095 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
3096}
3097EXPORT_SYMBOL_GPL(ata_bmdma_status);
3098
3099
3100/**
3101 * ata_bmdma_port_start - Set port up for bmdma.
3102 * @ap: Port to initialize
3103 *
3104 * Called just after data structures for each port are
3105 * initialized. Allocates space for PRD table.
3106 *
3107 * May be used as the port_start() entry in ata_port_operations.
3108 *
3109 * LOCKING:
3110 * Inherited from caller.
3111 */
3112int ata_bmdma_port_start(struct ata_port *ap)
3113{
3114 if (ap->mwdma_mask || ap->udma_mask) {
3115 ap->bmdma_prd =
3116 dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ,
3117 &ap->bmdma_prd_dma, GFP_KERNEL);
3118 if (!ap->bmdma_prd)
3119 return -ENOMEM;
3120 }
3121
3122 return 0;
3123}
3124EXPORT_SYMBOL_GPL(ata_bmdma_port_start);
3125
3126/**
3127 * ata_bmdma_port_start32 - Set port up for dma.
3128 * @ap: Port to initialize
3129 *
3130 * Called just after data structures for each port are
3131 * initialized. Enables 32bit PIO and allocates space for PRD
3132 * table.
3133 *
3134 * May be used as the port_start() entry in ata_port_operations for
3135 * devices that are capable of 32bit PIO.
3136 *
3137 * LOCKING:
3138 * Inherited from caller.
3139 */
3140int ata_bmdma_port_start32(struct ata_port *ap)
3141{
3142 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
3143 return ata_bmdma_port_start(ap);
3144}
3145EXPORT_SYMBOL_GPL(ata_bmdma_port_start32);
3146
3147#ifdef CONFIG_PCI
3148
3149/**
3150 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
3151 * @pdev: PCI device
3152 *
3153 * Some PCI ATA devices report simplex mode but in fact can be told to
3154 * enter non simplex mode. This implements the necessary logic to
3155 * perform the task on such devices. Calling it on other devices will
3156 * have -undefined- behaviour.
3157 */
3158int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
3159{
3160 unsigned long bmdma = pci_resource_start(pdev, 4);
3161 u8 simplex;
3162
3163 if (bmdma == 0)
3164 return -ENOENT;
3165
3166 simplex = inb(bmdma + 0x02);
3167 outb(simplex & 0x60, bmdma + 0x02);
3168 simplex = inb(bmdma + 0x02);
3169 if (simplex & 0x80)
3170 return -EOPNOTSUPP;
3171 return 0;
3172}
3173EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
3174
3175static void ata_bmdma_nodma(struct ata_host *host, const char *reason)
3176{
3177 int i;
3178
3179 dev_err(host->dev, "BMDMA: %s, falling back to PIO\n", reason);
3180
3181 for (i = 0; i < 2; i++) {
3182 host->ports[i]->mwdma_mask = 0;
3183 host->ports[i]->udma_mask = 0;
3184 }
3185}
3186
3187/**
3188 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
3189 * @host: target ATA host
3190 *
3191 * Acquire PCI BMDMA resources and initialize @host accordingly.
3192 *
3193 * LOCKING:
3194 * Inherited from calling layer (may sleep).
3195 */
3196void ata_pci_bmdma_init(struct ata_host *host)
3197{
3198 struct device *gdev = host->dev;
3199 struct pci_dev *pdev = to_pci_dev(gdev);
3200 int i, rc;
3201
3202 /* No BAR4 allocation: No DMA */
3203 if (pci_resource_start(pdev, 4) == 0) {
3204 ata_bmdma_nodma(host, "BAR4 is zero");
3205 return;
3206 }
3207
3208 /*
3209 * Some controllers require BMDMA region to be initialized
3210 * even if DMA is not in use to clear IRQ status via
3211 * ->sff_irq_clear method. Try to initialize bmdma_addr
3212 * regardless of dma masks.
3213 */
3214 rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
3215 if (rc)
3216 ata_bmdma_nodma(host, "failed to set dma mask");
3217 if (!rc) {
3218 rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
3219 if (rc)
3220 ata_bmdma_nodma(host,
3221 "failed to set consistent dma mask");
3222 }
3223
3224 /* request and iomap DMA region */
3225 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
3226 if (rc) {
3227 ata_bmdma_nodma(host, "failed to request/iomap BAR4");
3228 return;
3229 }
3230 host->iomap = pcim_iomap_table(pdev);
3231
3232 for (i = 0; i < 2; i++) {
3233 struct ata_port *ap = host->ports[i];
3234 void __iomem *bmdma = host->iomap[4] + 8 * i;
3235
3236 if (ata_port_is_dummy(ap))
3237 continue;
3238
3239 ap->ioaddr.bmdma_addr = bmdma;
3240 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
3241 (ioread8(bmdma + 2) & 0x80))
3242 host->flags |= ATA_HOST_SIMPLEX;
3243
3244 ata_port_desc(ap, "bmdma 0x%llx",
3245 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
3246 }
3247}
3248EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
3249
3250/**
3251 * ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host
3252 * @pdev: target PCI device
3253 * @ppi: array of port_info, must be enough for two ports
3254 * @r_host: out argument for the initialized ATA host
3255 *
3256 * Helper to allocate BMDMA ATA host for @pdev, acquire all PCI
3257 * resources and initialize it accordingly in one go.
3258 *
3259 * LOCKING:
3260 * Inherited from calling layer (may sleep).
3261 *
3262 * RETURNS:
3263 * 0 on success, -errno otherwise.
3264 */
3265int ata_pci_bmdma_prepare_host(struct pci_dev *pdev,
3266 const struct ata_port_info * const * ppi,
3267 struct ata_host **r_host)
3268{
3269 int rc;
3270
3271 rc = ata_pci_sff_prepare_host(pdev, ppi, r_host);
3272 if (rc)
3273 return rc;
3274
3275 ata_pci_bmdma_init(*r_host);
3276 return 0;
3277}
3278EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host);
3279
3280/**
3281 * ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller
3282 * @pdev: Controller to be initialized
3283 * @ppi: array of port_info, must be enough for two ports
3284 * @sht: scsi_host_template to use when registering the host
3285 * @host_priv: host private_data
3286 * @hflags: host flags
3287 *
3288 * This function is similar to ata_pci_sff_init_one() but also
3289 * takes care of BMDMA initialization.
3290 *
3291 * LOCKING:
3292 * Inherited from PCI layer (may sleep).
3293 *
3294 * RETURNS:
3295 * Zero on success, negative on errno-based value on error.
3296 */
3297int ata_pci_bmdma_init_one(struct pci_dev *pdev,
3298 const struct ata_port_info * const * ppi,
3299 struct scsi_host_template *sht, void *host_priv,
3300 int hflags)
3301{
3302 return ata_pci_init_one(pdev, ppi, sht, host_priv, hflags, 1);
3303}
3304EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one);
3305
3306#endif /* CONFIG_PCI */
3307#endif /* CONFIG_ATA_BMDMA */
3308
3309/**
3310 * ata_sff_port_init - Initialize SFF/BMDMA ATA port
3311 * @ap: Port to initialize
3312 *
3313 * Called on port allocation to initialize SFF/BMDMA specific
3314 * fields.
3315 *
3316 * LOCKING:
3317 * None.
3318 */
3319void ata_sff_port_init(struct ata_port *ap)
3320{
3321 INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task);
3322 ap->ctl = ATA_DEVCTL_OBS;
3323 ap->last_ctl = 0xFF;
3324}
3325
3326int __init ata_sff_init(void)
3327{
3328 ata_sff_wq = alloc_workqueue("ata_sff", WQ_MEM_RECLAIM, WQ_MAX_ACTIVE);
3329 if (!ata_sff_wq)
3330 return -ENOMEM;
3331
3332 return 0;
3333}
3334
3335void ata_sff_exit(void)
3336{
3337 destroy_workqueue(ata_sff_wq);
3338}