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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 */
10#include <linux/hardirq.h>
11#include <linux/init.h>
12#include <linux/highmem.h>
13#include <linux/kernel.h>
14#include <linux/linkage.h>
15#include <linux/sched.h>
16#include <linux/smp.h>
17#include <linux/mm.h>
18#include <linux/module.h>
19#include <linux/bitops.h>
20
21#include <asm/bcache.h>
22#include <asm/bootinfo.h>
23#include <asm/cache.h>
24#include <asm/cacheops.h>
25#include <asm/cpu.h>
26#include <asm/cpu-features.h>
27#include <asm/io.h>
28#include <asm/page.h>
29#include <asm/pgtable.h>
30#include <asm/r4kcache.h>
31#include <asm/sections.h>
32#include <asm/system.h>
33#include <asm/mmu_context.h>
34#include <asm/war.h>
35#include <asm/cacheflush.h> /* for run_uncached() */
36
37
38/*
39 * Special Variant of smp_call_function for use by cache functions:
40 *
41 * o No return value
42 * o collapses to normal function call on UP kernels
43 * o collapses to normal function call on systems with a single shared
44 * primary cache.
45 * o doesn't disable interrupts on the local CPU
46 */
47static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
48{
49 preempt_disable();
50
51#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
52 smp_call_function(func, info, 1);
53#endif
54 func(info);
55 preempt_enable();
56}
57
58#if defined(CONFIG_MIPS_CMP)
59#define cpu_has_safe_index_cacheops 0
60#else
61#define cpu_has_safe_index_cacheops 1
62#endif
63
64/*
65 * Must die.
66 */
67static unsigned long icache_size __read_mostly;
68static unsigned long dcache_size __read_mostly;
69static unsigned long scache_size __read_mostly;
70
71/*
72 * Dummy cache handling routines for machines without boardcaches
73 */
74static void cache_noop(void) {}
75
76static struct bcache_ops no_sc_ops = {
77 .bc_enable = (void *)cache_noop,
78 .bc_disable = (void *)cache_noop,
79 .bc_wback_inv = (void *)cache_noop,
80 .bc_inv = (void *)cache_noop
81};
82
83struct bcache_ops *bcops = &no_sc_ops;
84
85#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
86#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
87
88#define R4600_HIT_CACHEOP_WAR_IMPL \
89do { \
90 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
91 *(volatile unsigned long *)CKSEG1; \
92 if (R4600_V1_HIT_CACHEOP_WAR) \
93 __asm__ __volatile__("nop;nop;nop;nop"); \
94} while (0)
95
96static void (*r4k_blast_dcache_page)(unsigned long addr);
97
98static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
99{
100 R4600_HIT_CACHEOP_WAR_IMPL;
101 blast_dcache32_page(addr);
102}
103
104static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
105{
106 R4600_HIT_CACHEOP_WAR_IMPL;
107 blast_dcache64_page(addr);
108}
109
110static void __cpuinit r4k_blast_dcache_page_setup(void)
111{
112 unsigned long dc_lsize = cpu_dcache_line_size();
113
114 if (dc_lsize == 0)
115 r4k_blast_dcache_page = (void *)cache_noop;
116 else if (dc_lsize == 16)
117 r4k_blast_dcache_page = blast_dcache16_page;
118 else if (dc_lsize == 32)
119 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
120 else if (dc_lsize == 64)
121 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
122}
123
124static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
125
126static void __cpuinit r4k_blast_dcache_page_indexed_setup(void)
127{
128 unsigned long dc_lsize = cpu_dcache_line_size();
129
130 if (dc_lsize == 0)
131 r4k_blast_dcache_page_indexed = (void *)cache_noop;
132 else if (dc_lsize == 16)
133 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
134 else if (dc_lsize == 32)
135 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
136 else if (dc_lsize == 64)
137 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
138}
139
140static void (* r4k_blast_dcache)(void);
141
142static void __cpuinit r4k_blast_dcache_setup(void)
143{
144 unsigned long dc_lsize = cpu_dcache_line_size();
145
146 if (dc_lsize == 0)
147 r4k_blast_dcache = (void *)cache_noop;
148 else if (dc_lsize == 16)
149 r4k_blast_dcache = blast_dcache16;
150 else if (dc_lsize == 32)
151 r4k_blast_dcache = blast_dcache32;
152 else if (dc_lsize == 64)
153 r4k_blast_dcache = blast_dcache64;
154}
155
156/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
157#define JUMP_TO_ALIGN(order) \
158 __asm__ __volatile__( \
159 "b\t1f\n\t" \
160 ".align\t" #order "\n\t" \
161 "1:\n\t" \
162 )
163#define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
164#define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
165
166static inline void blast_r4600_v1_icache32(void)
167{
168 unsigned long flags;
169
170 local_irq_save(flags);
171 blast_icache32();
172 local_irq_restore(flags);
173}
174
175static inline void tx49_blast_icache32(void)
176{
177 unsigned long start = INDEX_BASE;
178 unsigned long end = start + current_cpu_data.icache.waysize;
179 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
180 unsigned long ws_end = current_cpu_data.icache.ways <<
181 current_cpu_data.icache.waybit;
182 unsigned long ws, addr;
183
184 CACHE32_UNROLL32_ALIGN2;
185 /* I'm in even chunk. blast odd chunks */
186 for (ws = 0; ws < ws_end; ws += ws_inc)
187 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
188 cache32_unroll32(addr|ws, Index_Invalidate_I);
189 CACHE32_UNROLL32_ALIGN;
190 /* I'm in odd chunk. blast even chunks */
191 for (ws = 0; ws < ws_end; ws += ws_inc)
192 for (addr = start; addr < end; addr += 0x400 * 2)
193 cache32_unroll32(addr|ws, Index_Invalidate_I);
194}
195
196static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
197{
198 unsigned long flags;
199
200 local_irq_save(flags);
201 blast_icache32_page_indexed(page);
202 local_irq_restore(flags);
203}
204
205static inline void tx49_blast_icache32_page_indexed(unsigned long page)
206{
207 unsigned long indexmask = current_cpu_data.icache.waysize - 1;
208 unsigned long start = INDEX_BASE + (page & indexmask);
209 unsigned long end = start + PAGE_SIZE;
210 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
211 unsigned long ws_end = current_cpu_data.icache.ways <<
212 current_cpu_data.icache.waybit;
213 unsigned long ws, addr;
214
215 CACHE32_UNROLL32_ALIGN2;
216 /* I'm in even chunk. blast odd chunks */
217 for (ws = 0; ws < ws_end; ws += ws_inc)
218 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
219 cache32_unroll32(addr|ws, Index_Invalidate_I);
220 CACHE32_UNROLL32_ALIGN;
221 /* I'm in odd chunk. blast even chunks */
222 for (ws = 0; ws < ws_end; ws += ws_inc)
223 for (addr = start; addr < end; addr += 0x400 * 2)
224 cache32_unroll32(addr|ws, Index_Invalidate_I);
225}
226
227static void (* r4k_blast_icache_page)(unsigned long addr);
228
229static void __cpuinit r4k_blast_icache_page_setup(void)
230{
231 unsigned long ic_lsize = cpu_icache_line_size();
232
233 if (ic_lsize == 0)
234 r4k_blast_icache_page = (void *)cache_noop;
235 else if (ic_lsize == 16)
236 r4k_blast_icache_page = blast_icache16_page;
237 else if (ic_lsize == 32)
238 r4k_blast_icache_page = blast_icache32_page;
239 else if (ic_lsize == 64)
240 r4k_blast_icache_page = blast_icache64_page;
241}
242
243
244static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
245
246static void __cpuinit r4k_blast_icache_page_indexed_setup(void)
247{
248 unsigned long ic_lsize = cpu_icache_line_size();
249
250 if (ic_lsize == 0)
251 r4k_blast_icache_page_indexed = (void *)cache_noop;
252 else if (ic_lsize == 16)
253 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
254 else if (ic_lsize == 32) {
255 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
256 r4k_blast_icache_page_indexed =
257 blast_icache32_r4600_v1_page_indexed;
258 else if (TX49XX_ICACHE_INDEX_INV_WAR)
259 r4k_blast_icache_page_indexed =
260 tx49_blast_icache32_page_indexed;
261 else
262 r4k_blast_icache_page_indexed =
263 blast_icache32_page_indexed;
264 } else if (ic_lsize == 64)
265 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
266}
267
268static void (* r4k_blast_icache)(void);
269
270static void __cpuinit r4k_blast_icache_setup(void)
271{
272 unsigned long ic_lsize = cpu_icache_line_size();
273
274 if (ic_lsize == 0)
275 r4k_blast_icache = (void *)cache_noop;
276 else if (ic_lsize == 16)
277 r4k_blast_icache = blast_icache16;
278 else if (ic_lsize == 32) {
279 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
280 r4k_blast_icache = blast_r4600_v1_icache32;
281 else if (TX49XX_ICACHE_INDEX_INV_WAR)
282 r4k_blast_icache = tx49_blast_icache32;
283 else
284 r4k_blast_icache = blast_icache32;
285 } else if (ic_lsize == 64)
286 r4k_blast_icache = blast_icache64;
287}
288
289static void (* r4k_blast_scache_page)(unsigned long addr);
290
291static void __cpuinit r4k_blast_scache_page_setup(void)
292{
293 unsigned long sc_lsize = cpu_scache_line_size();
294
295 if (scache_size == 0)
296 r4k_blast_scache_page = (void *)cache_noop;
297 else if (sc_lsize == 16)
298 r4k_blast_scache_page = blast_scache16_page;
299 else if (sc_lsize == 32)
300 r4k_blast_scache_page = blast_scache32_page;
301 else if (sc_lsize == 64)
302 r4k_blast_scache_page = blast_scache64_page;
303 else if (sc_lsize == 128)
304 r4k_blast_scache_page = blast_scache128_page;
305}
306
307static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
308
309static void __cpuinit r4k_blast_scache_page_indexed_setup(void)
310{
311 unsigned long sc_lsize = cpu_scache_line_size();
312
313 if (scache_size == 0)
314 r4k_blast_scache_page_indexed = (void *)cache_noop;
315 else if (sc_lsize == 16)
316 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
317 else if (sc_lsize == 32)
318 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
319 else if (sc_lsize == 64)
320 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
321 else if (sc_lsize == 128)
322 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
323}
324
325static void (* r4k_blast_scache)(void);
326
327static void __cpuinit r4k_blast_scache_setup(void)
328{
329 unsigned long sc_lsize = cpu_scache_line_size();
330
331 if (scache_size == 0)
332 r4k_blast_scache = (void *)cache_noop;
333 else if (sc_lsize == 16)
334 r4k_blast_scache = blast_scache16;
335 else if (sc_lsize == 32)
336 r4k_blast_scache = blast_scache32;
337 else if (sc_lsize == 64)
338 r4k_blast_scache = blast_scache64;
339 else if (sc_lsize == 128)
340 r4k_blast_scache = blast_scache128;
341}
342
343static inline void local_r4k___flush_cache_all(void * args)
344{
345#if defined(CONFIG_CPU_LOONGSON2)
346 r4k_blast_scache();
347 return;
348#endif
349 r4k_blast_dcache();
350 r4k_blast_icache();
351
352 switch (current_cpu_type()) {
353 case CPU_R4000SC:
354 case CPU_R4000MC:
355 case CPU_R4400SC:
356 case CPU_R4400MC:
357 case CPU_R10000:
358 case CPU_R12000:
359 case CPU_R14000:
360 r4k_blast_scache();
361 }
362}
363
364static void r4k___flush_cache_all(void)
365{
366 r4k_on_each_cpu(local_r4k___flush_cache_all, NULL);
367}
368
369static inline int has_valid_asid(const struct mm_struct *mm)
370{
371#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
372 int i;
373
374 for_each_online_cpu(i)
375 if (cpu_context(i, mm))
376 return 1;
377
378 return 0;
379#else
380 return cpu_context(smp_processor_id(), mm);
381#endif
382}
383
384static void r4k__flush_cache_vmap(void)
385{
386 r4k_blast_dcache();
387}
388
389static void r4k__flush_cache_vunmap(void)
390{
391 r4k_blast_dcache();
392}
393
394static inline void local_r4k_flush_cache_range(void * args)
395{
396 struct vm_area_struct *vma = args;
397 int exec = vma->vm_flags & VM_EXEC;
398
399 if (!(has_valid_asid(vma->vm_mm)))
400 return;
401
402 r4k_blast_dcache();
403 if (exec)
404 r4k_blast_icache();
405}
406
407static void r4k_flush_cache_range(struct vm_area_struct *vma,
408 unsigned long start, unsigned long end)
409{
410 int exec = vma->vm_flags & VM_EXEC;
411
412 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
413 r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
414}
415
416static inline void local_r4k_flush_cache_mm(void * args)
417{
418 struct mm_struct *mm = args;
419
420 if (!has_valid_asid(mm))
421 return;
422
423 /*
424 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
425 * only flush the primary caches but R10000 and R12000 behave sane ...
426 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
427 * caches, so we can bail out early.
428 */
429 if (current_cpu_type() == CPU_R4000SC ||
430 current_cpu_type() == CPU_R4000MC ||
431 current_cpu_type() == CPU_R4400SC ||
432 current_cpu_type() == CPU_R4400MC) {
433 r4k_blast_scache();
434 return;
435 }
436
437 r4k_blast_dcache();
438}
439
440static void r4k_flush_cache_mm(struct mm_struct *mm)
441{
442 if (!cpu_has_dc_aliases)
443 return;
444
445 r4k_on_each_cpu(local_r4k_flush_cache_mm, mm);
446}
447
448struct flush_cache_page_args {
449 struct vm_area_struct *vma;
450 unsigned long addr;
451 unsigned long pfn;
452};
453
454static inline void local_r4k_flush_cache_page(void *args)
455{
456 struct flush_cache_page_args *fcp_args = args;
457 struct vm_area_struct *vma = fcp_args->vma;
458 unsigned long addr = fcp_args->addr;
459 struct page *page = pfn_to_page(fcp_args->pfn);
460 int exec = vma->vm_flags & VM_EXEC;
461 struct mm_struct *mm = vma->vm_mm;
462 int map_coherent = 0;
463 pgd_t *pgdp;
464 pud_t *pudp;
465 pmd_t *pmdp;
466 pte_t *ptep;
467 void *vaddr;
468
469 /*
470 * If ownes no valid ASID yet, cannot possibly have gotten
471 * this page into the cache.
472 */
473 if (!has_valid_asid(mm))
474 return;
475
476 addr &= PAGE_MASK;
477 pgdp = pgd_offset(mm, addr);
478 pudp = pud_offset(pgdp, addr);
479 pmdp = pmd_offset(pudp, addr);
480 ptep = pte_offset(pmdp, addr);
481
482 /*
483 * If the page isn't marked valid, the page cannot possibly be
484 * in the cache.
485 */
486 if (!(pte_present(*ptep)))
487 return;
488
489 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
490 vaddr = NULL;
491 else {
492 /*
493 * Use kmap_coherent or kmap_atomic to do flushes for
494 * another ASID than the current one.
495 */
496 map_coherent = (cpu_has_dc_aliases &&
497 page_mapped(page) && !Page_dcache_dirty(page));
498 if (map_coherent)
499 vaddr = kmap_coherent(page, addr);
500 else
501 vaddr = kmap_atomic(page, KM_USER0);
502 addr = (unsigned long)vaddr;
503 }
504
505 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
506 r4k_blast_dcache_page(addr);
507 if (exec && !cpu_icache_snoops_remote_store)
508 r4k_blast_scache_page(addr);
509 }
510 if (exec) {
511 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
512 int cpu = smp_processor_id();
513
514 if (cpu_context(cpu, mm) != 0)
515 drop_mmu_context(mm, cpu);
516 } else
517 r4k_blast_icache_page(addr);
518 }
519
520 if (vaddr) {
521 if (map_coherent)
522 kunmap_coherent();
523 else
524 kunmap_atomic(vaddr, KM_USER0);
525 }
526}
527
528static void r4k_flush_cache_page(struct vm_area_struct *vma,
529 unsigned long addr, unsigned long pfn)
530{
531 struct flush_cache_page_args args;
532
533 args.vma = vma;
534 args.addr = addr;
535 args.pfn = pfn;
536
537 r4k_on_each_cpu(local_r4k_flush_cache_page, &args);
538}
539
540static inline void local_r4k_flush_data_cache_page(void * addr)
541{
542 r4k_blast_dcache_page((unsigned long) addr);
543}
544
545static void r4k_flush_data_cache_page(unsigned long addr)
546{
547 if (in_atomic())
548 local_r4k_flush_data_cache_page((void *)addr);
549 else
550 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
551}
552
553struct flush_icache_range_args {
554 unsigned long start;
555 unsigned long end;
556};
557
558static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end)
559{
560 if (!cpu_has_ic_fills_f_dc) {
561 if (end - start >= dcache_size) {
562 r4k_blast_dcache();
563 } else {
564 R4600_HIT_CACHEOP_WAR_IMPL;
565 protected_blast_dcache_range(start, end);
566 }
567 }
568
569 if (end - start > icache_size)
570 r4k_blast_icache();
571 else
572 protected_blast_icache_range(start, end);
573}
574
575static inline void local_r4k_flush_icache_range_ipi(void *args)
576{
577 struct flush_icache_range_args *fir_args = args;
578 unsigned long start = fir_args->start;
579 unsigned long end = fir_args->end;
580
581 local_r4k_flush_icache_range(start, end);
582}
583
584static void r4k_flush_icache_range(unsigned long start, unsigned long end)
585{
586 struct flush_icache_range_args args;
587
588 args.start = start;
589 args.end = end;
590
591 r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args);
592 instruction_hazard();
593}
594
595#ifdef CONFIG_DMA_NONCOHERENT
596
597static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
598{
599 /* Catch bad driver code */
600 BUG_ON(size == 0);
601
602 if (cpu_has_inclusive_pcaches) {
603 if (size >= scache_size)
604 r4k_blast_scache();
605 else
606 blast_scache_range(addr, addr + size);
607 __sync();
608 return;
609 }
610
611 /*
612 * Either no secondary cache or the available caches don't have the
613 * subset property so we have to flush the primary caches
614 * explicitly
615 */
616 if (cpu_has_safe_index_cacheops && size >= dcache_size) {
617 r4k_blast_dcache();
618 } else {
619 R4600_HIT_CACHEOP_WAR_IMPL;
620 blast_dcache_range(addr, addr + size);
621 }
622
623 bc_wback_inv(addr, size);
624 __sync();
625}
626
627static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
628{
629 /* Catch bad driver code */
630 BUG_ON(size == 0);
631
632 if (cpu_has_inclusive_pcaches) {
633 if (size >= scache_size)
634 r4k_blast_scache();
635 else {
636 unsigned long lsize = cpu_scache_line_size();
637 unsigned long almask = ~(lsize - 1);
638
639 /*
640 * There is no clearly documented alignment requirement
641 * for the cache instruction on MIPS processors and
642 * some processors, among them the RM5200 and RM7000
643 * QED processors will throw an address error for cache
644 * hit ops with insufficient alignment. Solved by
645 * aligning the address to cache line size.
646 */
647 cache_op(Hit_Writeback_Inv_SD, addr & almask);
648 cache_op(Hit_Writeback_Inv_SD,
649 (addr + size - 1) & almask);
650 blast_inv_scache_range(addr, addr + size);
651 }
652 __sync();
653 return;
654 }
655
656 if (cpu_has_safe_index_cacheops && size >= dcache_size) {
657 r4k_blast_dcache();
658 } else {
659 unsigned long lsize = cpu_dcache_line_size();
660 unsigned long almask = ~(lsize - 1);
661
662 R4600_HIT_CACHEOP_WAR_IMPL;
663 cache_op(Hit_Writeback_Inv_D, addr & almask);
664 cache_op(Hit_Writeback_Inv_D, (addr + size - 1) & almask);
665 blast_inv_dcache_range(addr, addr + size);
666 }
667
668 bc_inv(addr, size);
669 __sync();
670}
671#endif /* CONFIG_DMA_NONCOHERENT */
672
673/*
674 * While we're protected against bad userland addresses we don't care
675 * very much about what happens in that case. Usually a segmentation
676 * fault will dump the process later on anyway ...
677 */
678static void local_r4k_flush_cache_sigtramp(void * arg)
679{
680 unsigned long ic_lsize = cpu_icache_line_size();
681 unsigned long dc_lsize = cpu_dcache_line_size();
682 unsigned long sc_lsize = cpu_scache_line_size();
683 unsigned long addr = (unsigned long) arg;
684
685 R4600_HIT_CACHEOP_WAR_IMPL;
686 if (dc_lsize)
687 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
688 if (!cpu_icache_snoops_remote_store && scache_size)
689 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
690 if (ic_lsize)
691 protected_flush_icache_line(addr & ~(ic_lsize - 1));
692 if (MIPS4K_ICACHE_REFILL_WAR) {
693 __asm__ __volatile__ (
694 ".set push\n\t"
695 ".set noat\n\t"
696 ".set mips3\n\t"
697#ifdef CONFIG_32BIT
698 "la $at,1f\n\t"
699#endif
700#ifdef CONFIG_64BIT
701 "dla $at,1f\n\t"
702#endif
703 "cache %0,($at)\n\t"
704 "nop; nop; nop\n"
705 "1:\n\t"
706 ".set pop"
707 :
708 : "i" (Hit_Invalidate_I));
709 }
710 if (MIPS_CACHE_SYNC_WAR)
711 __asm__ __volatile__ ("sync");
712}
713
714static void r4k_flush_cache_sigtramp(unsigned long addr)
715{
716 r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
717}
718
719static void r4k_flush_icache_all(void)
720{
721 if (cpu_has_vtag_icache)
722 r4k_blast_icache();
723}
724
725static inline void rm7k_erratum31(void)
726{
727 const unsigned long ic_lsize = 32;
728 unsigned long addr;
729
730 /* RM7000 erratum #31. The icache is screwed at startup. */
731 write_c0_taglo(0);
732 write_c0_taghi(0);
733
734 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
735 __asm__ __volatile__ (
736 ".set push\n\t"
737 ".set noreorder\n\t"
738 ".set mips3\n\t"
739 "cache\t%1, 0(%0)\n\t"
740 "cache\t%1, 0x1000(%0)\n\t"
741 "cache\t%1, 0x2000(%0)\n\t"
742 "cache\t%1, 0x3000(%0)\n\t"
743 "cache\t%2, 0(%0)\n\t"
744 "cache\t%2, 0x1000(%0)\n\t"
745 "cache\t%2, 0x2000(%0)\n\t"
746 "cache\t%2, 0x3000(%0)\n\t"
747 "cache\t%1, 0(%0)\n\t"
748 "cache\t%1, 0x1000(%0)\n\t"
749 "cache\t%1, 0x2000(%0)\n\t"
750 "cache\t%1, 0x3000(%0)\n\t"
751 ".set pop\n"
752 :
753 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
754 }
755}
756
757static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way",
758 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
759};
760
761static void __cpuinit probe_pcache(void)
762{
763 struct cpuinfo_mips *c = ¤t_cpu_data;
764 unsigned int config = read_c0_config();
765 unsigned int prid = read_c0_prid();
766 unsigned long config1;
767 unsigned int lsize;
768
769 switch (c->cputype) {
770 case CPU_R4600: /* QED style two way caches? */
771 case CPU_R4700:
772 case CPU_R5000:
773 case CPU_NEVADA:
774 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
775 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
776 c->icache.ways = 2;
777 c->icache.waybit = __ffs(icache_size/2);
778
779 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
780 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
781 c->dcache.ways = 2;
782 c->dcache.waybit= __ffs(dcache_size/2);
783
784 c->options |= MIPS_CPU_CACHE_CDEX_P;
785 break;
786
787 case CPU_R5432:
788 case CPU_R5500:
789 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
790 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
791 c->icache.ways = 2;
792 c->icache.waybit= 0;
793
794 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
795 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
796 c->dcache.ways = 2;
797 c->dcache.waybit = 0;
798
799 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
800 break;
801
802 case CPU_TX49XX:
803 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
804 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
805 c->icache.ways = 4;
806 c->icache.waybit= 0;
807
808 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
809 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
810 c->dcache.ways = 4;
811 c->dcache.waybit = 0;
812
813 c->options |= MIPS_CPU_CACHE_CDEX_P;
814 c->options |= MIPS_CPU_PREFETCH;
815 break;
816
817 case CPU_R4000PC:
818 case CPU_R4000SC:
819 case CPU_R4000MC:
820 case CPU_R4400PC:
821 case CPU_R4400SC:
822 case CPU_R4400MC:
823 case CPU_R4300:
824 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
825 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
826 c->icache.ways = 1;
827 c->icache.waybit = 0; /* doesn't matter */
828
829 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
830 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
831 c->dcache.ways = 1;
832 c->dcache.waybit = 0; /* does not matter */
833
834 c->options |= MIPS_CPU_CACHE_CDEX_P;
835 break;
836
837 case CPU_R10000:
838 case CPU_R12000:
839 case CPU_R14000:
840 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
841 c->icache.linesz = 64;
842 c->icache.ways = 2;
843 c->icache.waybit = 0;
844
845 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
846 c->dcache.linesz = 32;
847 c->dcache.ways = 2;
848 c->dcache.waybit = 0;
849
850 c->options |= MIPS_CPU_PREFETCH;
851 break;
852
853 case CPU_VR4133:
854 write_c0_config(config & ~VR41_CONF_P4K);
855 case CPU_VR4131:
856 /* Workaround for cache instruction bug of VR4131 */
857 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
858 c->processor_id == 0x0c82U) {
859 config |= 0x00400000U;
860 if (c->processor_id == 0x0c80U)
861 config |= VR41_CONF_BP;
862 write_c0_config(config);
863 } else
864 c->options |= MIPS_CPU_CACHE_CDEX_P;
865
866 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
867 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
868 c->icache.ways = 2;
869 c->icache.waybit = __ffs(icache_size/2);
870
871 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
872 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
873 c->dcache.ways = 2;
874 c->dcache.waybit = __ffs(dcache_size/2);
875 break;
876
877 case CPU_VR41XX:
878 case CPU_VR4111:
879 case CPU_VR4121:
880 case CPU_VR4122:
881 case CPU_VR4181:
882 case CPU_VR4181A:
883 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
884 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
885 c->icache.ways = 1;
886 c->icache.waybit = 0; /* doesn't matter */
887
888 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
889 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
890 c->dcache.ways = 1;
891 c->dcache.waybit = 0; /* does not matter */
892
893 c->options |= MIPS_CPU_CACHE_CDEX_P;
894 break;
895
896 case CPU_RM7000:
897 rm7k_erratum31();
898
899 case CPU_RM9000:
900 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
901 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
902 c->icache.ways = 4;
903 c->icache.waybit = __ffs(icache_size / c->icache.ways);
904
905 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
906 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
907 c->dcache.ways = 4;
908 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
909
910#if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
911 c->options |= MIPS_CPU_CACHE_CDEX_P;
912#endif
913 c->options |= MIPS_CPU_PREFETCH;
914 break;
915
916 case CPU_LOONGSON2:
917 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
918 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
919 if (prid & 0x3)
920 c->icache.ways = 4;
921 else
922 c->icache.ways = 2;
923 c->icache.waybit = 0;
924
925 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
926 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
927 if (prid & 0x3)
928 c->dcache.ways = 4;
929 else
930 c->dcache.ways = 2;
931 c->dcache.waybit = 0;
932 break;
933
934 default:
935 if (!(config & MIPS_CONF_M))
936 panic("Don't know how to probe P-caches on this cpu.");
937
938 /*
939 * So we seem to be a MIPS32 or MIPS64 CPU
940 * So let's probe the I-cache ...
941 */
942 config1 = read_c0_config1();
943
944 if ((lsize = ((config1 >> 19) & 7)))
945 c->icache.linesz = 2 << lsize;
946 else
947 c->icache.linesz = lsize;
948 c->icache.sets = 64 << ((config1 >> 22) & 7);
949 c->icache.ways = 1 + ((config1 >> 16) & 7);
950
951 icache_size = c->icache.sets *
952 c->icache.ways *
953 c->icache.linesz;
954 c->icache.waybit = __ffs(icache_size/c->icache.ways);
955
956 if (config & 0x8) /* VI bit */
957 c->icache.flags |= MIPS_CACHE_VTAG;
958
959 /*
960 * Now probe the MIPS32 / MIPS64 data cache.
961 */
962 c->dcache.flags = 0;
963
964 if ((lsize = ((config1 >> 10) & 7)))
965 c->dcache.linesz = 2 << lsize;
966 else
967 c->dcache.linesz= lsize;
968 c->dcache.sets = 64 << ((config1 >> 13) & 7);
969 c->dcache.ways = 1 + ((config1 >> 7) & 7);
970
971 dcache_size = c->dcache.sets *
972 c->dcache.ways *
973 c->dcache.linesz;
974 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
975
976 c->options |= MIPS_CPU_PREFETCH;
977 break;
978 }
979
980 /*
981 * Processor configuration sanity check for the R4000SC erratum
982 * #5. With page sizes larger than 32kB there is no possibility
983 * to get a VCE exception anymore so we don't care about this
984 * misconfiguration. The case is rather theoretical anyway;
985 * presumably no vendor is shipping his hardware in the "bad"
986 * configuration.
987 */
988 if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
989 !(config & CONF_SC) && c->icache.linesz != 16 &&
990 PAGE_SIZE <= 0x8000)
991 panic("Improper R4000SC processor configuration detected");
992
993 /* compute a couple of other cache variables */
994 c->icache.waysize = icache_size / c->icache.ways;
995 c->dcache.waysize = dcache_size / c->dcache.ways;
996
997 c->icache.sets = c->icache.linesz ?
998 icache_size / (c->icache.linesz * c->icache.ways) : 0;
999 c->dcache.sets = c->dcache.linesz ?
1000 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1001
1002 /*
1003 * R10000 and R12000 P-caches are odd in a positive way. They're 32kB
1004 * 2-way virtually indexed so normally would suffer from aliases. So
1005 * normally they'd suffer from aliases but magic in the hardware deals
1006 * with that for us so we don't need to take care ourselves.
1007 */
1008 switch (c->cputype) {
1009 case CPU_20KC:
1010 case CPU_25KF:
1011 case CPU_SB1:
1012 case CPU_SB1A:
1013 case CPU_XLR:
1014 c->dcache.flags |= MIPS_CACHE_PINDEX;
1015 break;
1016
1017 case CPU_R10000:
1018 case CPU_R12000:
1019 case CPU_R14000:
1020 break;
1021
1022 case CPU_24K:
1023 case CPU_34K:
1024 case CPU_74K:
1025 case CPU_1004K:
1026 if ((read_c0_config7() & (1 << 16))) {
1027 /* effectively physically indexed dcache,
1028 thus no virtual aliases. */
1029 c->dcache.flags |= MIPS_CACHE_PINDEX;
1030 break;
1031 }
1032 default:
1033 if (c->dcache.waysize > PAGE_SIZE)
1034 c->dcache.flags |= MIPS_CACHE_ALIASES;
1035 }
1036
1037 switch (c->cputype) {
1038 case CPU_20KC:
1039 /*
1040 * Some older 20Kc chips doesn't have the 'VI' bit in
1041 * the config register.
1042 */
1043 c->icache.flags |= MIPS_CACHE_VTAG;
1044 break;
1045
1046 case CPU_ALCHEMY:
1047 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1048 break;
1049 }
1050
1051#ifdef CONFIG_CPU_LOONGSON2
1052 /*
1053 * LOONGSON2 has 4 way icache, but when using indexed cache op,
1054 * one op will act on all 4 ways
1055 */
1056 c->icache.ways = 1;
1057#endif
1058
1059 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1060 icache_size >> 10,
1061 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1062 way_string[c->icache.ways], c->icache.linesz);
1063
1064 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1065 dcache_size >> 10, way_string[c->dcache.ways],
1066 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1067 (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1068 "cache aliases" : "no aliases",
1069 c->dcache.linesz);
1070}
1071
1072/*
1073 * If you even _breathe_ on this function, look at the gcc output and make sure
1074 * it does not pop things on and off the stack for the cache sizing loop that
1075 * executes in KSEG1 space or else you will crash and burn badly. You have
1076 * been warned.
1077 */
1078static int __cpuinit probe_scache(void)
1079{
1080 unsigned long flags, addr, begin, end, pow2;
1081 unsigned int config = read_c0_config();
1082 struct cpuinfo_mips *c = ¤t_cpu_data;
1083
1084 if (config & CONF_SC)
1085 return 0;
1086
1087 begin = (unsigned long) &_stext;
1088 begin &= ~((4 * 1024 * 1024) - 1);
1089 end = begin + (4 * 1024 * 1024);
1090
1091 /*
1092 * This is such a bitch, you'd think they would make it easy to do
1093 * this. Away you daemons of stupidity!
1094 */
1095 local_irq_save(flags);
1096
1097 /* Fill each size-multiple cache line with a valid tag. */
1098 pow2 = (64 * 1024);
1099 for (addr = begin; addr < end; addr = (begin + pow2)) {
1100 unsigned long *p = (unsigned long *) addr;
1101 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1102 pow2 <<= 1;
1103 }
1104
1105 /* Load first line with zero (therefore invalid) tag. */
1106 write_c0_taglo(0);
1107 write_c0_taghi(0);
1108 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1109 cache_op(Index_Store_Tag_I, begin);
1110 cache_op(Index_Store_Tag_D, begin);
1111 cache_op(Index_Store_Tag_SD, begin);
1112
1113 /* Now search for the wrap around point. */
1114 pow2 = (128 * 1024);
1115 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1116 cache_op(Index_Load_Tag_SD, addr);
1117 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1118 if (!read_c0_taglo())
1119 break;
1120 pow2 <<= 1;
1121 }
1122 local_irq_restore(flags);
1123 addr -= begin;
1124
1125 scache_size = addr;
1126 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1127 c->scache.ways = 1;
1128 c->dcache.waybit = 0; /* does not matter */
1129
1130 return 1;
1131}
1132
1133#if defined(CONFIG_CPU_LOONGSON2)
1134static void __init loongson2_sc_init(void)
1135{
1136 struct cpuinfo_mips *c = ¤t_cpu_data;
1137
1138 scache_size = 512*1024;
1139 c->scache.linesz = 32;
1140 c->scache.ways = 4;
1141 c->scache.waybit = 0;
1142 c->scache.waysize = scache_size / (c->scache.ways);
1143 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1144 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1145 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1146
1147 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1148}
1149#endif
1150
1151extern int r5k_sc_init(void);
1152extern int rm7k_sc_init(void);
1153extern int mips_sc_init(void);
1154
1155static void __cpuinit setup_scache(void)
1156{
1157 struct cpuinfo_mips *c = ¤t_cpu_data;
1158 unsigned int config = read_c0_config();
1159 int sc_present = 0;
1160
1161 /*
1162 * Do the probing thing on R4000SC and R4400SC processors. Other
1163 * processors don't have a S-cache that would be relevant to the
1164 * Linux memory management.
1165 */
1166 switch (c->cputype) {
1167 case CPU_R4000SC:
1168 case CPU_R4000MC:
1169 case CPU_R4400SC:
1170 case CPU_R4400MC:
1171 sc_present = run_uncached(probe_scache);
1172 if (sc_present)
1173 c->options |= MIPS_CPU_CACHE_CDEX_S;
1174 break;
1175
1176 case CPU_R10000:
1177 case CPU_R12000:
1178 case CPU_R14000:
1179 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1180 c->scache.linesz = 64 << ((config >> 13) & 1);
1181 c->scache.ways = 2;
1182 c->scache.waybit= 0;
1183 sc_present = 1;
1184 break;
1185
1186 case CPU_R5000:
1187 case CPU_NEVADA:
1188#ifdef CONFIG_R5000_CPU_SCACHE
1189 r5k_sc_init();
1190#endif
1191 return;
1192
1193 case CPU_RM7000:
1194 case CPU_RM9000:
1195#ifdef CONFIG_RM7000_CPU_SCACHE
1196 rm7k_sc_init();
1197#endif
1198 return;
1199
1200#if defined(CONFIG_CPU_LOONGSON2)
1201 case CPU_LOONGSON2:
1202 loongson2_sc_init();
1203 return;
1204#endif
1205
1206 default:
1207 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1208 c->isa_level == MIPS_CPU_ISA_M32R2 ||
1209 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1210 c->isa_level == MIPS_CPU_ISA_M64R2) {
1211#ifdef CONFIG_MIPS_CPU_SCACHE
1212 if (mips_sc_init ()) {
1213 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1214 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1215 scache_size >> 10,
1216 way_string[c->scache.ways], c->scache.linesz);
1217 }
1218#else
1219 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1220 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1221#endif
1222 return;
1223 }
1224 sc_present = 0;
1225 }
1226
1227 if (!sc_present)
1228 return;
1229
1230 /* compute a couple of other cache variables */
1231 c->scache.waysize = scache_size / c->scache.ways;
1232
1233 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1234
1235 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1236 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1237
1238 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1239}
1240
1241void au1x00_fixup_config_od(void)
1242{
1243 /*
1244 * c0_config.od (bit 19) was write only (and read as 0)
1245 * on the early revisions of Alchemy SOCs. It disables the bus
1246 * transaction overlapping and needs to be set to fix various errata.
1247 */
1248 switch (read_c0_prid()) {
1249 case 0x00030100: /* Au1000 DA */
1250 case 0x00030201: /* Au1000 HA */
1251 case 0x00030202: /* Au1000 HB */
1252 case 0x01030200: /* Au1500 AB */
1253 /*
1254 * Au1100 errata actually keeps silence about this bit, so we set it
1255 * just in case for those revisions that require it to be set according
1256 * to the (now gone) cpu table.
1257 */
1258 case 0x02030200: /* Au1100 AB */
1259 case 0x02030201: /* Au1100 BA */
1260 case 0x02030202: /* Au1100 BC */
1261 set_c0_config(1 << 19);
1262 break;
1263 }
1264}
1265
1266/* CP0 hazard avoidance. */
1267#define NXP_BARRIER() \
1268 __asm__ __volatile__( \
1269 ".set noreorder\n\t" \
1270 "nop; nop; nop; nop; nop; nop;\n\t" \
1271 ".set reorder\n\t")
1272
1273static void nxp_pr4450_fixup_config(void)
1274{
1275 unsigned long config0;
1276
1277 config0 = read_c0_config();
1278
1279 /* clear all three cache coherency fields */
1280 config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1281 config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) |
1282 ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1283 ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1284 write_c0_config(config0);
1285 NXP_BARRIER();
1286}
1287
1288static int __cpuinitdata cca = -1;
1289
1290static int __init cca_setup(char *str)
1291{
1292 get_option(&str, &cca);
1293
1294 return 1;
1295}
1296
1297__setup("cca=", cca_setup);
1298
1299static void __cpuinit coherency_setup(void)
1300{
1301 if (cca < 0 || cca > 7)
1302 cca = read_c0_config() & CONF_CM_CMASK;
1303 _page_cachable_default = cca << _CACHE_SHIFT;
1304
1305 pr_debug("Using cache attribute %d\n", cca);
1306 change_c0_config(CONF_CM_CMASK, cca);
1307
1308 /*
1309 * c0_status.cu=0 specifies that updates by the sc instruction use
1310 * the coherency mode specified by the TLB; 1 means cachable
1311 * coherent update on write will be used. Not all processors have
1312 * this bit and; some wire it to zero, others like Toshiba had the
1313 * silly idea of putting something else there ...
1314 */
1315 switch (current_cpu_type()) {
1316 case CPU_R4000PC:
1317 case CPU_R4000SC:
1318 case CPU_R4000MC:
1319 case CPU_R4400PC:
1320 case CPU_R4400SC:
1321 case CPU_R4400MC:
1322 clear_c0_config(CONF_CU);
1323 break;
1324 /*
1325 * We need to catch the early Alchemy SOCs with
1326 * the write-only co_config.od bit and set it back to one on:
1327 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
1328 */
1329 case CPU_ALCHEMY:
1330 au1x00_fixup_config_od();
1331 break;
1332
1333 case PRID_IMP_PR4450:
1334 nxp_pr4450_fixup_config();
1335 break;
1336 }
1337}
1338
1339#if defined(CONFIG_DMA_NONCOHERENT)
1340
1341static int __cpuinitdata coherentio;
1342
1343static int __init setcoherentio(char *str)
1344{
1345 coherentio = 1;
1346
1347 return 1;
1348}
1349
1350__setup("coherentio", setcoherentio);
1351#endif
1352
1353void __cpuinit r4k_cache_init(void)
1354{
1355 extern void build_clear_page(void);
1356 extern void build_copy_page(void);
1357 extern char __weak except_vec2_generic;
1358 extern char __weak except_vec2_sb1;
1359 struct cpuinfo_mips *c = ¤t_cpu_data;
1360
1361 switch (c->cputype) {
1362 case CPU_SB1:
1363 case CPU_SB1A:
1364 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1365 break;
1366
1367 default:
1368 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1369 break;
1370 }
1371
1372 probe_pcache();
1373 setup_scache();
1374
1375 r4k_blast_dcache_page_setup();
1376 r4k_blast_dcache_page_indexed_setup();
1377 r4k_blast_dcache_setup();
1378 r4k_blast_icache_page_setup();
1379 r4k_blast_icache_page_indexed_setup();
1380 r4k_blast_icache_setup();
1381 r4k_blast_scache_page_setup();
1382 r4k_blast_scache_page_indexed_setup();
1383 r4k_blast_scache_setup();
1384
1385 /*
1386 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1387 * This code supports virtually indexed processors and will be
1388 * unnecessarily inefficient on physically indexed processors.
1389 */
1390 if (c->dcache.linesz)
1391 shm_align_mask = max_t( unsigned long,
1392 c->dcache.sets * c->dcache.linesz - 1,
1393 PAGE_SIZE - 1);
1394 else
1395 shm_align_mask = PAGE_SIZE-1;
1396
1397 __flush_cache_vmap = r4k__flush_cache_vmap;
1398 __flush_cache_vunmap = r4k__flush_cache_vunmap;
1399
1400 flush_cache_all = cache_noop;
1401 __flush_cache_all = r4k___flush_cache_all;
1402 flush_cache_mm = r4k_flush_cache_mm;
1403 flush_cache_page = r4k_flush_cache_page;
1404 flush_cache_range = r4k_flush_cache_range;
1405
1406 flush_cache_sigtramp = r4k_flush_cache_sigtramp;
1407 flush_icache_all = r4k_flush_icache_all;
1408 local_flush_data_cache_page = local_r4k_flush_data_cache_page;
1409 flush_data_cache_page = r4k_flush_data_cache_page;
1410 flush_icache_range = r4k_flush_icache_range;
1411 local_flush_icache_range = local_r4k_flush_icache_range;
1412
1413#if defined(CONFIG_DMA_NONCOHERENT)
1414 if (coherentio) {
1415 _dma_cache_wback_inv = (void *)cache_noop;
1416 _dma_cache_wback = (void *)cache_noop;
1417 _dma_cache_inv = (void *)cache_noop;
1418 } else {
1419 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1420 _dma_cache_wback = r4k_dma_cache_wback_inv;
1421 _dma_cache_inv = r4k_dma_cache_inv;
1422 }
1423#endif
1424
1425 build_clear_page();
1426 build_copy_page();
1427#if !defined(CONFIG_MIPS_CMP)
1428 local_r4k___flush_cache_all(NULL);
1429#endif
1430 coherency_setup();
1431}
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 */
10#include <linux/cpu_pm.h>
11#include <linux/hardirq.h>
12#include <linux/init.h>
13#include <linux/highmem.h>
14#include <linux/kernel.h>
15#include <linux/linkage.h>
16#include <linux/preempt.h>
17#include <linux/sched.h>
18#include <linux/smp.h>
19#include <linux/mm.h>
20#include <linux/module.h>
21#include <linux/bitops.h>
22
23#include <asm/bcache.h>
24#include <asm/bootinfo.h>
25#include <asm/cache.h>
26#include <asm/cacheops.h>
27#include <asm/cpu.h>
28#include <asm/cpu-features.h>
29#include <asm/cpu-type.h>
30#include <asm/io.h>
31#include <asm/page.h>
32#include <asm/pgtable.h>
33#include <asm/r4kcache.h>
34#include <asm/sections.h>
35#include <asm/mmu_context.h>
36#include <asm/war.h>
37#include <asm/cacheflush.h> /* for run_uncached() */
38#include <asm/traps.h>
39#include <asm/dma-coherence.h>
40#include <asm/mips-cm.h>
41
42/*
43 * Special Variant of smp_call_function for use by cache functions:
44 *
45 * o No return value
46 * o collapses to normal function call on UP kernels
47 * o collapses to normal function call on systems with a single shared
48 * primary cache.
49 * o doesn't disable interrupts on the local CPU
50 */
51static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
52{
53 preempt_disable();
54
55 /*
56 * The Coherent Manager propagates address-based cache ops to other
57 * cores but not index-based ops. However, r4k_on_each_cpu is used
58 * in both cases so there is no easy way to tell what kind of op is
59 * executed to the other cores. The best we can probably do is
60 * to restrict that call when a CM is not present because both
61 * CM-based SMP protocols (CMP & CPS) restrict index-based cache ops.
62 */
63 if (!mips_cm_present())
64 smp_call_function_many(&cpu_foreign_map, func, info, 1);
65 func(info);
66 preempt_enable();
67}
68
69#if defined(CONFIG_MIPS_CMP) || defined(CONFIG_MIPS_CPS)
70#define cpu_has_safe_index_cacheops 0
71#else
72#define cpu_has_safe_index_cacheops 1
73#endif
74
75/*
76 * Must die.
77 */
78static unsigned long icache_size __read_mostly;
79static unsigned long dcache_size __read_mostly;
80static unsigned long scache_size __read_mostly;
81
82/*
83 * Dummy cache handling routines for machines without boardcaches
84 */
85static void cache_noop(void) {}
86
87static struct bcache_ops no_sc_ops = {
88 .bc_enable = (void *)cache_noop,
89 .bc_disable = (void *)cache_noop,
90 .bc_wback_inv = (void *)cache_noop,
91 .bc_inv = (void *)cache_noop
92};
93
94struct bcache_ops *bcops = &no_sc_ops;
95
96#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
97#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
98
99#define R4600_HIT_CACHEOP_WAR_IMPL \
100do { \
101 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
102 *(volatile unsigned long *)CKSEG1; \
103 if (R4600_V1_HIT_CACHEOP_WAR) \
104 __asm__ __volatile__("nop;nop;nop;nop"); \
105} while (0)
106
107static void (*r4k_blast_dcache_page)(unsigned long addr);
108
109static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
110{
111 R4600_HIT_CACHEOP_WAR_IMPL;
112 blast_dcache32_page(addr);
113}
114
115static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
116{
117 blast_dcache64_page(addr);
118}
119
120static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
121{
122 blast_dcache128_page(addr);
123}
124
125static void r4k_blast_dcache_page_setup(void)
126{
127 unsigned long dc_lsize = cpu_dcache_line_size();
128
129 switch (dc_lsize) {
130 case 0:
131 r4k_blast_dcache_page = (void *)cache_noop;
132 break;
133 case 16:
134 r4k_blast_dcache_page = blast_dcache16_page;
135 break;
136 case 32:
137 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
138 break;
139 case 64:
140 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
141 break;
142 case 128:
143 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
144 break;
145 default:
146 break;
147 }
148}
149
150#ifndef CONFIG_EVA
151#define r4k_blast_dcache_user_page r4k_blast_dcache_page
152#else
153
154static void (*r4k_blast_dcache_user_page)(unsigned long addr);
155
156static void r4k_blast_dcache_user_page_setup(void)
157{
158 unsigned long dc_lsize = cpu_dcache_line_size();
159
160 if (dc_lsize == 0)
161 r4k_blast_dcache_user_page = (void *)cache_noop;
162 else if (dc_lsize == 16)
163 r4k_blast_dcache_user_page = blast_dcache16_user_page;
164 else if (dc_lsize == 32)
165 r4k_blast_dcache_user_page = blast_dcache32_user_page;
166 else if (dc_lsize == 64)
167 r4k_blast_dcache_user_page = blast_dcache64_user_page;
168}
169
170#endif
171
172static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
173
174static void r4k_blast_dcache_page_indexed_setup(void)
175{
176 unsigned long dc_lsize = cpu_dcache_line_size();
177
178 if (dc_lsize == 0)
179 r4k_blast_dcache_page_indexed = (void *)cache_noop;
180 else if (dc_lsize == 16)
181 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
182 else if (dc_lsize == 32)
183 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
184 else if (dc_lsize == 64)
185 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
186 else if (dc_lsize == 128)
187 r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;
188}
189
190void (* r4k_blast_dcache)(void);
191EXPORT_SYMBOL(r4k_blast_dcache);
192
193static void r4k_blast_dcache_setup(void)
194{
195 unsigned long dc_lsize = cpu_dcache_line_size();
196
197 if (dc_lsize == 0)
198 r4k_blast_dcache = (void *)cache_noop;
199 else if (dc_lsize == 16)
200 r4k_blast_dcache = blast_dcache16;
201 else if (dc_lsize == 32)
202 r4k_blast_dcache = blast_dcache32;
203 else if (dc_lsize == 64)
204 r4k_blast_dcache = blast_dcache64;
205 else if (dc_lsize == 128)
206 r4k_blast_dcache = blast_dcache128;
207}
208
209/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
210#define JUMP_TO_ALIGN(order) \
211 __asm__ __volatile__( \
212 "b\t1f\n\t" \
213 ".align\t" #order "\n\t" \
214 "1:\n\t" \
215 )
216#define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
217#define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
218
219static inline void blast_r4600_v1_icache32(void)
220{
221 unsigned long flags;
222
223 local_irq_save(flags);
224 blast_icache32();
225 local_irq_restore(flags);
226}
227
228static inline void tx49_blast_icache32(void)
229{
230 unsigned long start = INDEX_BASE;
231 unsigned long end = start + current_cpu_data.icache.waysize;
232 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
233 unsigned long ws_end = current_cpu_data.icache.ways <<
234 current_cpu_data.icache.waybit;
235 unsigned long ws, addr;
236
237 CACHE32_UNROLL32_ALIGN2;
238 /* I'm in even chunk. blast odd chunks */
239 for (ws = 0; ws < ws_end; ws += ws_inc)
240 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
241 cache32_unroll32(addr|ws, Index_Invalidate_I);
242 CACHE32_UNROLL32_ALIGN;
243 /* I'm in odd chunk. blast even chunks */
244 for (ws = 0; ws < ws_end; ws += ws_inc)
245 for (addr = start; addr < end; addr += 0x400 * 2)
246 cache32_unroll32(addr|ws, Index_Invalidate_I);
247}
248
249static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
250{
251 unsigned long flags;
252
253 local_irq_save(flags);
254 blast_icache32_page_indexed(page);
255 local_irq_restore(flags);
256}
257
258static inline void tx49_blast_icache32_page_indexed(unsigned long page)
259{
260 unsigned long indexmask = current_cpu_data.icache.waysize - 1;
261 unsigned long start = INDEX_BASE + (page & indexmask);
262 unsigned long end = start + PAGE_SIZE;
263 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
264 unsigned long ws_end = current_cpu_data.icache.ways <<
265 current_cpu_data.icache.waybit;
266 unsigned long ws, addr;
267
268 CACHE32_UNROLL32_ALIGN2;
269 /* I'm in even chunk. blast odd chunks */
270 for (ws = 0; ws < ws_end; ws += ws_inc)
271 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
272 cache32_unroll32(addr|ws, Index_Invalidate_I);
273 CACHE32_UNROLL32_ALIGN;
274 /* I'm in odd chunk. blast even chunks */
275 for (ws = 0; ws < ws_end; ws += ws_inc)
276 for (addr = start; addr < end; addr += 0x400 * 2)
277 cache32_unroll32(addr|ws, Index_Invalidate_I);
278}
279
280static void (* r4k_blast_icache_page)(unsigned long addr);
281
282static void r4k_blast_icache_page_setup(void)
283{
284 unsigned long ic_lsize = cpu_icache_line_size();
285
286 if (ic_lsize == 0)
287 r4k_blast_icache_page = (void *)cache_noop;
288 else if (ic_lsize == 16)
289 r4k_blast_icache_page = blast_icache16_page;
290 else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2)
291 r4k_blast_icache_page = loongson2_blast_icache32_page;
292 else if (ic_lsize == 32)
293 r4k_blast_icache_page = blast_icache32_page;
294 else if (ic_lsize == 64)
295 r4k_blast_icache_page = blast_icache64_page;
296 else if (ic_lsize == 128)
297 r4k_blast_icache_page = blast_icache128_page;
298}
299
300#ifndef CONFIG_EVA
301#define r4k_blast_icache_user_page r4k_blast_icache_page
302#else
303
304static void (*r4k_blast_icache_user_page)(unsigned long addr);
305
306static void r4k_blast_icache_user_page_setup(void)
307{
308 unsigned long ic_lsize = cpu_icache_line_size();
309
310 if (ic_lsize == 0)
311 r4k_blast_icache_user_page = (void *)cache_noop;
312 else if (ic_lsize == 16)
313 r4k_blast_icache_user_page = blast_icache16_user_page;
314 else if (ic_lsize == 32)
315 r4k_blast_icache_user_page = blast_icache32_user_page;
316 else if (ic_lsize == 64)
317 r4k_blast_icache_user_page = blast_icache64_user_page;
318}
319
320#endif
321
322static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
323
324static void r4k_blast_icache_page_indexed_setup(void)
325{
326 unsigned long ic_lsize = cpu_icache_line_size();
327
328 if (ic_lsize == 0)
329 r4k_blast_icache_page_indexed = (void *)cache_noop;
330 else if (ic_lsize == 16)
331 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
332 else if (ic_lsize == 32) {
333 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
334 r4k_blast_icache_page_indexed =
335 blast_icache32_r4600_v1_page_indexed;
336 else if (TX49XX_ICACHE_INDEX_INV_WAR)
337 r4k_blast_icache_page_indexed =
338 tx49_blast_icache32_page_indexed;
339 else if (current_cpu_type() == CPU_LOONGSON2)
340 r4k_blast_icache_page_indexed =
341 loongson2_blast_icache32_page_indexed;
342 else
343 r4k_blast_icache_page_indexed =
344 blast_icache32_page_indexed;
345 } else if (ic_lsize == 64)
346 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
347}
348
349void (* r4k_blast_icache)(void);
350EXPORT_SYMBOL(r4k_blast_icache);
351
352static void r4k_blast_icache_setup(void)
353{
354 unsigned long ic_lsize = cpu_icache_line_size();
355
356 if (ic_lsize == 0)
357 r4k_blast_icache = (void *)cache_noop;
358 else if (ic_lsize == 16)
359 r4k_blast_icache = blast_icache16;
360 else if (ic_lsize == 32) {
361 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
362 r4k_blast_icache = blast_r4600_v1_icache32;
363 else if (TX49XX_ICACHE_INDEX_INV_WAR)
364 r4k_blast_icache = tx49_blast_icache32;
365 else if (current_cpu_type() == CPU_LOONGSON2)
366 r4k_blast_icache = loongson2_blast_icache32;
367 else
368 r4k_blast_icache = blast_icache32;
369 } else if (ic_lsize == 64)
370 r4k_blast_icache = blast_icache64;
371 else if (ic_lsize == 128)
372 r4k_blast_icache = blast_icache128;
373}
374
375static void (* r4k_blast_scache_page)(unsigned long addr);
376
377static void r4k_blast_scache_page_setup(void)
378{
379 unsigned long sc_lsize = cpu_scache_line_size();
380
381 if (scache_size == 0)
382 r4k_blast_scache_page = (void *)cache_noop;
383 else if (sc_lsize == 16)
384 r4k_blast_scache_page = blast_scache16_page;
385 else if (sc_lsize == 32)
386 r4k_blast_scache_page = blast_scache32_page;
387 else if (sc_lsize == 64)
388 r4k_blast_scache_page = blast_scache64_page;
389 else if (sc_lsize == 128)
390 r4k_blast_scache_page = blast_scache128_page;
391}
392
393static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
394
395static void r4k_blast_scache_page_indexed_setup(void)
396{
397 unsigned long sc_lsize = cpu_scache_line_size();
398
399 if (scache_size == 0)
400 r4k_blast_scache_page_indexed = (void *)cache_noop;
401 else if (sc_lsize == 16)
402 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
403 else if (sc_lsize == 32)
404 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
405 else if (sc_lsize == 64)
406 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
407 else if (sc_lsize == 128)
408 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
409}
410
411static void (* r4k_blast_scache)(void);
412
413static void r4k_blast_scache_setup(void)
414{
415 unsigned long sc_lsize = cpu_scache_line_size();
416
417 if (scache_size == 0)
418 r4k_blast_scache = (void *)cache_noop;
419 else if (sc_lsize == 16)
420 r4k_blast_scache = blast_scache16;
421 else if (sc_lsize == 32)
422 r4k_blast_scache = blast_scache32;
423 else if (sc_lsize == 64)
424 r4k_blast_scache = blast_scache64;
425 else if (sc_lsize == 128)
426 r4k_blast_scache = blast_scache128;
427}
428
429static inline void local_r4k___flush_cache_all(void * args)
430{
431 switch (current_cpu_type()) {
432 case CPU_LOONGSON2:
433 case CPU_LOONGSON3:
434 case CPU_R4000SC:
435 case CPU_R4000MC:
436 case CPU_R4400SC:
437 case CPU_R4400MC:
438 case CPU_R10000:
439 case CPU_R12000:
440 case CPU_R14000:
441 case CPU_R16000:
442 /*
443 * These caches are inclusive caches, that is, if something
444 * is not cached in the S-cache, we know it also won't be
445 * in one of the primary caches.
446 */
447 r4k_blast_scache();
448 break;
449
450 default:
451 r4k_blast_dcache();
452 r4k_blast_icache();
453 break;
454 }
455}
456
457static void r4k___flush_cache_all(void)
458{
459 r4k_on_each_cpu(local_r4k___flush_cache_all, NULL);
460}
461
462static inline int has_valid_asid(const struct mm_struct *mm)
463{
464#ifdef CONFIG_MIPS_MT_SMP
465 int i;
466
467 for_each_online_cpu(i)
468 if (cpu_context(i, mm))
469 return 1;
470
471 return 0;
472#else
473 return cpu_context(smp_processor_id(), mm);
474#endif
475}
476
477static void r4k__flush_cache_vmap(void)
478{
479 r4k_blast_dcache();
480}
481
482static void r4k__flush_cache_vunmap(void)
483{
484 r4k_blast_dcache();
485}
486
487static inline void local_r4k_flush_cache_range(void * args)
488{
489 struct vm_area_struct *vma = args;
490 int exec = vma->vm_flags & VM_EXEC;
491
492 if (!(has_valid_asid(vma->vm_mm)))
493 return;
494
495 r4k_blast_dcache();
496 if (exec)
497 r4k_blast_icache();
498}
499
500static void r4k_flush_cache_range(struct vm_area_struct *vma,
501 unsigned long start, unsigned long end)
502{
503 int exec = vma->vm_flags & VM_EXEC;
504
505 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
506 r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
507}
508
509static inline void local_r4k_flush_cache_mm(void * args)
510{
511 struct mm_struct *mm = args;
512
513 if (!has_valid_asid(mm))
514 return;
515
516 /*
517 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
518 * only flush the primary caches but R1x000 behave sane ...
519 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
520 * caches, so we can bail out early.
521 */
522 if (current_cpu_type() == CPU_R4000SC ||
523 current_cpu_type() == CPU_R4000MC ||
524 current_cpu_type() == CPU_R4400SC ||
525 current_cpu_type() == CPU_R4400MC) {
526 r4k_blast_scache();
527 return;
528 }
529
530 r4k_blast_dcache();
531}
532
533static void r4k_flush_cache_mm(struct mm_struct *mm)
534{
535 if (!cpu_has_dc_aliases)
536 return;
537
538 r4k_on_each_cpu(local_r4k_flush_cache_mm, mm);
539}
540
541struct flush_cache_page_args {
542 struct vm_area_struct *vma;
543 unsigned long addr;
544 unsigned long pfn;
545};
546
547static inline void local_r4k_flush_cache_page(void *args)
548{
549 struct flush_cache_page_args *fcp_args = args;
550 struct vm_area_struct *vma = fcp_args->vma;
551 unsigned long addr = fcp_args->addr;
552 struct page *page = pfn_to_page(fcp_args->pfn);
553 int exec = vma->vm_flags & VM_EXEC;
554 struct mm_struct *mm = vma->vm_mm;
555 int map_coherent = 0;
556 pgd_t *pgdp;
557 pud_t *pudp;
558 pmd_t *pmdp;
559 pte_t *ptep;
560 void *vaddr;
561
562 /*
563 * If ownes no valid ASID yet, cannot possibly have gotten
564 * this page into the cache.
565 */
566 if (!has_valid_asid(mm))
567 return;
568
569 addr &= PAGE_MASK;
570 pgdp = pgd_offset(mm, addr);
571 pudp = pud_offset(pgdp, addr);
572 pmdp = pmd_offset(pudp, addr);
573 ptep = pte_offset(pmdp, addr);
574
575 /*
576 * If the page isn't marked valid, the page cannot possibly be
577 * in the cache.
578 */
579 if (!(pte_present(*ptep)))
580 return;
581
582 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
583 vaddr = NULL;
584 else {
585 /*
586 * Use kmap_coherent or kmap_atomic to do flushes for
587 * another ASID than the current one.
588 */
589 map_coherent = (cpu_has_dc_aliases &&
590 page_mapcount(page) &&
591 !Page_dcache_dirty(page));
592 if (map_coherent)
593 vaddr = kmap_coherent(page, addr);
594 else
595 vaddr = kmap_atomic(page);
596 addr = (unsigned long)vaddr;
597 }
598
599 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
600 vaddr ? r4k_blast_dcache_page(addr) :
601 r4k_blast_dcache_user_page(addr);
602 if (exec && !cpu_icache_snoops_remote_store)
603 r4k_blast_scache_page(addr);
604 }
605 if (exec) {
606 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
607 int cpu = smp_processor_id();
608
609 if (cpu_context(cpu, mm) != 0)
610 drop_mmu_context(mm, cpu);
611 } else
612 vaddr ? r4k_blast_icache_page(addr) :
613 r4k_blast_icache_user_page(addr);
614 }
615
616 if (vaddr) {
617 if (map_coherent)
618 kunmap_coherent();
619 else
620 kunmap_atomic(vaddr);
621 }
622}
623
624static void r4k_flush_cache_page(struct vm_area_struct *vma,
625 unsigned long addr, unsigned long pfn)
626{
627 struct flush_cache_page_args args;
628
629 args.vma = vma;
630 args.addr = addr;
631 args.pfn = pfn;
632
633 r4k_on_each_cpu(local_r4k_flush_cache_page, &args);
634}
635
636static inline void local_r4k_flush_data_cache_page(void * addr)
637{
638 r4k_blast_dcache_page((unsigned long) addr);
639}
640
641static void r4k_flush_data_cache_page(unsigned long addr)
642{
643 if (in_atomic())
644 local_r4k_flush_data_cache_page((void *)addr);
645 else
646 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
647}
648
649struct flush_icache_range_args {
650 unsigned long start;
651 unsigned long end;
652};
653
654static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end)
655{
656 if (!cpu_has_ic_fills_f_dc) {
657 if (end - start >= dcache_size) {
658 r4k_blast_dcache();
659 } else {
660 R4600_HIT_CACHEOP_WAR_IMPL;
661 protected_blast_dcache_range(start, end);
662 }
663 }
664
665 if (end - start > icache_size)
666 r4k_blast_icache();
667 else {
668 switch (boot_cpu_type()) {
669 case CPU_LOONGSON2:
670 protected_loongson2_blast_icache_range(start, end);
671 break;
672
673 default:
674 protected_blast_icache_range(start, end);
675 break;
676 }
677 }
678#ifdef CONFIG_EVA
679 /*
680 * Due to all possible segment mappings, there might cache aliases
681 * caused by the bootloader being in non-EVA mode, and the CPU switching
682 * to EVA during early kernel init. It's best to flush the scache
683 * to avoid having secondary cores fetching stale data and lead to
684 * kernel crashes.
685 */
686 bc_wback_inv(start, (end - start));
687 __sync();
688#endif
689}
690
691static inline void local_r4k_flush_icache_range_ipi(void *args)
692{
693 struct flush_icache_range_args *fir_args = args;
694 unsigned long start = fir_args->start;
695 unsigned long end = fir_args->end;
696
697 local_r4k_flush_icache_range(start, end);
698}
699
700static void r4k_flush_icache_range(unsigned long start, unsigned long end)
701{
702 struct flush_icache_range_args args;
703
704 args.start = start;
705 args.end = end;
706
707 r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args);
708 instruction_hazard();
709}
710
711#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
712
713static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
714{
715 /* Catch bad driver code */
716 BUG_ON(size == 0);
717
718 preempt_disable();
719 if (cpu_has_inclusive_pcaches) {
720 if (size >= scache_size)
721 r4k_blast_scache();
722 else
723 blast_scache_range(addr, addr + size);
724 preempt_enable();
725 __sync();
726 return;
727 }
728
729 /*
730 * Either no secondary cache or the available caches don't have the
731 * subset property so we have to flush the primary caches
732 * explicitly
733 */
734 if (cpu_has_safe_index_cacheops && size >= dcache_size) {
735 r4k_blast_dcache();
736 } else {
737 R4600_HIT_CACHEOP_WAR_IMPL;
738 blast_dcache_range(addr, addr + size);
739 }
740 preempt_enable();
741
742 bc_wback_inv(addr, size);
743 __sync();
744}
745
746static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
747{
748 /* Catch bad driver code */
749 BUG_ON(size == 0);
750
751 preempt_disable();
752 if (cpu_has_inclusive_pcaches) {
753 if (size >= scache_size)
754 r4k_blast_scache();
755 else {
756 /*
757 * There is no clearly documented alignment requirement
758 * for the cache instruction on MIPS processors and
759 * some processors, among them the RM5200 and RM7000
760 * QED processors will throw an address error for cache
761 * hit ops with insufficient alignment. Solved by
762 * aligning the address to cache line size.
763 */
764 blast_inv_scache_range(addr, addr + size);
765 }
766 preempt_enable();
767 __sync();
768 return;
769 }
770
771 if (cpu_has_safe_index_cacheops && size >= dcache_size) {
772 r4k_blast_dcache();
773 } else {
774 R4600_HIT_CACHEOP_WAR_IMPL;
775 blast_inv_dcache_range(addr, addr + size);
776 }
777 preempt_enable();
778
779 bc_inv(addr, size);
780 __sync();
781}
782#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
783
784/*
785 * While we're protected against bad userland addresses we don't care
786 * very much about what happens in that case. Usually a segmentation
787 * fault will dump the process later on anyway ...
788 */
789static void local_r4k_flush_cache_sigtramp(void * arg)
790{
791 unsigned long ic_lsize = cpu_icache_line_size();
792 unsigned long dc_lsize = cpu_dcache_line_size();
793 unsigned long sc_lsize = cpu_scache_line_size();
794 unsigned long addr = (unsigned long) arg;
795
796 R4600_HIT_CACHEOP_WAR_IMPL;
797 if (dc_lsize)
798 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
799 if (!cpu_icache_snoops_remote_store && scache_size)
800 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
801 if (ic_lsize)
802 protected_flush_icache_line(addr & ~(ic_lsize - 1));
803 if (MIPS4K_ICACHE_REFILL_WAR) {
804 __asm__ __volatile__ (
805 ".set push\n\t"
806 ".set noat\n\t"
807 ".set "MIPS_ISA_LEVEL"\n\t"
808#ifdef CONFIG_32BIT
809 "la $at,1f\n\t"
810#endif
811#ifdef CONFIG_64BIT
812 "dla $at,1f\n\t"
813#endif
814 "cache %0,($at)\n\t"
815 "nop; nop; nop\n"
816 "1:\n\t"
817 ".set pop"
818 :
819 : "i" (Hit_Invalidate_I));
820 }
821 if (MIPS_CACHE_SYNC_WAR)
822 __asm__ __volatile__ ("sync");
823}
824
825static void r4k_flush_cache_sigtramp(unsigned long addr)
826{
827 r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
828}
829
830static void r4k_flush_icache_all(void)
831{
832 if (cpu_has_vtag_icache)
833 r4k_blast_icache();
834}
835
836struct flush_kernel_vmap_range_args {
837 unsigned long vaddr;
838 int size;
839};
840
841static inline void local_r4k_flush_kernel_vmap_range(void *args)
842{
843 struct flush_kernel_vmap_range_args *vmra = args;
844 unsigned long vaddr = vmra->vaddr;
845 int size = vmra->size;
846
847 /*
848 * Aliases only affect the primary caches so don't bother with
849 * S-caches or T-caches.
850 */
851 if (cpu_has_safe_index_cacheops && size >= dcache_size)
852 r4k_blast_dcache();
853 else {
854 R4600_HIT_CACHEOP_WAR_IMPL;
855 blast_dcache_range(vaddr, vaddr + size);
856 }
857}
858
859static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
860{
861 struct flush_kernel_vmap_range_args args;
862
863 args.vaddr = (unsigned long) vaddr;
864 args.size = size;
865
866 r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args);
867}
868
869static inline void rm7k_erratum31(void)
870{
871 const unsigned long ic_lsize = 32;
872 unsigned long addr;
873
874 /* RM7000 erratum #31. The icache is screwed at startup. */
875 write_c0_taglo(0);
876 write_c0_taghi(0);
877
878 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
879 __asm__ __volatile__ (
880 ".set push\n\t"
881 ".set noreorder\n\t"
882 ".set mips3\n\t"
883 "cache\t%1, 0(%0)\n\t"
884 "cache\t%1, 0x1000(%0)\n\t"
885 "cache\t%1, 0x2000(%0)\n\t"
886 "cache\t%1, 0x3000(%0)\n\t"
887 "cache\t%2, 0(%0)\n\t"
888 "cache\t%2, 0x1000(%0)\n\t"
889 "cache\t%2, 0x2000(%0)\n\t"
890 "cache\t%2, 0x3000(%0)\n\t"
891 "cache\t%1, 0(%0)\n\t"
892 "cache\t%1, 0x1000(%0)\n\t"
893 "cache\t%1, 0x2000(%0)\n\t"
894 "cache\t%1, 0x3000(%0)\n\t"
895 ".set pop\n"
896 :
897 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
898 }
899}
900
901static inline int alias_74k_erratum(struct cpuinfo_mips *c)
902{
903 unsigned int imp = c->processor_id & PRID_IMP_MASK;
904 unsigned int rev = c->processor_id & PRID_REV_MASK;
905 int present = 0;
906
907 /*
908 * Early versions of the 74K do not update the cache tags on a
909 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
910 * aliases. In this case it is better to treat the cache as always
911 * having aliases. Also disable the synonym tag update feature
912 * where available. In this case no opportunistic tag update will
913 * happen where a load causes a virtual address miss but a physical
914 * address hit during a D-cache look-up.
915 */
916 switch (imp) {
917 case PRID_IMP_74K:
918 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
919 present = 1;
920 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
921 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
922 break;
923 case PRID_IMP_1074K:
924 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
925 present = 1;
926 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
927 }
928 break;
929 default:
930 BUG();
931 }
932
933 return present;
934}
935
936static void b5k_instruction_hazard(void)
937{
938 __sync();
939 __sync();
940 __asm__ __volatile__(
941 " nop; nop; nop; nop; nop; nop; nop; nop\n"
942 " nop; nop; nop; nop; nop; nop; nop; nop\n"
943 " nop; nop; nop; nop; nop; nop; nop; nop\n"
944 " nop; nop; nop; nop; nop; nop; nop; nop\n"
945 : : : "memory");
946}
947
948static char *way_string[] = { NULL, "direct mapped", "2-way",
949 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
950 "9-way", "10-way", "11-way", "12-way",
951 "13-way", "14-way", "15-way", "16-way",
952};
953
954static void probe_pcache(void)
955{
956 struct cpuinfo_mips *c = ¤t_cpu_data;
957 unsigned int config = read_c0_config();
958 unsigned int prid = read_c0_prid();
959 int has_74k_erratum = 0;
960 unsigned long config1;
961 unsigned int lsize;
962
963 switch (current_cpu_type()) {
964 case CPU_R4600: /* QED style two way caches? */
965 case CPU_R4700:
966 case CPU_R5000:
967 case CPU_NEVADA:
968 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
969 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
970 c->icache.ways = 2;
971 c->icache.waybit = __ffs(icache_size/2);
972
973 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
974 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
975 c->dcache.ways = 2;
976 c->dcache.waybit= __ffs(dcache_size/2);
977
978 c->options |= MIPS_CPU_CACHE_CDEX_P;
979 break;
980
981 case CPU_R5432:
982 case CPU_R5500:
983 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
984 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
985 c->icache.ways = 2;
986 c->icache.waybit= 0;
987
988 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
989 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
990 c->dcache.ways = 2;
991 c->dcache.waybit = 0;
992
993 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
994 break;
995
996 case CPU_TX49XX:
997 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
998 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
999 c->icache.ways = 4;
1000 c->icache.waybit= 0;
1001
1002 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1003 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1004 c->dcache.ways = 4;
1005 c->dcache.waybit = 0;
1006
1007 c->options |= MIPS_CPU_CACHE_CDEX_P;
1008 c->options |= MIPS_CPU_PREFETCH;
1009 break;
1010
1011 case CPU_R4000PC:
1012 case CPU_R4000SC:
1013 case CPU_R4000MC:
1014 case CPU_R4400PC:
1015 case CPU_R4400SC:
1016 case CPU_R4400MC:
1017 case CPU_R4300:
1018 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1019 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1020 c->icache.ways = 1;
1021 c->icache.waybit = 0; /* doesn't matter */
1022
1023 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1024 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1025 c->dcache.ways = 1;
1026 c->dcache.waybit = 0; /* does not matter */
1027
1028 c->options |= MIPS_CPU_CACHE_CDEX_P;
1029 break;
1030
1031 case CPU_R10000:
1032 case CPU_R12000:
1033 case CPU_R14000:
1034 case CPU_R16000:
1035 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
1036 c->icache.linesz = 64;
1037 c->icache.ways = 2;
1038 c->icache.waybit = 0;
1039
1040 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
1041 c->dcache.linesz = 32;
1042 c->dcache.ways = 2;
1043 c->dcache.waybit = 0;
1044
1045 c->options |= MIPS_CPU_PREFETCH;
1046 break;
1047
1048 case CPU_VR4133:
1049 write_c0_config(config & ~VR41_CONF_P4K);
1050 case CPU_VR4131:
1051 /* Workaround for cache instruction bug of VR4131 */
1052 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
1053 c->processor_id == 0x0c82U) {
1054 config |= 0x00400000U;
1055 if (c->processor_id == 0x0c80U)
1056 config |= VR41_CONF_BP;
1057 write_c0_config(config);
1058 } else
1059 c->options |= MIPS_CPU_CACHE_CDEX_P;
1060
1061 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1062 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1063 c->icache.ways = 2;
1064 c->icache.waybit = __ffs(icache_size/2);
1065
1066 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1067 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1068 c->dcache.ways = 2;
1069 c->dcache.waybit = __ffs(dcache_size/2);
1070 break;
1071
1072 case CPU_VR41XX:
1073 case CPU_VR4111:
1074 case CPU_VR4121:
1075 case CPU_VR4122:
1076 case CPU_VR4181:
1077 case CPU_VR4181A:
1078 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1079 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1080 c->icache.ways = 1;
1081 c->icache.waybit = 0; /* doesn't matter */
1082
1083 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1084 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1085 c->dcache.ways = 1;
1086 c->dcache.waybit = 0; /* does not matter */
1087
1088 c->options |= MIPS_CPU_CACHE_CDEX_P;
1089 break;
1090
1091 case CPU_RM7000:
1092 rm7k_erratum31();
1093
1094 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1095 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1096 c->icache.ways = 4;
1097 c->icache.waybit = __ffs(icache_size / c->icache.ways);
1098
1099 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1100 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1101 c->dcache.ways = 4;
1102 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
1103
1104 c->options |= MIPS_CPU_CACHE_CDEX_P;
1105 c->options |= MIPS_CPU_PREFETCH;
1106 break;
1107
1108 case CPU_LOONGSON2:
1109 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1110 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1111 if (prid & 0x3)
1112 c->icache.ways = 4;
1113 else
1114 c->icache.ways = 2;
1115 c->icache.waybit = 0;
1116
1117 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1118 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1119 if (prid & 0x3)
1120 c->dcache.ways = 4;
1121 else
1122 c->dcache.ways = 2;
1123 c->dcache.waybit = 0;
1124 break;
1125
1126 case CPU_LOONGSON3:
1127 config1 = read_c0_config1();
1128 lsize = (config1 >> 19) & 7;
1129 if (lsize)
1130 c->icache.linesz = 2 << lsize;
1131 else
1132 c->icache.linesz = 0;
1133 c->icache.sets = 64 << ((config1 >> 22) & 7);
1134 c->icache.ways = 1 + ((config1 >> 16) & 7);
1135 icache_size = c->icache.sets *
1136 c->icache.ways *
1137 c->icache.linesz;
1138 c->icache.waybit = 0;
1139
1140 lsize = (config1 >> 10) & 7;
1141 if (lsize)
1142 c->dcache.linesz = 2 << lsize;
1143 else
1144 c->dcache.linesz = 0;
1145 c->dcache.sets = 64 << ((config1 >> 13) & 7);
1146 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1147 dcache_size = c->dcache.sets *
1148 c->dcache.ways *
1149 c->dcache.linesz;
1150 c->dcache.waybit = 0;
1151 break;
1152
1153 case CPU_CAVIUM_OCTEON3:
1154 /* For now lie about the number of ways. */
1155 c->icache.linesz = 128;
1156 c->icache.sets = 16;
1157 c->icache.ways = 8;
1158 c->icache.flags |= MIPS_CACHE_VTAG;
1159 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
1160
1161 c->dcache.linesz = 128;
1162 c->dcache.ways = 8;
1163 c->dcache.sets = 8;
1164 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
1165 c->options |= MIPS_CPU_PREFETCH;
1166 break;
1167
1168 default:
1169 if (!(config & MIPS_CONF_M))
1170 panic("Don't know how to probe P-caches on this cpu.");
1171
1172 /*
1173 * So we seem to be a MIPS32 or MIPS64 CPU
1174 * So let's probe the I-cache ...
1175 */
1176 config1 = read_c0_config1();
1177
1178 lsize = (config1 >> 19) & 7;
1179
1180 /* IL == 7 is reserved */
1181 if (lsize == 7)
1182 panic("Invalid icache line size");
1183
1184 c->icache.linesz = lsize ? 2 << lsize : 0;
1185
1186 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
1187 c->icache.ways = 1 + ((config1 >> 16) & 7);
1188
1189 icache_size = c->icache.sets *
1190 c->icache.ways *
1191 c->icache.linesz;
1192 c->icache.waybit = __ffs(icache_size/c->icache.ways);
1193
1194 if (config & 0x8) /* VI bit */
1195 c->icache.flags |= MIPS_CACHE_VTAG;
1196
1197 /*
1198 * Now probe the MIPS32 / MIPS64 data cache.
1199 */
1200 c->dcache.flags = 0;
1201
1202 lsize = (config1 >> 10) & 7;
1203
1204 /* DL == 7 is reserved */
1205 if (lsize == 7)
1206 panic("Invalid dcache line size");
1207
1208 c->dcache.linesz = lsize ? 2 << lsize : 0;
1209
1210 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1211 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1212
1213 dcache_size = c->dcache.sets *
1214 c->dcache.ways *
1215 c->dcache.linesz;
1216 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
1217
1218 c->options |= MIPS_CPU_PREFETCH;
1219 break;
1220 }
1221
1222 /*
1223 * Processor configuration sanity check for the R4000SC erratum
1224 * #5. With page sizes larger than 32kB there is no possibility
1225 * to get a VCE exception anymore so we don't care about this
1226 * misconfiguration. The case is rather theoretical anyway;
1227 * presumably no vendor is shipping his hardware in the "bad"
1228 * configuration.
1229 */
1230 if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1231 (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
1232 !(config & CONF_SC) && c->icache.linesz != 16 &&
1233 PAGE_SIZE <= 0x8000)
1234 panic("Improper R4000SC processor configuration detected");
1235
1236 /* compute a couple of other cache variables */
1237 c->icache.waysize = icache_size / c->icache.ways;
1238 c->dcache.waysize = dcache_size / c->dcache.ways;
1239
1240 c->icache.sets = c->icache.linesz ?
1241 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1242 c->dcache.sets = c->dcache.linesz ?
1243 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1244
1245 /*
1246 * R1x000 P-caches are odd in a positive way. They're 32kB 2-way
1247 * virtually indexed so normally would suffer from aliases. So
1248 * normally they'd suffer from aliases but magic in the hardware deals
1249 * with that for us so we don't need to take care ourselves.
1250 */
1251 switch (current_cpu_type()) {
1252 case CPU_20KC:
1253 case CPU_25KF:
1254 case CPU_SB1:
1255 case CPU_SB1A:
1256 case CPU_XLR:
1257 c->dcache.flags |= MIPS_CACHE_PINDEX;
1258 break;
1259
1260 case CPU_R10000:
1261 case CPU_R12000:
1262 case CPU_R14000:
1263 case CPU_R16000:
1264 break;
1265
1266 case CPU_74K:
1267 case CPU_1074K:
1268 has_74k_erratum = alias_74k_erratum(c);
1269 /* Fall through. */
1270 case CPU_M14KC:
1271 case CPU_M14KEC:
1272 case CPU_24K:
1273 case CPU_34K:
1274 case CPU_1004K:
1275 case CPU_INTERAPTIV:
1276 case CPU_P5600:
1277 case CPU_PROAPTIV:
1278 case CPU_M5150:
1279 case CPU_QEMU_GENERIC:
1280 case CPU_I6400:
1281 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
1282 (c->icache.waysize > PAGE_SIZE))
1283 c->icache.flags |= MIPS_CACHE_ALIASES;
1284 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) {
1285 /*
1286 * Effectively physically indexed dcache,
1287 * thus no virtual aliases.
1288 */
1289 c->dcache.flags |= MIPS_CACHE_PINDEX;
1290 break;
1291 }
1292 default:
1293 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
1294 c->dcache.flags |= MIPS_CACHE_ALIASES;
1295 }
1296
1297 switch (current_cpu_type()) {
1298 case CPU_20KC:
1299 /*
1300 * Some older 20Kc chips doesn't have the 'VI' bit in
1301 * the config register.
1302 */
1303 c->icache.flags |= MIPS_CACHE_VTAG;
1304 break;
1305
1306 case CPU_ALCHEMY:
1307 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1308 break;
1309
1310 case CPU_LOONGSON2:
1311 /*
1312 * LOONGSON2 has 4 way icache, but when using indexed cache op,
1313 * one op will act on all 4 ways
1314 */
1315 c->icache.ways = 1;
1316 }
1317
1318 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1319 icache_size >> 10,
1320 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1321 way_string[c->icache.ways], c->icache.linesz);
1322
1323 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1324 dcache_size >> 10, way_string[c->dcache.ways],
1325 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1326 (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1327 "cache aliases" : "no aliases",
1328 c->dcache.linesz);
1329}
1330
1331/*
1332 * If you even _breathe_ on this function, look at the gcc output and make sure
1333 * it does not pop things on and off the stack for the cache sizing loop that
1334 * executes in KSEG1 space or else you will crash and burn badly. You have
1335 * been warned.
1336 */
1337static int probe_scache(void)
1338{
1339 unsigned long flags, addr, begin, end, pow2;
1340 unsigned int config = read_c0_config();
1341 struct cpuinfo_mips *c = ¤t_cpu_data;
1342
1343 if (config & CONF_SC)
1344 return 0;
1345
1346 begin = (unsigned long) &_stext;
1347 begin &= ~((4 * 1024 * 1024) - 1);
1348 end = begin + (4 * 1024 * 1024);
1349
1350 /*
1351 * This is such a bitch, you'd think they would make it easy to do
1352 * this. Away you daemons of stupidity!
1353 */
1354 local_irq_save(flags);
1355
1356 /* Fill each size-multiple cache line with a valid tag. */
1357 pow2 = (64 * 1024);
1358 for (addr = begin; addr < end; addr = (begin + pow2)) {
1359 unsigned long *p = (unsigned long *) addr;
1360 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1361 pow2 <<= 1;
1362 }
1363
1364 /* Load first line with zero (therefore invalid) tag. */
1365 write_c0_taglo(0);
1366 write_c0_taghi(0);
1367 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1368 cache_op(Index_Store_Tag_I, begin);
1369 cache_op(Index_Store_Tag_D, begin);
1370 cache_op(Index_Store_Tag_SD, begin);
1371
1372 /* Now search for the wrap around point. */
1373 pow2 = (128 * 1024);
1374 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1375 cache_op(Index_Load_Tag_SD, addr);
1376 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1377 if (!read_c0_taglo())
1378 break;
1379 pow2 <<= 1;
1380 }
1381 local_irq_restore(flags);
1382 addr -= begin;
1383
1384 scache_size = addr;
1385 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1386 c->scache.ways = 1;
1387 c->scache.waybit = 0; /* does not matter */
1388
1389 return 1;
1390}
1391
1392static void __init loongson2_sc_init(void)
1393{
1394 struct cpuinfo_mips *c = ¤t_cpu_data;
1395
1396 scache_size = 512*1024;
1397 c->scache.linesz = 32;
1398 c->scache.ways = 4;
1399 c->scache.waybit = 0;
1400 c->scache.waysize = scache_size / (c->scache.ways);
1401 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1402 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1403 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1404
1405 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1406}
1407
1408static void __init loongson3_sc_init(void)
1409{
1410 struct cpuinfo_mips *c = ¤t_cpu_data;
1411 unsigned int config2, lsize;
1412
1413 config2 = read_c0_config2();
1414 lsize = (config2 >> 4) & 15;
1415 if (lsize)
1416 c->scache.linesz = 2 << lsize;
1417 else
1418 c->scache.linesz = 0;
1419 c->scache.sets = 64 << ((config2 >> 8) & 15);
1420 c->scache.ways = 1 + (config2 & 15);
1421
1422 scache_size = c->scache.sets *
1423 c->scache.ways *
1424 c->scache.linesz;
1425 /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */
1426 scache_size *= 4;
1427 c->scache.waybit = 0;
1428 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1429 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1430 if (scache_size)
1431 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1432 return;
1433}
1434
1435extern int r5k_sc_init(void);
1436extern int rm7k_sc_init(void);
1437extern int mips_sc_init(void);
1438
1439static void setup_scache(void)
1440{
1441 struct cpuinfo_mips *c = ¤t_cpu_data;
1442 unsigned int config = read_c0_config();
1443 int sc_present = 0;
1444
1445 /*
1446 * Do the probing thing on R4000SC and R4400SC processors. Other
1447 * processors don't have a S-cache that would be relevant to the
1448 * Linux memory management.
1449 */
1450 switch (current_cpu_type()) {
1451 case CPU_R4000SC:
1452 case CPU_R4000MC:
1453 case CPU_R4400SC:
1454 case CPU_R4400MC:
1455 sc_present = run_uncached(probe_scache);
1456 if (sc_present)
1457 c->options |= MIPS_CPU_CACHE_CDEX_S;
1458 break;
1459
1460 case CPU_R10000:
1461 case CPU_R12000:
1462 case CPU_R14000:
1463 case CPU_R16000:
1464 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1465 c->scache.linesz = 64 << ((config >> 13) & 1);
1466 c->scache.ways = 2;
1467 c->scache.waybit= 0;
1468 sc_present = 1;
1469 break;
1470
1471 case CPU_R5000:
1472 case CPU_NEVADA:
1473#ifdef CONFIG_R5000_CPU_SCACHE
1474 r5k_sc_init();
1475#endif
1476 return;
1477
1478 case CPU_RM7000:
1479#ifdef CONFIG_RM7000_CPU_SCACHE
1480 rm7k_sc_init();
1481#endif
1482 return;
1483
1484 case CPU_LOONGSON2:
1485 loongson2_sc_init();
1486 return;
1487
1488 case CPU_LOONGSON3:
1489 loongson3_sc_init();
1490 return;
1491
1492 case CPU_CAVIUM_OCTEON3:
1493 case CPU_XLP:
1494 /* don't need to worry about L2, fully coherent */
1495 return;
1496
1497 default:
1498 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1499 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
1500 MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) {
1501#ifdef CONFIG_MIPS_CPU_SCACHE
1502 if (mips_sc_init ()) {
1503 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1504 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1505 scache_size >> 10,
1506 way_string[c->scache.ways], c->scache.linesz);
1507 }
1508#else
1509 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1510 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1511#endif
1512 return;
1513 }
1514 sc_present = 0;
1515 }
1516
1517 if (!sc_present)
1518 return;
1519
1520 /* compute a couple of other cache variables */
1521 c->scache.waysize = scache_size / c->scache.ways;
1522
1523 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1524
1525 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1526 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1527
1528 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1529}
1530
1531void au1x00_fixup_config_od(void)
1532{
1533 /*
1534 * c0_config.od (bit 19) was write only (and read as 0)
1535 * on the early revisions of Alchemy SOCs. It disables the bus
1536 * transaction overlapping and needs to be set to fix various errata.
1537 */
1538 switch (read_c0_prid()) {
1539 case 0x00030100: /* Au1000 DA */
1540 case 0x00030201: /* Au1000 HA */
1541 case 0x00030202: /* Au1000 HB */
1542 case 0x01030200: /* Au1500 AB */
1543 /*
1544 * Au1100 errata actually keeps silence about this bit, so we set it
1545 * just in case for those revisions that require it to be set according
1546 * to the (now gone) cpu table.
1547 */
1548 case 0x02030200: /* Au1100 AB */
1549 case 0x02030201: /* Au1100 BA */
1550 case 0x02030202: /* Au1100 BC */
1551 set_c0_config(1 << 19);
1552 break;
1553 }
1554}
1555
1556/* CP0 hazard avoidance. */
1557#define NXP_BARRIER() \
1558 __asm__ __volatile__( \
1559 ".set noreorder\n\t" \
1560 "nop; nop; nop; nop; nop; nop;\n\t" \
1561 ".set reorder\n\t")
1562
1563static void nxp_pr4450_fixup_config(void)
1564{
1565 unsigned long config0;
1566
1567 config0 = read_c0_config();
1568
1569 /* clear all three cache coherency fields */
1570 config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1571 config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) |
1572 ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1573 ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1574 write_c0_config(config0);
1575 NXP_BARRIER();
1576}
1577
1578static int cca = -1;
1579
1580static int __init cca_setup(char *str)
1581{
1582 get_option(&str, &cca);
1583
1584 return 0;
1585}
1586
1587early_param("cca", cca_setup);
1588
1589static void coherency_setup(void)
1590{
1591 if (cca < 0 || cca > 7)
1592 cca = read_c0_config() & CONF_CM_CMASK;
1593 _page_cachable_default = cca << _CACHE_SHIFT;
1594
1595 pr_debug("Using cache attribute %d\n", cca);
1596 change_c0_config(CONF_CM_CMASK, cca);
1597
1598 /*
1599 * c0_status.cu=0 specifies that updates by the sc instruction use
1600 * the coherency mode specified by the TLB; 1 means cachable
1601 * coherent update on write will be used. Not all processors have
1602 * this bit and; some wire it to zero, others like Toshiba had the
1603 * silly idea of putting something else there ...
1604 */
1605 switch (current_cpu_type()) {
1606 case CPU_R4000PC:
1607 case CPU_R4000SC:
1608 case CPU_R4000MC:
1609 case CPU_R4400PC:
1610 case CPU_R4400SC:
1611 case CPU_R4400MC:
1612 clear_c0_config(CONF_CU);
1613 break;
1614 /*
1615 * We need to catch the early Alchemy SOCs with
1616 * the write-only co_config.od bit and set it back to one on:
1617 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
1618 */
1619 case CPU_ALCHEMY:
1620 au1x00_fixup_config_od();
1621 break;
1622
1623 case PRID_IMP_PR4450:
1624 nxp_pr4450_fixup_config();
1625 break;
1626 }
1627}
1628
1629static void r4k_cache_error_setup(void)
1630{
1631 extern char __weak except_vec2_generic;
1632 extern char __weak except_vec2_sb1;
1633
1634 switch (current_cpu_type()) {
1635 case CPU_SB1:
1636 case CPU_SB1A:
1637 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1638 break;
1639
1640 default:
1641 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1642 break;
1643 }
1644}
1645
1646void r4k_cache_init(void)
1647{
1648 extern void build_clear_page(void);
1649 extern void build_copy_page(void);
1650 struct cpuinfo_mips *c = ¤t_cpu_data;
1651
1652 probe_pcache();
1653 setup_scache();
1654
1655 r4k_blast_dcache_page_setup();
1656 r4k_blast_dcache_page_indexed_setup();
1657 r4k_blast_dcache_setup();
1658 r4k_blast_icache_page_setup();
1659 r4k_blast_icache_page_indexed_setup();
1660 r4k_blast_icache_setup();
1661 r4k_blast_scache_page_setup();
1662 r4k_blast_scache_page_indexed_setup();
1663 r4k_blast_scache_setup();
1664#ifdef CONFIG_EVA
1665 r4k_blast_dcache_user_page_setup();
1666 r4k_blast_icache_user_page_setup();
1667#endif
1668
1669 /*
1670 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1671 * This code supports virtually indexed processors and will be
1672 * unnecessarily inefficient on physically indexed processors.
1673 */
1674 if (c->dcache.linesz)
1675 shm_align_mask = max_t( unsigned long,
1676 c->dcache.sets * c->dcache.linesz - 1,
1677 PAGE_SIZE - 1);
1678 else
1679 shm_align_mask = PAGE_SIZE-1;
1680
1681 __flush_cache_vmap = r4k__flush_cache_vmap;
1682 __flush_cache_vunmap = r4k__flush_cache_vunmap;
1683
1684 flush_cache_all = cache_noop;
1685 __flush_cache_all = r4k___flush_cache_all;
1686 flush_cache_mm = r4k_flush_cache_mm;
1687 flush_cache_page = r4k_flush_cache_page;
1688 flush_cache_range = r4k_flush_cache_range;
1689
1690 __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1691
1692 flush_cache_sigtramp = r4k_flush_cache_sigtramp;
1693 flush_icache_all = r4k_flush_icache_all;
1694 local_flush_data_cache_page = local_r4k_flush_data_cache_page;
1695 flush_data_cache_page = r4k_flush_data_cache_page;
1696 flush_icache_range = r4k_flush_icache_range;
1697 local_flush_icache_range = local_r4k_flush_icache_range;
1698
1699#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
1700 if (coherentio) {
1701 _dma_cache_wback_inv = (void *)cache_noop;
1702 _dma_cache_wback = (void *)cache_noop;
1703 _dma_cache_inv = (void *)cache_noop;
1704 } else {
1705 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1706 _dma_cache_wback = r4k_dma_cache_wback_inv;
1707 _dma_cache_inv = r4k_dma_cache_inv;
1708 }
1709#endif
1710
1711 build_clear_page();
1712 build_copy_page();
1713
1714 /*
1715 * We want to run CMP kernels on core with and without coherent
1716 * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
1717 * or not to flush caches.
1718 */
1719 local_r4k___flush_cache_all(NULL);
1720
1721 coherency_setup();
1722 board_cache_error_setup = r4k_cache_error_setup;
1723
1724 /*
1725 * Per-CPU overrides
1726 */
1727 switch (current_cpu_type()) {
1728 case CPU_BMIPS4350:
1729 case CPU_BMIPS4380:
1730 /* No IPI is needed because all CPUs share the same D$ */
1731 flush_data_cache_page = r4k_blast_dcache_page;
1732 break;
1733 case CPU_BMIPS5000:
1734 /* We lose our superpowers if L2 is disabled */
1735 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
1736 break;
1737
1738 /* I$ fills from D$ just by emptying the write buffers */
1739 flush_cache_page = (void *)b5k_instruction_hazard;
1740 flush_cache_range = (void *)b5k_instruction_hazard;
1741 flush_cache_sigtramp = (void *)b5k_instruction_hazard;
1742 local_flush_data_cache_page = (void *)b5k_instruction_hazard;
1743 flush_data_cache_page = (void *)b5k_instruction_hazard;
1744 flush_icache_range = (void *)b5k_instruction_hazard;
1745 local_flush_icache_range = (void *)b5k_instruction_hazard;
1746
1747 /* Cache aliases are handled in hardware; allow HIGHMEM */
1748 current_cpu_data.dcache.flags &= ~MIPS_CACHE_ALIASES;
1749
1750 /* Optimization: an L2 flush implicitly flushes the L1 */
1751 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
1752 break;
1753 }
1754}
1755
1756static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,
1757 void *v)
1758{
1759 switch (cmd) {
1760 case CPU_PM_ENTER_FAILED:
1761 case CPU_PM_EXIT:
1762 coherency_setup();
1763 break;
1764 }
1765
1766 return NOTIFY_OK;
1767}
1768
1769static struct notifier_block r4k_cache_pm_notifier_block = {
1770 .notifier_call = r4k_cache_pm_notifier,
1771};
1772
1773int __init r4k_cache_init_pm(void)
1774{
1775 return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block);
1776}
1777arch_initcall(r4k_cache_init_pm);