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1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <asm/unaligned.h>
24
25#include "xhci.h"
26
27#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
28#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
29 PORT_RC | PORT_PLC | PORT_PE)
30
31static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
32 struct usb_hub_descriptor *desc, int ports)
33{
34 u16 temp;
35
36 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
37 desc->bHubContrCurrent = 0;
38
39 desc->bNbrPorts = ports;
40 /* Ugh, these should be #defines, FIXME */
41 /* Using table 11-13 in USB 2.0 spec. */
42 temp = 0;
43 /* Bits 1:0 - support port power switching, or power always on */
44 if (HCC_PPC(xhci->hcc_params))
45 temp |= 0x0001;
46 else
47 temp |= 0x0002;
48 /* Bit 2 - root hubs are not part of a compound device */
49 /* Bits 4:3 - individual port over current protection */
50 temp |= 0x0008;
51 /* Bits 6:5 - no TTs in root ports */
52 /* Bit 7 - no port indicators */
53 desc->wHubCharacteristics = cpu_to_le16(temp);
54}
55
56/* Fill in the USB 2.0 roothub descriptor */
57static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
58 struct usb_hub_descriptor *desc)
59{
60 int ports;
61 u16 temp;
62 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
63 u32 portsc;
64 unsigned int i;
65
66 ports = xhci->num_usb2_ports;
67
68 xhci_common_hub_descriptor(xhci, desc, ports);
69 desc->bDescriptorType = 0x29;
70 temp = 1 + (ports / 8);
71 desc->bDescLength = 7 + 2 * temp;
72
73 /* The Device Removable bits are reported on a byte granularity.
74 * If the port doesn't exist within that byte, the bit is set to 0.
75 */
76 memset(port_removable, 0, sizeof(port_removable));
77 for (i = 0; i < ports; i++) {
78 portsc = xhci_readl(xhci, xhci->usb3_ports[i]);
79 /* If a device is removable, PORTSC reports a 0, same as in the
80 * hub descriptor DeviceRemovable bits.
81 */
82 if (portsc & PORT_DEV_REMOVE)
83 /* This math is hairy because bit 0 of DeviceRemovable
84 * is reserved, and bit 1 is for port 1, etc.
85 */
86 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
87 }
88
89 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
90 * ports on it. The USB 2.0 specification says that there are two
91 * variable length fields at the end of the hub descriptor:
92 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
93 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
94 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
95 * 0xFF, so we initialize the both arrays (DeviceRemovable and
96 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
97 * set of ports that actually exist.
98 */
99 memset(desc->u.hs.DeviceRemovable, 0xff,
100 sizeof(desc->u.hs.DeviceRemovable));
101 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
102 sizeof(desc->u.hs.PortPwrCtrlMask));
103
104 for (i = 0; i < (ports + 1 + 7) / 8; i++)
105 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
106 sizeof(__u8));
107}
108
109/* Fill in the USB 3.0 roothub descriptor */
110static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
111 struct usb_hub_descriptor *desc)
112{
113 int ports;
114 u16 port_removable;
115 u32 portsc;
116 unsigned int i;
117
118 ports = xhci->num_usb3_ports;
119 xhci_common_hub_descriptor(xhci, desc, ports);
120 desc->bDescriptorType = 0x2a;
121 desc->bDescLength = 12;
122
123 /* header decode latency should be zero for roothubs,
124 * see section 4.23.5.2.
125 */
126 desc->u.ss.bHubHdrDecLat = 0;
127 desc->u.ss.wHubDelay = 0;
128
129 port_removable = 0;
130 /* bit 0 is reserved, bit 1 is for port 1, etc. */
131 for (i = 0; i < ports; i++) {
132 portsc = xhci_readl(xhci, xhci->usb3_ports[i]);
133 if (portsc & PORT_DEV_REMOVE)
134 port_removable |= 1 << (i + 1);
135 }
136 memset(&desc->u.ss.DeviceRemovable,
137 (__force __u16) cpu_to_le16(port_removable),
138 sizeof(__u16));
139}
140
141static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
142 struct usb_hub_descriptor *desc)
143{
144
145 if (hcd->speed == HCD_USB3)
146 xhci_usb3_hub_descriptor(hcd, xhci, desc);
147 else
148 xhci_usb2_hub_descriptor(hcd, xhci, desc);
149
150}
151
152static unsigned int xhci_port_speed(unsigned int port_status)
153{
154 if (DEV_LOWSPEED(port_status))
155 return USB_PORT_STAT_LOW_SPEED;
156 if (DEV_HIGHSPEED(port_status))
157 return USB_PORT_STAT_HIGH_SPEED;
158 /*
159 * FIXME: Yes, we should check for full speed, but the core uses that as
160 * a default in portspeed() in usb/core/hub.c (which is the only place
161 * USB_PORT_STAT_*_SPEED is used).
162 */
163 return 0;
164}
165
166/*
167 * These bits are Read Only (RO) and should be saved and written to the
168 * registers: 0, 3, 10:13, 30
169 * connect status, over-current status, port speed, and device removable.
170 * connect status and port speed are also sticky - meaning they're in
171 * the AUX well and they aren't changed by a hot, warm, or cold reset.
172 */
173#define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
174/*
175 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
176 * bits 5:8, 9, 14:15, 25:27
177 * link state, port power, port indicator state, "wake on" enable state
178 */
179#define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
180/*
181 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
182 * bit 4 (port reset)
183 */
184#define XHCI_PORT_RW1S ((1<<4))
185/*
186 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
187 * bits 1, 17, 18, 19, 20, 21, 22, 23
188 * port enable/disable, and
189 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
190 * over-current, reset, link state, and L1 change
191 */
192#define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
193/*
194 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
195 * latched in
196 */
197#define XHCI_PORT_RW ((1<<16))
198/*
199 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
200 * bits 2, 24, 28:31
201 */
202#define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
203
204/*
205 * Given a port state, this function returns a value that would result in the
206 * port being in the same state, if the value was written to the port status
207 * control register.
208 * Save Read Only (RO) bits and save read/write bits where
209 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
210 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
211 */
212u32 xhci_port_state_to_neutral(u32 state)
213{
214 /* Save read-only status and port state */
215 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
216}
217
218/*
219 * find slot id based on port number.
220 * @port: The one-based port number from one of the two split roothubs.
221 */
222int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
223 u16 port)
224{
225 int slot_id;
226 int i;
227 enum usb_device_speed speed;
228
229 slot_id = 0;
230 for (i = 0; i < MAX_HC_SLOTS; i++) {
231 if (!xhci->devs[i])
232 continue;
233 speed = xhci->devs[i]->udev->speed;
234 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
235 && xhci->devs[i]->port == port) {
236 slot_id = i;
237 break;
238 }
239 }
240
241 return slot_id;
242}
243
244/*
245 * Stop device
246 * It issues stop endpoint command for EP 0 to 30. And wait the last command
247 * to complete.
248 * suspend will set to 1, if suspend bit need to set in command.
249 */
250static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
251{
252 struct xhci_virt_device *virt_dev;
253 struct xhci_command *cmd;
254 unsigned long flags;
255 int timeleft;
256 int ret;
257 int i;
258
259 ret = 0;
260 virt_dev = xhci->devs[slot_id];
261 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
262 if (!cmd) {
263 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
264 return -ENOMEM;
265 }
266
267 spin_lock_irqsave(&xhci->lock, flags);
268 for (i = LAST_EP_INDEX; i > 0; i--) {
269 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
270 xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
271 }
272 cmd->command_trb = xhci->cmd_ring->enqueue;
273 list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
274 xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
275 xhci_ring_cmd_db(xhci);
276 spin_unlock_irqrestore(&xhci->lock, flags);
277
278 /* Wait for last stop endpoint command to finish */
279 timeleft = wait_for_completion_interruptible_timeout(
280 cmd->completion,
281 USB_CTRL_SET_TIMEOUT);
282 if (timeleft <= 0) {
283 xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
284 timeleft == 0 ? "Timeout" : "Signal");
285 spin_lock_irqsave(&xhci->lock, flags);
286 /* The timeout might have raced with the event ring handler, so
287 * only delete from the list if the item isn't poisoned.
288 */
289 if (cmd->cmd_list.next != LIST_POISON1)
290 list_del(&cmd->cmd_list);
291 spin_unlock_irqrestore(&xhci->lock, flags);
292 ret = -ETIME;
293 goto command_cleanup;
294 }
295
296command_cleanup:
297 xhci_free_command(xhci, cmd);
298 return ret;
299}
300
301/*
302 * Ring device, it rings the all doorbells unconditionally.
303 */
304void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
305{
306 int i;
307
308 for (i = 0; i < LAST_EP_INDEX + 1; i++)
309 if (xhci->devs[slot_id]->eps[i].ring &&
310 xhci->devs[slot_id]->eps[i].ring->dequeue)
311 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
312
313 return;
314}
315
316static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
317 u16 wIndex, __le32 __iomem *addr, u32 port_status)
318{
319 /* Don't allow the USB core to disable SuperSpeed ports. */
320 if (hcd->speed == HCD_USB3) {
321 xhci_dbg(xhci, "Ignoring request to disable "
322 "SuperSpeed port.\n");
323 return;
324 }
325
326 /* Write 1 to disable the port */
327 xhci_writel(xhci, port_status | PORT_PE, addr);
328 port_status = xhci_readl(xhci, addr);
329 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
330 wIndex, port_status);
331}
332
333static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
334 u16 wIndex, __le32 __iomem *addr, u32 port_status)
335{
336 char *port_change_bit;
337 u32 status;
338
339 switch (wValue) {
340 case USB_PORT_FEAT_C_RESET:
341 status = PORT_RC;
342 port_change_bit = "reset";
343 break;
344 case USB_PORT_FEAT_C_BH_PORT_RESET:
345 status = PORT_WRC;
346 port_change_bit = "warm(BH) reset";
347 break;
348 case USB_PORT_FEAT_C_CONNECTION:
349 status = PORT_CSC;
350 port_change_bit = "connect";
351 break;
352 case USB_PORT_FEAT_C_OVER_CURRENT:
353 status = PORT_OCC;
354 port_change_bit = "over-current";
355 break;
356 case USB_PORT_FEAT_C_ENABLE:
357 status = PORT_PEC;
358 port_change_bit = "enable/disable";
359 break;
360 case USB_PORT_FEAT_C_SUSPEND:
361 status = PORT_PLC;
362 port_change_bit = "suspend/resume";
363 break;
364 case USB_PORT_FEAT_C_PORT_LINK_STATE:
365 status = PORT_PLC;
366 port_change_bit = "link state";
367 break;
368 default:
369 /* Should never happen */
370 return;
371 }
372 /* Change bits are all write 1 to clear */
373 xhci_writel(xhci, port_status | status, addr);
374 port_status = xhci_readl(xhci, addr);
375 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
376 port_change_bit, wIndex, port_status);
377}
378
379static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
380{
381 int max_ports;
382 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
383
384 if (hcd->speed == HCD_USB3) {
385 max_ports = xhci->num_usb3_ports;
386 *port_array = xhci->usb3_ports;
387 } else {
388 max_ports = xhci->num_usb2_ports;
389 *port_array = xhci->usb2_ports;
390 }
391
392 return max_ports;
393}
394
395int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
396 u16 wIndex, char *buf, u16 wLength)
397{
398 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
399 int max_ports;
400 unsigned long flags;
401 u32 temp, temp1, status;
402 int retval = 0;
403 __le32 __iomem **port_array;
404 int slot_id;
405 struct xhci_bus_state *bus_state;
406 u16 link_state = 0;
407
408 max_ports = xhci_get_ports(hcd, &port_array);
409 bus_state = &xhci->bus_state[hcd_index(hcd)];
410
411 spin_lock_irqsave(&xhci->lock, flags);
412 switch (typeReq) {
413 case GetHubStatus:
414 /* No power source, over-current reported per port */
415 memset(buf, 0, 4);
416 break;
417 case GetHubDescriptor:
418 /* Check to make sure userspace is asking for the USB 3.0 hub
419 * descriptor for the USB 3.0 roothub. If not, we stall the
420 * endpoint, like external hubs do.
421 */
422 if (hcd->speed == HCD_USB3 &&
423 (wLength < USB_DT_SS_HUB_SIZE ||
424 wValue != (USB_DT_SS_HUB << 8))) {
425 xhci_dbg(xhci, "Wrong hub descriptor type for "
426 "USB 3.0 roothub.\n");
427 goto error;
428 }
429 xhci_hub_descriptor(hcd, xhci,
430 (struct usb_hub_descriptor *) buf);
431 break;
432 case GetPortStatus:
433 if (!wIndex || wIndex > max_ports)
434 goto error;
435 wIndex--;
436 status = 0;
437 temp = xhci_readl(xhci, port_array[wIndex]);
438 if (temp == 0xffffffff) {
439 retval = -ENODEV;
440 break;
441 }
442 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp);
443
444 /* wPortChange bits */
445 if (temp & PORT_CSC)
446 status |= USB_PORT_STAT_C_CONNECTION << 16;
447 if (temp & PORT_PEC)
448 status |= USB_PORT_STAT_C_ENABLE << 16;
449 if ((temp & PORT_OCC))
450 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
451 if ((temp & PORT_RC))
452 status |= USB_PORT_STAT_C_RESET << 16;
453 /* USB3.0 only */
454 if (hcd->speed == HCD_USB3) {
455 if ((temp & PORT_PLC))
456 status |= USB_PORT_STAT_C_LINK_STATE << 16;
457 if ((temp & PORT_WRC))
458 status |= USB_PORT_STAT_C_BH_RESET << 16;
459 }
460
461 if (hcd->speed != HCD_USB3) {
462 if ((temp & PORT_PLS_MASK) == XDEV_U3
463 && (temp & PORT_POWER))
464 status |= USB_PORT_STAT_SUSPEND;
465 }
466 if ((temp & PORT_PLS_MASK) == XDEV_RESUME &&
467 !DEV_SUPERSPEED(temp)) {
468 if ((temp & PORT_RESET) || !(temp & PORT_PE))
469 goto error;
470 if (time_after_eq(jiffies,
471 bus_state->resume_done[wIndex])) {
472 xhci_dbg(xhci, "Resume USB2 port %d\n",
473 wIndex + 1);
474 bus_state->resume_done[wIndex] = 0;
475 temp1 = xhci_port_state_to_neutral(temp);
476 temp1 &= ~PORT_PLS_MASK;
477 temp1 |= PORT_LINK_STROBE | XDEV_U0;
478 xhci_writel(xhci, temp1, port_array[wIndex]);
479
480 xhci_dbg(xhci, "set port %d resume\n",
481 wIndex + 1);
482 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
483 wIndex + 1);
484 if (!slot_id) {
485 xhci_dbg(xhci, "slot_id is zero\n");
486 goto error;
487 }
488 xhci_ring_device(xhci, slot_id);
489 bus_state->port_c_suspend |= 1 << wIndex;
490 bus_state->suspended_ports &= ~(1 << wIndex);
491 } else {
492 /*
493 * The resume has been signaling for less than
494 * 20ms. Report the port status as SUSPEND,
495 * let the usbcore check port status again
496 * and clear resume signaling later.
497 */
498 status |= USB_PORT_STAT_SUSPEND;
499 }
500 }
501 if ((temp & PORT_PLS_MASK) == XDEV_U0
502 && (temp & PORT_POWER)
503 && (bus_state->suspended_ports & (1 << wIndex))) {
504 bus_state->suspended_ports &= ~(1 << wIndex);
505 if (hcd->speed != HCD_USB3)
506 bus_state->port_c_suspend |= 1 << wIndex;
507 }
508 if (temp & PORT_CONNECT) {
509 status |= USB_PORT_STAT_CONNECTION;
510 status |= xhci_port_speed(temp);
511 }
512 if (temp & PORT_PE)
513 status |= USB_PORT_STAT_ENABLE;
514 if (temp & PORT_OC)
515 status |= USB_PORT_STAT_OVERCURRENT;
516 if (temp & PORT_RESET)
517 status |= USB_PORT_STAT_RESET;
518 if (temp & PORT_POWER) {
519 if (hcd->speed == HCD_USB3)
520 status |= USB_SS_PORT_STAT_POWER;
521 else
522 status |= USB_PORT_STAT_POWER;
523 }
524 /* Port Link State */
525 if (hcd->speed == HCD_USB3) {
526 /* resume state is a xHCI internal state.
527 * Do not report it to usb core.
528 */
529 if ((temp & PORT_PLS_MASK) != XDEV_RESUME)
530 status |= (temp & PORT_PLS_MASK);
531 }
532 if (bus_state->port_c_suspend & (1 << wIndex))
533 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
534 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
535 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
536 break;
537 case SetPortFeature:
538 if (wValue == USB_PORT_FEAT_LINK_STATE)
539 link_state = (wIndex & 0xff00) >> 3;
540 wIndex &= 0xff;
541 if (!wIndex || wIndex > max_ports)
542 goto error;
543 wIndex--;
544 temp = xhci_readl(xhci, port_array[wIndex]);
545 if (temp == 0xffffffff) {
546 retval = -ENODEV;
547 break;
548 }
549 temp = xhci_port_state_to_neutral(temp);
550 /* FIXME: What new port features do we need to support? */
551 switch (wValue) {
552 case USB_PORT_FEAT_SUSPEND:
553 temp = xhci_readl(xhci, port_array[wIndex]);
554 /* In spec software should not attempt to suspend
555 * a port unless the port reports that it is in the
556 * enabled (PED = ‘1’,PLS < ‘3’) state.
557 */
558 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
559 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
560 xhci_warn(xhci, "USB core suspending device "
561 "not in U0/U1/U2.\n");
562 goto error;
563 }
564
565 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
566 wIndex + 1);
567 if (!slot_id) {
568 xhci_warn(xhci, "slot_id is zero\n");
569 goto error;
570 }
571 /* unlock to execute stop endpoint commands */
572 spin_unlock_irqrestore(&xhci->lock, flags);
573 xhci_stop_device(xhci, slot_id, 1);
574 spin_lock_irqsave(&xhci->lock, flags);
575
576 temp = xhci_port_state_to_neutral(temp);
577 temp &= ~PORT_PLS_MASK;
578 temp |= PORT_LINK_STROBE | XDEV_U3;
579 xhci_writel(xhci, temp, port_array[wIndex]);
580
581 spin_unlock_irqrestore(&xhci->lock, flags);
582 msleep(10); /* wait device to enter */
583 spin_lock_irqsave(&xhci->lock, flags);
584
585 temp = xhci_readl(xhci, port_array[wIndex]);
586 bus_state->suspended_ports |= 1 << wIndex;
587 break;
588 case USB_PORT_FEAT_LINK_STATE:
589 temp = xhci_readl(xhci, port_array[wIndex]);
590 /* Software should not attempt to set
591 * port link state above '5' (Rx.Detect) and the port
592 * must be enabled.
593 */
594 if ((temp & PORT_PE) == 0 ||
595 (link_state > USB_SS_PORT_LS_RX_DETECT)) {
596 xhci_warn(xhci, "Cannot set link state.\n");
597 goto error;
598 }
599
600 if (link_state == USB_SS_PORT_LS_U3) {
601 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
602 wIndex + 1);
603 if (slot_id) {
604 /* unlock to execute stop endpoint
605 * commands */
606 spin_unlock_irqrestore(&xhci->lock,
607 flags);
608 xhci_stop_device(xhci, slot_id, 1);
609 spin_lock_irqsave(&xhci->lock, flags);
610 }
611 }
612
613 temp = xhci_port_state_to_neutral(temp);
614 temp &= ~PORT_PLS_MASK;
615 temp |= PORT_LINK_STROBE | link_state;
616 xhci_writel(xhci, temp, port_array[wIndex]);
617
618 spin_unlock_irqrestore(&xhci->lock, flags);
619 msleep(20); /* wait device to enter */
620 spin_lock_irqsave(&xhci->lock, flags);
621
622 temp = xhci_readl(xhci, port_array[wIndex]);
623 if (link_state == USB_SS_PORT_LS_U3)
624 bus_state->suspended_ports |= 1 << wIndex;
625 break;
626 case USB_PORT_FEAT_POWER:
627 /*
628 * Turn on ports, even if there isn't per-port switching.
629 * HC will report connect events even before this is set.
630 * However, khubd will ignore the roothub events until
631 * the roothub is registered.
632 */
633 xhci_writel(xhci, temp | PORT_POWER,
634 port_array[wIndex]);
635
636 temp = xhci_readl(xhci, port_array[wIndex]);
637 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
638 break;
639 case USB_PORT_FEAT_RESET:
640 temp = (temp | PORT_RESET);
641 xhci_writel(xhci, temp, port_array[wIndex]);
642
643 temp = xhci_readl(xhci, port_array[wIndex]);
644 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
645 break;
646 case USB_PORT_FEAT_BH_PORT_RESET:
647 temp |= PORT_WR;
648 xhci_writel(xhci, temp, port_array[wIndex]);
649
650 temp = xhci_readl(xhci, port_array[wIndex]);
651 break;
652 default:
653 goto error;
654 }
655 /* unblock any posted writes */
656 temp = xhci_readl(xhci, port_array[wIndex]);
657 break;
658 case ClearPortFeature:
659 if (!wIndex || wIndex > max_ports)
660 goto error;
661 wIndex--;
662 temp = xhci_readl(xhci, port_array[wIndex]);
663 if (temp == 0xffffffff) {
664 retval = -ENODEV;
665 break;
666 }
667 /* FIXME: What new port features do we need to support? */
668 temp = xhci_port_state_to_neutral(temp);
669 switch (wValue) {
670 case USB_PORT_FEAT_SUSPEND:
671 temp = xhci_readl(xhci, port_array[wIndex]);
672 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
673 xhci_dbg(xhci, "PORTSC %04x\n", temp);
674 if (temp & PORT_RESET)
675 goto error;
676 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
677 if ((temp & PORT_PE) == 0)
678 goto error;
679
680 temp = xhci_port_state_to_neutral(temp);
681 temp &= ~PORT_PLS_MASK;
682 temp |= PORT_LINK_STROBE | XDEV_RESUME;
683 xhci_writel(xhci, temp,
684 port_array[wIndex]);
685
686 spin_unlock_irqrestore(&xhci->lock,
687 flags);
688 msleep(20);
689 spin_lock_irqsave(&xhci->lock, flags);
690
691 temp = xhci_readl(xhci,
692 port_array[wIndex]);
693 temp = xhci_port_state_to_neutral(temp);
694 temp &= ~PORT_PLS_MASK;
695 temp |= PORT_LINK_STROBE | XDEV_U0;
696 xhci_writel(xhci, temp,
697 port_array[wIndex]);
698 }
699 bus_state->port_c_suspend |= 1 << wIndex;
700
701 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
702 wIndex + 1);
703 if (!slot_id) {
704 xhci_dbg(xhci, "slot_id is zero\n");
705 goto error;
706 }
707 xhci_ring_device(xhci, slot_id);
708 break;
709 case USB_PORT_FEAT_C_SUSPEND:
710 bus_state->port_c_suspend &= ~(1 << wIndex);
711 case USB_PORT_FEAT_C_RESET:
712 case USB_PORT_FEAT_C_BH_PORT_RESET:
713 case USB_PORT_FEAT_C_CONNECTION:
714 case USB_PORT_FEAT_C_OVER_CURRENT:
715 case USB_PORT_FEAT_C_ENABLE:
716 case USB_PORT_FEAT_C_PORT_LINK_STATE:
717 xhci_clear_port_change_bit(xhci, wValue, wIndex,
718 port_array[wIndex], temp);
719 break;
720 case USB_PORT_FEAT_ENABLE:
721 xhci_disable_port(hcd, xhci, wIndex,
722 port_array[wIndex], temp);
723 break;
724 default:
725 goto error;
726 }
727 break;
728 default:
729error:
730 /* "stall" on error */
731 retval = -EPIPE;
732 }
733 spin_unlock_irqrestore(&xhci->lock, flags);
734 return retval;
735}
736
737/*
738 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
739 * Ports are 0-indexed from the HCD point of view,
740 * and 1-indexed from the USB core pointer of view.
741 *
742 * Note that the status change bits will be cleared as soon as a port status
743 * change event is generated, so we use the saved status from that event.
744 */
745int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
746{
747 unsigned long flags;
748 u32 temp, status;
749 u32 mask;
750 int i, retval;
751 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
752 int max_ports;
753 __le32 __iomem **port_array;
754 struct xhci_bus_state *bus_state;
755
756 max_ports = xhci_get_ports(hcd, &port_array);
757 bus_state = &xhci->bus_state[hcd_index(hcd)];
758
759 /* Initial status is no changes */
760 retval = (max_ports + 8) / 8;
761 memset(buf, 0, retval);
762 status = 0;
763
764 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
765
766 spin_lock_irqsave(&xhci->lock, flags);
767 /* For each port, did anything change? If so, set that bit in buf. */
768 for (i = 0; i < max_ports; i++) {
769 temp = xhci_readl(xhci, port_array[i]);
770 if (temp == 0xffffffff) {
771 retval = -ENODEV;
772 break;
773 }
774 if ((temp & mask) != 0 ||
775 (bus_state->port_c_suspend & 1 << i) ||
776 (bus_state->resume_done[i] && time_after_eq(
777 jiffies, bus_state->resume_done[i]))) {
778 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
779 status = 1;
780 }
781 }
782 spin_unlock_irqrestore(&xhci->lock, flags);
783 return status ? retval : 0;
784}
785
786#ifdef CONFIG_PM
787
788int xhci_bus_suspend(struct usb_hcd *hcd)
789{
790 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
791 int max_ports, port_index;
792 __le32 __iomem **port_array;
793 struct xhci_bus_state *bus_state;
794 unsigned long flags;
795
796 max_ports = xhci_get_ports(hcd, &port_array);
797 bus_state = &xhci->bus_state[hcd_index(hcd)];
798
799 spin_lock_irqsave(&xhci->lock, flags);
800
801 if (hcd->self.root_hub->do_remote_wakeup) {
802 port_index = max_ports;
803 while (port_index--) {
804 if (bus_state->resume_done[port_index] != 0) {
805 spin_unlock_irqrestore(&xhci->lock, flags);
806 xhci_dbg(xhci, "suspend failed because "
807 "port %d is resuming\n",
808 port_index + 1);
809 return -EBUSY;
810 }
811 }
812 }
813
814 port_index = max_ports;
815 bus_state->bus_suspended = 0;
816 while (port_index--) {
817 /* suspend the port if the port is not suspended */
818 u32 t1, t2;
819 int slot_id;
820
821 t1 = xhci_readl(xhci, port_array[port_index]);
822 t2 = xhci_port_state_to_neutral(t1);
823
824 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
825 xhci_dbg(xhci, "port %d not suspended\n", port_index);
826 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
827 port_index + 1);
828 if (slot_id) {
829 spin_unlock_irqrestore(&xhci->lock, flags);
830 xhci_stop_device(xhci, slot_id, 1);
831 spin_lock_irqsave(&xhci->lock, flags);
832 }
833 t2 &= ~PORT_PLS_MASK;
834 t2 |= PORT_LINK_STROBE | XDEV_U3;
835 set_bit(port_index, &bus_state->bus_suspended);
836 }
837 if (hcd->self.root_hub->do_remote_wakeup) {
838 if (t1 & PORT_CONNECT) {
839 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
840 t2 &= ~PORT_WKCONN_E;
841 } else {
842 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
843 t2 &= ~PORT_WKDISC_E;
844 }
845 } else
846 t2 &= ~PORT_WAKE_BITS;
847
848 t1 = xhci_port_state_to_neutral(t1);
849 if (t1 != t2)
850 xhci_writel(xhci, t2, port_array[port_index]);
851
852 if (hcd->speed != HCD_USB3) {
853 /* enable remote wake up for USB 2.0 */
854 __le32 __iomem *addr;
855 u32 tmp;
856
857 /* Add one to the port status register address to get
858 * the port power control register address.
859 */
860 addr = port_array[port_index] + 1;
861 tmp = xhci_readl(xhci, addr);
862 tmp |= PORT_RWE;
863 xhci_writel(xhci, tmp, addr);
864 }
865 }
866 hcd->state = HC_STATE_SUSPENDED;
867 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
868 spin_unlock_irqrestore(&xhci->lock, flags);
869 return 0;
870}
871
872int xhci_bus_resume(struct usb_hcd *hcd)
873{
874 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
875 int max_ports, port_index;
876 __le32 __iomem **port_array;
877 struct xhci_bus_state *bus_state;
878 u32 temp;
879 unsigned long flags;
880
881 max_ports = xhci_get_ports(hcd, &port_array);
882 bus_state = &xhci->bus_state[hcd_index(hcd)];
883
884 if (time_before(jiffies, bus_state->next_statechange))
885 msleep(5);
886
887 spin_lock_irqsave(&xhci->lock, flags);
888 if (!HCD_HW_ACCESSIBLE(hcd)) {
889 spin_unlock_irqrestore(&xhci->lock, flags);
890 return -ESHUTDOWN;
891 }
892
893 /* delay the irqs */
894 temp = xhci_readl(xhci, &xhci->op_regs->command);
895 temp &= ~CMD_EIE;
896 xhci_writel(xhci, temp, &xhci->op_regs->command);
897
898 port_index = max_ports;
899 while (port_index--) {
900 /* Check whether need resume ports. If needed
901 resume port and disable remote wakeup */
902 u32 temp;
903 int slot_id;
904
905 temp = xhci_readl(xhci, port_array[port_index]);
906 if (DEV_SUPERSPEED(temp))
907 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
908 else
909 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
910 if (test_bit(port_index, &bus_state->bus_suspended) &&
911 (temp & PORT_PLS_MASK)) {
912 if (DEV_SUPERSPEED(temp)) {
913 temp = xhci_port_state_to_neutral(temp);
914 temp &= ~PORT_PLS_MASK;
915 temp |= PORT_LINK_STROBE | XDEV_U0;
916 xhci_writel(xhci, temp, port_array[port_index]);
917 } else {
918 temp = xhci_port_state_to_neutral(temp);
919 temp &= ~PORT_PLS_MASK;
920 temp |= PORT_LINK_STROBE | XDEV_RESUME;
921 xhci_writel(xhci, temp, port_array[port_index]);
922
923 spin_unlock_irqrestore(&xhci->lock, flags);
924 msleep(20);
925 spin_lock_irqsave(&xhci->lock, flags);
926
927 temp = xhci_readl(xhci, port_array[port_index]);
928 temp = xhci_port_state_to_neutral(temp);
929 temp &= ~PORT_PLS_MASK;
930 temp |= PORT_LINK_STROBE | XDEV_U0;
931 xhci_writel(xhci, temp, port_array[port_index]);
932 }
933 /* wait for the port to enter U0 and report port link
934 * state change.
935 */
936 spin_unlock_irqrestore(&xhci->lock, flags);
937 msleep(20);
938 spin_lock_irqsave(&xhci->lock, flags);
939
940 /* Clear PLC */
941 temp = xhci_readl(xhci, port_array[port_index]);
942 if (temp & PORT_PLC) {
943 temp = xhci_port_state_to_neutral(temp);
944 temp |= PORT_PLC;
945 xhci_writel(xhci, temp, port_array[port_index]);
946 }
947
948 slot_id = xhci_find_slot_id_by_port(hcd,
949 xhci, port_index + 1);
950 if (slot_id)
951 xhci_ring_device(xhci, slot_id);
952 } else
953 xhci_writel(xhci, temp, port_array[port_index]);
954
955 if (hcd->speed != HCD_USB3) {
956 /* disable remote wake up for USB 2.0 */
957 __le32 __iomem *addr;
958 u32 tmp;
959
960 /* Add one to the port status register address to get
961 * the port power control register address.
962 */
963 addr = port_array[port_index] + 1;
964 tmp = xhci_readl(xhci, addr);
965 tmp &= ~PORT_RWE;
966 xhci_writel(xhci, tmp, addr);
967 }
968 }
969
970 (void) xhci_readl(xhci, &xhci->op_regs->command);
971
972 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
973 /* re-enable irqs */
974 temp = xhci_readl(xhci, &xhci->op_regs->command);
975 temp |= CMD_EIE;
976 xhci_writel(xhci, temp, &xhci->op_regs->command);
977 temp = xhci_readl(xhci, &xhci->op_regs->command);
978
979 spin_unlock_irqrestore(&xhci->lock, flags);
980 return 0;
981}
982
983#endif /* CONFIG_PM */
1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23
24#include <linux/slab.h>
25#include <asm/unaligned.h>
26
27#include "xhci.h"
28#include "xhci-trace.h"
29
30#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
32 PORT_RC | PORT_PLC | PORT_PE)
33
34/* USB 3 BOS descriptor and a capability descriptors, combined.
35 * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
36 */
37static u8 usb_bos_descriptor [] = {
38 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
39 USB_DT_BOS, /* __u8 bDescriptorType */
40 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
41 0x1, /* __u8 bNumDeviceCaps */
42 /* First device capability, SuperSpeed */
43 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
44 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
45 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
46 0x00, /* bmAttributes, LTM off by default */
47 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
48 0x03, /* bFunctionalitySupport,
49 USB 3.0 speed only */
50 0x00, /* bU1DevExitLat, set later. */
51 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
52 /* Second device capability, SuperSpeedPlus */
53 0x1c, /* bLength 28, will be adjusted later */
54 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
55 USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */
56 0x00, /* bReserved 0 */
57 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */
58 0x01, 0x00, /* wFunctionalitySupport */
59 0x00, 0x00, /* wReserved 0 */
60 /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
61 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */
62 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */
63 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */
64 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */
65};
66
67static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
68 u16 wLength)
69{
70 int i, ssa_count;
71 u32 temp;
72 u16 desc_size, ssp_cap_size, ssa_size = 0;
73 bool usb3_1 = false;
74
75 desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
76 ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
77
78 /* does xhci support USB 3.1 Enhanced SuperSpeed */
79 if (xhci->usb3_rhub.min_rev >= 0x01) {
80 /* does xhci provide a PSI table for SSA speed attributes? */
81 if (xhci->usb3_rhub.psi_count) {
82 /* two SSA entries for each unique PSI ID, RX and TX */
83 ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
84 ssa_size = ssa_count * sizeof(u32);
85 ssp_cap_size -= 16; /* skip copying the default SSA */
86 }
87 desc_size += ssp_cap_size;
88 usb3_1 = true;
89 }
90 memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
91
92 if (usb3_1) {
93 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
94 buf[4] += 1;
95 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
96 }
97
98 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
99 return wLength;
100
101 /* Indicate whether the host has LTM support. */
102 temp = readl(&xhci->cap_regs->hcc_params);
103 if (HCC_LTC(temp))
104 buf[8] |= USB_LTM_SUPPORT;
105
106 /* Set the U1 and U2 exit latencies. */
107 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
108 temp = readl(&xhci->cap_regs->hcs_params3);
109 buf[12] = HCS_U1_LATENCY(temp);
110 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
111 }
112
113 /* If PSI table exists, add the custom speed attributes from it */
114 if (usb3_1 && xhci->usb3_rhub.psi_count) {
115 u32 ssp_cap_base, bm_attrib, psi;
116 int offset;
117
118 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
119
120 if (wLength < desc_size)
121 return wLength;
122 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
123
124 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
125 bm_attrib = (ssa_count - 1) & 0x1f;
126 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
127 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
128
129 if (wLength < desc_size + ssa_size)
130 return wLength;
131 /*
132 * Create the Sublink Speed Attributes (SSA) array.
133 * The xhci PSI field and USB 3.1 SSA fields are very similar,
134 * but link type bits 7:6 differ for values 01b and 10b.
135 * xhci has also only one PSI entry for a symmetric link when
136 * USB 3.1 requires two SSA entries (RX and TX) for every link
137 */
138 offset = desc_size;
139 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
140 psi = xhci->usb3_rhub.psi[i];
141 psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
142 if ((psi & PLT_MASK) == PLT_SYM) {
143 /* Symmetric, create SSA RX and TX from one PSI entry */
144 put_unaligned_le32(psi, &buf[offset]);
145 psi |= 1 << 7; /* turn entry to TX */
146 offset += 4;
147 if (offset >= desc_size + ssa_size)
148 return desc_size + ssa_size;
149 } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
150 /* Asymetric RX, flip bits 7:6 for SSA */
151 psi ^= PLT_MASK;
152 }
153 put_unaligned_le32(psi, &buf[offset]);
154 offset += 4;
155 if (offset >= desc_size + ssa_size)
156 return desc_size + ssa_size;
157 }
158 }
159 /* ssa_size is 0 for other than usb 3.1 hosts */
160 return desc_size + ssa_size;
161}
162
163static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
164 struct usb_hub_descriptor *desc, int ports)
165{
166 u16 temp;
167
168 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
169 desc->bHubContrCurrent = 0;
170
171 desc->bNbrPorts = ports;
172 temp = 0;
173 /* Bits 1:0 - support per-port power switching, or power always on */
174 if (HCC_PPC(xhci->hcc_params))
175 temp |= HUB_CHAR_INDV_PORT_LPSM;
176 else
177 temp |= HUB_CHAR_NO_LPSM;
178 /* Bit 2 - root hubs are not part of a compound device */
179 /* Bits 4:3 - individual port over current protection */
180 temp |= HUB_CHAR_INDV_PORT_OCPM;
181 /* Bits 6:5 - no TTs in root ports */
182 /* Bit 7 - no port indicators */
183 desc->wHubCharacteristics = cpu_to_le16(temp);
184}
185
186/* Fill in the USB 2.0 roothub descriptor */
187static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
188 struct usb_hub_descriptor *desc)
189{
190 int ports;
191 u16 temp;
192 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
193 u32 portsc;
194 unsigned int i;
195
196 ports = xhci->num_usb2_ports;
197
198 xhci_common_hub_descriptor(xhci, desc, ports);
199 desc->bDescriptorType = USB_DT_HUB;
200 temp = 1 + (ports / 8);
201 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
202
203 /* The Device Removable bits are reported on a byte granularity.
204 * If the port doesn't exist within that byte, the bit is set to 0.
205 */
206 memset(port_removable, 0, sizeof(port_removable));
207 for (i = 0; i < ports; i++) {
208 portsc = readl(xhci->usb2_ports[i]);
209 /* If a device is removable, PORTSC reports a 0, same as in the
210 * hub descriptor DeviceRemovable bits.
211 */
212 if (portsc & PORT_DEV_REMOVE)
213 /* This math is hairy because bit 0 of DeviceRemovable
214 * is reserved, and bit 1 is for port 1, etc.
215 */
216 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
217 }
218
219 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
220 * ports on it. The USB 2.0 specification says that there are two
221 * variable length fields at the end of the hub descriptor:
222 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
223 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
224 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
225 * 0xFF, so we initialize the both arrays (DeviceRemovable and
226 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
227 * set of ports that actually exist.
228 */
229 memset(desc->u.hs.DeviceRemovable, 0xff,
230 sizeof(desc->u.hs.DeviceRemovable));
231 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
232 sizeof(desc->u.hs.PortPwrCtrlMask));
233
234 for (i = 0; i < (ports + 1 + 7) / 8; i++)
235 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
236 sizeof(__u8));
237}
238
239/* Fill in the USB 3.0 roothub descriptor */
240static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
241 struct usb_hub_descriptor *desc)
242{
243 int ports;
244 u16 port_removable;
245 u32 portsc;
246 unsigned int i;
247
248 ports = xhci->num_usb3_ports;
249 xhci_common_hub_descriptor(xhci, desc, ports);
250 desc->bDescriptorType = USB_DT_SS_HUB;
251 desc->bDescLength = USB_DT_SS_HUB_SIZE;
252
253 /* header decode latency should be zero for roothubs,
254 * see section 4.23.5.2.
255 */
256 desc->u.ss.bHubHdrDecLat = 0;
257 desc->u.ss.wHubDelay = 0;
258
259 port_removable = 0;
260 /* bit 0 is reserved, bit 1 is for port 1, etc. */
261 for (i = 0; i < ports; i++) {
262 portsc = readl(xhci->usb3_ports[i]);
263 if (portsc & PORT_DEV_REMOVE)
264 port_removable |= 1 << (i + 1);
265 }
266
267 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
268}
269
270static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
271 struct usb_hub_descriptor *desc)
272{
273
274 if (hcd->speed >= HCD_USB3)
275 xhci_usb3_hub_descriptor(hcd, xhci, desc);
276 else
277 xhci_usb2_hub_descriptor(hcd, xhci, desc);
278
279}
280
281static unsigned int xhci_port_speed(unsigned int port_status)
282{
283 if (DEV_LOWSPEED(port_status))
284 return USB_PORT_STAT_LOW_SPEED;
285 if (DEV_HIGHSPEED(port_status))
286 return USB_PORT_STAT_HIGH_SPEED;
287 /*
288 * FIXME: Yes, we should check for full speed, but the core uses that as
289 * a default in portspeed() in usb/core/hub.c (which is the only place
290 * USB_PORT_STAT_*_SPEED is used).
291 */
292 return 0;
293}
294
295/*
296 * These bits are Read Only (RO) and should be saved and written to the
297 * registers: 0, 3, 10:13, 30
298 * connect status, over-current status, port speed, and device removable.
299 * connect status and port speed are also sticky - meaning they're in
300 * the AUX well and they aren't changed by a hot, warm, or cold reset.
301 */
302#define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
303/*
304 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
305 * bits 5:8, 9, 14:15, 25:27
306 * link state, port power, port indicator state, "wake on" enable state
307 */
308#define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
309/*
310 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
311 * bit 4 (port reset)
312 */
313#define XHCI_PORT_RW1S ((1<<4))
314/*
315 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
316 * bits 1, 17, 18, 19, 20, 21, 22, 23
317 * port enable/disable, and
318 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
319 * over-current, reset, link state, and L1 change
320 */
321#define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
322/*
323 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
324 * latched in
325 */
326#define XHCI_PORT_RW ((1<<16))
327/*
328 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
329 * bits 2, 24, 28:31
330 */
331#define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
332
333/*
334 * Given a port state, this function returns a value that would result in the
335 * port being in the same state, if the value was written to the port status
336 * control register.
337 * Save Read Only (RO) bits and save read/write bits where
338 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
339 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
340 */
341u32 xhci_port_state_to_neutral(u32 state)
342{
343 /* Save read-only status and port state */
344 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
345}
346
347/*
348 * find slot id based on port number.
349 * @port: The one-based port number from one of the two split roothubs.
350 */
351int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
352 u16 port)
353{
354 int slot_id;
355 int i;
356 enum usb_device_speed speed;
357
358 slot_id = 0;
359 for (i = 0; i < MAX_HC_SLOTS; i++) {
360 if (!xhci->devs[i])
361 continue;
362 speed = xhci->devs[i]->udev->speed;
363 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
364 && xhci->devs[i]->fake_port == port) {
365 slot_id = i;
366 break;
367 }
368 }
369
370 return slot_id;
371}
372
373/*
374 * Stop device
375 * It issues stop endpoint command for EP 0 to 30. And wait the last command
376 * to complete.
377 * suspend will set to 1, if suspend bit need to set in command.
378 */
379static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
380{
381 struct xhci_virt_device *virt_dev;
382 struct xhci_command *cmd;
383 unsigned long flags;
384 int ret;
385 int i;
386
387 ret = 0;
388 virt_dev = xhci->devs[slot_id];
389 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
390 if (!cmd) {
391 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
392 return -ENOMEM;
393 }
394
395 spin_lock_irqsave(&xhci->lock, flags);
396 for (i = LAST_EP_INDEX; i > 0; i--) {
397 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
398 struct xhci_command *command;
399 command = xhci_alloc_command(xhci, false, false,
400 GFP_NOWAIT);
401 if (!command) {
402 spin_unlock_irqrestore(&xhci->lock, flags);
403 xhci_free_command(xhci, cmd);
404 return -ENOMEM;
405
406 }
407 xhci_queue_stop_endpoint(xhci, command, slot_id, i,
408 suspend);
409 }
410 }
411 xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
412 xhci_ring_cmd_db(xhci);
413 spin_unlock_irqrestore(&xhci->lock, flags);
414
415 /* Wait for last stop endpoint command to finish */
416 wait_for_completion(cmd->completion);
417
418 if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) {
419 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
420 ret = -ETIME;
421 }
422 xhci_free_command(xhci, cmd);
423 return ret;
424}
425
426/*
427 * Ring device, it rings the all doorbells unconditionally.
428 */
429void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
430{
431 int i, s;
432 struct xhci_virt_ep *ep;
433
434 for (i = 0; i < LAST_EP_INDEX + 1; i++) {
435 ep = &xhci->devs[slot_id]->eps[i];
436
437 if (ep->ep_state & EP_HAS_STREAMS) {
438 for (s = 1; s < ep->stream_info->num_streams; s++)
439 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
440 } else if (ep->ring && ep->ring->dequeue) {
441 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
442 }
443 }
444
445 return;
446}
447
448static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
449 u16 wIndex, __le32 __iomem *addr, u32 port_status)
450{
451 /* Don't allow the USB core to disable SuperSpeed ports. */
452 if (hcd->speed >= HCD_USB3) {
453 xhci_dbg(xhci, "Ignoring request to disable "
454 "SuperSpeed port.\n");
455 return;
456 }
457
458 /* Write 1 to disable the port */
459 writel(port_status | PORT_PE, addr);
460 port_status = readl(addr);
461 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
462 wIndex, port_status);
463}
464
465static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
466 u16 wIndex, __le32 __iomem *addr, u32 port_status)
467{
468 char *port_change_bit;
469 u32 status;
470
471 switch (wValue) {
472 case USB_PORT_FEAT_C_RESET:
473 status = PORT_RC;
474 port_change_bit = "reset";
475 break;
476 case USB_PORT_FEAT_C_BH_PORT_RESET:
477 status = PORT_WRC;
478 port_change_bit = "warm(BH) reset";
479 break;
480 case USB_PORT_FEAT_C_CONNECTION:
481 status = PORT_CSC;
482 port_change_bit = "connect";
483 break;
484 case USB_PORT_FEAT_C_OVER_CURRENT:
485 status = PORT_OCC;
486 port_change_bit = "over-current";
487 break;
488 case USB_PORT_FEAT_C_ENABLE:
489 status = PORT_PEC;
490 port_change_bit = "enable/disable";
491 break;
492 case USB_PORT_FEAT_C_SUSPEND:
493 status = PORT_PLC;
494 port_change_bit = "suspend/resume";
495 break;
496 case USB_PORT_FEAT_C_PORT_LINK_STATE:
497 status = PORT_PLC;
498 port_change_bit = "link state";
499 break;
500 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
501 status = PORT_CEC;
502 port_change_bit = "config error";
503 break;
504 default:
505 /* Should never happen */
506 return;
507 }
508 /* Change bits are all write 1 to clear */
509 writel(port_status | status, addr);
510 port_status = readl(addr);
511 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
512 port_change_bit, wIndex, port_status);
513}
514
515static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
516{
517 int max_ports;
518 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
519
520 if (hcd->speed >= HCD_USB3) {
521 max_ports = xhci->num_usb3_ports;
522 *port_array = xhci->usb3_ports;
523 } else {
524 max_ports = xhci->num_usb2_ports;
525 *port_array = xhci->usb2_ports;
526 }
527
528 return max_ports;
529}
530
531void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
532 int port_id, u32 link_state)
533{
534 u32 temp;
535
536 temp = readl(port_array[port_id]);
537 temp = xhci_port_state_to_neutral(temp);
538 temp &= ~PORT_PLS_MASK;
539 temp |= PORT_LINK_STROBE | link_state;
540 writel(temp, port_array[port_id]);
541}
542
543static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
544 __le32 __iomem **port_array, int port_id, u16 wake_mask)
545{
546 u32 temp;
547
548 temp = readl(port_array[port_id]);
549 temp = xhci_port_state_to_neutral(temp);
550
551 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
552 temp |= PORT_WKCONN_E;
553 else
554 temp &= ~PORT_WKCONN_E;
555
556 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
557 temp |= PORT_WKDISC_E;
558 else
559 temp &= ~PORT_WKDISC_E;
560
561 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
562 temp |= PORT_WKOC_E;
563 else
564 temp &= ~PORT_WKOC_E;
565
566 writel(temp, port_array[port_id]);
567}
568
569/* Test and clear port RWC bit */
570void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
571 int port_id, u32 port_bit)
572{
573 u32 temp;
574
575 temp = readl(port_array[port_id]);
576 if (temp & port_bit) {
577 temp = xhci_port_state_to_neutral(temp);
578 temp |= port_bit;
579 writel(temp, port_array[port_id]);
580 }
581}
582
583/* Updates Link Status for USB 2.1 port */
584static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
585{
586 if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
587 *status |= USB_PORT_STAT_L1;
588}
589
590/* Updates Link Status for super Speed port */
591static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
592 u32 *status, u32 status_reg)
593{
594 u32 pls = status_reg & PORT_PLS_MASK;
595
596 /* resume state is a xHCI internal state.
597 * Do not report it to usb core, instead, pretend to be U3,
598 * thus usb core knows it's not ready for transfer
599 */
600 if (pls == XDEV_RESUME) {
601 *status |= USB_SS_PORT_LS_U3;
602 return;
603 }
604
605 /* When the CAS bit is set then warm reset
606 * should be performed on port
607 */
608 if (status_reg & PORT_CAS) {
609 /* The CAS bit can be set while the port is
610 * in any link state.
611 * Only roothubs have CAS bit, so we
612 * pretend to be in compliance mode
613 * unless we're already in compliance
614 * or the inactive state.
615 */
616 if (pls != USB_SS_PORT_LS_COMP_MOD &&
617 pls != USB_SS_PORT_LS_SS_INACTIVE) {
618 pls = USB_SS_PORT_LS_COMP_MOD;
619 }
620 /* Return also connection bit -
621 * hub state machine resets port
622 * when this bit is set.
623 */
624 pls |= USB_PORT_STAT_CONNECTION;
625 } else {
626 /*
627 * If CAS bit isn't set but the Port is already at
628 * Compliance Mode, fake a connection so the USB core
629 * notices the Compliance state and resets the port.
630 * This resolves an issue generated by the SN65LVPE502CP
631 * in which sometimes the port enters compliance mode
632 * caused by a delay on the host-device negotiation.
633 */
634 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
635 (pls == USB_SS_PORT_LS_COMP_MOD))
636 pls |= USB_PORT_STAT_CONNECTION;
637 }
638
639 /* update status field */
640 *status |= pls;
641}
642
643/*
644 * Function for Compliance Mode Quirk.
645 *
646 * This Function verifies if all xhc USB3 ports have entered U0, if so,
647 * the compliance mode timer is deleted. A port won't enter
648 * compliance mode if it has previously entered U0.
649 */
650static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
651 u16 wIndex)
652{
653 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
654 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
655
656 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
657 return;
658
659 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
660 xhci->port_status_u0 |= 1 << wIndex;
661 if (xhci->port_status_u0 == all_ports_seen_u0) {
662 del_timer_sync(&xhci->comp_mode_recovery_timer);
663 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
664 "All USB3 ports have entered U0 already!");
665 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
666 "Compliance Mode Recovery Timer Deleted.");
667 }
668 }
669}
670
671static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
672{
673 u32 ext_stat = 0;
674 int speed_id;
675
676 /* only support rx and tx lane counts of 1 in usb3.1 spec */
677 speed_id = DEV_PORT_SPEED(raw_port_status);
678 ext_stat |= speed_id; /* bits 3:0, RX speed id */
679 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */
680
681 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */
682 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
683
684 return ext_stat;
685}
686
687/*
688 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
689 * 3.0 hubs use.
690 *
691 * Possible side effects:
692 * - Mark a port as being done with device resume,
693 * and ring the endpoint doorbells.
694 * - Stop the Synopsys redriver Compliance Mode polling.
695 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
696 */
697static u32 xhci_get_port_status(struct usb_hcd *hcd,
698 struct xhci_bus_state *bus_state,
699 __le32 __iomem **port_array,
700 u16 wIndex, u32 raw_port_status,
701 unsigned long flags)
702 __releases(&xhci->lock)
703 __acquires(&xhci->lock)
704{
705 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
706 u32 status = 0;
707 int slot_id;
708
709 /* wPortChange bits */
710 if (raw_port_status & PORT_CSC)
711 status |= USB_PORT_STAT_C_CONNECTION << 16;
712 if (raw_port_status & PORT_PEC)
713 status |= USB_PORT_STAT_C_ENABLE << 16;
714 if ((raw_port_status & PORT_OCC))
715 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
716 if ((raw_port_status & PORT_RC))
717 status |= USB_PORT_STAT_C_RESET << 16;
718 /* USB3.0 only */
719 if (hcd->speed >= HCD_USB3) {
720 /* Port link change with port in resume state should not be
721 * reported to usbcore, as this is an internal state to be
722 * handled by xhci driver. Reporting PLC to usbcore may
723 * cause usbcore clearing PLC first and port change event
724 * irq won't be generated.
725 */
726 if ((raw_port_status & PORT_PLC) &&
727 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
728 status |= USB_PORT_STAT_C_LINK_STATE << 16;
729 if ((raw_port_status & PORT_WRC))
730 status |= USB_PORT_STAT_C_BH_RESET << 16;
731 if ((raw_port_status & PORT_CEC))
732 status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
733 }
734
735 if (hcd->speed < HCD_USB3) {
736 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
737 && (raw_port_status & PORT_POWER))
738 status |= USB_PORT_STAT_SUSPEND;
739 }
740 if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
741 !DEV_SUPERSPEED_ANY(raw_port_status)) {
742 if ((raw_port_status & PORT_RESET) ||
743 !(raw_port_status & PORT_PE))
744 return 0xffffffff;
745 /* did port event handler already start resume timing? */
746 if (!bus_state->resume_done[wIndex]) {
747 /* If not, maybe we are in a host initated resume? */
748 if (test_bit(wIndex, &bus_state->resuming_ports)) {
749 /* Host initated resume doesn't time the resume
750 * signalling using resume_done[].
751 * It manually sets RESUME state, sleeps 20ms
752 * and sets U0 state. This should probably be
753 * changed, but not right now.
754 */
755 } else {
756 /* port resume was discovered now and here,
757 * start resume timing
758 */
759 unsigned long timeout = jiffies +
760 msecs_to_jiffies(USB_RESUME_TIMEOUT);
761
762 set_bit(wIndex, &bus_state->resuming_ports);
763 bus_state->resume_done[wIndex] = timeout;
764 mod_timer(&hcd->rh_timer, timeout);
765 }
766 /* Has resume been signalled for USB_RESUME_TIME yet? */
767 } else if (time_after_eq(jiffies,
768 bus_state->resume_done[wIndex])) {
769 int time_left;
770
771 xhci_dbg(xhci, "Resume USB2 port %d\n",
772 wIndex + 1);
773 bus_state->resume_done[wIndex] = 0;
774 clear_bit(wIndex, &bus_state->resuming_ports);
775
776 set_bit(wIndex, &bus_state->rexit_ports);
777 xhci_set_link_state(xhci, port_array, wIndex,
778 XDEV_U0);
779
780 spin_unlock_irqrestore(&xhci->lock, flags);
781 time_left = wait_for_completion_timeout(
782 &bus_state->rexit_done[wIndex],
783 msecs_to_jiffies(
784 XHCI_MAX_REXIT_TIMEOUT));
785 spin_lock_irqsave(&xhci->lock, flags);
786
787 if (time_left) {
788 slot_id = xhci_find_slot_id_by_port(hcd,
789 xhci, wIndex + 1);
790 if (!slot_id) {
791 xhci_dbg(xhci, "slot_id is zero\n");
792 return 0xffffffff;
793 }
794 xhci_ring_device(xhci, slot_id);
795 } else {
796 int port_status = readl(port_array[wIndex]);
797 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
798 XHCI_MAX_REXIT_TIMEOUT,
799 port_status);
800 status |= USB_PORT_STAT_SUSPEND;
801 clear_bit(wIndex, &bus_state->rexit_ports);
802 }
803
804 bus_state->port_c_suspend |= 1 << wIndex;
805 bus_state->suspended_ports &= ~(1 << wIndex);
806 } else {
807 /*
808 * The resume has been signaling for less than
809 * USB_RESUME_TIME. Report the port status as SUSPEND,
810 * let the usbcore check port status again and clear
811 * resume signaling later.
812 */
813 status |= USB_PORT_STAT_SUSPEND;
814 }
815 }
816 /*
817 * Clear stale usb2 resume signalling variables in case port changed
818 * state during resume signalling. For example on error
819 */
820 if ((bus_state->resume_done[wIndex] ||
821 test_bit(wIndex, &bus_state->resuming_ports)) &&
822 (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
823 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
824 bus_state->resume_done[wIndex] = 0;
825 clear_bit(wIndex, &bus_state->resuming_ports);
826 }
827
828
829 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
830 (raw_port_status & PORT_POWER)) {
831 if (bus_state->suspended_ports & (1 << wIndex)) {
832 bus_state->suspended_ports &= ~(1 << wIndex);
833 if (hcd->speed < HCD_USB3)
834 bus_state->port_c_suspend |= 1 << wIndex;
835 }
836 bus_state->resume_done[wIndex] = 0;
837 clear_bit(wIndex, &bus_state->resuming_ports);
838 }
839 if (raw_port_status & PORT_CONNECT) {
840 status |= USB_PORT_STAT_CONNECTION;
841 status |= xhci_port_speed(raw_port_status);
842 }
843 if (raw_port_status & PORT_PE)
844 status |= USB_PORT_STAT_ENABLE;
845 if (raw_port_status & PORT_OC)
846 status |= USB_PORT_STAT_OVERCURRENT;
847 if (raw_port_status & PORT_RESET)
848 status |= USB_PORT_STAT_RESET;
849 if (raw_port_status & PORT_POWER) {
850 if (hcd->speed >= HCD_USB3)
851 status |= USB_SS_PORT_STAT_POWER;
852 else
853 status |= USB_PORT_STAT_POWER;
854 }
855 /* Update Port Link State */
856 if (hcd->speed >= HCD_USB3) {
857 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
858 /*
859 * Verify if all USB3 Ports Have entered U0 already.
860 * Delete Compliance Mode Timer if so.
861 */
862 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
863 } else {
864 xhci_hub_report_usb2_link_state(&status, raw_port_status);
865 }
866 if (bus_state->port_c_suspend & (1 << wIndex))
867 status |= USB_PORT_STAT_C_SUSPEND << 16;
868
869 return status;
870}
871
872int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
873 u16 wIndex, char *buf, u16 wLength)
874{
875 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
876 int max_ports;
877 unsigned long flags;
878 u32 temp, status;
879 int retval = 0;
880 __le32 __iomem **port_array;
881 int slot_id;
882 struct xhci_bus_state *bus_state;
883 u16 link_state = 0;
884 u16 wake_mask = 0;
885 u16 timeout = 0;
886
887 max_ports = xhci_get_ports(hcd, &port_array);
888 bus_state = &xhci->bus_state[hcd_index(hcd)];
889
890 spin_lock_irqsave(&xhci->lock, flags);
891 switch (typeReq) {
892 case GetHubStatus:
893 /* No power source, over-current reported per port */
894 memset(buf, 0, 4);
895 break;
896 case GetHubDescriptor:
897 /* Check to make sure userspace is asking for the USB 3.0 hub
898 * descriptor for the USB 3.0 roothub. If not, we stall the
899 * endpoint, like external hubs do.
900 */
901 if (hcd->speed >= HCD_USB3 &&
902 (wLength < USB_DT_SS_HUB_SIZE ||
903 wValue != (USB_DT_SS_HUB << 8))) {
904 xhci_dbg(xhci, "Wrong hub descriptor type for "
905 "USB 3.0 roothub.\n");
906 goto error;
907 }
908 xhci_hub_descriptor(hcd, xhci,
909 (struct usb_hub_descriptor *) buf);
910 break;
911 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
912 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
913 goto error;
914
915 if (hcd->speed < HCD_USB3)
916 goto error;
917
918 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
919 spin_unlock_irqrestore(&xhci->lock, flags);
920 return retval;
921 case GetPortStatus:
922 if (!wIndex || wIndex > max_ports)
923 goto error;
924 wIndex--;
925 temp = readl(port_array[wIndex]);
926 if (temp == 0xffffffff) {
927 retval = -ENODEV;
928 break;
929 }
930 status = xhci_get_port_status(hcd, bus_state, port_array,
931 wIndex, temp, flags);
932 if (status == 0xffffffff)
933 goto error;
934
935 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n",
936 wIndex, temp);
937 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
938
939 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
940 /* if USB 3.1 extended port status return additional 4 bytes */
941 if (wValue == 0x02) {
942 u32 port_li;
943
944 if (hcd->speed < HCD_USB31 || wLength != 8) {
945 xhci_err(xhci, "get ext port status invalid parameter\n");
946 retval = -EINVAL;
947 break;
948 }
949 port_li = readl(port_array[wIndex] + PORTLI);
950 status = xhci_get_ext_port_status(temp, port_li);
951 put_unaligned_le32(cpu_to_le32(status), &buf[4]);
952 }
953 break;
954 case SetPortFeature:
955 if (wValue == USB_PORT_FEAT_LINK_STATE)
956 link_state = (wIndex & 0xff00) >> 3;
957 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
958 wake_mask = wIndex & 0xff00;
959 /* The MSB of wIndex is the U1/U2 timeout */
960 timeout = (wIndex & 0xff00) >> 8;
961 wIndex &= 0xff;
962 if (!wIndex || wIndex > max_ports)
963 goto error;
964 wIndex--;
965 temp = readl(port_array[wIndex]);
966 if (temp == 0xffffffff) {
967 retval = -ENODEV;
968 break;
969 }
970 temp = xhci_port_state_to_neutral(temp);
971 /* FIXME: What new port features do we need to support? */
972 switch (wValue) {
973 case USB_PORT_FEAT_SUSPEND:
974 temp = readl(port_array[wIndex]);
975 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
976 /* Resume the port to U0 first */
977 xhci_set_link_state(xhci, port_array, wIndex,
978 XDEV_U0);
979 spin_unlock_irqrestore(&xhci->lock, flags);
980 msleep(10);
981 spin_lock_irqsave(&xhci->lock, flags);
982 }
983 /* In spec software should not attempt to suspend
984 * a port unless the port reports that it is in the
985 * enabled (PED = ‘1’,PLS < ‘3’) state.
986 */
987 temp = readl(port_array[wIndex]);
988 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
989 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
990 xhci_warn(xhci, "USB core suspending device "
991 "not in U0/U1/U2.\n");
992 goto error;
993 }
994
995 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
996 wIndex + 1);
997 if (!slot_id) {
998 xhci_warn(xhci, "slot_id is zero\n");
999 goto error;
1000 }
1001 /* unlock to execute stop endpoint commands */
1002 spin_unlock_irqrestore(&xhci->lock, flags);
1003 xhci_stop_device(xhci, slot_id, 1);
1004 spin_lock_irqsave(&xhci->lock, flags);
1005
1006 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1007
1008 spin_unlock_irqrestore(&xhci->lock, flags);
1009 msleep(10); /* wait device to enter */
1010 spin_lock_irqsave(&xhci->lock, flags);
1011
1012 temp = readl(port_array[wIndex]);
1013 bus_state->suspended_ports |= 1 << wIndex;
1014 break;
1015 case USB_PORT_FEAT_LINK_STATE:
1016 temp = readl(port_array[wIndex]);
1017
1018 /* Disable port */
1019 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1020 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1021 temp = xhci_port_state_to_neutral(temp);
1022 /*
1023 * Clear all change bits, so that we get a new
1024 * connection event.
1025 */
1026 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1027 PORT_OCC | PORT_RC | PORT_PLC |
1028 PORT_CEC;
1029 writel(temp | PORT_PE, port_array[wIndex]);
1030 temp = readl(port_array[wIndex]);
1031 break;
1032 }
1033
1034 /* Put link in RxDetect (enable port) */
1035 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1036 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1037 xhci_set_link_state(xhci, port_array, wIndex,
1038 link_state);
1039 temp = readl(port_array[wIndex]);
1040 break;
1041 }
1042
1043 /* Software should not attempt to set
1044 * port link state above '3' (U3) and the port
1045 * must be enabled.
1046 */
1047 if ((temp & PORT_PE) == 0 ||
1048 (link_state > USB_SS_PORT_LS_U3)) {
1049 xhci_warn(xhci, "Cannot set link state.\n");
1050 goto error;
1051 }
1052
1053 if (link_state == USB_SS_PORT_LS_U3) {
1054 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1055 wIndex + 1);
1056 if (slot_id) {
1057 /* unlock to execute stop endpoint
1058 * commands */
1059 spin_unlock_irqrestore(&xhci->lock,
1060 flags);
1061 xhci_stop_device(xhci, slot_id, 1);
1062 spin_lock_irqsave(&xhci->lock, flags);
1063 }
1064 }
1065
1066 xhci_set_link_state(xhci, port_array, wIndex,
1067 link_state);
1068
1069 spin_unlock_irqrestore(&xhci->lock, flags);
1070 msleep(20); /* wait device to enter */
1071 spin_lock_irqsave(&xhci->lock, flags);
1072
1073 temp = readl(port_array[wIndex]);
1074 if (link_state == USB_SS_PORT_LS_U3)
1075 bus_state->suspended_ports |= 1 << wIndex;
1076 break;
1077 case USB_PORT_FEAT_POWER:
1078 /*
1079 * Turn on ports, even if there isn't per-port switching.
1080 * HC will report connect events even before this is set.
1081 * However, hub_wq will ignore the roothub events until
1082 * the roothub is registered.
1083 */
1084 writel(temp | PORT_POWER, port_array[wIndex]);
1085
1086 temp = readl(port_array[wIndex]);
1087 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
1088
1089 spin_unlock_irqrestore(&xhci->lock, flags);
1090 temp = usb_acpi_power_manageable(hcd->self.root_hub,
1091 wIndex);
1092 if (temp)
1093 usb_acpi_set_power_state(hcd->self.root_hub,
1094 wIndex, true);
1095 spin_lock_irqsave(&xhci->lock, flags);
1096 break;
1097 case USB_PORT_FEAT_RESET:
1098 temp = (temp | PORT_RESET);
1099 writel(temp, port_array[wIndex]);
1100
1101 temp = readl(port_array[wIndex]);
1102 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
1103 break;
1104 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1105 xhci_set_remote_wake_mask(xhci, port_array,
1106 wIndex, wake_mask);
1107 temp = readl(port_array[wIndex]);
1108 xhci_dbg(xhci, "set port remote wake mask, "
1109 "actual port %d status = 0x%x\n",
1110 wIndex, temp);
1111 break;
1112 case USB_PORT_FEAT_BH_PORT_RESET:
1113 temp |= PORT_WR;
1114 writel(temp, port_array[wIndex]);
1115
1116 temp = readl(port_array[wIndex]);
1117 break;
1118 case USB_PORT_FEAT_U1_TIMEOUT:
1119 if (hcd->speed < HCD_USB3)
1120 goto error;
1121 temp = readl(port_array[wIndex] + PORTPMSC);
1122 temp &= ~PORT_U1_TIMEOUT_MASK;
1123 temp |= PORT_U1_TIMEOUT(timeout);
1124 writel(temp, port_array[wIndex] + PORTPMSC);
1125 break;
1126 case USB_PORT_FEAT_U2_TIMEOUT:
1127 if (hcd->speed < HCD_USB3)
1128 goto error;
1129 temp = readl(port_array[wIndex] + PORTPMSC);
1130 temp &= ~PORT_U2_TIMEOUT_MASK;
1131 temp |= PORT_U2_TIMEOUT(timeout);
1132 writel(temp, port_array[wIndex] + PORTPMSC);
1133 break;
1134 default:
1135 goto error;
1136 }
1137 /* unblock any posted writes */
1138 temp = readl(port_array[wIndex]);
1139 break;
1140 case ClearPortFeature:
1141 if (!wIndex || wIndex > max_ports)
1142 goto error;
1143 wIndex--;
1144 temp = readl(port_array[wIndex]);
1145 if (temp == 0xffffffff) {
1146 retval = -ENODEV;
1147 break;
1148 }
1149 /* FIXME: What new port features do we need to support? */
1150 temp = xhci_port_state_to_neutral(temp);
1151 switch (wValue) {
1152 case USB_PORT_FEAT_SUSPEND:
1153 temp = readl(port_array[wIndex]);
1154 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1155 xhci_dbg(xhci, "PORTSC %04x\n", temp);
1156 if (temp & PORT_RESET)
1157 goto error;
1158 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1159 if ((temp & PORT_PE) == 0)
1160 goto error;
1161
1162 set_bit(wIndex, &bus_state->resuming_ports);
1163 xhci_set_link_state(xhci, port_array, wIndex,
1164 XDEV_RESUME);
1165 spin_unlock_irqrestore(&xhci->lock, flags);
1166 msleep(20);
1167 spin_lock_irqsave(&xhci->lock, flags);
1168 xhci_set_link_state(xhci, port_array, wIndex,
1169 XDEV_U0);
1170 clear_bit(wIndex, &bus_state->resuming_ports);
1171 }
1172 bus_state->port_c_suspend |= 1 << wIndex;
1173
1174 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1175 wIndex + 1);
1176 if (!slot_id) {
1177 xhci_dbg(xhci, "slot_id is zero\n");
1178 goto error;
1179 }
1180 xhci_ring_device(xhci, slot_id);
1181 break;
1182 case USB_PORT_FEAT_C_SUSPEND:
1183 bus_state->port_c_suspend &= ~(1 << wIndex);
1184 case USB_PORT_FEAT_C_RESET:
1185 case USB_PORT_FEAT_C_BH_PORT_RESET:
1186 case USB_PORT_FEAT_C_CONNECTION:
1187 case USB_PORT_FEAT_C_OVER_CURRENT:
1188 case USB_PORT_FEAT_C_ENABLE:
1189 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1190 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1191 xhci_clear_port_change_bit(xhci, wValue, wIndex,
1192 port_array[wIndex], temp);
1193 break;
1194 case USB_PORT_FEAT_ENABLE:
1195 xhci_disable_port(hcd, xhci, wIndex,
1196 port_array[wIndex], temp);
1197 break;
1198 case USB_PORT_FEAT_POWER:
1199 writel(temp & ~PORT_POWER, port_array[wIndex]);
1200
1201 spin_unlock_irqrestore(&xhci->lock, flags);
1202 temp = usb_acpi_power_manageable(hcd->self.root_hub,
1203 wIndex);
1204 if (temp)
1205 usb_acpi_set_power_state(hcd->self.root_hub,
1206 wIndex, false);
1207 spin_lock_irqsave(&xhci->lock, flags);
1208 break;
1209 default:
1210 goto error;
1211 }
1212 break;
1213 default:
1214error:
1215 /* "stall" on error */
1216 retval = -EPIPE;
1217 }
1218 spin_unlock_irqrestore(&xhci->lock, flags);
1219 return retval;
1220}
1221
1222/*
1223 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1224 * Ports are 0-indexed from the HCD point of view,
1225 * and 1-indexed from the USB core pointer of view.
1226 *
1227 * Note that the status change bits will be cleared as soon as a port status
1228 * change event is generated, so we use the saved status from that event.
1229 */
1230int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1231{
1232 unsigned long flags;
1233 u32 temp, status;
1234 u32 mask;
1235 int i, retval;
1236 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1237 int max_ports;
1238 __le32 __iomem **port_array;
1239 struct xhci_bus_state *bus_state;
1240 bool reset_change = false;
1241
1242 max_ports = xhci_get_ports(hcd, &port_array);
1243 bus_state = &xhci->bus_state[hcd_index(hcd)];
1244
1245 /* Initial status is no changes */
1246 retval = (max_ports + 8) / 8;
1247 memset(buf, 0, retval);
1248
1249 /*
1250 * Inform the usbcore about resume-in-progress by returning
1251 * a non-zero value even if there are no status changes.
1252 */
1253 status = bus_state->resuming_ports;
1254
1255 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1256
1257 spin_lock_irqsave(&xhci->lock, flags);
1258 /* For each port, did anything change? If so, set that bit in buf. */
1259 for (i = 0; i < max_ports; i++) {
1260 temp = readl(port_array[i]);
1261 if (temp == 0xffffffff) {
1262 retval = -ENODEV;
1263 break;
1264 }
1265 if ((temp & mask) != 0 ||
1266 (bus_state->port_c_suspend & 1 << i) ||
1267 (bus_state->resume_done[i] && time_after_eq(
1268 jiffies, bus_state->resume_done[i]))) {
1269 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1270 status = 1;
1271 }
1272 if ((temp & PORT_RC))
1273 reset_change = true;
1274 }
1275 if (!status && !reset_change) {
1276 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1277 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1278 }
1279 spin_unlock_irqrestore(&xhci->lock, flags);
1280 return status ? retval : 0;
1281}
1282
1283#ifdef CONFIG_PM
1284
1285int xhci_bus_suspend(struct usb_hcd *hcd)
1286{
1287 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1288 int max_ports, port_index;
1289 __le32 __iomem **port_array;
1290 struct xhci_bus_state *bus_state;
1291 unsigned long flags;
1292
1293 max_ports = xhci_get_ports(hcd, &port_array);
1294 bus_state = &xhci->bus_state[hcd_index(hcd)];
1295
1296 spin_lock_irqsave(&xhci->lock, flags);
1297
1298 if (hcd->self.root_hub->do_remote_wakeup) {
1299 if (bus_state->resuming_ports || /* USB2 */
1300 bus_state->port_remote_wakeup) { /* USB3 */
1301 spin_unlock_irqrestore(&xhci->lock, flags);
1302 xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1303 return -EBUSY;
1304 }
1305 }
1306
1307 port_index = max_ports;
1308 bus_state->bus_suspended = 0;
1309 while (port_index--) {
1310 /* suspend the port if the port is not suspended */
1311 u32 t1, t2;
1312 int slot_id;
1313
1314 t1 = readl(port_array[port_index]);
1315 t2 = xhci_port_state_to_neutral(t1);
1316
1317 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1318 xhci_dbg(xhci, "port %d not suspended\n", port_index);
1319 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1320 port_index + 1);
1321 if (slot_id) {
1322 spin_unlock_irqrestore(&xhci->lock, flags);
1323 xhci_stop_device(xhci, slot_id, 1);
1324 spin_lock_irqsave(&xhci->lock, flags);
1325 }
1326 t2 &= ~PORT_PLS_MASK;
1327 t2 |= PORT_LINK_STROBE | XDEV_U3;
1328 set_bit(port_index, &bus_state->bus_suspended);
1329 }
1330 /* USB core sets remote wake mask for USB 3.0 hubs,
1331 * including the USB 3.0 roothub, but only if CONFIG_PM
1332 * is enabled, so also enable remote wake here.
1333 */
1334 if (hcd->self.root_hub->do_remote_wakeup) {
1335 if (t1 & PORT_CONNECT) {
1336 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1337 t2 &= ~PORT_WKCONN_E;
1338 } else {
1339 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1340 t2 &= ~PORT_WKDISC_E;
1341 }
1342 } else
1343 t2 &= ~PORT_WAKE_BITS;
1344
1345 t1 = xhci_port_state_to_neutral(t1);
1346 if (t1 != t2)
1347 writel(t2, port_array[port_index]);
1348 }
1349 hcd->state = HC_STATE_SUSPENDED;
1350 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1351 spin_unlock_irqrestore(&xhci->lock, flags);
1352 return 0;
1353}
1354
1355int xhci_bus_resume(struct usb_hcd *hcd)
1356{
1357 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1358 int max_ports, port_index;
1359 __le32 __iomem **port_array;
1360 struct xhci_bus_state *bus_state;
1361 u32 temp;
1362 unsigned long flags;
1363 unsigned long port_was_suspended = 0;
1364 bool need_usb2_u3_exit = false;
1365 int slot_id;
1366 int sret;
1367
1368 max_ports = xhci_get_ports(hcd, &port_array);
1369 bus_state = &xhci->bus_state[hcd_index(hcd)];
1370
1371 if (time_before(jiffies, bus_state->next_statechange))
1372 msleep(5);
1373
1374 spin_lock_irqsave(&xhci->lock, flags);
1375 if (!HCD_HW_ACCESSIBLE(hcd)) {
1376 spin_unlock_irqrestore(&xhci->lock, flags);
1377 return -ESHUTDOWN;
1378 }
1379
1380 /* delay the irqs */
1381 temp = readl(&xhci->op_regs->command);
1382 temp &= ~CMD_EIE;
1383 writel(temp, &xhci->op_regs->command);
1384
1385 port_index = max_ports;
1386 while (port_index--) {
1387 /* Check whether need resume ports. If needed
1388 resume port and disable remote wakeup */
1389 u32 temp;
1390
1391 temp = readl(port_array[port_index]);
1392 if (DEV_SUPERSPEED_ANY(temp))
1393 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1394 else
1395 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1396 if (test_bit(port_index, &bus_state->bus_suspended) &&
1397 (temp & PORT_PLS_MASK)) {
1398 set_bit(port_index, &port_was_suspended);
1399 if (!DEV_SUPERSPEED_ANY(temp)) {
1400 xhci_set_link_state(xhci, port_array,
1401 port_index, XDEV_RESUME);
1402 need_usb2_u3_exit = true;
1403 }
1404 } else
1405 writel(temp, port_array[port_index]);
1406 }
1407
1408 if (need_usb2_u3_exit) {
1409 spin_unlock_irqrestore(&xhci->lock, flags);
1410 msleep(20);
1411 spin_lock_irqsave(&xhci->lock, flags);
1412 }
1413
1414 port_index = max_ports;
1415 while (port_index--) {
1416 if (!(port_was_suspended & BIT(port_index)))
1417 continue;
1418 /* Clear PLC to poll it later after XDEV_U0 */
1419 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1420 xhci_set_link_state(xhci, port_array, port_index, XDEV_U0);
1421 }
1422
1423 port_index = max_ports;
1424 while (port_index--) {
1425 if (!(port_was_suspended & BIT(port_index)))
1426 continue;
1427 /* Poll and Clear PLC */
1428 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1429 PORT_PLC, 10 * 1000);
1430 if (sret)
1431 xhci_warn(xhci, "port %d resume PLC timeout\n",
1432 port_index);
1433 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1434 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1435 if (slot_id)
1436 xhci_ring_device(xhci, slot_id);
1437 }
1438
1439 (void) readl(&xhci->op_regs->command);
1440
1441 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1442 /* re-enable irqs */
1443 temp = readl(&xhci->op_regs->command);
1444 temp |= CMD_EIE;
1445 writel(temp, &xhci->op_regs->command);
1446 temp = readl(&xhci->op_regs->command);
1447
1448 spin_unlock_irqrestore(&xhci->lock, flags);
1449 return 0;
1450}
1451
1452#endif /* CONFIG_PM */