Loading...
Note: File does not exist in v3.1.
1/*
2 * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37/*
38 * This file contains the interrupt handlers for Host mode
39 */
40#include <linux/kernel.h>
41#include <linux/module.h>
42#include <linux/spinlock.h>
43#include <linux/interrupt.h>
44#include <linux/dma-mapping.h>
45#include <linux/io.h>
46#include <linux/slab.h>
47#include <linux/usb.h>
48
49#include <linux/usb/hcd.h>
50#include <linux/usb/ch11.h>
51
52#include "core.h"
53#include "hcd.h"
54
55/* This function is for debug only */
56static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
57{
58 u16 curr_frame_number = hsotg->frame_number;
59 u16 expected = dwc2_frame_num_inc(hsotg->last_frame_num, 1);
60
61 if (expected != curr_frame_number)
62 dwc2_sch_vdbg(hsotg, "MISSED SOF %04x != %04x\n",
63 expected, curr_frame_number);
64
65#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
66 if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
67 if (expected != curr_frame_number) {
68 hsotg->frame_num_array[hsotg->frame_num_idx] =
69 curr_frame_number;
70 hsotg->last_frame_num_array[hsotg->frame_num_idx] =
71 hsotg->last_frame_num;
72 hsotg->frame_num_idx++;
73 }
74 } else if (!hsotg->dumped_frame_num_array) {
75 int i;
76
77 dev_info(hsotg->dev, "Frame Last Frame\n");
78 dev_info(hsotg->dev, "----- ----------\n");
79 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
80 dev_info(hsotg->dev, "0x%04x 0x%04x\n",
81 hsotg->frame_num_array[i],
82 hsotg->last_frame_num_array[i]);
83 }
84 hsotg->dumped_frame_num_array = 1;
85 }
86#endif
87 hsotg->last_frame_num = curr_frame_number;
88}
89
90static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
91 struct dwc2_host_chan *chan,
92 struct dwc2_qtd *qtd)
93{
94 struct usb_device *root_hub = dwc2_hsotg_to_hcd(hsotg)->self.root_hub;
95 struct urb *usb_urb;
96
97 if (!chan->qh)
98 return;
99
100 if (chan->qh->dev_speed == USB_SPEED_HIGH)
101 return;
102
103 if (!qtd->urb)
104 return;
105
106 usb_urb = qtd->urb->priv;
107 if (!usb_urb || !usb_urb->dev || !usb_urb->dev->tt)
108 return;
109
110 /*
111 * The root hub doesn't really have a TT, but Linux thinks it
112 * does because how could you have a "high speed hub" that
113 * directly talks directly to low speed devices without a TT?
114 * It's all lies. Lies, I tell you.
115 */
116 if (usb_urb->dev->tt->hub == root_hub)
117 return;
118
119 if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) {
120 chan->qh->tt_buffer_dirty = 1;
121 if (usb_hub_clear_tt_buffer(usb_urb))
122 /* Clear failed; let's hope things work anyway */
123 chan->qh->tt_buffer_dirty = 0;
124 }
125}
126
127/*
128 * Handles the start-of-frame interrupt in host mode. Non-periodic
129 * transactions may be queued to the DWC_otg controller for the current
130 * (micro)frame. Periodic transactions may be queued to the controller
131 * for the next (micro)frame.
132 */
133static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
134{
135 struct list_head *qh_entry;
136 struct dwc2_qh *qh;
137 enum dwc2_transaction_type tr_type;
138
139 /* Clear interrupt */
140 dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
141
142#ifdef DEBUG_SOF
143 dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
144#endif
145
146 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
147
148 dwc2_track_missed_sofs(hsotg);
149
150 /* Determine whether any periodic QHs should be executed */
151 qh_entry = hsotg->periodic_sched_inactive.next;
152 while (qh_entry != &hsotg->periodic_sched_inactive) {
153 qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry);
154 qh_entry = qh_entry->next;
155 if (dwc2_frame_num_le(qh->next_active_frame,
156 hsotg->frame_number)) {
157 dwc2_sch_vdbg(hsotg, "QH=%p ready fn=%04x, nxt=%04x\n",
158 qh, hsotg->frame_number,
159 qh->next_active_frame);
160
161 /*
162 * Move QH to the ready list to be executed next
163 * (micro)frame
164 */
165 list_move_tail(&qh->qh_list_entry,
166 &hsotg->periodic_sched_ready);
167 }
168 }
169 tr_type = dwc2_hcd_select_transactions(hsotg);
170 if (tr_type != DWC2_TRANSACTION_NONE)
171 dwc2_hcd_queue_transactions(hsotg, tr_type);
172}
173
174/*
175 * Handles the Rx FIFO Level Interrupt, which indicates that there is
176 * at least one packet in the Rx FIFO. The packets are moved from the FIFO to
177 * memory if the DWC_otg controller is operating in Slave mode.
178 */
179static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
180{
181 u32 grxsts, chnum, bcnt, dpid, pktsts;
182 struct dwc2_host_chan *chan;
183
184 if (dbg_perio())
185 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
186
187 grxsts = dwc2_readl(hsotg->regs + GRXSTSP);
188 chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
189 chan = hsotg->hc_ptr_array[chnum];
190 if (!chan) {
191 dev_err(hsotg->dev, "Unable to get corresponding channel\n");
192 return;
193 }
194
195 bcnt = (grxsts & GRXSTS_BYTECNT_MASK) >> GRXSTS_BYTECNT_SHIFT;
196 dpid = (grxsts & GRXSTS_DPID_MASK) >> GRXSTS_DPID_SHIFT;
197 pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT;
198
199 /* Packet Status */
200 if (dbg_perio()) {
201 dev_vdbg(hsotg->dev, " Ch num = %d\n", chnum);
202 dev_vdbg(hsotg->dev, " Count = %d\n", bcnt);
203 dev_vdbg(hsotg->dev, " DPID = %d, chan.dpid = %d\n", dpid,
204 chan->data_pid_start);
205 dev_vdbg(hsotg->dev, " PStatus = %d\n", pktsts);
206 }
207
208 switch (pktsts) {
209 case GRXSTS_PKTSTS_HCHIN:
210 /* Read the data into the host buffer */
211 if (bcnt > 0) {
212 dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
213
214 /* Update the HC fields for the next packet received */
215 chan->xfer_count += bcnt;
216 chan->xfer_buf += bcnt;
217 }
218 break;
219 case GRXSTS_PKTSTS_HCHIN_XFER_COMP:
220 case GRXSTS_PKTSTS_DATATOGGLEERR:
221 case GRXSTS_PKTSTS_HCHHALTED:
222 /* Handled in interrupt, just ignore data */
223 break;
224 default:
225 dev_err(hsotg->dev,
226 "RxFIFO Level Interrupt: Unknown status %d\n", pktsts);
227 break;
228 }
229}
230
231/*
232 * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
233 * data packets may be written to the FIFO for OUT transfers. More requests
234 * may be written to the non-periodic request queue for IN transfers. This
235 * interrupt is enabled only in Slave mode.
236 */
237static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
238{
239 dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
240 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
241}
242
243/*
244 * This interrupt occurs when the periodic Tx FIFO is half-empty. More data
245 * packets may be written to the FIFO for OUT transfers. More requests may be
246 * written to the periodic request queue for IN transfers. This interrupt is
247 * enabled only in Slave mode.
248 */
249static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
250{
251 if (dbg_perio())
252 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
253 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
254}
255
256static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
257 u32 *hprt0_modify)
258{
259 struct dwc2_core_params *params = hsotg->core_params;
260 int do_reset = 0;
261 u32 usbcfg;
262 u32 prtspd;
263 u32 hcfg;
264 u32 fslspclksel;
265 u32 hfir;
266
267 dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
268
269 /* Every time when port enables calculate HFIR.FrInterval */
270 hfir = dwc2_readl(hsotg->regs + HFIR);
271 hfir &= ~HFIR_FRINT_MASK;
272 hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
273 HFIR_FRINT_MASK;
274 dwc2_writel(hfir, hsotg->regs + HFIR);
275
276 /* Check if we need to adjust the PHY clock speed for low power */
277 if (!params->host_support_fs_ls_low_power) {
278 /* Port has been enabled, set the reset change flag */
279 hsotg->flags.b.port_reset_change = 1;
280 return;
281 }
282
283 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
284 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
285
286 if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
287 /* Low power */
288 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
289 /* Set PHY low power clock select for FS/LS devices */
290 usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
291 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
292 do_reset = 1;
293 }
294
295 hcfg = dwc2_readl(hsotg->regs + HCFG);
296 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
297 HCFG_FSLSPCLKSEL_SHIFT;
298
299 if (prtspd == HPRT0_SPD_LOW_SPEED &&
300 params->host_ls_low_power_phy_clk ==
301 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
302 /* 6 MHZ */
303 dev_vdbg(hsotg->dev,
304 "FS_PHY programming HCFG to 6 MHz\n");
305 if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) {
306 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
307 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
308 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
309 dwc2_writel(hcfg, hsotg->regs + HCFG);
310 do_reset = 1;
311 }
312 } else {
313 /* 48 MHZ */
314 dev_vdbg(hsotg->dev,
315 "FS_PHY programming HCFG to 48 MHz\n");
316 if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) {
317 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
318 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
319 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
320 dwc2_writel(hcfg, hsotg->regs + HCFG);
321 do_reset = 1;
322 }
323 }
324 } else {
325 /* Not low power */
326 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
327 usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
328 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
329 do_reset = 1;
330 }
331 }
332
333 if (do_reset) {
334 *hprt0_modify |= HPRT0_RST;
335 dwc2_writel(*hprt0_modify, hsotg->regs + HPRT0);
336 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
337 msecs_to_jiffies(60));
338 } else {
339 /* Port has been enabled, set the reset change flag */
340 hsotg->flags.b.port_reset_change = 1;
341 }
342}
343
344/*
345 * There are multiple conditions that can cause a port interrupt. This function
346 * determines which interrupt conditions have occurred and handles them
347 * appropriately.
348 */
349static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
350{
351 u32 hprt0;
352 u32 hprt0_modify;
353
354 dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
355
356 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
357 hprt0_modify = hprt0;
358
359 /*
360 * Clear appropriate bits in HPRT0 to clear the interrupt bit in
361 * GINTSTS
362 */
363 hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG |
364 HPRT0_OVRCURRCHG);
365
366 /*
367 * Port Connect Detected
368 * Set flag and clear if detected
369 */
370 if (hprt0 & HPRT0_CONNDET) {
371 dwc2_writel(hprt0_modify | HPRT0_CONNDET, hsotg->regs + HPRT0);
372
373 dev_vdbg(hsotg->dev,
374 "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
375 hprt0);
376 dwc2_hcd_connect(hsotg);
377
378 /*
379 * The Hub driver asserts a reset when it sees port connect
380 * status change flag
381 */
382 }
383
384 /*
385 * Port Enable Changed
386 * Clear if detected - Set internal flag if disabled
387 */
388 if (hprt0 & HPRT0_ENACHG) {
389 dwc2_writel(hprt0_modify | HPRT0_ENACHG, hsotg->regs + HPRT0);
390 dev_vdbg(hsotg->dev,
391 " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
392 hprt0, !!(hprt0 & HPRT0_ENA));
393 if (hprt0 & HPRT0_ENA) {
394 hsotg->new_connection = true;
395 dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
396 } else {
397 hsotg->flags.b.port_enable_change = 1;
398 if (hsotg->core_params->dma_desc_fs_enable) {
399 u32 hcfg;
400
401 hsotg->core_params->dma_desc_enable = 0;
402 hsotg->new_connection = false;
403 hcfg = dwc2_readl(hsotg->regs + HCFG);
404 hcfg &= ~HCFG_DESCDMA;
405 dwc2_writel(hcfg, hsotg->regs + HCFG);
406 }
407 }
408 }
409
410 /* Overcurrent Change Interrupt */
411 if (hprt0 & HPRT0_OVRCURRCHG) {
412 dwc2_writel(hprt0_modify | HPRT0_OVRCURRCHG,
413 hsotg->regs + HPRT0);
414 dev_vdbg(hsotg->dev,
415 " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
416 hprt0);
417 hsotg->flags.b.port_over_current_change = 1;
418 }
419}
420
421/*
422 * Gets the actual length of a transfer after the transfer halts. halt_status
423 * holds the reason for the halt.
424 *
425 * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read
426 * is set to 1 upon return if less than the requested number of bytes were
427 * transferred. short_read may also be NULL on entry, in which case it remains
428 * unchanged.
429 */
430static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
431 struct dwc2_host_chan *chan, int chnum,
432 struct dwc2_qtd *qtd,
433 enum dwc2_halt_status halt_status,
434 int *short_read)
435{
436 u32 hctsiz, count, length;
437
438 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
439
440 if (halt_status == DWC2_HC_XFER_COMPLETE) {
441 if (chan->ep_is_in) {
442 count = (hctsiz & TSIZ_XFERSIZE_MASK) >>
443 TSIZ_XFERSIZE_SHIFT;
444 length = chan->xfer_len - count;
445 if (short_read != NULL)
446 *short_read = (count != 0);
447 } else if (chan->qh->do_split) {
448 length = qtd->ssplit_out_xfer_count;
449 } else {
450 length = chan->xfer_len;
451 }
452 } else {
453 /*
454 * Must use the hctsiz.pktcnt field to determine how much data
455 * has been transferred. This field reflects the number of
456 * packets that have been transferred via the USB. This is
457 * always an integral number of packets if the transfer was
458 * halted before its normal completion. (Can't use the
459 * hctsiz.xfersize field because that reflects the number of
460 * bytes transferred via the AHB, not the USB).
461 */
462 count = (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT;
463 length = (chan->start_pkt_count - count) * chan->max_packet;
464 }
465
466 return length;
467}
468
469/**
470 * dwc2_update_urb_state() - Updates the state of the URB after a Transfer
471 * Complete interrupt on the host channel. Updates the actual_length field
472 * of the URB based on the number of bytes transferred via the host channel.
473 * Sets the URB status if the data transfer is finished.
474 *
475 * Return: 1 if the data transfer specified by the URB is completely finished,
476 * 0 otherwise
477 */
478static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
479 struct dwc2_host_chan *chan, int chnum,
480 struct dwc2_hcd_urb *urb,
481 struct dwc2_qtd *qtd)
482{
483 u32 hctsiz;
484 int xfer_done = 0;
485 int short_read = 0;
486 int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
487 DWC2_HC_XFER_COMPLETE,
488 &short_read);
489
490 if (urb->actual_length + xfer_length > urb->length) {
491 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
492 xfer_length = urb->length - urb->actual_length;
493 }
494
495 dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
496 urb->actual_length, xfer_length);
497 urb->actual_length += xfer_length;
498
499 if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK &&
500 (urb->flags & URB_SEND_ZERO_PACKET) &&
501 urb->actual_length >= urb->length &&
502 !(urb->length % chan->max_packet)) {
503 xfer_done = 0;
504 } else if (short_read || urb->actual_length >= urb->length) {
505 xfer_done = 1;
506 urb->status = 0;
507 }
508
509 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
510 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
511 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
512 dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len);
513 dev_vdbg(hsotg->dev, " hctsiz.xfersize %d\n",
514 (hctsiz & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT);
515 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", urb->length);
516 dev_vdbg(hsotg->dev, " urb->actual_length %d\n", urb->actual_length);
517 dev_vdbg(hsotg->dev, " short_read %d, xfer_done %d\n", short_read,
518 xfer_done);
519
520 return xfer_done;
521}
522
523/*
524 * Save the starting data toggle for the next transfer. The data toggle is
525 * saved in the QH for non-control transfers and it's saved in the QTD for
526 * control transfers.
527 */
528void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
529 struct dwc2_host_chan *chan, int chnum,
530 struct dwc2_qtd *qtd)
531{
532 u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
533 u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
534
535 if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
536 if (WARN(!chan || !chan->qh,
537 "chan->qh must be specified for non-control eps\n"))
538 return;
539
540 if (pid == TSIZ_SC_MC_PID_DATA0)
541 chan->qh->data_toggle = DWC2_HC_PID_DATA0;
542 else
543 chan->qh->data_toggle = DWC2_HC_PID_DATA1;
544 } else {
545 if (WARN(!qtd,
546 "qtd must be specified for control eps\n"))
547 return;
548
549 if (pid == TSIZ_SC_MC_PID_DATA0)
550 qtd->data_toggle = DWC2_HC_PID_DATA0;
551 else
552 qtd->data_toggle = DWC2_HC_PID_DATA1;
553 }
554}
555
556/**
557 * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when
558 * the transfer is stopped for any reason. The fields of the current entry in
559 * the frame descriptor array are set based on the transfer state and the input
560 * halt_status. Completes the Isochronous URB if all the URB frames have been
561 * completed.
562 *
563 * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be
564 * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE.
565 */
566static enum dwc2_halt_status dwc2_update_isoc_urb_state(
567 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
568 int chnum, struct dwc2_qtd *qtd,
569 enum dwc2_halt_status halt_status)
570{
571 struct dwc2_hcd_iso_packet_desc *frame_desc;
572 struct dwc2_hcd_urb *urb = qtd->urb;
573
574 if (!urb)
575 return DWC2_HC_XFER_NO_HALT_STATUS;
576
577 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
578
579 switch (halt_status) {
580 case DWC2_HC_XFER_COMPLETE:
581 frame_desc->status = 0;
582 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
583 chan, chnum, qtd, halt_status, NULL);
584 break;
585 case DWC2_HC_XFER_FRAME_OVERRUN:
586 urb->error_count++;
587 if (chan->ep_is_in)
588 frame_desc->status = -ENOSR;
589 else
590 frame_desc->status = -ECOMM;
591 frame_desc->actual_length = 0;
592 break;
593 case DWC2_HC_XFER_BABBLE_ERR:
594 urb->error_count++;
595 frame_desc->status = -EOVERFLOW;
596 /* Don't need to update actual_length in this case */
597 break;
598 case DWC2_HC_XFER_XACT_ERR:
599 urb->error_count++;
600 frame_desc->status = -EPROTO;
601 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
602 chan, chnum, qtd, halt_status, NULL);
603
604 /* Skip whole frame */
605 if (chan->qh->do_split &&
606 chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
607 hsotg->core_params->dma_enable > 0) {
608 qtd->complete_split = 0;
609 qtd->isoc_split_offset = 0;
610 }
611
612 break;
613 default:
614 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
615 halt_status);
616 break;
617 }
618
619 if (++qtd->isoc_frame_index == urb->packet_count) {
620 /*
621 * urb->status is not used for isoc transfers. The individual
622 * frame_desc statuses are used instead.
623 */
624 dwc2_host_complete(hsotg, qtd, 0);
625 halt_status = DWC2_HC_XFER_URB_COMPLETE;
626 } else {
627 halt_status = DWC2_HC_XFER_COMPLETE;
628 }
629
630 return halt_status;
631}
632
633/*
634 * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
635 * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
636 * still linked to the QH, the QH is added to the end of the inactive
637 * non-periodic schedule. For periodic QHs, removes the QH from the periodic
638 * schedule if no more QTDs are linked to the QH.
639 */
640static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
641 int free_qtd)
642{
643 int continue_split = 0;
644 struct dwc2_qtd *qtd;
645
646 if (dbg_qh(qh))
647 dev_vdbg(hsotg->dev, " %s(%p,%p,%d)\n", __func__,
648 hsotg, qh, free_qtd);
649
650 if (list_empty(&qh->qtd_list)) {
651 dev_dbg(hsotg->dev, "## QTD list empty ##\n");
652 goto no_qtd;
653 }
654
655 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
656
657 if (qtd->complete_split)
658 continue_split = 1;
659 else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID ||
660 qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END)
661 continue_split = 1;
662
663 if (free_qtd) {
664 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
665 continue_split = 0;
666 }
667
668no_qtd:
669 qh->channel = NULL;
670 dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
671}
672
673/**
674 * dwc2_release_channel() - Releases a host channel for use by other transfers
675 *
676 * @hsotg: The HCD state structure
677 * @chan: The host channel to release
678 * @qtd: The QTD associated with the host channel. This QTD may be
679 * freed if the transfer is complete or an error has occurred.
680 * @halt_status: Reason the channel is being released. This status
681 * determines the actions taken by this function.
682 *
683 * Also attempts to select and queue more transactions since at least one host
684 * channel is available.
685 */
686static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
687 struct dwc2_host_chan *chan,
688 struct dwc2_qtd *qtd,
689 enum dwc2_halt_status halt_status)
690{
691 enum dwc2_transaction_type tr_type;
692 u32 haintmsk;
693 int free_qtd = 0;
694
695 if (dbg_hc(chan))
696 dev_vdbg(hsotg->dev, " %s: channel %d, halt_status %d\n",
697 __func__, chan->hc_num, halt_status);
698
699 switch (halt_status) {
700 case DWC2_HC_XFER_URB_COMPLETE:
701 free_qtd = 1;
702 break;
703 case DWC2_HC_XFER_AHB_ERR:
704 case DWC2_HC_XFER_STALL:
705 case DWC2_HC_XFER_BABBLE_ERR:
706 free_qtd = 1;
707 break;
708 case DWC2_HC_XFER_XACT_ERR:
709 if (qtd && qtd->error_count >= 3) {
710 dev_vdbg(hsotg->dev,
711 " Complete URB with transaction error\n");
712 free_qtd = 1;
713 dwc2_host_complete(hsotg, qtd, -EPROTO);
714 }
715 break;
716 case DWC2_HC_XFER_URB_DEQUEUE:
717 /*
718 * The QTD has already been removed and the QH has been
719 * deactivated. Don't want to do anything except release the
720 * host channel and try to queue more transfers.
721 */
722 goto cleanup;
723 case DWC2_HC_XFER_PERIODIC_INCOMPLETE:
724 dev_vdbg(hsotg->dev, " Complete URB with I/O error\n");
725 free_qtd = 1;
726 dwc2_host_complete(hsotg, qtd, -EIO);
727 break;
728 case DWC2_HC_XFER_NO_HALT_STATUS:
729 default:
730 break;
731 }
732
733 dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
734
735cleanup:
736 /*
737 * Release the host channel for use by other transfers. The cleanup
738 * function clears the channel interrupt enables and conditions, so
739 * there's no need to clear the Channel Halted interrupt separately.
740 */
741 if (!list_empty(&chan->hc_list_entry))
742 list_del(&chan->hc_list_entry);
743 dwc2_hc_cleanup(hsotg, chan);
744 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
745
746 if (hsotg->core_params->uframe_sched > 0) {
747 hsotg->available_host_channels++;
748 } else {
749 switch (chan->ep_type) {
750 case USB_ENDPOINT_XFER_CONTROL:
751 case USB_ENDPOINT_XFER_BULK:
752 hsotg->non_periodic_channels--;
753 break;
754 default:
755 /*
756 * Don't release reservations for periodic channels
757 * here. That's done when a periodic transfer is
758 * descheduled (i.e. when the QH is removed from the
759 * periodic schedule).
760 */
761 break;
762 }
763 }
764
765 haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
766 haintmsk &= ~(1 << chan->hc_num);
767 dwc2_writel(haintmsk, hsotg->regs + HAINTMSK);
768
769 /* Try to queue more transfers now that there's a free channel */
770 tr_type = dwc2_hcd_select_transactions(hsotg);
771 if (tr_type != DWC2_TRANSACTION_NONE)
772 dwc2_hcd_queue_transactions(hsotg, tr_type);
773}
774
775/*
776 * Halts a host channel. If the channel cannot be halted immediately because
777 * the request queue is full, this function ensures that the FIFO empty
778 * interrupt for the appropriate queue is enabled so that the halt request can
779 * be queued when there is space in the request queue.
780 *
781 * This function may also be called in DMA mode. In that case, the channel is
782 * simply released since the core always halts the channel automatically in
783 * DMA mode.
784 */
785static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
786 struct dwc2_host_chan *chan, struct dwc2_qtd *qtd,
787 enum dwc2_halt_status halt_status)
788{
789 if (dbg_hc(chan))
790 dev_vdbg(hsotg->dev, "%s()\n", __func__);
791
792 if (hsotg->core_params->dma_enable > 0) {
793 if (dbg_hc(chan))
794 dev_vdbg(hsotg->dev, "DMA enabled\n");
795 dwc2_release_channel(hsotg, chan, qtd, halt_status);
796 return;
797 }
798
799 /* Slave mode processing */
800 dwc2_hc_halt(hsotg, chan, halt_status);
801
802 if (chan->halt_on_queue) {
803 u32 gintmsk;
804
805 dev_vdbg(hsotg->dev, "Halt on queue\n");
806 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
807 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
808 dev_vdbg(hsotg->dev, "control/bulk\n");
809 /*
810 * Make sure the Non-periodic Tx FIFO empty interrupt
811 * is enabled so that the non-periodic schedule will
812 * be processed
813 */
814 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
815 gintmsk |= GINTSTS_NPTXFEMP;
816 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
817 } else {
818 dev_vdbg(hsotg->dev, "isoc/intr\n");
819 /*
820 * Move the QH from the periodic queued schedule to
821 * the periodic assigned schedule. This allows the
822 * halt to be queued when the periodic schedule is
823 * processed.
824 */
825 list_move_tail(&chan->qh->qh_list_entry,
826 &hsotg->periodic_sched_assigned);
827
828 /*
829 * Make sure the Periodic Tx FIFO Empty interrupt is
830 * enabled so that the periodic schedule will be
831 * processed
832 */
833 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
834 gintmsk |= GINTSTS_PTXFEMP;
835 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
836 }
837 }
838}
839
840/*
841 * Performs common cleanup for non-periodic transfers after a Transfer
842 * Complete interrupt. This function should be called after any endpoint type
843 * specific handling is finished to release the host channel.
844 */
845static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
846 struct dwc2_host_chan *chan,
847 int chnum, struct dwc2_qtd *qtd,
848 enum dwc2_halt_status halt_status)
849{
850 dev_vdbg(hsotg->dev, "%s()\n", __func__);
851
852 qtd->error_count = 0;
853
854 if (chan->hcint & HCINTMSK_NYET) {
855 /*
856 * Got a NYET on the last transaction of the transfer. This
857 * means that the endpoint should be in the PING state at the
858 * beginning of the next transfer.
859 */
860 dev_vdbg(hsotg->dev, "got NYET\n");
861 chan->qh->ping_state = 1;
862 }
863
864 /*
865 * Always halt and release the host channel to make it available for
866 * more transfers. There may still be more phases for a control
867 * transfer or more data packets for a bulk transfer at this point,
868 * but the host channel is still halted. A channel will be reassigned
869 * to the transfer when the non-periodic schedule is processed after
870 * the channel is released. This allows transactions to be queued
871 * properly via dwc2_hcd_queue_transactions, which also enables the
872 * Tx FIFO Empty interrupt if necessary.
873 */
874 if (chan->ep_is_in) {
875 /*
876 * IN transfers in Slave mode require an explicit disable to
877 * halt the channel. (In DMA mode, this call simply releases
878 * the channel.)
879 */
880 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
881 } else {
882 /*
883 * The channel is automatically disabled by the core for OUT
884 * transfers in Slave mode
885 */
886 dwc2_release_channel(hsotg, chan, qtd, halt_status);
887 }
888}
889
890/*
891 * Performs common cleanup for periodic transfers after a Transfer Complete
892 * interrupt. This function should be called after any endpoint type specific
893 * handling is finished to release the host channel.
894 */
895static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
896 struct dwc2_host_chan *chan, int chnum,
897 struct dwc2_qtd *qtd,
898 enum dwc2_halt_status halt_status)
899{
900 u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
901
902 qtd->error_count = 0;
903
904 if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0)
905 /* Core halts channel in these cases */
906 dwc2_release_channel(hsotg, chan, qtd, halt_status);
907 else
908 /* Flush any outstanding requests from the Tx queue */
909 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
910}
911
912static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
913 struct dwc2_host_chan *chan, int chnum,
914 struct dwc2_qtd *qtd)
915{
916 struct dwc2_hcd_iso_packet_desc *frame_desc;
917 u32 len;
918
919 if (!qtd->urb)
920 return 0;
921
922 frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
923 len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
924 DWC2_HC_XFER_COMPLETE, NULL);
925 if (!len) {
926 qtd->complete_split = 0;
927 qtd->isoc_split_offset = 0;
928 return 0;
929 }
930
931 frame_desc->actual_length += len;
932
933 qtd->isoc_split_offset += len;
934
935 if (frame_desc->actual_length >= frame_desc->length) {
936 frame_desc->status = 0;
937 qtd->isoc_frame_index++;
938 qtd->complete_split = 0;
939 qtd->isoc_split_offset = 0;
940 }
941
942 if (qtd->isoc_frame_index == qtd->urb->packet_count) {
943 dwc2_host_complete(hsotg, qtd, 0);
944 dwc2_release_channel(hsotg, chan, qtd,
945 DWC2_HC_XFER_URB_COMPLETE);
946 } else {
947 dwc2_release_channel(hsotg, chan, qtd,
948 DWC2_HC_XFER_NO_HALT_STATUS);
949 }
950
951 return 1; /* Indicates that channel released */
952}
953
954/*
955 * Handles a host channel Transfer Complete interrupt. This handler may be
956 * called in either DMA mode or Slave mode.
957 */
958static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
959 struct dwc2_host_chan *chan, int chnum,
960 struct dwc2_qtd *qtd)
961{
962 struct dwc2_hcd_urb *urb = qtd->urb;
963 enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE;
964 int pipe_type;
965 int urb_xfer_done;
966
967 if (dbg_hc(chan))
968 dev_vdbg(hsotg->dev,
969 "--Host Channel %d Interrupt: Transfer Complete--\n",
970 chnum);
971
972 if (!urb)
973 goto handle_xfercomp_done;
974
975 pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
976
977 if (hsotg->core_params->dma_desc_enable > 0) {
978 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
979 if (pipe_type == USB_ENDPOINT_XFER_ISOC)
980 /* Do not disable the interrupt, just clear it */
981 return;
982 goto handle_xfercomp_done;
983 }
984
985 /* Handle xfer complete on CSPLIT */
986 if (chan->qh->do_split) {
987 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
988 hsotg->core_params->dma_enable > 0) {
989 if (qtd->complete_split &&
990 dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
991 qtd))
992 goto handle_xfercomp_done;
993 } else {
994 qtd->complete_split = 0;
995 }
996 }
997
998 /* Update the QTD and URB states */
999 switch (pipe_type) {
1000 case USB_ENDPOINT_XFER_CONTROL:
1001 switch (qtd->control_phase) {
1002 case DWC2_CONTROL_SETUP:
1003 if (urb->length > 0)
1004 qtd->control_phase = DWC2_CONTROL_DATA;
1005 else
1006 qtd->control_phase = DWC2_CONTROL_STATUS;
1007 dev_vdbg(hsotg->dev,
1008 " Control setup transaction done\n");
1009 halt_status = DWC2_HC_XFER_COMPLETE;
1010 break;
1011 case DWC2_CONTROL_DATA:
1012 urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1013 chnum, urb, qtd);
1014 if (urb_xfer_done) {
1015 qtd->control_phase = DWC2_CONTROL_STATUS;
1016 dev_vdbg(hsotg->dev,
1017 " Control data transfer done\n");
1018 } else {
1019 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1020 qtd);
1021 }
1022 halt_status = DWC2_HC_XFER_COMPLETE;
1023 break;
1024 case DWC2_CONTROL_STATUS:
1025 dev_vdbg(hsotg->dev, " Control transfer complete\n");
1026 if (urb->status == -EINPROGRESS)
1027 urb->status = 0;
1028 dwc2_host_complete(hsotg, qtd, urb->status);
1029 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1030 break;
1031 }
1032
1033 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1034 halt_status);
1035 break;
1036 case USB_ENDPOINT_XFER_BULK:
1037 dev_vdbg(hsotg->dev, " Bulk transfer complete\n");
1038 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1039 qtd);
1040 if (urb_xfer_done) {
1041 dwc2_host_complete(hsotg, qtd, urb->status);
1042 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1043 } else {
1044 halt_status = DWC2_HC_XFER_COMPLETE;
1045 }
1046
1047 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1048 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1049 halt_status);
1050 break;
1051 case USB_ENDPOINT_XFER_INT:
1052 dev_vdbg(hsotg->dev, " Interrupt transfer complete\n");
1053 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1054 qtd);
1055
1056 /*
1057 * Interrupt URB is done on the first transfer complete
1058 * interrupt
1059 */
1060 if (urb_xfer_done) {
1061 dwc2_host_complete(hsotg, qtd, urb->status);
1062 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1063 } else {
1064 halt_status = DWC2_HC_XFER_COMPLETE;
1065 }
1066
1067 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1068 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1069 halt_status);
1070 break;
1071 case USB_ENDPOINT_XFER_ISOC:
1072 if (dbg_perio())
1073 dev_vdbg(hsotg->dev, " Isochronous transfer complete\n");
1074 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
1075 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1076 chnum, qtd, DWC2_HC_XFER_COMPLETE);
1077 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1078 halt_status);
1079 break;
1080 }
1081
1082handle_xfercomp_done:
1083 disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1084}
1085
1086/*
1087 * Handles a host channel STALL interrupt. This handler may be called in
1088 * either DMA mode or Slave mode.
1089 */
1090static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1091 struct dwc2_host_chan *chan, int chnum,
1092 struct dwc2_qtd *qtd)
1093{
1094 struct dwc2_hcd_urb *urb = qtd->urb;
1095 int pipe_type;
1096
1097 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1098 chnum);
1099
1100 if (hsotg->core_params->dma_desc_enable > 0) {
1101 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1102 DWC2_HC_XFER_STALL);
1103 goto handle_stall_done;
1104 }
1105
1106 if (!urb)
1107 goto handle_stall_halt;
1108
1109 pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1110
1111 if (pipe_type == USB_ENDPOINT_XFER_CONTROL)
1112 dwc2_host_complete(hsotg, qtd, -EPIPE);
1113
1114 if (pipe_type == USB_ENDPOINT_XFER_BULK ||
1115 pipe_type == USB_ENDPOINT_XFER_INT) {
1116 dwc2_host_complete(hsotg, qtd, -EPIPE);
1117 /*
1118 * USB protocol requires resetting the data toggle for bulk
1119 * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1120 * setup command is issued to the endpoint. Anticipate the
1121 * CLEAR_FEATURE command since a STALL has occurred and reset
1122 * the data toggle now.
1123 */
1124 chan->qh->data_toggle = 0;
1125 }
1126
1127handle_stall_halt:
1128 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1129
1130handle_stall_done:
1131 disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1132}
1133
1134/*
1135 * Updates the state of the URB when a transfer has been stopped due to an
1136 * abnormal condition before the transfer completes. Modifies the
1137 * actual_length field of the URB to reflect the number of bytes that have
1138 * actually been transferred via the host channel.
1139 */
1140static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1141 struct dwc2_host_chan *chan, int chnum,
1142 struct dwc2_hcd_urb *urb,
1143 struct dwc2_qtd *qtd,
1144 enum dwc2_halt_status halt_status)
1145{
1146 u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1147 qtd, halt_status, NULL);
1148 u32 hctsiz;
1149
1150 if (urb->actual_length + xfer_length > urb->length) {
1151 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1152 xfer_length = urb->length - urb->actual_length;
1153 }
1154
1155 urb->actual_length += xfer_length;
1156
1157 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1158 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1159 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
1160 dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n",
1161 chan->start_pkt_count);
1162 dev_vdbg(hsotg->dev, " hctsiz.pktcnt %d\n",
1163 (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT);
1164 dev_vdbg(hsotg->dev, " chan->max_packet %d\n", chan->max_packet);
1165 dev_vdbg(hsotg->dev, " bytes_transferred %d\n",
1166 xfer_length);
1167 dev_vdbg(hsotg->dev, " urb->actual_length %d\n",
1168 urb->actual_length);
1169 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n",
1170 urb->length);
1171}
1172
1173/*
1174 * Handles a host channel NAK interrupt. This handler may be called in either
1175 * DMA mode or Slave mode.
1176 */
1177static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1178 struct dwc2_host_chan *chan, int chnum,
1179 struct dwc2_qtd *qtd)
1180{
1181 if (!qtd) {
1182 dev_dbg(hsotg->dev, "%s: qtd is NULL\n", __func__);
1183 return;
1184 }
1185
1186 if (!qtd->urb) {
1187 dev_dbg(hsotg->dev, "%s: qtd->urb is NULL\n", __func__);
1188 return;
1189 }
1190
1191 if (dbg_hc(chan))
1192 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1193 chnum);
1194
1195 /*
1196 * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1197 * interrupt. Re-start the SSPLIT transfer.
1198 */
1199 if (chan->do_split) {
1200 if (chan->complete_split)
1201 qtd->error_count = 0;
1202 qtd->complete_split = 0;
1203 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1204 goto handle_nak_done;
1205 }
1206
1207 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1208 case USB_ENDPOINT_XFER_CONTROL:
1209 case USB_ENDPOINT_XFER_BULK:
1210 if (hsotg->core_params->dma_enable > 0 && chan->ep_is_in) {
1211 /*
1212 * NAK interrupts are enabled on bulk/control IN
1213 * transfers in DMA mode for the sole purpose of
1214 * resetting the error count after a transaction error
1215 * occurs. The core will continue transferring data.
1216 */
1217 qtd->error_count = 0;
1218 break;
1219 }
1220
1221 /*
1222 * NAK interrupts normally occur during OUT transfers in DMA
1223 * or Slave mode. For IN transfers, more requests will be
1224 * queued as request queue space is available.
1225 */
1226 qtd->error_count = 0;
1227
1228 if (!chan->qh->ping_state) {
1229 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1230 qtd, DWC2_HC_XFER_NAK);
1231 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1232
1233 if (chan->speed == USB_SPEED_HIGH)
1234 chan->qh->ping_state = 1;
1235 }
1236
1237 /*
1238 * Halt the channel so the transfer can be re-started from
1239 * the appropriate point or the PING protocol will
1240 * start/continue
1241 */
1242 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1243 break;
1244 case USB_ENDPOINT_XFER_INT:
1245 qtd->error_count = 0;
1246 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1247 break;
1248 case USB_ENDPOINT_XFER_ISOC:
1249 /* Should never get called for isochronous transfers */
1250 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1251 break;
1252 }
1253
1254handle_nak_done:
1255 disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1256}
1257
1258/*
1259 * Handles a host channel ACK interrupt. This interrupt is enabled when
1260 * performing the PING protocol in Slave mode, when errors occur during
1261 * either Slave mode or DMA mode, and during Start Split transactions.
1262 */
1263static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1264 struct dwc2_host_chan *chan, int chnum,
1265 struct dwc2_qtd *qtd)
1266{
1267 struct dwc2_hcd_iso_packet_desc *frame_desc;
1268
1269 if (dbg_hc(chan))
1270 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1271 chnum);
1272
1273 if (chan->do_split) {
1274 /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */
1275 if (!chan->ep_is_in &&
1276 chan->data_pid_start != DWC2_HC_PID_SETUP)
1277 qtd->ssplit_out_xfer_count = chan->xfer_len;
1278
1279 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) {
1280 qtd->complete_split = 1;
1281 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1282 } else {
1283 /* ISOC OUT */
1284 switch (chan->xact_pos) {
1285 case DWC2_HCSPLT_XACTPOS_ALL:
1286 break;
1287 case DWC2_HCSPLT_XACTPOS_END:
1288 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1289 qtd->isoc_split_offset = 0;
1290 break;
1291 case DWC2_HCSPLT_XACTPOS_BEGIN:
1292 case DWC2_HCSPLT_XACTPOS_MID:
1293 /*
1294 * For BEGIN or MID, calculate the length for
1295 * the next microframe to determine the correct
1296 * SSPLIT token, either MID or END
1297 */
1298 frame_desc = &qtd->urb->iso_descs[
1299 qtd->isoc_frame_index];
1300 qtd->isoc_split_offset += 188;
1301
1302 if (frame_desc->length - qtd->isoc_split_offset
1303 <= 188)
1304 qtd->isoc_split_pos =
1305 DWC2_HCSPLT_XACTPOS_END;
1306 else
1307 qtd->isoc_split_pos =
1308 DWC2_HCSPLT_XACTPOS_MID;
1309 break;
1310 }
1311 }
1312 } else {
1313 qtd->error_count = 0;
1314
1315 if (chan->qh->ping_state) {
1316 chan->qh->ping_state = 0;
1317 /*
1318 * Halt the channel so the transfer can be re-started
1319 * from the appropriate point. This only happens in
1320 * Slave mode. In DMA mode, the ping_state is cleared
1321 * when the transfer is started because the core
1322 * automatically executes the PING, then the transfer.
1323 */
1324 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1325 }
1326 }
1327
1328 /*
1329 * If the ACK occurred when _not_ in the PING state, let the channel
1330 * continue transferring data after clearing the error count
1331 */
1332 disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1333}
1334
1335/*
1336 * Handles a host channel NYET interrupt. This interrupt should only occur on
1337 * Bulk and Control OUT endpoints and for complete split transactions. If a
1338 * NYET occurs at the same time as a Transfer Complete interrupt, it is
1339 * handled in the xfercomp interrupt handler, not here. This handler may be
1340 * called in either DMA mode or Slave mode.
1341 */
1342static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1343 struct dwc2_host_chan *chan, int chnum,
1344 struct dwc2_qtd *qtd)
1345{
1346 if (dbg_hc(chan))
1347 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1348 chnum);
1349
1350 /*
1351 * NYET on CSPLIT
1352 * re-do the CSPLIT immediately on non-periodic
1353 */
1354 if (chan->do_split && chan->complete_split) {
1355 if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC &&
1356 hsotg->core_params->dma_enable > 0) {
1357 qtd->complete_split = 0;
1358 qtd->isoc_split_offset = 0;
1359 qtd->isoc_frame_index++;
1360 if (qtd->urb &&
1361 qtd->isoc_frame_index == qtd->urb->packet_count) {
1362 dwc2_host_complete(hsotg, qtd, 0);
1363 dwc2_release_channel(hsotg, chan, qtd,
1364 DWC2_HC_XFER_URB_COMPLETE);
1365 } else {
1366 dwc2_release_channel(hsotg, chan, qtd,
1367 DWC2_HC_XFER_NO_HALT_STATUS);
1368 }
1369 goto handle_nyet_done;
1370 }
1371
1372 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1373 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1374 struct dwc2_qh *qh = chan->qh;
1375 bool past_end;
1376
1377 if (hsotg->core_params->uframe_sched <= 0) {
1378 int frnum = dwc2_hcd_get_frame_number(hsotg);
1379
1380 /* Don't have num_hs_transfers; simple logic */
1381 past_end = dwc2_full_frame_num(frnum) !=
1382 dwc2_full_frame_num(qh->next_active_frame);
1383 } else {
1384 int end_frnum;
1385
1386 /*
1387 * Figure out the end frame based on schedule.
1388 *
1389 * We don't want to go on trying again and again
1390 * forever. Let's stop when we've done all the
1391 * transfers that were scheduled.
1392 *
1393 * We're going to be comparing start_active_frame
1394 * and next_active_frame, both of which are 1
1395 * before the time the packet goes on the wire,
1396 * so that cancels out. Basically if had 1
1397 * transfer and we saw 1 NYET then we're done.
1398 * We're getting a NYET here so if next >=
1399 * (start + num_transfers) we're done. The
1400 * complexity is that for all but ISOC_OUT we
1401 * skip one slot.
1402 */
1403 end_frnum = dwc2_frame_num_inc(
1404 qh->start_active_frame,
1405 qh->num_hs_transfers);
1406
1407 if (qh->ep_type != USB_ENDPOINT_XFER_ISOC ||
1408 qh->ep_is_in)
1409 end_frnum =
1410 dwc2_frame_num_inc(end_frnum, 1);
1411
1412 past_end = dwc2_frame_num_le(
1413 end_frnum, qh->next_active_frame);
1414 }
1415
1416 if (past_end) {
1417 /* Treat this as a transaction error. */
1418#if 0
1419 /*
1420 * Todo: Fix system performance so this can
1421 * be treated as an error. Right now complete
1422 * splits cannot be scheduled precisely enough
1423 * due to other system activity, so this error
1424 * occurs regularly in Slave mode.
1425 */
1426 qtd->error_count++;
1427#endif
1428 qtd->complete_split = 0;
1429 dwc2_halt_channel(hsotg, chan, qtd,
1430 DWC2_HC_XFER_XACT_ERR);
1431 /* Todo: add support for isoc release */
1432 goto handle_nyet_done;
1433 }
1434 }
1435
1436 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1437 goto handle_nyet_done;
1438 }
1439
1440 chan->qh->ping_state = 1;
1441 qtd->error_count = 0;
1442
1443 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1444 DWC2_HC_XFER_NYET);
1445 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1446
1447 /*
1448 * Halt the channel and re-start the transfer so the PING protocol
1449 * will start
1450 */
1451 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1452
1453handle_nyet_done:
1454 disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1455}
1456
1457/*
1458 * Handles a host channel babble interrupt. This handler may be called in
1459 * either DMA mode or Slave mode.
1460 */
1461static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1462 struct dwc2_host_chan *chan, int chnum,
1463 struct dwc2_qtd *qtd)
1464{
1465 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1466 chnum);
1467
1468 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1469
1470 if (hsotg->core_params->dma_desc_enable > 0) {
1471 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1472 DWC2_HC_XFER_BABBLE_ERR);
1473 goto disable_int;
1474 }
1475
1476 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1477 dwc2_host_complete(hsotg, qtd, -EOVERFLOW);
1478 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1479 } else {
1480 enum dwc2_halt_status halt_status;
1481
1482 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1483 qtd, DWC2_HC_XFER_BABBLE_ERR);
1484 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1485 }
1486
1487disable_int:
1488 disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1489}
1490
1491/*
1492 * Handles a host channel AHB error interrupt. This handler is only called in
1493 * DMA mode.
1494 */
1495static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1496 struct dwc2_host_chan *chan, int chnum,
1497 struct dwc2_qtd *qtd)
1498{
1499 struct dwc2_hcd_urb *urb = qtd->urb;
1500 char *pipetype, *speed;
1501 u32 hcchar;
1502 u32 hcsplt;
1503 u32 hctsiz;
1504 u32 hc_dma;
1505
1506 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1507 chnum);
1508
1509 if (!urb)
1510 goto handle_ahberr_halt;
1511
1512 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1513
1514 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1515 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1516 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1517 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum));
1518
1519 dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1520 dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1521 dev_err(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1522 dev_err(hsotg->dev, " Device address: %d\n",
1523 dwc2_hcd_get_dev_addr(&urb->pipe_info));
1524 dev_err(hsotg->dev, " Endpoint: %d, %s\n",
1525 dwc2_hcd_get_ep_num(&urb->pipe_info),
1526 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
1527
1528 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
1529 case USB_ENDPOINT_XFER_CONTROL:
1530 pipetype = "CONTROL";
1531 break;
1532 case USB_ENDPOINT_XFER_BULK:
1533 pipetype = "BULK";
1534 break;
1535 case USB_ENDPOINT_XFER_INT:
1536 pipetype = "INTERRUPT";
1537 break;
1538 case USB_ENDPOINT_XFER_ISOC:
1539 pipetype = "ISOCHRONOUS";
1540 break;
1541 default:
1542 pipetype = "UNKNOWN";
1543 break;
1544 }
1545
1546 dev_err(hsotg->dev, " Endpoint type: %s\n", pipetype);
1547
1548 switch (chan->speed) {
1549 case USB_SPEED_HIGH:
1550 speed = "HIGH";
1551 break;
1552 case USB_SPEED_FULL:
1553 speed = "FULL";
1554 break;
1555 case USB_SPEED_LOW:
1556 speed = "LOW";
1557 break;
1558 default:
1559 speed = "UNKNOWN";
1560 break;
1561 }
1562
1563 dev_err(hsotg->dev, " Speed: %s\n", speed);
1564
1565 dev_err(hsotg->dev, " Max packet size: %d\n",
1566 dwc2_hcd_get_mps(&urb->pipe_info));
1567 dev_err(hsotg->dev, " Data buffer length: %d\n", urb->length);
1568 dev_err(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
1569 urb->buf, (unsigned long)urb->dma);
1570 dev_err(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
1571 urb->setup_packet, (unsigned long)urb->setup_dma);
1572 dev_err(hsotg->dev, " Interval: %d\n", urb->interval);
1573
1574 /* Core halts the channel for Descriptor DMA mode */
1575 if (hsotg->core_params->dma_desc_enable > 0) {
1576 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1577 DWC2_HC_XFER_AHB_ERR);
1578 goto handle_ahberr_done;
1579 }
1580
1581 dwc2_host_complete(hsotg, qtd, -EIO);
1582
1583handle_ahberr_halt:
1584 /*
1585 * Force a channel halt. Don't call dwc2_halt_channel because that won't
1586 * write to the HCCHARn register in DMA mode to force the halt.
1587 */
1588 dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1589
1590handle_ahberr_done:
1591 disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1592}
1593
1594/*
1595 * Handles a host channel transaction error interrupt. This handler may be
1596 * called in either DMA mode or Slave mode.
1597 */
1598static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1599 struct dwc2_host_chan *chan, int chnum,
1600 struct dwc2_qtd *qtd)
1601{
1602 dev_dbg(hsotg->dev,
1603 "--Host Channel %d Interrupt: Transaction Error--\n", chnum);
1604
1605 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1606
1607 if (hsotg->core_params->dma_desc_enable > 0) {
1608 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1609 DWC2_HC_XFER_XACT_ERR);
1610 goto handle_xacterr_done;
1611 }
1612
1613 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1614 case USB_ENDPOINT_XFER_CONTROL:
1615 case USB_ENDPOINT_XFER_BULK:
1616 qtd->error_count++;
1617 if (!chan->qh->ping_state) {
1618
1619 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1620 qtd, DWC2_HC_XFER_XACT_ERR);
1621 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1622 if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH)
1623 chan->qh->ping_state = 1;
1624 }
1625
1626 /*
1627 * Halt the channel so the transfer can be re-started from
1628 * the appropriate point or the PING protocol will start
1629 */
1630 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1631 break;
1632 case USB_ENDPOINT_XFER_INT:
1633 qtd->error_count++;
1634 if (chan->do_split && chan->complete_split)
1635 qtd->complete_split = 0;
1636 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1637 break;
1638 case USB_ENDPOINT_XFER_ISOC:
1639 {
1640 enum dwc2_halt_status halt_status;
1641
1642 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1643 chnum, qtd, DWC2_HC_XFER_XACT_ERR);
1644 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1645 }
1646 break;
1647 }
1648
1649handle_xacterr_done:
1650 disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1651}
1652
1653/*
1654 * Handles a host channel frame overrun interrupt. This handler may be called
1655 * in either DMA mode or Slave mode.
1656 */
1657static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1658 struct dwc2_host_chan *chan, int chnum,
1659 struct dwc2_qtd *qtd)
1660{
1661 enum dwc2_halt_status halt_status;
1662
1663 if (dbg_hc(chan))
1664 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1665 chnum);
1666
1667 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1668
1669 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1670 case USB_ENDPOINT_XFER_CONTROL:
1671 case USB_ENDPOINT_XFER_BULK:
1672 break;
1673 case USB_ENDPOINT_XFER_INT:
1674 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1675 break;
1676 case USB_ENDPOINT_XFER_ISOC:
1677 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1678 qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1679 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1680 break;
1681 }
1682
1683 disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1684}
1685
1686/*
1687 * Handles a host channel data toggle error interrupt. This handler may be
1688 * called in either DMA mode or Slave mode.
1689 */
1690static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1691 struct dwc2_host_chan *chan, int chnum,
1692 struct dwc2_qtd *qtd)
1693{
1694 dev_dbg(hsotg->dev,
1695 "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum);
1696
1697 if (chan->ep_is_in)
1698 qtd->error_count = 0;
1699 else
1700 dev_err(hsotg->dev,
1701 "Data Toggle Error on OUT transfer, channel %d\n",
1702 chnum);
1703
1704 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1705 disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1706}
1707
1708/*
1709 * For debug only. It checks that a valid halt status is set and that
1710 * HCCHARn.chdis is clear. If there's a problem, corrective action is
1711 * taken and a warning is issued.
1712 *
1713 * Return: true if halt status is ok, false otherwise
1714 */
1715static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1716 struct dwc2_host_chan *chan, int chnum,
1717 struct dwc2_qtd *qtd)
1718{
1719#ifdef DEBUG
1720 u32 hcchar;
1721 u32 hctsiz;
1722 u32 hcintmsk;
1723 u32 hcsplt;
1724
1725 if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) {
1726 /*
1727 * This code is here only as a check. This condition should
1728 * never happen. Ignore the halt if it does occur.
1729 */
1730 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1731 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1732 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1733 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1734 dev_dbg(hsotg->dev,
1735 "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
1736 __func__);
1737 dev_dbg(hsotg->dev,
1738 "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n",
1739 chnum, hcchar, hctsiz);
1740 dev_dbg(hsotg->dev,
1741 "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n",
1742 chan->hcint, hcintmsk, hcsplt);
1743 if (qtd)
1744 dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1745 qtd->complete_split);
1746 dev_warn(hsotg->dev,
1747 "%s: no halt status, channel %d, ignoring interrupt\n",
1748 __func__, chnum);
1749 return false;
1750 }
1751
1752 /*
1753 * This code is here only as a check. hcchar.chdis should never be set
1754 * when the halt interrupt occurs. Halt the channel again if it does
1755 * occur.
1756 */
1757 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1758 if (hcchar & HCCHAR_CHDIS) {
1759 dev_warn(hsotg->dev,
1760 "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
1761 __func__, hcchar);
1762 chan->halt_pending = 0;
1763 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1764 return false;
1765 }
1766#endif
1767
1768 return true;
1769}
1770
1771/*
1772 * Handles a host Channel Halted interrupt in DMA mode. This handler
1773 * determines the reason the channel halted and proceeds accordingly.
1774 */
1775static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1776 struct dwc2_host_chan *chan, int chnum,
1777 struct dwc2_qtd *qtd)
1778{
1779 u32 hcintmsk;
1780 int out_nak_enh = 0;
1781
1782 if (dbg_hc(chan))
1783 dev_vdbg(hsotg->dev,
1784 "--Host Channel %d Interrupt: DMA Channel Halted--\n",
1785 chnum);
1786
1787 /*
1788 * For core with OUT NAK enhancement, the flow for high-speed
1789 * CONTROL/BULK OUT is handled a little differently
1790 */
1791 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) {
1792 if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in &&
1793 (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1794 chan->ep_type == USB_ENDPOINT_XFER_BULK)) {
1795 out_nak_enh = 1;
1796 }
1797 }
1798
1799 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1800 (chan->halt_status == DWC2_HC_XFER_AHB_ERR &&
1801 hsotg->core_params->dma_desc_enable <= 0)) {
1802 if (hsotg->core_params->dma_desc_enable > 0)
1803 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1804 chan->halt_status);
1805 else
1806 /*
1807 * Just release the channel. A dequeue can happen on a
1808 * transfer timeout. In the case of an AHB Error, the
1809 * channel was forced to halt because there's no way to
1810 * gracefully recover.
1811 */
1812 dwc2_release_channel(hsotg, chan, qtd,
1813 chan->halt_status);
1814 return;
1815 }
1816
1817 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1818
1819 if (chan->hcint & HCINTMSK_XFERCOMPL) {
1820 /*
1821 * Todo: This is here because of a possible hardware bug. Spec
1822 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1823 * interrupt w/ACK bit set should occur, but I only see the
1824 * XFERCOMP bit, even with it masked out. This is a workaround
1825 * for that behavior. Should fix this when hardware is fixed.
1826 */
1827 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in)
1828 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1829 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1830 } else if (chan->hcint & HCINTMSK_STALL) {
1831 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1832 } else if ((chan->hcint & HCINTMSK_XACTERR) &&
1833 hsotg->core_params->dma_desc_enable <= 0) {
1834 if (out_nak_enh) {
1835 if (chan->hcint &
1836 (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
1837 dev_vdbg(hsotg->dev,
1838 "XactErr with NYET/NAK/ACK\n");
1839 qtd->error_count = 0;
1840 } else {
1841 dev_vdbg(hsotg->dev,
1842 "XactErr without NYET/NAK/ACK\n");
1843 }
1844 }
1845
1846 /*
1847 * Must handle xacterr before nak or ack. Could get a xacterr
1848 * at the same time as either of these on a BULK/CONTROL OUT
1849 * that started with a PING. The xacterr takes precedence.
1850 */
1851 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1852 } else if ((chan->hcint & HCINTMSK_XCS_XACT) &&
1853 hsotg->core_params->dma_desc_enable > 0) {
1854 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1855 } else if ((chan->hcint & HCINTMSK_AHBERR) &&
1856 hsotg->core_params->dma_desc_enable > 0) {
1857 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1858 } else if (chan->hcint & HCINTMSK_BBLERR) {
1859 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1860 } else if (chan->hcint & HCINTMSK_FRMOVRUN) {
1861 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1862 } else if (!out_nak_enh) {
1863 if (chan->hcint & HCINTMSK_NYET) {
1864 /*
1865 * Must handle nyet before nak or ack. Could get a nyet
1866 * at the same time as either of those on a BULK/CONTROL
1867 * OUT that started with a PING. The nyet takes
1868 * precedence.
1869 */
1870 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1871 } else if ((chan->hcint & HCINTMSK_NAK) &&
1872 !(hcintmsk & HCINTMSK_NAK)) {
1873 /*
1874 * If nak is not masked, it's because a non-split IN
1875 * transfer is in an error state. In that case, the nak
1876 * is handled by the nak interrupt handler, not here.
1877 * Handle nak here for BULK/CONTROL OUT transfers, which
1878 * halt on a NAK to allow rewinding the buffer pointer.
1879 */
1880 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1881 } else if ((chan->hcint & HCINTMSK_ACK) &&
1882 !(hcintmsk & HCINTMSK_ACK)) {
1883 /*
1884 * If ack is not masked, it's because a non-split IN
1885 * transfer is in an error state. In that case, the ack
1886 * is handled by the ack interrupt handler, not here.
1887 * Handle ack here for split transfers. Start splits
1888 * halt on ACK.
1889 */
1890 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1891 } else {
1892 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1893 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1894 /*
1895 * A periodic transfer halted with no other
1896 * channel interrupts set. Assume it was halted
1897 * by the core because it could not be completed
1898 * in its scheduled (micro)frame.
1899 */
1900 dev_dbg(hsotg->dev,
1901 "%s: Halt channel %d (assume incomplete periodic transfer)\n",
1902 __func__, chnum);
1903 dwc2_halt_channel(hsotg, chan, qtd,
1904 DWC2_HC_XFER_PERIODIC_INCOMPLETE);
1905 } else {
1906 dev_err(hsotg->dev,
1907 "%s: Channel %d - ChHltd set, but reason is unknown\n",
1908 __func__, chnum);
1909 dev_err(hsotg->dev,
1910 "hcint 0x%08x, intsts 0x%08x\n",
1911 chan->hcint,
1912 dwc2_readl(hsotg->regs + GINTSTS));
1913 goto error;
1914 }
1915 }
1916 } else {
1917 dev_info(hsotg->dev,
1918 "NYET/NAK/ACK/other in non-error case, 0x%08x\n",
1919 chan->hcint);
1920error:
1921 /* Failthrough: use 3-strikes rule */
1922 qtd->error_count++;
1923 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1924 qtd, DWC2_HC_XFER_XACT_ERR);
1925 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1926 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1927 }
1928}
1929
1930/*
1931 * Handles a host channel Channel Halted interrupt
1932 *
1933 * In slave mode, this handler is called only when the driver specifically
1934 * requests a halt. This occurs during handling other host channel interrupts
1935 * (e.g. nak, xacterr, stall, nyet, etc.).
1936 *
1937 * In DMA mode, this is the interrupt that occurs when the core has finished
1938 * processing a transfer on a channel. Other host channel interrupts (except
1939 * ahberr) are disabled in DMA mode.
1940 */
1941static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
1942 struct dwc2_host_chan *chan, int chnum,
1943 struct dwc2_qtd *qtd)
1944{
1945 if (dbg_hc(chan))
1946 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
1947 chnum);
1948
1949 if (hsotg->core_params->dma_enable > 0) {
1950 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
1951 } else {
1952 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
1953 return;
1954 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
1955 }
1956}
1957
1958/*
1959 * Check if the given qtd is still the top of the list (and thus valid).
1960 *
1961 * If dwc2_hcd_qtd_unlink_and_free() has been called since we grabbed
1962 * the qtd from the top of the list, this will return false (otherwise true).
1963 */
1964static bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh)
1965{
1966 struct dwc2_qtd *cur_head;
1967
1968 if (qh == NULL)
1969 return false;
1970
1971 cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd,
1972 qtd_list_entry);
1973 return (cur_head == qtd);
1974}
1975
1976/* Handles interrupt for a specific Host Channel */
1977static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
1978{
1979 struct dwc2_qtd *qtd;
1980 struct dwc2_host_chan *chan;
1981 u32 hcint, hcintmsk;
1982
1983 chan = hsotg->hc_ptr_array[chnum];
1984
1985 hcint = dwc2_readl(hsotg->regs + HCINT(chnum));
1986 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1987 if (!chan) {
1988 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
1989 dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
1990 return;
1991 }
1992
1993 if (dbg_hc(chan)) {
1994 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
1995 chnum);
1996 dev_vdbg(hsotg->dev,
1997 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
1998 hcint, hcintmsk, hcint & hcintmsk);
1999 }
2000
2001 dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
2002
2003 /*
2004 * If we got an interrupt after someone called
2005 * dwc2_hcd_endpoint_disable() we don't want to crash below
2006 */
2007 if (!chan->qh) {
2008 dev_warn(hsotg->dev, "Interrupt on disabled channel\n");
2009 return;
2010 }
2011
2012 chan->hcint = hcint;
2013 hcint &= hcintmsk;
2014
2015 /*
2016 * If the channel was halted due to a dequeue, the qtd list might
2017 * be empty or at least the first entry will not be the active qtd.
2018 * In this case, take a shortcut and just release the channel.
2019 */
2020 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) {
2021 /*
2022 * If the channel was halted, this should be the only
2023 * interrupt unmasked
2024 */
2025 WARN_ON(hcint != HCINTMSK_CHHLTD);
2026 if (hsotg->core_params->dma_desc_enable > 0)
2027 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
2028 chan->halt_status);
2029 else
2030 dwc2_release_channel(hsotg, chan, NULL,
2031 chan->halt_status);
2032 return;
2033 }
2034
2035 if (list_empty(&chan->qh->qtd_list)) {
2036 /*
2037 * TODO: Will this ever happen with the
2038 * DWC2_HC_XFER_URB_DEQUEUE handling above?
2039 */
2040 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
2041 chnum);
2042 dev_dbg(hsotg->dev,
2043 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2044 chan->hcint, hcintmsk, hcint);
2045 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2046 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
2047 chan->hcint = 0;
2048 return;
2049 }
2050
2051 qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd,
2052 qtd_list_entry);
2053
2054 if (hsotg->core_params->dma_enable <= 0) {
2055 if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD)
2056 hcint &= ~HCINTMSK_CHHLTD;
2057 }
2058
2059 if (hcint & HCINTMSK_XFERCOMPL) {
2060 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
2061 /*
2062 * If NYET occurred at same time as Xfer Complete, the NYET is
2063 * handled by the Xfer Complete interrupt handler. Don't want
2064 * to call the NYET interrupt handler in this case.
2065 */
2066 hcint &= ~HCINTMSK_NYET;
2067 }
2068
2069 if (hcint & HCINTMSK_CHHLTD) {
2070 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
2071 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2072 goto exit;
2073 }
2074 if (hcint & HCINTMSK_AHBERR) {
2075 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
2076 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2077 goto exit;
2078 }
2079 if (hcint & HCINTMSK_STALL) {
2080 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
2081 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2082 goto exit;
2083 }
2084 if (hcint & HCINTMSK_NAK) {
2085 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
2086 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2087 goto exit;
2088 }
2089 if (hcint & HCINTMSK_ACK) {
2090 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
2091 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2092 goto exit;
2093 }
2094 if (hcint & HCINTMSK_NYET) {
2095 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
2096 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2097 goto exit;
2098 }
2099 if (hcint & HCINTMSK_XACTERR) {
2100 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
2101 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2102 goto exit;
2103 }
2104 if (hcint & HCINTMSK_BBLERR) {
2105 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
2106 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2107 goto exit;
2108 }
2109 if (hcint & HCINTMSK_FRMOVRUN) {
2110 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
2111 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2112 goto exit;
2113 }
2114 if (hcint & HCINTMSK_DATATGLERR) {
2115 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
2116 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2117 goto exit;
2118 }
2119
2120exit:
2121 chan->hcint = 0;
2122}
2123
2124/*
2125 * This interrupt indicates that one or more host channels has a pending
2126 * interrupt. There are multiple conditions that can cause each host channel
2127 * interrupt. This function determines which conditions have occurred for each
2128 * host channel interrupt and handles them appropriately.
2129 */
2130static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2131{
2132 u32 haint;
2133 int i;
2134 struct dwc2_host_chan *chan, *chan_tmp;
2135
2136 haint = dwc2_readl(hsotg->regs + HAINT);
2137 if (dbg_perio()) {
2138 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2139
2140 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2141 }
2142
2143 /*
2144 * According to USB 2.0 spec section 11.18.8, a host must
2145 * issue complete-split transactions in a microframe for a
2146 * set of full-/low-speed endpoints in the same relative
2147 * order as the start-splits were issued in a microframe for.
2148 */
2149 list_for_each_entry_safe(chan, chan_tmp, &hsotg->split_order,
2150 split_order_list_entry) {
2151 int hc_num = chan->hc_num;
2152
2153 if (haint & (1 << hc_num)) {
2154 dwc2_hc_n_intr(hsotg, hc_num);
2155 haint &= ~(1 << hc_num);
2156 }
2157 }
2158
2159 for (i = 0; i < hsotg->core_params->host_channels; i++) {
2160 if (haint & (1 << i))
2161 dwc2_hc_n_intr(hsotg, i);
2162 }
2163}
2164
2165/* This function handles interrupts for the HCD */
2166irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2167{
2168 u32 gintsts, dbg_gintsts;
2169 irqreturn_t retval = IRQ_NONE;
2170
2171 if (!dwc2_is_controller_alive(hsotg)) {
2172 dev_warn(hsotg->dev, "Controller is dead\n");
2173 return retval;
2174 }
2175
2176 spin_lock(&hsotg->lock);
2177
2178 /* Check if HOST Mode */
2179 if (dwc2_is_host_mode(hsotg)) {
2180 gintsts = dwc2_read_core_intr(hsotg);
2181 if (!gintsts) {
2182 spin_unlock(&hsotg->lock);
2183 return retval;
2184 }
2185
2186 retval = IRQ_HANDLED;
2187
2188 dbg_gintsts = gintsts;
2189#ifndef DEBUG_SOF
2190 dbg_gintsts &= ~GINTSTS_SOF;
2191#endif
2192 if (!dbg_perio())
2193 dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL |
2194 GINTSTS_PTXFEMP);
2195
2196 /* Only print if there are any non-suppressed interrupts left */
2197 if (dbg_gintsts)
2198 dev_vdbg(hsotg->dev,
2199 "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
2200 gintsts);
2201
2202 if (gintsts & GINTSTS_SOF)
2203 dwc2_sof_intr(hsotg);
2204 if (gintsts & GINTSTS_RXFLVL)
2205 dwc2_rx_fifo_level_intr(hsotg);
2206 if (gintsts & GINTSTS_NPTXFEMP)
2207 dwc2_np_tx_fifo_empty_intr(hsotg);
2208 if (gintsts & GINTSTS_PRTINT)
2209 dwc2_port_intr(hsotg);
2210 if (gintsts & GINTSTS_HCHINT)
2211 dwc2_hc_intr(hsotg);
2212 if (gintsts & GINTSTS_PTXFEMP)
2213 dwc2_perio_tx_fifo_empty_intr(hsotg);
2214
2215 if (dbg_gintsts) {
2216 dev_vdbg(hsotg->dev,
2217 "DWC OTG HCD Finished Servicing Interrupts\n");
2218 dev_vdbg(hsotg->dev,
2219 "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
2220 dwc2_readl(hsotg->regs + GINTSTS),
2221 dwc2_readl(hsotg->regs + GINTMSK));
2222 }
2223 }
2224
2225 spin_unlock(&hsotg->lock);
2226
2227 return retval;
2228}