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1/*
2 * Copyright 2009 Wolfson Microelectronics plc
3 *
4 * S3C64xx CPUfreq Support
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/cpufreq.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/regulator/consumer.h>
18
19static struct clk *armclk;
20static struct regulator *vddarm;
21static unsigned long regulator_latency;
22
23#ifdef CONFIG_CPU_S3C6410
24struct s3c64xx_dvfs {
25 unsigned int vddarm_min;
26 unsigned int vddarm_max;
27};
28
29static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
30 [0] = { 1000000, 1150000 },
31 [1] = { 1050000, 1150000 },
32 [2] = { 1100000, 1150000 },
33 [3] = { 1200000, 1350000 },
34 [4] = { 1300000, 1350000 },
35};
36
37static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
38 { 0, 66000 },
39 { 0, 100000 },
40 { 0, 133000 },
41 { 1, 200000 },
42 { 1, 222000 },
43 { 1, 266000 },
44 { 2, 333000 },
45 { 2, 400000 },
46 { 2, 532000 },
47 { 2, 533000 },
48 { 3, 667000 },
49 { 4, 800000 },
50 { 0, CPUFREQ_TABLE_END },
51};
52#endif
53
54static int s3c64xx_cpufreq_verify_speed(struct cpufreq_policy *policy)
55{
56 if (policy->cpu != 0)
57 return -EINVAL;
58
59 return cpufreq_frequency_table_verify(policy, s3c64xx_freq_table);
60}
61
62static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu)
63{
64 if (cpu != 0)
65 return 0;
66
67 return clk_get_rate(armclk) / 1000;
68}
69
70static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
71 unsigned int target_freq,
72 unsigned int relation)
73{
74 int ret;
75 unsigned int i;
76 struct cpufreq_freqs freqs;
77 struct s3c64xx_dvfs *dvfs;
78
79 ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table,
80 target_freq, relation, &i);
81 if (ret != 0)
82 return ret;
83
84 freqs.cpu = 0;
85 freqs.old = clk_get_rate(armclk) / 1000;
86 freqs.new = s3c64xx_freq_table[i].frequency;
87 freqs.flags = 0;
88 dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index];
89
90 if (freqs.old == freqs.new)
91 return 0;
92
93 pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new);
94
95 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
96
97#ifdef CONFIG_REGULATOR
98 if (vddarm && freqs.new > freqs.old) {
99 ret = regulator_set_voltage(vddarm,
100 dvfs->vddarm_min,
101 dvfs->vddarm_max);
102 if (ret != 0) {
103 pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
104 freqs.new, ret);
105 goto err;
106 }
107 }
108#endif
109
110 ret = clk_set_rate(armclk, freqs.new * 1000);
111 if (ret < 0) {
112 pr_err("cpufreq: Failed to set rate %dkHz: %d\n",
113 freqs.new, ret);
114 goto err;
115 }
116
117 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
118
119#ifdef CONFIG_REGULATOR
120 if (vddarm && freqs.new < freqs.old) {
121 ret = regulator_set_voltage(vddarm,
122 dvfs->vddarm_min,
123 dvfs->vddarm_max);
124 if (ret != 0) {
125 pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
126 freqs.new, ret);
127 goto err_clk;
128 }
129 }
130#endif
131
132 pr_debug("cpufreq: Set actual frequency %lukHz\n",
133 clk_get_rate(armclk) / 1000);
134
135 return 0;
136
137err_clk:
138 if (clk_set_rate(armclk, freqs.old * 1000) < 0)
139 pr_err("Failed to restore original clock rate\n");
140err:
141 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
142
143 return ret;
144}
145
146#ifdef CONFIG_REGULATOR
147static void __init s3c64xx_cpufreq_config_regulator(void)
148{
149 int count, v, i, found;
150 struct cpufreq_frequency_table *freq;
151 struct s3c64xx_dvfs *dvfs;
152
153 count = regulator_count_voltages(vddarm);
154 if (count < 0) {
155 pr_err("cpufreq: Unable to check supported voltages\n");
156 }
157
158 freq = s3c64xx_freq_table;
159 while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) {
160 if (freq->frequency == CPUFREQ_ENTRY_INVALID)
161 continue;
162
163 dvfs = &s3c64xx_dvfs_table[freq->index];
164 found = 0;
165
166 for (i = 0; i < count; i++) {
167 v = regulator_list_voltage(vddarm, i);
168 if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
169 found = 1;
170 }
171
172 if (!found) {
173 pr_debug("cpufreq: %dkHz unsupported by regulator\n",
174 freq->frequency);
175 freq->frequency = CPUFREQ_ENTRY_INVALID;
176 }
177
178 freq++;
179 }
180
181 /* Guess based on having to do an I2C/SPI write; in future we
182 * will be able to query the regulator performance here. */
183 regulator_latency = 1 * 1000 * 1000;
184}
185#endif
186
187static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
188{
189 int ret;
190 struct cpufreq_frequency_table *freq;
191
192 if (policy->cpu != 0)
193 return -EINVAL;
194
195 if (s3c64xx_freq_table == NULL) {
196 pr_err("cpufreq: No frequency information for this CPU\n");
197 return -ENODEV;
198 }
199
200 armclk = clk_get(NULL, "armclk");
201 if (IS_ERR(armclk)) {
202 pr_err("cpufreq: Unable to obtain ARMCLK: %ld\n",
203 PTR_ERR(armclk));
204 return PTR_ERR(armclk);
205 }
206
207#ifdef CONFIG_REGULATOR
208 vddarm = regulator_get(NULL, "vddarm");
209 if (IS_ERR(vddarm)) {
210 ret = PTR_ERR(vddarm);
211 pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret);
212 pr_err("cpufreq: Only frequency scaling available\n");
213 vddarm = NULL;
214 } else {
215 s3c64xx_cpufreq_config_regulator();
216 }
217#endif
218
219 freq = s3c64xx_freq_table;
220 while (freq->frequency != CPUFREQ_TABLE_END) {
221 unsigned long r;
222
223 /* Check for frequencies we can generate */
224 r = clk_round_rate(armclk, freq->frequency * 1000);
225 r /= 1000;
226 if (r != freq->frequency) {
227 pr_debug("cpufreq: %dkHz unsupported by clock\n",
228 freq->frequency);
229 freq->frequency = CPUFREQ_ENTRY_INVALID;
230 }
231
232 /* If we have no regulator then assume startup
233 * frequency is the maximum we can support. */
234 if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0))
235 freq->frequency = CPUFREQ_ENTRY_INVALID;
236
237 freq++;
238 }
239
240 policy->cur = clk_get_rate(armclk) / 1000;
241
242 /* Datasheet says PLL stabalisation time (if we were to use
243 * the PLLs, which we don't currently) is ~300us worst case,
244 * but add some fudge.
245 */
246 policy->cpuinfo.transition_latency = (500 * 1000) + regulator_latency;
247
248 ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
249 if (ret != 0) {
250 pr_err("cpufreq: Failed to configure frequency table: %d\n",
251 ret);
252 regulator_put(vddarm);
253 clk_put(armclk);
254 }
255
256 return ret;
257}
258
259static struct cpufreq_driver s3c64xx_cpufreq_driver = {
260 .owner = THIS_MODULE,
261 .flags = 0,
262 .verify = s3c64xx_cpufreq_verify_speed,
263 .target = s3c64xx_cpufreq_set_target,
264 .get = s3c64xx_cpufreq_get_speed,
265 .init = s3c64xx_cpufreq_driver_init,
266 .name = "s3c",
267};
268
269static int __init s3c64xx_cpufreq_init(void)
270{
271 return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
272}
273module_init(s3c64xx_cpufreq_init);
1/*
2 * Copyright 2009 Wolfson Microelectronics plc
3 *
4 * S3C64xx CPUfreq Support
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#define pr_fmt(fmt) "cpufreq: " fmt
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/init.h>
16#include <linux/cpufreq.h>
17#include <linux/clk.h>
18#include <linux/err.h>
19#include <linux/regulator/consumer.h>
20#include <linux/module.h>
21
22static struct regulator *vddarm;
23static unsigned long regulator_latency;
24
25#ifdef CONFIG_CPU_S3C6410
26struct s3c64xx_dvfs {
27 unsigned int vddarm_min;
28 unsigned int vddarm_max;
29};
30
31static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
32 [0] = { 1000000, 1150000 },
33 [1] = { 1050000, 1150000 },
34 [2] = { 1100000, 1150000 },
35 [3] = { 1200000, 1350000 },
36 [4] = { 1300000, 1350000 },
37};
38
39static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
40 { 0, 0, 66000 },
41 { 0, 0, 100000 },
42 { 0, 0, 133000 },
43 { 0, 1, 200000 },
44 { 0, 1, 222000 },
45 { 0, 1, 266000 },
46 { 0, 2, 333000 },
47 { 0, 2, 400000 },
48 { 0, 2, 532000 },
49 { 0, 2, 533000 },
50 { 0, 3, 667000 },
51 { 0, 4, 800000 },
52 { 0, 0, CPUFREQ_TABLE_END },
53};
54#endif
55
56static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
57 unsigned int index)
58{
59 struct s3c64xx_dvfs *dvfs;
60 unsigned int old_freq, new_freq;
61 int ret;
62
63 old_freq = clk_get_rate(policy->clk) / 1000;
64 new_freq = s3c64xx_freq_table[index].frequency;
65 dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[index].driver_data];
66
67#ifdef CONFIG_REGULATOR
68 if (vddarm && new_freq > old_freq) {
69 ret = regulator_set_voltage(vddarm,
70 dvfs->vddarm_min,
71 dvfs->vddarm_max);
72 if (ret != 0) {
73 pr_err("Failed to set VDDARM for %dkHz: %d\n",
74 new_freq, ret);
75 return ret;
76 }
77 }
78#endif
79
80 ret = clk_set_rate(policy->clk, new_freq * 1000);
81 if (ret < 0) {
82 pr_err("Failed to set rate %dkHz: %d\n",
83 new_freq, ret);
84 return ret;
85 }
86
87#ifdef CONFIG_REGULATOR
88 if (vddarm && new_freq < old_freq) {
89 ret = regulator_set_voltage(vddarm,
90 dvfs->vddarm_min,
91 dvfs->vddarm_max);
92 if (ret != 0) {
93 pr_err("Failed to set VDDARM for %dkHz: %d\n",
94 new_freq, ret);
95 if (clk_set_rate(policy->clk, old_freq * 1000) < 0)
96 pr_err("Failed to restore original clock rate\n");
97
98 return ret;
99 }
100 }
101#endif
102
103 pr_debug("Set actual frequency %lukHz\n",
104 clk_get_rate(policy->clk) / 1000);
105
106 return 0;
107}
108
109#ifdef CONFIG_REGULATOR
110static void __init s3c64xx_cpufreq_config_regulator(void)
111{
112 int count, v, i, found;
113 struct cpufreq_frequency_table *freq;
114 struct s3c64xx_dvfs *dvfs;
115
116 count = regulator_count_voltages(vddarm);
117 if (count < 0) {
118 pr_err("Unable to check supported voltages\n");
119 }
120
121 if (!count)
122 goto out;
123
124 cpufreq_for_each_valid_entry(freq, s3c64xx_freq_table) {
125 dvfs = &s3c64xx_dvfs_table[freq->driver_data];
126 found = 0;
127
128 for (i = 0; i < count; i++) {
129 v = regulator_list_voltage(vddarm, i);
130 if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
131 found = 1;
132 }
133
134 if (!found) {
135 pr_debug("%dkHz unsupported by regulator\n",
136 freq->frequency);
137 freq->frequency = CPUFREQ_ENTRY_INVALID;
138 }
139 }
140
141out:
142 /* Guess based on having to do an I2C/SPI write; in future we
143 * will be able to query the regulator performance here. */
144 regulator_latency = 1 * 1000 * 1000;
145}
146#endif
147
148static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
149{
150 int ret;
151 struct cpufreq_frequency_table *freq;
152
153 if (policy->cpu != 0)
154 return -EINVAL;
155
156 if (s3c64xx_freq_table == NULL) {
157 pr_err("No frequency information for this CPU\n");
158 return -ENODEV;
159 }
160
161 policy->clk = clk_get(NULL, "armclk");
162 if (IS_ERR(policy->clk)) {
163 pr_err("Unable to obtain ARMCLK: %ld\n",
164 PTR_ERR(policy->clk));
165 return PTR_ERR(policy->clk);
166 }
167
168#ifdef CONFIG_REGULATOR
169 vddarm = regulator_get(NULL, "vddarm");
170 if (IS_ERR(vddarm)) {
171 ret = PTR_ERR(vddarm);
172 pr_err("Failed to obtain VDDARM: %d\n", ret);
173 pr_err("Only frequency scaling available\n");
174 vddarm = NULL;
175 } else {
176 s3c64xx_cpufreq_config_regulator();
177 }
178#endif
179
180 cpufreq_for_each_entry(freq, s3c64xx_freq_table) {
181 unsigned long r;
182
183 /* Check for frequencies we can generate */
184 r = clk_round_rate(policy->clk, freq->frequency * 1000);
185 r /= 1000;
186 if (r != freq->frequency) {
187 pr_debug("%dkHz unsupported by clock\n",
188 freq->frequency);
189 freq->frequency = CPUFREQ_ENTRY_INVALID;
190 }
191
192 /* If we have no regulator then assume startup
193 * frequency is the maximum we can support. */
194 if (!vddarm && freq->frequency > clk_get_rate(policy->clk) / 1000)
195 freq->frequency = CPUFREQ_ENTRY_INVALID;
196 }
197
198 /* Datasheet says PLL stabalisation time (if we were to use
199 * the PLLs, which we don't currently) is ~300us worst case,
200 * but add some fudge.
201 */
202 ret = cpufreq_generic_init(policy, s3c64xx_freq_table,
203 (500 * 1000) + regulator_latency);
204 if (ret != 0) {
205 pr_err("Failed to configure frequency table: %d\n",
206 ret);
207 regulator_put(vddarm);
208 clk_put(policy->clk);
209 }
210
211 return ret;
212}
213
214static struct cpufreq_driver s3c64xx_cpufreq_driver = {
215 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
216 .verify = cpufreq_generic_frequency_table_verify,
217 .target_index = s3c64xx_cpufreq_set_target,
218 .get = cpufreq_generic_get,
219 .init = s3c64xx_cpufreq_driver_init,
220 .name = "s3c",
221};
222
223static int __init s3c64xx_cpufreq_init(void)
224{
225 return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
226}
227module_init(s3c64xx_cpufreq_init);