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1/*
2 * Derived from arch/powerpc/kernel/iommu.c
3 *
4 * Copyright IBM Corporation, 2006-2007
5 * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us>
6 *
7 * Author: Jon Mason <jdmason@kudzu.us>
8 * Author: Muli Ben-Yehuda <muli@il.ibm.com>
9
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25#include <linux/kernel.h>
26#include <linux/init.h>
27#include <linux/types.h>
28#include <linux/slab.h>
29#include <linux/mm.h>
30#include <linux/spinlock.h>
31#include <linux/string.h>
32#include <linux/crash_dump.h>
33#include <linux/dma-mapping.h>
34#include <linux/bitmap.h>
35#include <linux/pci_ids.h>
36#include <linux/pci.h>
37#include <linux/delay.h>
38#include <linux/scatterlist.h>
39#include <linux/iommu-helper.h>
40
41#include <asm/iommu.h>
42#include <asm/calgary.h>
43#include <asm/tce.h>
44#include <asm/pci-direct.h>
45#include <asm/system.h>
46#include <asm/dma.h>
47#include <asm/rio.h>
48#include <asm/bios_ebda.h>
49#include <asm/x86_init.h>
50#include <asm/iommu_table.h>
51
52#ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
53int use_calgary __read_mostly = 1;
54#else
55int use_calgary __read_mostly = 0;
56#endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
57
58#define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
59#define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
60
61/* register offsets inside the host bridge space */
62#define CALGARY_CONFIG_REG 0x0108
63#define PHB_CSR_OFFSET 0x0110 /* Channel Status */
64#define PHB_PLSSR_OFFSET 0x0120
65#define PHB_CONFIG_RW_OFFSET 0x0160
66#define PHB_IOBASE_BAR_LOW 0x0170
67#define PHB_IOBASE_BAR_HIGH 0x0180
68#define PHB_MEM_1_LOW 0x0190
69#define PHB_MEM_1_HIGH 0x01A0
70#define PHB_IO_ADDR_SIZE 0x01B0
71#define PHB_MEM_1_SIZE 0x01C0
72#define PHB_MEM_ST_OFFSET 0x01D0
73#define PHB_AER_OFFSET 0x0200
74#define PHB_CONFIG_0_HIGH 0x0220
75#define PHB_CONFIG_0_LOW 0x0230
76#define PHB_CONFIG_0_END 0x0240
77#define PHB_MEM_2_LOW 0x02B0
78#define PHB_MEM_2_HIGH 0x02C0
79#define PHB_MEM_2_SIZE_HIGH 0x02D0
80#define PHB_MEM_2_SIZE_LOW 0x02E0
81#define PHB_DOSHOLE_OFFSET 0x08E0
82
83/* CalIOC2 specific */
84#define PHB_SAVIOR_L2 0x0DB0
85#define PHB_PAGE_MIG_CTRL 0x0DA8
86#define PHB_PAGE_MIG_DEBUG 0x0DA0
87#define PHB_ROOT_COMPLEX_STATUS 0x0CB0
88
89/* PHB_CONFIG_RW */
90#define PHB_TCE_ENABLE 0x20000000
91#define PHB_SLOT_DISABLE 0x1C000000
92#define PHB_DAC_DISABLE 0x01000000
93#define PHB_MEM2_ENABLE 0x00400000
94#define PHB_MCSR_ENABLE 0x00100000
95/* TAR (Table Address Register) */
96#define TAR_SW_BITS 0x0000ffffffff800fUL
97#define TAR_VALID 0x0000000000000008UL
98/* CSR (Channel/DMA Status Register) */
99#define CSR_AGENT_MASK 0xffe0ffff
100/* CCR (Calgary Configuration Register) */
101#define CCR_2SEC_TIMEOUT 0x000000000000000EUL
102/* PMCR/PMDR (Page Migration Control/Debug Registers */
103#define PMR_SOFTSTOP 0x80000000
104#define PMR_SOFTSTOPFAULT 0x40000000
105#define PMR_HARDSTOP 0x20000000
106
107/*
108 * The maximum PHB bus number.
109 * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
110 * x3950M2: 4 chassis, 48 PHBs per chassis = 192
111 * x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
112 * x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
113 */
114#define MAX_PHB_BUS_NUM 256
115
116#define PHBS_PER_CALGARY 4
117
118/* register offsets in Calgary's internal register space */
119static const unsigned long tar_offsets[] = {
120 0x0580 /* TAR0 */,
121 0x0588 /* TAR1 */,
122 0x0590 /* TAR2 */,
123 0x0598 /* TAR3 */
124};
125
126static const unsigned long split_queue_offsets[] = {
127 0x4870 /* SPLIT QUEUE 0 */,
128 0x5870 /* SPLIT QUEUE 1 */,
129 0x6870 /* SPLIT QUEUE 2 */,
130 0x7870 /* SPLIT QUEUE 3 */
131};
132
133static const unsigned long phb_offsets[] = {
134 0x8000 /* PHB0 */,
135 0x9000 /* PHB1 */,
136 0xA000 /* PHB2 */,
137 0xB000 /* PHB3 */
138};
139
140/* PHB debug registers */
141
142static const unsigned long phb_debug_offsets[] = {
143 0x4000 /* PHB 0 DEBUG */,
144 0x5000 /* PHB 1 DEBUG */,
145 0x6000 /* PHB 2 DEBUG */,
146 0x7000 /* PHB 3 DEBUG */
147};
148
149/*
150 * STUFF register for each debug PHB,
151 * byte 1 = start bus number, byte 2 = end bus number
152 */
153
154#define PHB_DEBUG_STUFF_OFFSET 0x0020
155
156#define EMERGENCY_PAGES 32 /* = 128KB */
157
158unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
159static int translate_empty_slots __read_mostly = 0;
160static int calgary_detected __read_mostly = 0;
161
162static struct rio_table_hdr *rio_table_hdr __initdata;
163static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata;
164static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata;
165
166struct calgary_bus_info {
167 void *tce_space;
168 unsigned char translation_disabled;
169 signed char phbid;
170 void __iomem *bbar;
171};
172
173static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
174static void calgary_tce_cache_blast(struct iommu_table *tbl);
175static void calgary_dump_error_regs(struct iommu_table *tbl);
176static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
177static void calioc2_tce_cache_blast(struct iommu_table *tbl);
178static void calioc2_dump_error_regs(struct iommu_table *tbl);
179static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
180static void get_tce_space_from_tar(void);
181
182static struct cal_chipset_ops calgary_chip_ops = {
183 .handle_quirks = calgary_handle_quirks,
184 .tce_cache_blast = calgary_tce_cache_blast,
185 .dump_error_regs = calgary_dump_error_regs
186};
187
188static struct cal_chipset_ops calioc2_chip_ops = {
189 .handle_quirks = calioc2_handle_quirks,
190 .tce_cache_blast = calioc2_tce_cache_blast,
191 .dump_error_regs = calioc2_dump_error_regs
192};
193
194static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
195
196static inline int translation_enabled(struct iommu_table *tbl)
197{
198 /* only PHBs with translation enabled have an IOMMU table */
199 return (tbl != NULL);
200}
201
202static void iommu_range_reserve(struct iommu_table *tbl,
203 unsigned long start_addr, unsigned int npages)
204{
205 unsigned long index;
206 unsigned long end;
207 unsigned long flags;
208
209 index = start_addr >> PAGE_SHIFT;
210
211 /* bail out if we're asked to reserve a region we don't cover */
212 if (index >= tbl->it_size)
213 return;
214
215 end = index + npages;
216 if (end > tbl->it_size) /* don't go off the table */
217 end = tbl->it_size;
218
219 spin_lock_irqsave(&tbl->it_lock, flags);
220
221 bitmap_set(tbl->it_map, index, npages);
222
223 spin_unlock_irqrestore(&tbl->it_lock, flags);
224}
225
226static unsigned long iommu_range_alloc(struct device *dev,
227 struct iommu_table *tbl,
228 unsigned int npages)
229{
230 unsigned long flags;
231 unsigned long offset;
232 unsigned long boundary_size;
233
234 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
235 PAGE_SIZE) >> PAGE_SHIFT;
236
237 BUG_ON(npages == 0);
238
239 spin_lock_irqsave(&tbl->it_lock, flags);
240
241 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
242 npages, 0, boundary_size, 0);
243 if (offset == ~0UL) {
244 tbl->chip_ops->tce_cache_blast(tbl);
245
246 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
247 npages, 0, boundary_size, 0);
248 if (offset == ~0UL) {
249 printk(KERN_WARNING "Calgary: IOMMU full.\n");
250 spin_unlock_irqrestore(&tbl->it_lock, flags);
251 if (panic_on_overflow)
252 panic("Calgary: fix the allocator.\n");
253 else
254 return DMA_ERROR_CODE;
255 }
256 }
257
258 tbl->it_hint = offset + npages;
259 BUG_ON(tbl->it_hint > tbl->it_size);
260
261 spin_unlock_irqrestore(&tbl->it_lock, flags);
262
263 return offset;
264}
265
266static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
267 void *vaddr, unsigned int npages, int direction)
268{
269 unsigned long entry;
270 dma_addr_t ret;
271
272 entry = iommu_range_alloc(dev, tbl, npages);
273
274 if (unlikely(entry == DMA_ERROR_CODE)) {
275 printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
276 "iommu %p\n", npages, tbl);
277 return DMA_ERROR_CODE;
278 }
279
280 /* set the return dma address */
281 ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
282
283 /* put the TCEs in the HW table */
284 tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
285 direction);
286 return ret;
287}
288
289static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
290 unsigned int npages)
291{
292 unsigned long entry;
293 unsigned long badend;
294 unsigned long flags;
295
296 /* were we called with bad_dma_address? */
297 badend = DMA_ERROR_CODE + (EMERGENCY_PAGES * PAGE_SIZE);
298 if (unlikely((dma_addr >= DMA_ERROR_CODE) && (dma_addr < badend))) {
299 WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
300 "address 0x%Lx\n", dma_addr);
301 return;
302 }
303
304 entry = dma_addr >> PAGE_SHIFT;
305
306 BUG_ON(entry + npages > tbl->it_size);
307
308 tce_free(tbl, entry, npages);
309
310 spin_lock_irqsave(&tbl->it_lock, flags);
311
312 bitmap_clear(tbl->it_map, entry, npages);
313
314 spin_unlock_irqrestore(&tbl->it_lock, flags);
315}
316
317static inline struct iommu_table *find_iommu_table(struct device *dev)
318{
319 struct pci_dev *pdev;
320 struct pci_bus *pbus;
321 struct iommu_table *tbl;
322
323 pdev = to_pci_dev(dev);
324
325 /* search up the device tree for an iommu */
326 pbus = pdev->bus;
327 do {
328 tbl = pci_iommu(pbus);
329 if (tbl && tbl->it_busno == pbus->number)
330 break;
331 tbl = NULL;
332 pbus = pbus->parent;
333 } while (pbus);
334
335 BUG_ON(tbl && (tbl->it_busno != pbus->number));
336
337 return tbl;
338}
339
340static void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
341 int nelems,enum dma_data_direction dir,
342 struct dma_attrs *attrs)
343{
344 struct iommu_table *tbl = find_iommu_table(dev);
345 struct scatterlist *s;
346 int i;
347
348 if (!translation_enabled(tbl))
349 return;
350
351 for_each_sg(sglist, s, nelems, i) {
352 unsigned int npages;
353 dma_addr_t dma = s->dma_address;
354 unsigned int dmalen = s->dma_length;
355
356 if (dmalen == 0)
357 break;
358
359 npages = iommu_num_pages(dma, dmalen, PAGE_SIZE);
360 iommu_free(tbl, dma, npages);
361 }
362}
363
364static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
365 int nelems, enum dma_data_direction dir,
366 struct dma_attrs *attrs)
367{
368 struct iommu_table *tbl = find_iommu_table(dev);
369 struct scatterlist *s;
370 unsigned long vaddr;
371 unsigned int npages;
372 unsigned long entry;
373 int i;
374
375 for_each_sg(sg, s, nelems, i) {
376 BUG_ON(!sg_page(s));
377
378 vaddr = (unsigned long) sg_virt(s);
379 npages = iommu_num_pages(vaddr, s->length, PAGE_SIZE);
380
381 entry = iommu_range_alloc(dev, tbl, npages);
382 if (entry == DMA_ERROR_CODE) {
383 /* makes sure unmap knows to stop */
384 s->dma_length = 0;
385 goto error;
386 }
387
388 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
389
390 /* insert into HW table */
391 tce_build(tbl, entry, npages, vaddr & PAGE_MASK, dir);
392
393 s->dma_length = s->length;
394 }
395
396 return nelems;
397error:
398 calgary_unmap_sg(dev, sg, nelems, dir, NULL);
399 for_each_sg(sg, s, nelems, i) {
400 sg->dma_address = DMA_ERROR_CODE;
401 sg->dma_length = 0;
402 }
403 return 0;
404}
405
406static dma_addr_t calgary_map_page(struct device *dev, struct page *page,
407 unsigned long offset, size_t size,
408 enum dma_data_direction dir,
409 struct dma_attrs *attrs)
410{
411 void *vaddr = page_address(page) + offset;
412 unsigned long uaddr;
413 unsigned int npages;
414 struct iommu_table *tbl = find_iommu_table(dev);
415
416 uaddr = (unsigned long)vaddr;
417 npages = iommu_num_pages(uaddr, size, PAGE_SIZE);
418
419 return iommu_alloc(dev, tbl, vaddr, npages, dir);
420}
421
422static void calgary_unmap_page(struct device *dev, dma_addr_t dma_addr,
423 size_t size, enum dma_data_direction dir,
424 struct dma_attrs *attrs)
425{
426 struct iommu_table *tbl = find_iommu_table(dev);
427 unsigned int npages;
428
429 npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
430 iommu_free(tbl, dma_addr, npages);
431}
432
433static void* calgary_alloc_coherent(struct device *dev, size_t size,
434 dma_addr_t *dma_handle, gfp_t flag)
435{
436 void *ret = NULL;
437 dma_addr_t mapping;
438 unsigned int npages, order;
439 struct iommu_table *tbl = find_iommu_table(dev);
440
441 size = PAGE_ALIGN(size); /* size rounded up to full pages */
442 npages = size >> PAGE_SHIFT;
443 order = get_order(size);
444
445 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
446
447 /* alloc enough pages (and possibly more) */
448 ret = (void *)__get_free_pages(flag, order);
449 if (!ret)
450 goto error;
451 memset(ret, 0, size);
452
453 /* set up tces to cover the allocated range */
454 mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
455 if (mapping == DMA_ERROR_CODE)
456 goto free;
457 *dma_handle = mapping;
458 return ret;
459free:
460 free_pages((unsigned long)ret, get_order(size));
461 ret = NULL;
462error:
463 return ret;
464}
465
466static void calgary_free_coherent(struct device *dev, size_t size,
467 void *vaddr, dma_addr_t dma_handle)
468{
469 unsigned int npages;
470 struct iommu_table *tbl = find_iommu_table(dev);
471
472 size = PAGE_ALIGN(size);
473 npages = size >> PAGE_SHIFT;
474
475 iommu_free(tbl, dma_handle, npages);
476 free_pages((unsigned long)vaddr, get_order(size));
477}
478
479static struct dma_map_ops calgary_dma_ops = {
480 .alloc_coherent = calgary_alloc_coherent,
481 .free_coherent = calgary_free_coherent,
482 .map_sg = calgary_map_sg,
483 .unmap_sg = calgary_unmap_sg,
484 .map_page = calgary_map_page,
485 .unmap_page = calgary_unmap_page,
486};
487
488static inline void __iomem * busno_to_bbar(unsigned char num)
489{
490 return bus_info[num].bbar;
491}
492
493static inline int busno_to_phbid(unsigned char num)
494{
495 return bus_info[num].phbid;
496}
497
498static inline unsigned long split_queue_offset(unsigned char num)
499{
500 size_t idx = busno_to_phbid(num);
501
502 return split_queue_offsets[idx];
503}
504
505static inline unsigned long tar_offset(unsigned char num)
506{
507 size_t idx = busno_to_phbid(num);
508
509 return tar_offsets[idx];
510}
511
512static inline unsigned long phb_offset(unsigned char num)
513{
514 size_t idx = busno_to_phbid(num);
515
516 return phb_offsets[idx];
517}
518
519static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
520{
521 unsigned long target = ((unsigned long)bar) | offset;
522 return (void __iomem*)target;
523}
524
525static inline int is_calioc2(unsigned short device)
526{
527 return (device == PCI_DEVICE_ID_IBM_CALIOC2);
528}
529
530static inline int is_calgary(unsigned short device)
531{
532 return (device == PCI_DEVICE_ID_IBM_CALGARY);
533}
534
535static inline int is_cal_pci_dev(unsigned short device)
536{
537 return (is_calgary(device) || is_calioc2(device));
538}
539
540static void calgary_tce_cache_blast(struct iommu_table *tbl)
541{
542 u64 val;
543 u32 aer;
544 int i = 0;
545 void __iomem *bbar = tbl->bbar;
546 void __iomem *target;
547
548 /* disable arbitration on the bus */
549 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
550 aer = readl(target);
551 writel(0, target);
552
553 /* read plssr to ensure it got there */
554 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
555 val = readl(target);
556
557 /* poll split queues until all DMA activity is done */
558 target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
559 do {
560 val = readq(target);
561 i++;
562 } while ((val & 0xff) != 0xff && i < 100);
563 if (i == 100)
564 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
565 "continuing anyway\n");
566
567 /* invalidate TCE cache */
568 target = calgary_reg(bbar, tar_offset(tbl->it_busno));
569 writeq(tbl->tar_val, target);
570
571 /* enable arbitration */
572 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
573 writel(aer, target);
574 (void)readl(target); /* flush */
575}
576
577static void calioc2_tce_cache_blast(struct iommu_table *tbl)
578{
579 void __iomem *bbar = tbl->bbar;
580 void __iomem *target;
581 u64 val64;
582 u32 val;
583 int i = 0;
584 int count = 1;
585 unsigned char bus = tbl->it_busno;
586
587begin:
588 printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
589 "sequence - count %d\n", bus, count);
590
591 /* 1. using the Page Migration Control reg set SoftStop */
592 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
593 val = be32_to_cpu(readl(target));
594 printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
595 val |= PMR_SOFTSTOP;
596 printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
597 writel(cpu_to_be32(val), target);
598
599 /* 2. poll split queues until all DMA activity is done */
600 printk(KERN_DEBUG "2a. starting to poll split queues\n");
601 target = calgary_reg(bbar, split_queue_offset(bus));
602 do {
603 val64 = readq(target);
604 i++;
605 } while ((val64 & 0xff) != 0xff && i < 100);
606 if (i == 100)
607 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
608 "continuing anyway\n");
609
610 /* 3. poll Page Migration DEBUG for SoftStopFault */
611 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
612 val = be32_to_cpu(readl(target));
613 printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
614
615 /* 4. if SoftStopFault - goto (1) */
616 if (val & PMR_SOFTSTOPFAULT) {
617 if (++count < 100)
618 goto begin;
619 else {
620 printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
621 "aborting TCE cache flush sequence!\n");
622 return; /* pray for the best */
623 }
624 }
625
626 /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
627 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
628 printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
629 val = be32_to_cpu(readl(target));
630 printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
631 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
632 val = be32_to_cpu(readl(target));
633 printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
634
635 /* 6. invalidate TCE cache */
636 printk(KERN_DEBUG "6. invalidating TCE cache\n");
637 target = calgary_reg(bbar, tar_offset(bus));
638 writeq(tbl->tar_val, target);
639
640 /* 7. Re-read PMCR */
641 printk(KERN_DEBUG "7a. Re-reading PMCR\n");
642 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
643 val = be32_to_cpu(readl(target));
644 printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
645
646 /* 8. Remove HardStop */
647 printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
648 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
649 val = 0;
650 printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
651 writel(cpu_to_be32(val), target);
652 val = be32_to_cpu(readl(target));
653 printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
654}
655
656static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
657 u64 limit)
658{
659 unsigned int numpages;
660
661 limit = limit | 0xfffff;
662 limit++;
663
664 numpages = ((limit - start) >> PAGE_SHIFT);
665 iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
666}
667
668static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
669{
670 void __iomem *target;
671 u64 low, high, sizelow;
672 u64 start, limit;
673 struct iommu_table *tbl = pci_iommu(dev->bus);
674 unsigned char busnum = dev->bus->number;
675 void __iomem *bbar = tbl->bbar;
676
677 /* peripheral MEM_1 region */
678 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
679 low = be32_to_cpu(readl(target));
680 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
681 high = be32_to_cpu(readl(target));
682 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
683 sizelow = be32_to_cpu(readl(target));
684
685 start = (high << 32) | low;
686 limit = sizelow;
687
688 calgary_reserve_mem_region(dev, start, limit);
689}
690
691static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
692{
693 void __iomem *target;
694 u32 val32;
695 u64 low, high, sizelow, sizehigh;
696 u64 start, limit;
697 struct iommu_table *tbl = pci_iommu(dev->bus);
698 unsigned char busnum = dev->bus->number;
699 void __iomem *bbar = tbl->bbar;
700
701 /* is it enabled? */
702 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
703 val32 = be32_to_cpu(readl(target));
704 if (!(val32 & PHB_MEM2_ENABLE))
705 return;
706
707 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
708 low = be32_to_cpu(readl(target));
709 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
710 high = be32_to_cpu(readl(target));
711 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
712 sizelow = be32_to_cpu(readl(target));
713 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
714 sizehigh = be32_to_cpu(readl(target));
715
716 start = (high << 32) | low;
717 limit = (sizehigh << 32) | sizelow;
718
719 calgary_reserve_mem_region(dev, start, limit);
720}
721
722/*
723 * some regions of the IO address space do not get translated, so we
724 * must not give devices IO addresses in those regions. The regions
725 * are the 640KB-1MB region and the two PCI peripheral memory holes.
726 * Reserve all of them in the IOMMU bitmap to avoid giving them out
727 * later.
728 */
729static void __init calgary_reserve_regions(struct pci_dev *dev)
730{
731 unsigned int npages;
732 u64 start;
733 struct iommu_table *tbl = pci_iommu(dev->bus);
734
735 /* reserve EMERGENCY_PAGES from bad_dma_address and up */
736 iommu_range_reserve(tbl, DMA_ERROR_CODE, EMERGENCY_PAGES);
737
738 /* avoid the BIOS/VGA first 640KB-1MB region */
739 /* for CalIOC2 - avoid the entire first MB */
740 if (is_calgary(dev->device)) {
741 start = (640 * 1024);
742 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
743 } else { /* calioc2 */
744 start = 0;
745 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
746 }
747 iommu_range_reserve(tbl, start, npages);
748
749 /* reserve the two PCI peripheral memory regions in IO space */
750 calgary_reserve_peripheral_mem_1(dev);
751 calgary_reserve_peripheral_mem_2(dev);
752}
753
754static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
755{
756 u64 val64;
757 u64 table_phys;
758 void __iomem *target;
759 int ret;
760 struct iommu_table *tbl;
761
762 /* build TCE tables for each PHB */
763 ret = build_tce_table(dev, bbar);
764 if (ret)
765 return ret;
766
767 tbl = pci_iommu(dev->bus);
768 tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
769
770 if (is_kdump_kernel())
771 calgary_init_bitmap_from_tce_table(tbl);
772 else
773 tce_free(tbl, 0, tbl->it_size);
774
775 if (is_calgary(dev->device))
776 tbl->chip_ops = &calgary_chip_ops;
777 else if (is_calioc2(dev->device))
778 tbl->chip_ops = &calioc2_chip_ops;
779 else
780 BUG();
781
782 calgary_reserve_regions(dev);
783
784 /* set TARs for each PHB */
785 target = calgary_reg(bbar, tar_offset(dev->bus->number));
786 val64 = be64_to_cpu(readq(target));
787
788 /* zero out all TAR bits under sw control */
789 val64 &= ~TAR_SW_BITS;
790 table_phys = (u64)__pa(tbl->it_base);
791
792 val64 |= table_phys;
793
794 BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
795 val64 |= (u64) specified_table_size;
796
797 tbl->tar_val = cpu_to_be64(val64);
798
799 writeq(tbl->tar_val, target);
800 readq(target); /* flush */
801
802 return 0;
803}
804
805static void __init calgary_free_bus(struct pci_dev *dev)
806{
807 u64 val64;
808 struct iommu_table *tbl = pci_iommu(dev->bus);
809 void __iomem *target;
810 unsigned int bitmapsz;
811
812 target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
813 val64 = be64_to_cpu(readq(target));
814 val64 &= ~TAR_SW_BITS;
815 writeq(cpu_to_be64(val64), target);
816 readq(target); /* flush */
817
818 bitmapsz = tbl->it_size / BITS_PER_BYTE;
819 free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
820 tbl->it_map = NULL;
821
822 kfree(tbl);
823
824 set_pci_iommu(dev->bus, NULL);
825
826 /* Can't free bootmem allocated memory after system is up :-( */
827 bus_info[dev->bus->number].tce_space = NULL;
828}
829
830static void calgary_dump_error_regs(struct iommu_table *tbl)
831{
832 void __iomem *bbar = tbl->bbar;
833 void __iomem *target;
834 u32 csr, plssr;
835
836 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
837 csr = be32_to_cpu(readl(target));
838
839 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
840 plssr = be32_to_cpu(readl(target));
841
842 /* If no error, the agent ID in the CSR is not valid */
843 printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
844 "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
845}
846
847static void calioc2_dump_error_regs(struct iommu_table *tbl)
848{
849 void __iomem *bbar = tbl->bbar;
850 u32 csr, csmr, plssr, mck, rcstat;
851 void __iomem *target;
852 unsigned long phboff = phb_offset(tbl->it_busno);
853 unsigned long erroff;
854 u32 errregs[7];
855 int i;
856
857 /* dump CSR */
858 target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
859 csr = be32_to_cpu(readl(target));
860 /* dump PLSSR */
861 target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
862 plssr = be32_to_cpu(readl(target));
863 /* dump CSMR */
864 target = calgary_reg(bbar, phboff | 0x290);
865 csmr = be32_to_cpu(readl(target));
866 /* dump mck */
867 target = calgary_reg(bbar, phboff | 0x800);
868 mck = be32_to_cpu(readl(target));
869
870 printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
871 tbl->it_busno);
872
873 printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
874 csr, plssr, csmr, mck);
875
876 /* dump rest of error regs */
877 printk(KERN_EMERG "Calgary: ");
878 for (i = 0; i < ARRAY_SIZE(errregs); i++) {
879 /* err regs are at 0x810 - 0x870 */
880 erroff = (0x810 + (i * 0x10));
881 target = calgary_reg(bbar, phboff | erroff);
882 errregs[i] = be32_to_cpu(readl(target));
883 printk("0x%08x@0x%lx ", errregs[i], erroff);
884 }
885 printk("\n");
886
887 /* root complex status */
888 target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
889 rcstat = be32_to_cpu(readl(target));
890 printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
891 PHB_ROOT_COMPLEX_STATUS);
892}
893
894static void calgary_watchdog(unsigned long data)
895{
896 struct pci_dev *dev = (struct pci_dev *)data;
897 struct iommu_table *tbl = pci_iommu(dev->bus);
898 void __iomem *bbar = tbl->bbar;
899 u32 val32;
900 void __iomem *target;
901
902 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
903 val32 = be32_to_cpu(readl(target));
904
905 /* If no error, the agent ID in the CSR is not valid */
906 if (val32 & CSR_AGENT_MASK) {
907 tbl->chip_ops->dump_error_regs(tbl);
908
909 /* reset error */
910 writel(0, target);
911
912 /* Disable bus that caused the error */
913 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
914 PHB_CONFIG_RW_OFFSET);
915 val32 = be32_to_cpu(readl(target));
916 val32 |= PHB_SLOT_DISABLE;
917 writel(cpu_to_be32(val32), target);
918 readl(target); /* flush */
919 } else {
920 /* Reset the timer */
921 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
922 }
923}
924
925static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
926 unsigned char busnum, unsigned long timeout)
927{
928 u64 val64;
929 void __iomem *target;
930 unsigned int phb_shift = ~0; /* silence gcc */
931 u64 mask;
932
933 switch (busno_to_phbid(busnum)) {
934 case 0: phb_shift = (63 - 19);
935 break;
936 case 1: phb_shift = (63 - 23);
937 break;
938 case 2: phb_shift = (63 - 27);
939 break;
940 case 3: phb_shift = (63 - 35);
941 break;
942 default:
943 BUG_ON(busno_to_phbid(busnum));
944 }
945
946 target = calgary_reg(bbar, CALGARY_CONFIG_REG);
947 val64 = be64_to_cpu(readq(target));
948
949 /* zero out this PHB's timer bits */
950 mask = ~(0xFUL << phb_shift);
951 val64 &= mask;
952 val64 |= (timeout << phb_shift);
953 writeq(cpu_to_be64(val64), target);
954 readq(target); /* flush */
955}
956
957static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
958{
959 unsigned char busnum = dev->bus->number;
960 void __iomem *bbar = tbl->bbar;
961 void __iomem *target;
962 u32 val;
963
964 /*
965 * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
966 */
967 target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
968 val = cpu_to_be32(readl(target));
969 val |= 0x00800000;
970 writel(cpu_to_be32(val), target);
971}
972
973static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
974{
975 unsigned char busnum = dev->bus->number;
976
977 /*
978 * Give split completion a longer timeout on bus 1 for aic94xx
979 * http://bugzilla.kernel.org/show_bug.cgi?id=7180
980 */
981 if (is_calgary(dev->device) && (busnum == 1))
982 calgary_set_split_completion_timeout(tbl->bbar, busnum,
983 CCR_2SEC_TIMEOUT);
984}
985
986static void __init calgary_enable_translation(struct pci_dev *dev)
987{
988 u32 val32;
989 unsigned char busnum;
990 void __iomem *target;
991 void __iomem *bbar;
992 struct iommu_table *tbl;
993
994 busnum = dev->bus->number;
995 tbl = pci_iommu(dev->bus);
996 bbar = tbl->bbar;
997
998 /* enable TCE in PHB Config Register */
999 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1000 val32 = be32_to_cpu(readl(target));
1001 val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1002
1003 printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1004 (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1005 "Calgary" : "CalIOC2", busnum);
1006 printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1007 "bus.\n");
1008
1009 writel(cpu_to_be32(val32), target);
1010 readl(target); /* flush */
1011
1012 init_timer(&tbl->watchdog_timer);
1013 tbl->watchdog_timer.function = &calgary_watchdog;
1014 tbl->watchdog_timer.data = (unsigned long)dev;
1015 mod_timer(&tbl->watchdog_timer, jiffies);
1016}
1017
1018static void __init calgary_disable_translation(struct pci_dev *dev)
1019{
1020 u32 val32;
1021 unsigned char busnum;
1022 void __iomem *target;
1023 void __iomem *bbar;
1024 struct iommu_table *tbl;
1025
1026 busnum = dev->bus->number;
1027 tbl = pci_iommu(dev->bus);
1028 bbar = tbl->bbar;
1029
1030 /* disable TCE in PHB Config Register */
1031 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1032 val32 = be32_to_cpu(readl(target));
1033 val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1034
1035 printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1036 writel(cpu_to_be32(val32), target);
1037 readl(target); /* flush */
1038
1039 del_timer_sync(&tbl->watchdog_timer);
1040}
1041
1042static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1043{
1044 pci_dev_get(dev);
1045 set_pci_iommu(dev->bus, NULL);
1046
1047 /* is the device behind a bridge? */
1048 if (dev->bus->parent)
1049 dev->bus->parent->self = dev;
1050 else
1051 dev->bus->self = dev;
1052}
1053
1054static int __init calgary_init_one(struct pci_dev *dev)
1055{
1056 void __iomem *bbar;
1057 struct iommu_table *tbl;
1058 int ret;
1059
1060 bbar = busno_to_bbar(dev->bus->number);
1061 ret = calgary_setup_tar(dev, bbar);
1062 if (ret)
1063 goto done;
1064
1065 pci_dev_get(dev);
1066
1067 if (dev->bus->parent) {
1068 if (dev->bus->parent->self)
1069 printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1070 "bus->parent->self!\n", dev);
1071 dev->bus->parent->self = dev;
1072 } else
1073 dev->bus->self = dev;
1074
1075 tbl = pci_iommu(dev->bus);
1076 tbl->chip_ops->handle_quirks(tbl, dev);
1077
1078 calgary_enable_translation(dev);
1079
1080 return 0;
1081
1082done:
1083 return ret;
1084}
1085
1086static int __init calgary_locate_bbars(void)
1087{
1088 int ret;
1089 int rioidx, phb, bus;
1090 void __iomem *bbar;
1091 void __iomem *target;
1092 unsigned long offset;
1093 u8 start_bus, end_bus;
1094 u32 val;
1095
1096 ret = -ENODATA;
1097 for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1098 struct rio_detail *rio = rio_devs[rioidx];
1099
1100 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1101 continue;
1102
1103 /* map entire 1MB of Calgary config space */
1104 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1105 if (!bbar)
1106 goto error;
1107
1108 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1109 offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1110 target = calgary_reg(bbar, offset);
1111
1112 val = be32_to_cpu(readl(target));
1113
1114 start_bus = (u8)((val & 0x00FF0000) >> 16);
1115 end_bus = (u8)((val & 0x0000FF00) >> 8);
1116
1117 if (end_bus) {
1118 for (bus = start_bus; bus <= end_bus; bus++) {
1119 bus_info[bus].bbar = bbar;
1120 bus_info[bus].phbid = phb;
1121 }
1122 } else {
1123 bus_info[start_bus].bbar = bbar;
1124 bus_info[start_bus].phbid = phb;
1125 }
1126 }
1127 }
1128
1129 return 0;
1130
1131error:
1132 /* scan bus_info and iounmap any bbars we previously ioremap'd */
1133 for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1134 if (bus_info[bus].bbar)
1135 iounmap(bus_info[bus].bbar);
1136
1137 return ret;
1138}
1139
1140static int __init calgary_init(void)
1141{
1142 int ret;
1143 struct pci_dev *dev = NULL;
1144 struct calgary_bus_info *info;
1145
1146 ret = calgary_locate_bbars();
1147 if (ret)
1148 return ret;
1149
1150 /* Purely for kdump kernel case */
1151 if (is_kdump_kernel())
1152 get_tce_space_from_tar();
1153
1154 do {
1155 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1156 if (!dev)
1157 break;
1158 if (!is_cal_pci_dev(dev->device))
1159 continue;
1160
1161 info = &bus_info[dev->bus->number];
1162 if (info->translation_disabled) {
1163 calgary_init_one_nontraslated(dev);
1164 continue;
1165 }
1166
1167 if (!info->tce_space && !translate_empty_slots)
1168 continue;
1169
1170 ret = calgary_init_one(dev);
1171 if (ret)
1172 goto error;
1173 } while (1);
1174
1175 dev = NULL;
1176 for_each_pci_dev(dev) {
1177 struct iommu_table *tbl;
1178
1179 tbl = find_iommu_table(&dev->dev);
1180
1181 if (translation_enabled(tbl))
1182 dev->dev.archdata.dma_ops = &calgary_dma_ops;
1183 }
1184
1185 return ret;
1186
1187error:
1188 do {
1189 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1190 if (!dev)
1191 break;
1192 if (!is_cal_pci_dev(dev->device))
1193 continue;
1194
1195 info = &bus_info[dev->bus->number];
1196 if (info->translation_disabled) {
1197 pci_dev_put(dev);
1198 continue;
1199 }
1200 if (!info->tce_space && !translate_empty_slots)
1201 continue;
1202
1203 calgary_disable_translation(dev);
1204 calgary_free_bus(dev);
1205 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1206 dev->dev.archdata.dma_ops = NULL;
1207 } while (1);
1208
1209 return ret;
1210}
1211
1212static inline int __init determine_tce_table_size(u64 ram)
1213{
1214 int ret;
1215
1216 if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1217 return specified_table_size;
1218
1219 /*
1220 * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1221 * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1222 * larger table size has twice as many entries, so shift the
1223 * max ram address by 13 to divide by 8K and then look at the
1224 * order of the result to choose between 0-7.
1225 */
1226 ret = get_order(ram >> 13);
1227 if (ret > TCE_TABLE_SIZE_8M)
1228 ret = TCE_TABLE_SIZE_8M;
1229
1230 return ret;
1231}
1232
1233static int __init build_detail_arrays(void)
1234{
1235 unsigned long ptr;
1236 unsigned numnodes, i;
1237 int scal_detail_size, rio_detail_size;
1238
1239 numnodes = rio_table_hdr->num_scal_dev;
1240 if (numnodes > MAX_NUMNODES){
1241 printk(KERN_WARNING
1242 "Calgary: MAX_NUMNODES too low! Defined as %d, "
1243 "but system has %d nodes.\n",
1244 MAX_NUMNODES, numnodes);
1245 return -ENODEV;
1246 }
1247
1248 switch (rio_table_hdr->version){
1249 case 2:
1250 scal_detail_size = 11;
1251 rio_detail_size = 13;
1252 break;
1253 case 3:
1254 scal_detail_size = 12;
1255 rio_detail_size = 15;
1256 break;
1257 default:
1258 printk(KERN_WARNING
1259 "Calgary: Invalid Rio Grande Table Version: %d\n",
1260 rio_table_hdr->version);
1261 return -EPROTO;
1262 }
1263
1264 ptr = ((unsigned long)rio_table_hdr) + 3;
1265 for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
1266 scal_devs[i] = (struct scal_detail *)ptr;
1267
1268 for (i = 0; i < rio_table_hdr->num_rio_dev;
1269 i++, ptr += rio_detail_size)
1270 rio_devs[i] = (struct rio_detail *)ptr;
1271
1272 return 0;
1273}
1274
1275static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1276{
1277 int dev;
1278 u32 val;
1279
1280 if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1281 /*
1282 * FIXME: properly scan for devices across the
1283 * PCI-to-PCI bridge on every CalIOC2 port.
1284 */
1285 return 1;
1286 }
1287
1288 for (dev = 1; dev < 8; dev++) {
1289 val = read_pci_config(bus, dev, 0, 0);
1290 if (val != 0xffffffff)
1291 break;
1292 }
1293 return (val != 0xffffffff);
1294}
1295
1296/*
1297 * calgary_init_bitmap_from_tce_table():
1298 * Function for kdump case. In the second/kdump kernel initialize
1299 * the bitmap based on the tce table entries obtained from first kernel
1300 */
1301static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1302{
1303 u64 *tp;
1304 unsigned int index;
1305 tp = ((u64 *)tbl->it_base);
1306 for (index = 0 ; index < tbl->it_size; index++) {
1307 if (*tp != 0x0)
1308 set_bit(index, tbl->it_map);
1309 tp++;
1310 }
1311}
1312
1313/*
1314 * get_tce_space_from_tar():
1315 * Function for kdump case. Get the tce tables from first kernel
1316 * by reading the contents of the base address register of calgary iommu
1317 */
1318static void __init get_tce_space_from_tar(void)
1319{
1320 int bus;
1321 void __iomem *target;
1322 unsigned long tce_space;
1323
1324 for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1325 struct calgary_bus_info *info = &bus_info[bus];
1326 unsigned short pci_device;
1327 u32 val;
1328
1329 val = read_pci_config(bus, 0, 0, 0);
1330 pci_device = (val & 0xFFFF0000) >> 16;
1331
1332 if (!is_cal_pci_dev(pci_device))
1333 continue;
1334 if (info->translation_disabled)
1335 continue;
1336
1337 if (calgary_bus_has_devices(bus, pci_device) ||
1338 translate_empty_slots) {
1339 target = calgary_reg(bus_info[bus].bbar,
1340 tar_offset(bus));
1341 tce_space = be64_to_cpu(readq(target));
1342 tce_space = tce_space & TAR_SW_BITS;
1343
1344 tce_space = tce_space & (~specified_table_size);
1345 info->tce_space = (u64 *)__va(tce_space);
1346 }
1347 }
1348 return;
1349}
1350
1351static int __init calgary_iommu_init(void)
1352{
1353 int ret;
1354
1355 /* ok, we're trying to use Calgary - let's roll */
1356 printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1357
1358 ret = calgary_init();
1359 if (ret) {
1360 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1361 "falling back to no_iommu\n", ret);
1362 return ret;
1363 }
1364
1365 return 0;
1366}
1367
1368int __init detect_calgary(void)
1369{
1370 int bus;
1371 void *tbl;
1372 int calgary_found = 0;
1373 unsigned long ptr;
1374 unsigned int offset, prev_offset;
1375 int ret;
1376
1377 /*
1378 * if the user specified iommu=off or iommu=soft or we found
1379 * another HW IOMMU already, bail out.
1380 */
1381 if (no_iommu || iommu_detected)
1382 return -ENODEV;
1383
1384 if (!use_calgary)
1385 return -ENODEV;
1386
1387 if (!early_pci_allowed())
1388 return -ENODEV;
1389
1390 printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1391
1392 ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1393
1394 rio_table_hdr = NULL;
1395 prev_offset = 0;
1396 offset = 0x180;
1397 /*
1398 * The next offset is stored in the 1st word.
1399 * Only parse up until the offset increases:
1400 */
1401 while (offset > prev_offset) {
1402 /* The block id is stored in the 2nd word */
1403 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1404 /* set the pointer past the offset & block id */
1405 rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1406 break;
1407 }
1408 prev_offset = offset;
1409 offset = *((unsigned short *)(ptr + offset));
1410 }
1411 if (!rio_table_hdr) {
1412 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1413 "in EBDA - bailing!\n");
1414 return -ENODEV;
1415 }
1416
1417 ret = build_detail_arrays();
1418 if (ret) {
1419 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1420 return -ENOMEM;
1421 }
1422
1423 specified_table_size = determine_tce_table_size((is_kdump_kernel() ?
1424 saved_max_pfn : max_pfn) * PAGE_SIZE);
1425
1426 for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1427 struct calgary_bus_info *info = &bus_info[bus];
1428 unsigned short pci_device;
1429 u32 val;
1430
1431 val = read_pci_config(bus, 0, 0, 0);
1432 pci_device = (val & 0xFFFF0000) >> 16;
1433
1434 if (!is_cal_pci_dev(pci_device))
1435 continue;
1436
1437 if (info->translation_disabled)
1438 continue;
1439
1440 if (calgary_bus_has_devices(bus, pci_device) ||
1441 translate_empty_slots) {
1442 /*
1443 * If it is kdump kernel, find and use tce tables
1444 * from first kernel, else allocate tce tables here
1445 */
1446 if (!is_kdump_kernel()) {
1447 tbl = alloc_tce_table();
1448 if (!tbl)
1449 goto cleanup;
1450 info->tce_space = tbl;
1451 }
1452 calgary_found = 1;
1453 }
1454 }
1455
1456 printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1457 calgary_found ? "found" : "not found");
1458
1459 if (calgary_found) {
1460 iommu_detected = 1;
1461 calgary_detected = 1;
1462 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1463 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d\n",
1464 specified_table_size);
1465
1466 x86_init.iommu.iommu_init = calgary_iommu_init;
1467 }
1468 return calgary_found;
1469
1470cleanup:
1471 for (--bus; bus >= 0; --bus) {
1472 struct calgary_bus_info *info = &bus_info[bus];
1473
1474 if (info->tce_space)
1475 free_tce_table(info->tce_space);
1476 }
1477 return -ENOMEM;
1478}
1479
1480static int __init calgary_parse_options(char *p)
1481{
1482 unsigned int bridge;
1483 size_t len;
1484 char* endp;
1485
1486 while (*p) {
1487 if (!strncmp(p, "64k", 3))
1488 specified_table_size = TCE_TABLE_SIZE_64K;
1489 else if (!strncmp(p, "128k", 4))
1490 specified_table_size = TCE_TABLE_SIZE_128K;
1491 else if (!strncmp(p, "256k", 4))
1492 specified_table_size = TCE_TABLE_SIZE_256K;
1493 else if (!strncmp(p, "512k", 4))
1494 specified_table_size = TCE_TABLE_SIZE_512K;
1495 else if (!strncmp(p, "1M", 2))
1496 specified_table_size = TCE_TABLE_SIZE_1M;
1497 else if (!strncmp(p, "2M", 2))
1498 specified_table_size = TCE_TABLE_SIZE_2M;
1499 else if (!strncmp(p, "4M", 2))
1500 specified_table_size = TCE_TABLE_SIZE_4M;
1501 else if (!strncmp(p, "8M", 2))
1502 specified_table_size = TCE_TABLE_SIZE_8M;
1503
1504 len = strlen("translate_empty_slots");
1505 if (!strncmp(p, "translate_empty_slots", len))
1506 translate_empty_slots = 1;
1507
1508 len = strlen("disable");
1509 if (!strncmp(p, "disable", len)) {
1510 p += len;
1511 if (*p == '=')
1512 ++p;
1513 if (*p == '\0')
1514 break;
1515 bridge = simple_strtoul(p, &endp, 0);
1516 if (p == endp)
1517 break;
1518
1519 if (bridge < MAX_PHB_BUS_NUM) {
1520 printk(KERN_INFO "Calgary: disabling "
1521 "translation for PHB %#x\n", bridge);
1522 bus_info[bridge].translation_disabled = 1;
1523 }
1524 }
1525
1526 p = strpbrk(p, ",");
1527 if (!p)
1528 break;
1529
1530 p++; /* skip ',' */
1531 }
1532 return 1;
1533}
1534__setup("calgary=", calgary_parse_options);
1535
1536static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1537{
1538 struct iommu_table *tbl;
1539 unsigned int npages;
1540 int i;
1541
1542 tbl = pci_iommu(dev->bus);
1543
1544 for (i = 0; i < 4; i++) {
1545 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1546
1547 /* Don't give out TCEs that map MEM resources */
1548 if (!(r->flags & IORESOURCE_MEM))
1549 continue;
1550
1551 /* 0-based? we reserve the whole 1st MB anyway */
1552 if (!r->start)
1553 continue;
1554
1555 /* cover the whole region */
1556 npages = resource_size(r) >> PAGE_SHIFT;
1557 npages++;
1558
1559 iommu_range_reserve(tbl, r->start, npages);
1560 }
1561}
1562
1563static int __init calgary_fixup_tce_spaces(void)
1564{
1565 struct pci_dev *dev = NULL;
1566 struct calgary_bus_info *info;
1567
1568 if (no_iommu || swiotlb || !calgary_detected)
1569 return -ENODEV;
1570
1571 printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1572
1573 do {
1574 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1575 if (!dev)
1576 break;
1577 if (!is_cal_pci_dev(dev->device))
1578 continue;
1579
1580 info = &bus_info[dev->bus->number];
1581 if (info->translation_disabled)
1582 continue;
1583
1584 if (!info->tce_space)
1585 continue;
1586
1587 calgary_fixup_one_tce_space(dev);
1588
1589 } while (1);
1590
1591 return 0;
1592}
1593
1594/*
1595 * We need to be call after pcibios_assign_resources (fs_initcall level)
1596 * and before device_initcall.
1597 */
1598rootfs_initcall(calgary_fixup_tce_spaces);
1599
1600IOMMU_INIT_POST(detect_calgary);
1/*
2 * Derived from arch/powerpc/kernel/iommu.c
3 *
4 * Copyright IBM Corporation, 2006-2007
5 * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us>
6 *
7 * Author: Jon Mason <jdmason@kudzu.us>
8 * Author: Muli Ben-Yehuda <muli@il.ibm.com>
9
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25#define pr_fmt(fmt) "Calgary: " fmt
26
27#include <linux/kernel.h>
28#include <linux/init.h>
29#include <linux/types.h>
30#include <linux/slab.h>
31#include <linux/mm.h>
32#include <linux/spinlock.h>
33#include <linux/string.h>
34#include <linux/crash_dump.h>
35#include <linux/dma-mapping.h>
36#include <linux/bitmap.h>
37#include <linux/pci_ids.h>
38#include <linux/pci.h>
39#include <linux/delay.h>
40#include <linux/scatterlist.h>
41#include <linux/iommu-helper.h>
42
43#include <asm/iommu.h>
44#include <asm/calgary.h>
45#include <asm/tce.h>
46#include <asm/pci-direct.h>
47#include <asm/dma.h>
48#include <asm/rio.h>
49#include <asm/bios_ebda.h>
50#include <asm/x86_init.h>
51#include <asm/iommu_table.h>
52
53#ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
54int use_calgary __read_mostly = 1;
55#else
56int use_calgary __read_mostly = 0;
57#endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
58
59#define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
60#define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
61
62/* register offsets inside the host bridge space */
63#define CALGARY_CONFIG_REG 0x0108
64#define PHB_CSR_OFFSET 0x0110 /* Channel Status */
65#define PHB_PLSSR_OFFSET 0x0120
66#define PHB_CONFIG_RW_OFFSET 0x0160
67#define PHB_IOBASE_BAR_LOW 0x0170
68#define PHB_IOBASE_BAR_HIGH 0x0180
69#define PHB_MEM_1_LOW 0x0190
70#define PHB_MEM_1_HIGH 0x01A0
71#define PHB_IO_ADDR_SIZE 0x01B0
72#define PHB_MEM_1_SIZE 0x01C0
73#define PHB_MEM_ST_OFFSET 0x01D0
74#define PHB_AER_OFFSET 0x0200
75#define PHB_CONFIG_0_HIGH 0x0220
76#define PHB_CONFIG_0_LOW 0x0230
77#define PHB_CONFIG_0_END 0x0240
78#define PHB_MEM_2_LOW 0x02B0
79#define PHB_MEM_2_HIGH 0x02C0
80#define PHB_MEM_2_SIZE_HIGH 0x02D0
81#define PHB_MEM_2_SIZE_LOW 0x02E0
82#define PHB_DOSHOLE_OFFSET 0x08E0
83
84/* CalIOC2 specific */
85#define PHB_SAVIOR_L2 0x0DB0
86#define PHB_PAGE_MIG_CTRL 0x0DA8
87#define PHB_PAGE_MIG_DEBUG 0x0DA0
88#define PHB_ROOT_COMPLEX_STATUS 0x0CB0
89
90/* PHB_CONFIG_RW */
91#define PHB_TCE_ENABLE 0x20000000
92#define PHB_SLOT_DISABLE 0x1C000000
93#define PHB_DAC_DISABLE 0x01000000
94#define PHB_MEM2_ENABLE 0x00400000
95#define PHB_MCSR_ENABLE 0x00100000
96/* TAR (Table Address Register) */
97#define TAR_SW_BITS 0x0000ffffffff800fUL
98#define TAR_VALID 0x0000000000000008UL
99/* CSR (Channel/DMA Status Register) */
100#define CSR_AGENT_MASK 0xffe0ffff
101/* CCR (Calgary Configuration Register) */
102#define CCR_2SEC_TIMEOUT 0x000000000000000EUL
103/* PMCR/PMDR (Page Migration Control/Debug Registers */
104#define PMR_SOFTSTOP 0x80000000
105#define PMR_SOFTSTOPFAULT 0x40000000
106#define PMR_HARDSTOP 0x20000000
107
108/*
109 * The maximum PHB bus number.
110 * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
111 * x3950M2: 4 chassis, 48 PHBs per chassis = 192
112 * x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
113 * x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
114 */
115#define MAX_PHB_BUS_NUM 256
116
117#define PHBS_PER_CALGARY 4
118
119/* register offsets in Calgary's internal register space */
120static const unsigned long tar_offsets[] = {
121 0x0580 /* TAR0 */,
122 0x0588 /* TAR1 */,
123 0x0590 /* TAR2 */,
124 0x0598 /* TAR3 */
125};
126
127static const unsigned long split_queue_offsets[] = {
128 0x4870 /* SPLIT QUEUE 0 */,
129 0x5870 /* SPLIT QUEUE 1 */,
130 0x6870 /* SPLIT QUEUE 2 */,
131 0x7870 /* SPLIT QUEUE 3 */
132};
133
134static const unsigned long phb_offsets[] = {
135 0x8000 /* PHB0 */,
136 0x9000 /* PHB1 */,
137 0xA000 /* PHB2 */,
138 0xB000 /* PHB3 */
139};
140
141/* PHB debug registers */
142
143static const unsigned long phb_debug_offsets[] = {
144 0x4000 /* PHB 0 DEBUG */,
145 0x5000 /* PHB 1 DEBUG */,
146 0x6000 /* PHB 2 DEBUG */,
147 0x7000 /* PHB 3 DEBUG */
148};
149
150/*
151 * STUFF register for each debug PHB,
152 * byte 1 = start bus number, byte 2 = end bus number
153 */
154
155#define PHB_DEBUG_STUFF_OFFSET 0x0020
156
157#define EMERGENCY_PAGES 32 /* = 128KB */
158
159unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
160static int translate_empty_slots __read_mostly = 0;
161static int calgary_detected __read_mostly = 0;
162
163static struct rio_table_hdr *rio_table_hdr __initdata;
164static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata;
165static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata;
166
167struct calgary_bus_info {
168 void *tce_space;
169 unsigned char translation_disabled;
170 signed char phbid;
171 void __iomem *bbar;
172};
173
174static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
175static void calgary_tce_cache_blast(struct iommu_table *tbl);
176static void calgary_dump_error_regs(struct iommu_table *tbl);
177static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
178static void calioc2_tce_cache_blast(struct iommu_table *tbl);
179static void calioc2_dump_error_regs(struct iommu_table *tbl);
180static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
181static void get_tce_space_from_tar(void);
182
183static const struct cal_chipset_ops calgary_chip_ops = {
184 .handle_quirks = calgary_handle_quirks,
185 .tce_cache_blast = calgary_tce_cache_blast,
186 .dump_error_regs = calgary_dump_error_regs
187};
188
189static const struct cal_chipset_ops calioc2_chip_ops = {
190 .handle_quirks = calioc2_handle_quirks,
191 .tce_cache_blast = calioc2_tce_cache_blast,
192 .dump_error_regs = calioc2_dump_error_regs
193};
194
195static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
196
197static inline int translation_enabled(struct iommu_table *tbl)
198{
199 /* only PHBs with translation enabled have an IOMMU table */
200 return (tbl != NULL);
201}
202
203static void iommu_range_reserve(struct iommu_table *tbl,
204 unsigned long start_addr, unsigned int npages)
205{
206 unsigned long index;
207 unsigned long end;
208 unsigned long flags;
209
210 index = start_addr >> PAGE_SHIFT;
211
212 /* bail out if we're asked to reserve a region we don't cover */
213 if (index >= tbl->it_size)
214 return;
215
216 end = index + npages;
217 if (end > tbl->it_size) /* don't go off the table */
218 end = tbl->it_size;
219
220 spin_lock_irqsave(&tbl->it_lock, flags);
221
222 bitmap_set(tbl->it_map, index, npages);
223
224 spin_unlock_irqrestore(&tbl->it_lock, flags);
225}
226
227static unsigned long iommu_range_alloc(struct device *dev,
228 struct iommu_table *tbl,
229 unsigned int npages)
230{
231 unsigned long flags;
232 unsigned long offset;
233 unsigned long boundary_size;
234
235 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
236 PAGE_SIZE) >> PAGE_SHIFT;
237
238 BUG_ON(npages == 0);
239
240 spin_lock_irqsave(&tbl->it_lock, flags);
241
242 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
243 npages, 0, boundary_size, 0);
244 if (offset == ~0UL) {
245 tbl->chip_ops->tce_cache_blast(tbl);
246
247 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
248 npages, 0, boundary_size, 0);
249 if (offset == ~0UL) {
250 pr_warn("IOMMU full\n");
251 spin_unlock_irqrestore(&tbl->it_lock, flags);
252 if (panic_on_overflow)
253 panic("Calgary: fix the allocator.\n");
254 else
255 return DMA_ERROR_CODE;
256 }
257 }
258
259 tbl->it_hint = offset + npages;
260 BUG_ON(tbl->it_hint > tbl->it_size);
261
262 spin_unlock_irqrestore(&tbl->it_lock, flags);
263
264 return offset;
265}
266
267static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
268 void *vaddr, unsigned int npages, int direction)
269{
270 unsigned long entry;
271 dma_addr_t ret;
272
273 entry = iommu_range_alloc(dev, tbl, npages);
274
275 if (unlikely(entry == DMA_ERROR_CODE)) {
276 pr_warn("failed to allocate %u pages in iommu %p\n",
277 npages, tbl);
278 return DMA_ERROR_CODE;
279 }
280
281 /* set the return dma address */
282 ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
283
284 /* put the TCEs in the HW table */
285 tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
286 direction);
287 return ret;
288}
289
290static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
291 unsigned int npages)
292{
293 unsigned long entry;
294 unsigned long badend;
295 unsigned long flags;
296
297 /* were we called with bad_dma_address? */
298 badend = DMA_ERROR_CODE + (EMERGENCY_PAGES * PAGE_SIZE);
299 if (unlikely((dma_addr >= DMA_ERROR_CODE) && (dma_addr < badend))) {
300 WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
301 "address 0x%Lx\n", dma_addr);
302 return;
303 }
304
305 entry = dma_addr >> PAGE_SHIFT;
306
307 BUG_ON(entry + npages > tbl->it_size);
308
309 tce_free(tbl, entry, npages);
310
311 spin_lock_irqsave(&tbl->it_lock, flags);
312
313 bitmap_clear(tbl->it_map, entry, npages);
314
315 spin_unlock_irqrestore(&tbl->it_lock, flags);
316}
317
318static inline struct iommu_table *find_iommu_table(struct device *dev)
319{
320 struct pci_dev *pdev;
321 struct pci_bus *pbus;
322 struct iommu_table *tbl;
323
324 pdev = to_pci_dev(dev);
325
326 /* search up the device tree for an iommu */
327 pbus = pdev->bus;
328 do {
329 tbl = pci_iommu(pbus);
330 if (tbl && tbl->it_busno == pbus->number)
331 break;
332 tbl = NULL;
333 pbus = pbus->parent;
334 } while (pbus);
335
336 BUG_ON(tbl && (tbl->it_busno != pbus->number));
337
338 return tbl;
339}
340
341static void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
342 int nelems,enum dma_data_direction dir,
343 struct dma_attrs *attrs)
344{
345 struct iommu_table *tbl = find_iommu_table(dev);
346 struct scatterlist *s;
347 int i;
348
349 if (!translation_enabled(tbl))
350 return;
351
352 for_each_sg(sglist, s, nelems, i) {
353 unsigned int npages;
354 dma_addr_t dma = s->dma_address;
355 unsigned int dmalen = s->dma_length;
356
357 if (dmalen == 0)
358 break;
359
360 npages = iommu_num_pages(dma, dmalen, PAGE_SIZE);
361 iommu_free(tbl, dma, npages);
362 }
363}
364
365static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
366 int nelems, enum dma_data_direction dir,
367 struct dma_attrs *attrs)
368{
369 struct iommu_table *tbl = find_iommu_table(dev);
370 struct scatterlist *s;
371 unsigned long vaddr;
372 unsigned int npages;
373 unsigned long entry;
374 int i;
375
376 for_each_sg(sg, s, nelems, i) {
377 BUG_ON(!sg_page(s));
378
379 vaddr = (unsigned long) sg_virt(s);
380 npages = iommu_num_pages(vaddr, s->length, PAGE_SIZE);
381
382 entry = iommu_range_alloc(dev, tbl, npages);
383 if (entry == DMA_ERROR_CODE) {
384 /* makes sure unmap knows to stop */
385 s->dma_length = 0;
386 goto error;
387 }
388
389 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
390
391 /* insert into HW table */
392 tce_build(tbl, entry, npages, vaddr & PAGE_MASK, dir);
393
394 s->dma_length = s->length;
395 }
396
397 return nelems;
398error:
399 calgary_unmap_sg(dev, sg, nelems, dir, NULL);
400 for_each_sg(sg, s, nelems, i) {
401 sg->dma_address = DMA_ERROR_CODE;
402 sg->dma_length = 0;
403 }
404 return 0;
405}
406
407static dma_addr_t calgary_map_page(struct device *dev, struct page *page,
408 unsigned long offset, size_t size,
409 enum dma_data_direction dir,
410 struct dma_attrs *attrs)
411{
412 void *vaddr = page_address(page) + offset;
413 unsigned long uaddr;
414 unsigned int npages;
415 struct iommu_table *tbl = find_iommu_table(dev);
416
417 uaddr = (unsigned long)vaddr;
418 npages = iommu_num_pages(uaddr, size, PAGE_SIZE);
419
420 return iommu_alloc(dev, tbl, vaddr, npages, dir);
421}
422
423static void calgary_unmap_page(struct device *dev, dma_addr_t dma_addr,
424 size_t size, enum dma_data_direction dir,
425 struct dma_attrs *attrs)
426{
427 struct iommu_table *tbl = find_iommu_table(dev);
428 unsigned int npages;
429
430 npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
431 iommu_free(tbl, dma_addr, npages);
432}
433
434static void* calgary_alloc_coherent(struct device *dev, size_t size,
435 dma_addr_t *dma_handle, gfp_t flag, struct dma_attrs *attrs)
436{
437 void *ret = NULL;
438 dma_addr_t mapping;
439 unsigned int npages, order;
440 struct iommu_table *tbl = find_iommu_table(dev);
441
442 size = PAGE_ALIGN(size); /* size rounded up to full pages */
443 npages = size >> PAGE_SHIFT;
444 order = get_order(size);
445
446 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
447
448 /* alloc enough pages (and possibly more) */
449 ret = (void *)__get_free_pages(flag, order);
450 if (!ret)
451 goto error;
452 memset(ret, 0, size);
453
454 /* set up tces to cover the allocated range */
455 mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
456 if (mapping == DMA_ERROR_CODE)
457 goto free;
458 *dma_handle = mapping;
459 return ret;
460free:
461 free_pages((unsigned long)ret, get_order(size));
462 ret = NULL;
463error:
464 return ret;
465}
466
467static void calgary_free_coherent(struct device *dev, size_t size,
468 void *vaddr, dma_addr_t dma_handle,
469 struct dma_attrs *attrs)
470{
471 unsigned int npages;
472 struct iommu_table *tbl = find_iommu_table(dev);
473
474 size = PAGE_ALIGN(size);
475 npages = size >> PAGE_SHIFT;
476
477 iommu_free(tbl, dma_handle, npages);
478 free_pages((unsigned long)vaddr, get_order(size));
479}
480
481static struct dma_map_ops calgary_dma_ops = {
482 .alloc = calgary_alloc_coherent,
483 .free = calgary_free_coherent,
484 .map_sg = calgary_map_sg,
485 .unmap_sg = calgary_unmap_sg,
486 .map_page = calgary_map_page,
487 .unmap_page = calgary_unmap_page,
488};
489
490static inline void __iomem * busno_to_bbar(unsigned char num)
491{
492 return bus_info[num].bbar;
493}
494
495static inline int busno_to_phbid(unsigned char num)
496{
497 return bus_info[num].phbid;
498}
499
500static inline unsigned long split_queue_offset(unsigned char num)
501{
502 size_t idx = busno_to_phbid(num);
503
504 return split_queue_offsets[idx];
505}
506
507static inline unsigned long tar_offset(unsigned char num)
508{
509 size_t idx = busno_to_phbid(num);
510
511 return tar_offsets[idx];
512}
513
514static inline unsigned long phb_offset(unsigned char num)
515{
516 size_t idx = busno_to_phbid(num);
517
518 return phb_offsets[idx];
519}
520
521static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
522{
523 unsigned long target = ((unsigned long)bar) | offset;
524 return (void __iomem*)target;
525}
526
527static inline int is_calioc2(unsigned short device)
528{
529 return (device == PCI_DEVICE_ID_IBM_CALIOC2);
530}
531
532static inline int is_calgary(unsigned short device)
533{
534 return (device == PCI_DEVICE_ID_IBM_CALGARY);
535}
536
537static inline int is_cal_pci_dev(unsigned short device)
538{
539 return (is_calgary(device) || is_calioc2(device));
540}
541
542static void calgary_tce_cache_blast(struct iommu_table *tbl)
543{
544 u64 val;
545 u32 aer;
546 int i = 0;
547 void __iomem *bbar = tbl->bbar;
548 void __iomem *target;
549
550 /* disable arbitration on the bus */
551 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
552 aer = readl(target);
553 writel(0, target);
554
555 /* read plssr to ensure it got there */
556 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
557 val = readl(target);
558
559 /* poll split queues until all DMA activity is done */
560 target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
561 do {
562 val = readq(target);
563 i++;
564 } while ((val & 0xff) != 0xff && i < 100);
565 if (i == 100)
566 pr_warn("PCI bus not quiesced, continuing anyway\n");
567
568 /* invalidate TCE cache */
569 target = calgary_reg(bbar, tar_offset(tbl->it_busno));
570 writeq(tbl->tar_val, target);
571
572 /* enable arbitration */
573 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
574 writel(aer, target);
575 (void)readl(target); /* flush */
576}
577
578static void calioc2_tce_cache_blast(struct iommu_table *tbl)
579{
580 void __iomem *bbar = tbl->bbar;
581 void __iomem *target;
582 u64 val64;
583 u32 val;
584 int i = 0;
585 int count = 1;
586 unsigned char bus = tbl->it_busno;
587
588begin:
589 printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
590 "sequence - count %d\n", bus, count);
591
592 /* 1. using the Page Migration Control reg set SoftStop */
593 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
594 val = be32_to_cpu(readl(target));
595 printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
596 val |= PMR_SOFTSTOP;
597 printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
598 writel(cpu_to_be32(val), target);
599
600 /* 2. poll split queues until all DMA activity is done */
601 printk(KERN_DEBUG "2a. starting to poll split queues\n");
602 target = calgary_reg(bbar, split_queue_offset(bus));
603 do {
604 val64 = readq(target);
605 i++;
606 } while ((val64 & 0xff) != 0xff && i < 100);
607 if (i == 100)
608 pr_warn("CalIOC2: PCI bus not quiesced, continuing anyway\n");
609
610 /* 3. poll Page Migration DEBUG for SoftStopFault */
611 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
612 val = be32_to_cpu(readl(target));
613 printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
614
615 /* 4. if SoftStopFault - goto (1) */
616 if (val & PMR_SOFTSTOPFAULT) {
617 if (++count < 100)
618 goto begin;
619 else {
620 pr_warn("CalIOC2: too many SoftStopFaults, aborting TCE cache flush sequence!\n");
621 return; /* pray for the best */
622 }
623 }
624
625 /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
626 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
627 printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
628 val = be32_to_cpu(readl(target));
629 printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
630 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
631 val = be32_to_cpu(readl(target));
632 printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
633
634 /* 6. invalidate TCE cache */
635 printk(KERN_DEBUG "6. invalidating TCE cache\n");
636 target = calgary_reg(bbar, tar_offset(bus));
637 writeq(tbl->tar_val, target);
638
639 /* 7. Re-read PMCR */
640 printk(KERN_DEBUG "7a. Re-reading PMCR\n");
641 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
642 val = be32_to_cpu(readl(target));
643 printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
644
645 /* 8. Remove HardStop */
646 printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
647 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
648 val = 0;
649 printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
650 writel(cpu_to_be32(val), target);
651 val = be32_to_cpu(readl(target));
652 printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
653}
654
655static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
656 u64 limit)
657{
658 unsigned int numpages;
659
660 limit = limit | 0xfffff;
661 limit++;
662
663 numpages = ((limit - start) >> PAGE_SHIFT);
664 iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
665}
666
667static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
668{
669 void __iomem *target;
670 u64 low, high, sizelow;
671 u64 start, limit;
672 struct iommu_table *tbl = pci_iommu(dev->bus);
673 unsigned char busnum = dev->bus->number;
674 void __iomem *bbar = tbl->bbar;
675
676 /* peripheral MEM_1 region */
677 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
678 low = be32_to_cpu(readl(target));
679 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
680 high = be32_to_cpu(readl(target));
681 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
682 sizelow = be32_to_cpu(readl(target));
683
684 start = (high << 32) | low;
685 limit = sizelow;
686
687 calgary_reserve_mem_region(dev, start, limit);
688}
689
690static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
691{
692 void __iomem *target;
693 u32 val32;
694 u64 low, high, sizelow, sizehigh;
695 u64 start, limit;
696 struct iommu_table *tbl = pci_iommu(dev->bus);
697 unsigned char busnum = dev->bus->number;
698 void __iomem *bbar = tbl->bbar;
699
700 /* is it enabled? */
701 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
702 val32 = be32_to_cpu(readl(target));
703 if (!(val32 & PHB_MEM2_ENABLE))
704 return;
705
706 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
707 low = be32_to_cpu(readl(target));
708 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
709 high = be32_to_cpu(readl(target));
710 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
711 sizelow = be32_to_cpu(readl(target));
712 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
713 sizehigh = be32_to_cpu(readl(target));
714
715 start = (high << 32) | low;
716 limit = (sizehigh << 32) | sizelow;
717
718 calgary_reserve_mem_region(dev, start, limit);
719}
720
721/*
722 * some regions of the IO address space do not get translated, so we
723 * must not give devices IO addresses in those regions. The regions
724 * are the 640KB-1MB region and the two PCI peripheral memory holes.
725 * Reserve all of them in the IOMMU bitmap to avoid giving them out
726 * later.
727 */
728static void __init calgary_reserve_regions(struct pci_dev *dev)
729{
730 unsigned int npages;
731 u64 start;
732 struct iommu_table *tbl = pci_iommu(dev->bus);
733
734 /* reserve EMERGENCY_PAGES from bad_dma_address and up */
735 iommu_range_reserve(tbl, DMA_ERROR_CODE, EMERGENCY_PAGES);
736
737 /* avoid the BIOS/VGA first 640KB-1MB region */
738 /* for CalIOC2 - avoid the entire first MB */
739 if (is_calgary(dev->device)) {
740 start = (640 * 1024);
741 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
742 } else { /* calioc2 */
743 start = 0;
744 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
745 }
746 iommu_range_reserve(tbl, start, npages);
747
748 /* reserve the two PCI peripheral memory regions in IO space */
749 calgary_reserve_peripheral_mem_1(dev);
750 calgary_reserve_peripheral_mem_2(dev);
751}
752
753static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
754{
755 u64 val64;
756 u64 table_phys;
757 void __iomem *target;
758 int ret;
759 struct iommu_table *tbl;
760
761 /* build TCE tables for each PHB */
762 ret = build_tce_table(dev, bbar);
763 if (ret)
764 return ret;
765
766 tbl = pci_iommu(dev->bus);
767 tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
768
769 if (is_kdump_kernel())
770 calgary_init_bitmap_from_tce_table(tbl);
771 else
772 tce_free(tbl, 0, tbl->it_size);
773
774 if (is_calgary(dev->device))
775 tbl->chip_ops = &calgary_chip_ops;
776 else if (is_calioc2(dev->device))
777 tbl->chip_ops = &calioc2_chip_ops;
778 else
779 BUG();
780
781 calgary_reserve_regions(dev);
782
783 /* set TARs for each PHB */
784 target = calgary_reg(bbar, tar_offset(dev->bus->number));
785 val64 = be64_to_cpu(readq(target));
786
787 /* zero out all TAR bits under sw control */
788 val64 &= ~TAR_SW_BITS;
789 table_phys = (u64)__pa(tbl->it_base);
790
791 val64 |= table_phys;
792
793 BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
794 val64 |= (u64) specified_table_size;
795
796 tbl->tar_val = cpu_to_be64(val64);
797
798 writeq(tbl->tar_val, target);
799 readq(target); /* flush */
800
801 return 0;
802}
803
804static void __init calgary_free_bus(struct pci_dev *dev)
805{
806 u64 val64;
807 struct iommu_table *tbl = pci_iommu(dev->bus);
808 void __iomem *target;
809 unsigned int bitmapsz;
810
811 target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
812 val64 = be64_to_cpu(readq(target));
813 val64 &= ~TAR_SW_BITS;
814 writeq(cpu_to_be64(val64), target);
815 readq(target); /* flush */
816
817 bitmapsz = tbl->it_size / BITS_PER_BYTE;
818 free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
819 tbl->it_map = NULL;
820
821 kfree(tbl);
822
823 set_pci_iommu(dev->bus, NULL);
824
825 /* Can't free bootmem allocated memory after system is up :-( */
826 bus_info[dev->bus->number].tce_space = NULL;
827}
828
829static void calgary_dump_error_regs(struct iommu_table *tbl)
830{
831 void __iomem *bbar = tbl->bbar;
832 void __iomem *target;
833 u32 csr, plssr;
834
835 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
836 csr = be32_to_cpu(readl(target));
837
838 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
839 plssr = be32_to_cpu(readl(target));
840
841 /* If no error, the agent ID in the CSR is not valid */
842 pr_emerg("DMA error on Calgary PHB 0x%x, 0x%08x@CSR 0x%08x@PLSSR\n",
843 tbl->it_busno, csr, plssr);
844}
845
846static void calioc2_dump_error_regs(struct iommu_table *tbl)
847{
848 void __iomem *bbar = tbl->bbar;
849 u32 csr, csmr, plssr, mck, rcstat;
850 void __iomem *target;
851 unsigned long phboff = phb_offset(tbl->it_busno);
852 unsigned long erroff;
853 u32 errregs[7];
854 int i;
855
856 /* dump CSR */
857 target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
858 csr = be32_to_cpu(readl(target));
859 /* dump PLSSR */
860 target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
861 plssr = be32_to_cpu(readl(target));
862 /* dump CSMR */
863 target = calgary_reg(bbar, phboff | 0x290);
864 csmr = be32_to_cpu(readl(target));
865 /* dump mck */
866 target = calgary_reg(bbar, phboff | 0x800);
867 mck = be32_to_cpu(readl(target));
868
869 pr_emerg("DMA error on CalIOC2 PHB 0x%x\n", tbl->it_busno);
870
871 pr_emerg("0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
872 csr, plssr, csmr, mck);
873
874 /* dump rest of error regs */
875 pr_emerg("");
876 for (i = 0; i < ARRAY_SIZE(errregs); i++) {
877 /* err regs are at 0x810 - 0x870 */
878 erroff = (0x810 + (i * 0x10));
879 target = calgary_reg(bbar, phboff | erroff);
880 errregs[i] = be32_to_cpu(readl(target));
881 pr_cont("0x%08x@0x%lx ", errregs[i], erroff);
882 }
883 pr_cont("\n");
884
885 /* root complex status */
886 target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
887 rcstat = be32_to_cpu(readl(target));
888 printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
889 PHB_ROOT_COMPLEX_STATUS);
890}
891
892static void calgary_watchdog(unsigned long data)
893{
894 struct pci_dev *dev = (struct pci_dev *)data;
895 struct iommu_table *tbl = pci_iommu(dev->bus);
896 void __iomem *bbar = tbl->bbar;
897 u32 val32;
898 void __iomem *target;
899
900 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
901 val32 = be32_to_cpu(readl(target));
902
903 /* If no error, the agent ID in the CSR is not valid */
904 if (val32 & CSR_AGENT_MASK) {
905 tbl->chip_ops->dump_error_regs(tbl);
906
907 /* reset error */
908 writel(0, target);
909
910 /* Disable bus that caused the error */
911 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
912 PHB_CONFIG_RW_OFFSET);
913 val32 = be32_to_cpu(readl(target));
914 val32 |= PHB_SLOT_DISABLE;
915 writel(cpu_to_be32(val32), target);
916 readl(target); /* flush */
917 } else {
918 /* Reset the timer */
919 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
920 }
921}
922
923static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
924 unsigned char busnum, unsigned long timeout)
925{
926 u64 val64;
927 void __iomem *target;
928 unsigned int phb_shift = ~0; /* silence gcc */
929 u64 mask;
930
931 switch (busno_to_phbid(busnum)) {
932 case 0: phb_shift = (63 - 19);
933 break;
934 case 1: phb_shift = (63 - 23);
935 break;
936 case 2: phb_shift = (63 - 27);
937 break;
938 case 3: phb_shift = (63 - 35);
939 break;
940 default:
941 BUG_ON(busno_to_phbid(busnum));
942 }
943
944 target = calgary_reg(bbar, CALGARY_CONFIG_REG);
945 val64 = be64_to_cpu(readq(target));
946
947 /* zero out this PHB's timer bits */
948 mask = ~(0xFUL << phb_shift);
949 val64 &= mask;
950 val64 |= (timeout << phb_shift);
951 writeq(cpu_to_be64(val64), target);
952 readq(target); /* flush */
953}
954
955static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
956{
957 unsigned char busnum = dev->bus->number;
958 void __iomem *bbar = tbl->bbar;
959 void __iomem *target;
960 u32 val;
961
962 /*
963 * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
964 */
965 target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
966 val = cpu_to_be32(readl(target));
967 val |= 0x00800000;
968 writel(cpu_to_be32(val), target);
969}
970
971static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
972{
973 unsigned char busnum = dev->bus->number;
974
975 /*
976 * Give split completion a longer timeout on bus 1 for aic94xx
977 * http://bugzilla.kernel.org/show_bug.cgi?id=7180
978 */
979 if (is_calgary(dev->device) && (busnum == 1))
980 calgary_set_split_completion_timeout(tbl->bbar, busnum,
981 CCR_2SEC_TIMEOUT);
982}
983
984static void __init calgary_enable_translation(struct pci_dev *dev)
985{
986 u32 val32;
987 unsigned char busnum;
988 void __iomem *target;
989 void __iomem *bbar;
990 struct iommu_table *tbl;
991
992 busnum = dev->bus->number;
993 tbl = pci_iommu(dev->bus);
994 bbar = tbl->bbar;
995
996 /* enable TCE in PHB Config Register */
997 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
998 val32 = be32_to_cpu(readl(target));
999 val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1000
1001 printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1002 (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1003 "Calgary" : "CalIOC2", busnum);
1004 printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1005 "bus.\n");
1006
1007 writel(cpu_to_be32(val32), target);
1008 readl(target); /* flush */
1009
1010 init_timer(&tbl->watchdog_timer);
1011 tbl->watchdog_timer.function = &calgary_watchdog;
1012 tbl->watchdog_timer.data = (unsigned long)dev;
1013 mod_timer(&tbl->watchdog_timer, jiffies);
1014}
1015
1016static void __init calgary_disable_translation(struct pci_dev *dev)
1017{
1018 u32 val32;
1019 unsigned char busnum;
1020 void __iomem *target;
1021 void __iomem *bbar;
1022 struct iommu_table *tbl;
1023
1024 busnum = dev->bus->number;
1025 tbl = pci_iommu(dev->bus);
1026 bbar = tbl->bbar;
1027
1028 /* disable TCE in PHB Config Register */
1029 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1030 val32 = be32_to_cpu(readl(target));
1031 val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1032
1033 printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1034 writel(cpu_to_be32(val32), target);
1035 readl(target); /* flush */
1036
1037 del_timer_sync(&tbl->watchdog_timer);
1038}
1039
1040static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1041{
1042 pci_dev_get(dev);
1043 set_pci_iommu(dev->bus, NULL);
1044
1045 /* is the device behind a bridge? */
1046 if (dev->bus->parent)
1047 dev->bus->parent->self = dev;
1048 else
1049 dev->bus->self = dev;
1050}
1051
1052static int __init calgary_init_one(struct pci_dev *dev)
1053{
1054 void __iomem *bbar;
1055 struct iommu_table *tbl;
1056 int ret;
1057
1058 bbar = busno_to_bbar(dev->bus->number);
1059 ret = calgary_setup_tar(dev, bbar);
1060 if (ret)
1061 goto done;
1062
1063 pci_dev_get(dev);
1064
1065 if (dev->bus->parent) {
1066 if (dev->bus->parent->self)
1067 printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1068 "bus->parent->self!\n", dev);
1069 dev->bus->parent->self = dev;
1070 } else
1071 dev->bus->self = dev;
1072
1073 tbl = pci_iommu(dev->bus);
1074 tbl->chip_ops->handle_quirks(tbl, dev);
1075
1076 calgary_enable_translation(dev);
1077
1078 return 0;
1079
1080done:
1081 return ret;
1082}
1083
1084static int __init calgary_locate_bbars(void)
1085{
1086 int ret;
1087 int rioidx, phb, bus;
1088 void __iomem *bbar;
1089 void __iomem *target;
1090 unsigned long offset;
1091 u8 start_bus, end_bus;
1092 u32 val;
1093
1094 ret = -ENODATA;
1095 for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1096 struct rio_detail *rio = rio_devs[rioidx];
1097
1098 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1099 continue;
1100
1101 /* map entire 1MB of Calgary config space */
1102 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1103 if (!bbar)
1104 goto error;
1105
1106 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1107 offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1108 target = calgary_reg(bbar, offset);
1109
1110 val = be32_to_cpu(readl(target));
1111
1112 start_bus = (u8)((val & 0x00FF0000) >> 16);
1113 end_bus = (u8)((val & 0x0000FF00) >> 8);
1114
1115 if (end_bus) {
1116 for (bus = start_bus; bus <= end_bus; bus++) {
1117 bus_info[bus].bbar = bbar;
1118 bus_info[bus].phbid = phb;
1119 }
1120 } else {
1121 bus_info[start_bus].bbar = bbar;
1122 bus_info[start_bus].phbid = phb;
1123 }
1124 }
1125 }
1126
1127 return 0;
1128
1129error:
1130 /* scan bus_info and iounmap any bbars we previously ioremap'd */
1131 for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1132 if (bus_info[bus].bbar)
1133 iounmap(bus_info[bus].bbar);
1134
1135 return ret;
1136}
1137
1138static int __init calgary_init(void)
1139{
1140 int ret;
1141 struct pci_dev *dev = NULL;
1142 struct calgary_bus_info *info;
1143
1144 ret = calgary_locate_bbars();
1145 if (ret)
1146 return ret;
1147
1148 /* Purely for kdump kernel case */
1149 if (is_kdump_kernel())
1150 get_tce_space_from_tar();
1151
1152 do {
1153 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1154 if (!dev)
1155 break;
1156 if (!is_cal_pci_dev(dev->device))
1157 continue;
1158
1159 info = &bus_info[dev->bus->number];
1160 if (info->translation_disabled) {
1161 calgary_init_one_nontraslated(dev);
1162 continue;
1163 }
1164
1165 if (!info->tce_space && !translate_empty_slots)
1166 continue;
1167
1168 ret = calgary_init_one(dev);
1169 if (ret)
1170 goto error;
1171 } while (1);
1172
1173 dev = NULL;
1174 for_each_pci_dev(dev) {
1175 struct iommu_table *tbl;
1176
1177 tbl = find_iommu_table(&dev->dev);
1178
1179 if (translation_enabled(tbl))
1180 dev->dev.archdata.dma_ops = &calgary_dma_ops;
1181 }
1182
1183 return ret;
1184
1185error:
1186 do {
1187 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1188 if (!dev)
1189 break;
1190 if (!is_cal_pci_dev(dev->device))
1191 continue;
1192
1193 info = &bus_info[dev->bus->number];
1194 if (info->translation_disabled) {
1195 pci_dev_put(dev);
1196 continue;
1197 }
1198 if (!info->tce_space && !translate_empty_slots)
1199 continue;
1200
1201 calgary_disable_translation(dev);
1202 calgary_free_bus(dev);
1203 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1204 dev->dev.archdata.dma_ops = NULL;
1205 } while (1);
1206
1207 return ret;
1208}
1209
1210static inline int __init determine_tce_table_size(void)
1211{
1212 int ret;
1213
1214 if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1215 return specified_table_size;
1216
1217 if (is_kdump_kernel() && saved_max_pfn) {
1218 /*
1219 * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1220 * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1221 * larger table size has twice as many entries, so shift the
1222 * max ram address by 13 to divide by 8K and then look at the
1223 * order of the result to choose between 0-7.
1224 */
1225 ret = get_order((saved_max_pfn * PAGE_SIZE) >> 13);
1226 if (ret > TCE_TABLE_SIZE_8M)
1227 ret = TCE_TABLE_SIZE_8M;
1228 } else {
1229 /*
1230 * Use 8M by default (suggested by Muli) if it's not
1231 * kdump kernel and saved_max_pfn isn't set.
1232 */
1233 ret = TCE_TABLE_SIZE_8M;
1234 }
1235
1236 return ret;
1237}
1238
1239static int __init build_detail_arrays(void)
1240{
1241 unsigned long ptr;
1242 unsigned numnodes, i;
1243 int scal_detail_size, rio_detail_size;
1244
1245 numnodes = rio_table_hdr->num_scal_dev;
1246 if (numnodes > MAX_NUMNODES){
1247 printk(KERN_WARNING
1248 "Calgary: MAX_NUMNODES too low! Defined as %d, "
1249 "but system has %d nodes.\n",
1250 MAX_NUMNODES, numnodes);
1251 return -ENODEV;
1252 }
1253
1254 switch (rio_table_hdr->version){
1255 case 2:
1256 scal_detail_size = 11;
1257 rio_detail_size = 13;
1258 break;
1259 case 3:
1260 scal_detail_size = 12;
1261 rio_detail_size = 15;
1262 break;
1263 default:
1264 printk(KERN_WARNING
1265 "Calgary: Invalid Rio Grande Table Version: %d\n",
1266 rio_table_hdr->version);
1267 return -EPROTO;
1268 }
1269
1270 ptr = ((unsigned long)rio_table_hdr) + 3;
1271 for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
1272 scal_devs[i] = (struct scal_detail *)ptr;
1273
1274 for (i = 0; i < rio_table_hdr->num_rio_dev;
1275 i++, ptr += rio_detail_size)
1276 rio_devs[i] = (struct rio_detail *)ptr;
1277
1278 return 0;
1279}
1280
1281static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1282{
1283 int dev;
1284 u32 val;
1285
1286 if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1287 /*
1288 * FIXME: properly scan for devices across the
1289 * PCI-to-PCI bridge on every CalIOC2 port.
1290 */
1291 return 1;
1292 }
1293
1294 for (dev = 1; dev < 8; dev++) {
1295 val = read_pci_config(bus, dev, 0, 0);
1296 if (val != 0xffffffff)
1297 break;
1298 }
1299 return (val != 0xffffffff);
1300}
1301
1302/*
1303 * calgary_init_bitmap_from_tce_table():
1304 * Function for kdump case. In the second/kdump kernel initialize
1305 * the bitmap based on the tce table entries obtained from first kernel
1306 */
1307static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1308{
1309 u64 *tp;
1310 unsigned int index;
1311 tp = ((u64 *)tbl->it_base);
1312 for (index = 0 ; index < tbl->it_size; index++) {
1313 if (*tp != 0x0)
1314 set_bit(index, tbl->it_map);
1315 tp++;
1316 }
1317}
1318
1319/*
1320 * get_tce_space_from_tar():
1321 * Function for kdump case. Get the tce tables from first kernel
1322 * by reading the contents of the base address register of calgary iommu
1323 */
1324static void __init get_tce_space_from_tar(void)
1325{
1326 int bus;
1327 void __iomem *target;
1328 unsigned long tce_space;
1329
1330 for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1331 struct calgary_bus_info *info = &bus_info[bus];
1332 unsigned short pci_device;
1333 u32 val;
1334
1335 val = read_pci_config(bus, 0, 0, 0);
1336 pci_device = (val & 0xFFFF0000) >> 16;
1337
1338 if (!is_cal_pci_dev(pci_device))
1339 continue;
1340 if (info->translation_disabled)
1341 continue;
1342
1343 if (calgary_bus_has_devices(bus, pci_device) ||
1344 translate_empty_slots) {
1345 target = calgary_reg(bus_info[bus].bbar,
1346 tar_offset(bus));
1347 tce_space = be64_to_cpu(readq(target));
1348 tce_space = tce_space & TAR_SW_BITS;
1349
1350 tce_space = tce_space & (~specified_table_size);
1351 info->tce_space = (u64 *)__va(tce_space);
1352 }
1353 }
1354 return;
1355}
1356
1357static int __init calgary_iommu_init(void)
1358{
1359 int ret;
1360
1361 /* ok, we're trying to use Calgary - let's roll */
1362 printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1363
1364 ret = calgary_init();
1365 if (ret) {
1366 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1367 "falling back to no_iommu\n", ret);
1368 return ret;
1369 }
1370
1371 return 0;
1372}
1373
1374int __init detect_calgary(void)
1375{
1376 int bus;
1377 void *tbl;
1378 int calgary_found = 0;
1379 unsigned long ptr;
1380 unsigned int offset, prev_offset;
1381 int ret;
1382
1383 /*
1384 * if the user specified iommu=off or iommu=soft or we found
1385 * another HW IOMMU already, bail out.
1386 */
1387 if (no_iommu || iommu_detected)
1388 return -ENODEV;
1389
1390 if (!use_calgary)
1391 return -ENODEV;
1392
1393 if (!early_pci_allowed())
1394 return -ENODEV;
1395
1396 printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1397
1398 ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1399
1400 rio_table_hdr = NULL;
1401 prev_offset = 0;
1402 offset = 0x180;
1403 /*
1404 * The next offset is stored in the 1st word.
1405 * Only parse up until the offset increases:
1406 */
1407 while (offset > prev_offset) {
1408 /* The block id is stored in the 2nd word */
1409 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1410 /* set the pointer past the offset & block id */
1411 rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1412 break;
1413 }
1414 prev_offset = offset;
1415 offset = *((unsigned short *)(ptr + offset));
1416 }
1417 if (!rio_table_hdr) {
1418 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1419 "in EBDA - bailing!\n");
1420 return -ENODEV;
1421 }
1422
1423 ret = build_detail_arrays();
1424 if (ret) {
1425 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1426 return -ENOMEM;
1427 }
1428
1429 specified_table_size = determine_tce_table_size();
1430
1431 for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1432 struct calgary_bus_info *info = &bus_info[bus];
1433 unsigned short pci_device;
1434 u32 val;
1435
1436 val = read_pci_config(bus, 0, 0, 0);
1437 pci_device = (val & 0xFFFF0000) >> 16;
1438
1439 if (!is_cal_pci_dev(pci_device))
1440 continue;
1441
1442 if (info->translation_disabled)
1443 continue;
1444
1445 if (calgary_bus_has_devices(bus, pci_device) ||
1446 translate_empty_slots) {
1447 /*
1448 * If it is kdump kernel, find and use tce tables
1449 * from first kernel, else allocate tce tables here
1450 */
1451 if (!is_kdump_kernel()) {
1452 tbl = alloc_tce_table();
1453 if (!tbl)
1454 goto cleanup;
1455 info->tce_space = tbl;
1456 }
1457 calgary_found = 1;
1458 }
1459 }
1460
1461 printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1462 calgary_found ? "found" : "not found");
1463
1464 if (calgary_found) {
1465 iommu_detected = 1;
1466 calgary_detected = 1;
1467 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1468 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d\n",
1469 specified_table_size);
1470
1471 x86_init.iommu.iommu_init = calgary_iommu_init;
1472 }
1473 return calgary_found;
1474
1475cleanup:
1476 for (--bus; bus >= 0; --bus) {
1477 struct calgary_bus_info *info = &bus_info[bus];
1478
1479 if (info->tce_space)
1480 free_tce_table(info->tce_space);
1481 }
1482 return -ENOMEM;
1483}
1484
1485static int __init calgary_parse_options(char *p)
1486{
1487 unsigned int bridge;
1488 unsigned long val;
1489 size_t len;
1490 ssize_t ret;
1491
1492 while (*p) {
1493 if (!strncmp(p, "64k", 3))
1494 specified_table_size = TCE_TABLE_SIZE_64K;
1495 else if (!strncmp(p, "128k", 4))
1496 specified_table_size = TCE_TABLE_SIZE_128K;
1497 else if (!strncmp(p, "256k", 4))
1498 specified_table_size = TCE_TABLE_SIZE_256K;
1499 else if (!strncmp(p, "512k", 4))
1500 specified_table_size = TCE_TABLE_SIZE_512K;
1501 else if (!strncmp(p, "1M", 2))
1502 specified_table_size = TCE_TABLE_SIZE_1M;
1503 else if (!strncmp(p, "2M", 2))
1504 specified_table_size = TCE_TABLE_SIZE_2M;
1505 else if (!strncmp(p, "4M", 2))
1506 specified_table_size = TCE_TABLE_SIZE_4M;
1507 else if (!strncmp(p, "8M", 2))
1508 specified_table_size = TCE_TABLE_SIZE_8M;
1509
1510 len = strlen("translate_empty_slots");
1511 if (!strncmp(p, "translate_empty_slots", len))
1512 translate_empty_slots = 1;
1513
1514 len = strlen("disable");
1515 if (!strncmp(p, "disable", len)) {
1516 p += len;
1517 if (*p == '=')
1518 ++p;
1519 if (*p == '\0')
1520 break;
1521 ret = kstrtoul(p, 0, &val);
1522 if (ret)
1523 break;
1524
1525 bridge = val;
1526 if (bridge < MAX_PHB_BUS_NUM) {
1527 printk(KERN_INFO "Calgary: disabling "
1528 "translation for PHB %#x\n", bridge);
1529 bus_info[bridge].translation_disabled = 1;
1530 }
1531 }
1532
1533 p = strpbrk(p, ",");
1534 if (!p)
1535 break;
1536
1537 p++; /* skip ',' */
1538 }
1539 return 1;
1540}
1541__setup("calgary=", calgary_parse_options);
1542
1543static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1544{
1545 struct iommu_table *tbl;
1546 unsigned int npages;
1547 int i;
1548
1549 tbl = pci_iommu(dev->bus);
1550
1551 for (i = 0; i < 4; i++) {
1552 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1553
1554 /* Don't give out TCEs that map MEM resources */
1555 if (!(r->flags & IORESOURCE_MEM))
1556 continue;
1557
1558 /* 0-based? we reserve the whole 1st MB anyway */
1559 if (!r->start)
1560 continue;
1561
1562 /* cover the whole region */
1563 npages = resource_size(r) >> PAGE_SHIFT;
1564 npages++;
1565
1566 iommu_range_reserve(tbl, r->start, npages);
1567 }
1568}
1569
1570static int __init calgary_fixup_tce_spaces(void)
1571{
1572 struct pci_dev *dev = NULL;
1573 struct calgary_bus_info *info;
1574
1575 if (no_iommu || swiotlb || !calgary_detected)
1576 return -ENODEV;
1577
1578 printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1579
1580 do {
1581 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1582 if (!dev)
1583 break;
1584 if (!is_cal_pci_dev(dev->device))
1585 continue;
1586
1587 info = &bus_info[dev->bus->number];
1588 if (info->translation_disabled)
1589 continue;
1590
1591 if (!info->tce_space)
1592 continue;
1593
1594 calgary_fixup_one_tce_space(dev);
1595
1596 } while (1);
1597
1598 return 0;
1599}
1600
1601/*
1602 * We need to be call after pcibios_assign_resources (fs_initcall level)
1603 * and before device_initcall.
1604 */
1605rootfs_initcall(calgary_fixup_tce_spaces);
1606
1607IOMMU_INIT_POST(detect_calgary);