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1/*
2 * Watchdog driver for IMX2 and later processors
3 *
4 * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
5 *
6 * some parts adapted by similar drivers from Darius Augulis and Vladimir
7 * Zapolskiy, additional improvements by Wim Van Sebroeck.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
14 *
15 * MX1: MX2+:
16 * ---- -----
17 * Registers: 32-bit 16-bit
18 * Stopable timer: Yes No
19 * Need to enable clk: No Yes
20 * Halt on suspend: Manual Can be automatic
21 */
22
23#include <linux/init.h>
24#include <linux/kernel.h>
25#include <linux/miscdevice.h>
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/platform_device.h>
29#include <linux/watchdog.h>
30#include <linux/clk.h>
31#include <linux/fs.h>
32#include <linux/io.h>
33#include <linux/uaccess.h>
34#include <linux/timer.h>
35#include <linux/jiffies.h>
36#include <mach/hardware.h>
37
38#define DRIVER_NAME "imx2-wdt"
39
40#define IMX2_WDT_WCR 0x00 /* Control Register */
41#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
42#define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
43#define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */
44
45#define IMX2_WDT_WSR 0x02 /* Service Register */
46#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
47#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
48
49#define IMX2_WDT_MAX_TIME 128
50#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
51
52#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
53
54#define IMX2_WDT_STATUS_OPEN 0
55#define IMX2_WDT_STATUS_STARTED 1
56#define IMX2_WDT_EXPECT_CLOSE 2
57
58static struct {
59 struct clk *clk;
60 void __iomem *base;
61 unsigned timeout;
62 unsigned long status;
63 struct timer_list timer; /* Pings the watchdog when closed */
64} imx2_wdt;
65
66static struct miscdevice imx2_wdt_miscdev;
67
68static int nowayout = WATCHDOG_NOWAYOUT;
69module_param(nowayout, int, 0);
70MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
71 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
72
73
74static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
75module_param(timeout, uint, 0);
76MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
77 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
78
79static const struct watchdog_info imx2_wdt_info = {
80 .identity = "imx2+ watchdog",
81 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
82};
83
84static inline void imx2_wdt_setup(void)
85{
86 u16 val = __raw_readw(imx2_wdt.base + IMX2_WDT_WCR);
87
88 /* Strip the old watchdog Time-Out value */
89 val &= ~IMX2_WDT_WCR_WT;
90 /* Generate reset if WDOG times out */
91 val &= ~IMX2_WDT_WCR_WRE;
92 /* Keep Watchdog Disabled */
93 val &= ~IMX2_WDT_WCR_WDE;
94 /* Set the watchdog's Time-Out value */
95 val |= WDOG_SEC_TO_COUNT(imx2_wdt.timeout);
96
97 __raw_writew(val, imx2_wdt.base + IMX2_WDT_WCR);
98
99 /* enable the watchdog */
100 val |= IMX2_WDT_WCR_WDE;
101 __raw_writew(val, imx2_wdt.base + IMX2_WDT_WCR);
102}
103
104static inline void imx2_wdt_ping(void)
105{
106 __raw_writew(IMX2_WDT_SEQ1, imx2_wdt.base + IMX2_WDT_WSR);
107 __raw_writew(IMX2_WDT_SEQ2, imx2_wdt.base + IMX2_WDT_WSR);
108}
109
110static void imx2_wdt_timer_ping(unsigned long arg)
111{
112 /* ping it every imx2_wdt.timeout / 2 seconds to prevent reboot */
113 imx2_wdt_ping();
114 mod_timer(&imx2_wdt.timer, jiffies + imx2_wdt.timeout * HZ / 2);
115}
116
117static void imx2_wdt_start(void)
118{
119 if (!test_and_set_bit(IMX2_WDT_STATUS_STARTED, &imx2_wdt.status)) {
120 /* at our first start we enable clock and do initialisations */
121 clk_enable(imx2_wdt.clk);
122
123 imx2_wdt_setup();
124 } else /* delete the timer that pings the watchdog after close */
125 del_timer_sync(&imx2_wdt.timer);
126
127 /* Watchdog is enabled - time to reload the timeout value */
128 imx2_wdt_ping();
129}
130
131static void imx2_wdt_stop(void)
132{
133 /* we don't need a clk_disable, it cannot be disabled once started.
134 * We use a timer to ping the watchdog while /dev/watchdog is closed */
135 imx2_wdt_timer_ping(0);
136}
137
138static void imx2_wdt_set_timeout(int new_timeout)
139{
140 u16 val = __raw_readw(imx2_wdt.base + IMX2_WDT_WCR);
141
142 /* set the new timeout value in the WSR */
143 val &= ~IMX2_WDT_WCR_WT;
144 val |= WDOG_SEC_TO_COUNT(new_timeout);
145 __raw_writew(val, imx2_wdt.base + IMX2_WDT_WCR);
146}
147
148static int imx2_wdt_open(struct inode *inode, struct file *file)
149{
150 if (test_and_set_bit(IMX2_WDT_STATUS_OPEN, &imx2_wdt.status))
151 return -EBUSY;
152
153 imx2_wdt_start();
154 return nonseekable_open(inode, file);
155}
156
157static int imx2_wdt_close(struct inode *inode, struct file *file)
158{
159 if (test_bit(IMX2_WDT_EXPECT_CLOSE, &imx2_wdt.status) && !nowayout)
160 imx2_wdt_stop();
161 else {
162 dev_crit(imx2_wdt_miscdev.parent,
163 "Unexpected close: Expect reboot!\n");
164 imx2_wdt_ping();
165 }
166
167 clear_bit(IMX2_WDT_EXPECT_CLOSE, &imx2_wdt.status);
168 clear_bit(IMX2_WDT_STATUS_OPEN, &imx2_wdt.status);
169 return 0;
170}
171
172static long imx2_wdt_ioctl(struct file *file, unsigned int cmd,
173 unsigned long arg)
174{
175 void __user *argp = (void __user *)arg;
176 int __user *p = argp;
177 int new_value;
178
179 switch (cmd) {
180 case WDIOC_GETSUPPORT:
181 return copy_to_user(argp, &imx2_wdt_info,
182 sizeof(struct watchdog_info)) ? -EFAULT : 0;
183
184 case WDIOC_GETSTATUS:
185 case WDIOC_GETBOOTSTATUS:
186 return put_user(0, p);
187
188 case WDIOC_KEEPALIVE:
189 imx2_wdt_ping();
190 return 0;
191
192 case WDIOC_SETTIMEOUT:
193 if (get_user(new_value, p))
194 return -EFAULT;
195 if ((new_value < 1) || (new_value > IMX2_WDT_MAX_TIME))
196 return -EINVAL;
197 imx2_wdt_set_timeout(new_value);
198 imx2_wdt.timeout = new_value;
199 imx2_wdt_ping();
200
201 /* Fallthrough to return current value */
202 case WDIOC_GETTIMEOUT:
203 return put_user(imx2_wdt.timeout, p);
204
205 default:
206 return -ENOTTY;
207 }
208}
209
210static ssize_t imx2_wdt_write(struct file *file, const char __user *data,
211 size_t len, loff_t *ppos)
212{
213 size_t i;
214 char c;
215
216 if (len == 0) /* Can we see this even ? */
217 return 0;
218
219 clear_bit(IMX2_WDT_EXPECT_CLOSE, &imx2_wdt.status);
220 /* scan to see whether or not we got the magic character */
221 for (i = 0; i != len; i++) {
222 if (get_user(c, data + i))
223 return -EFAULT;
224 if (c == 'V')
225 set_bit(IMX2_WDT_EXPECT_CLOSE, &imx2_wdt.status);
226 }
227
228 imx2_wdt_ping();
229 return len;
230}
231
232static const struct file_operations imx2_wdt_fops = {
233 .owner = THIS_MODULE,
234 .llseek = no_llseek,
235 .unlocked_ioctl = imx2_wdt_ioctl,
236 .open = imx2_wdt_open,
237 .release = imx2_wdt_close,
238 .write = imx2_wdt_write,
239};
240
241static struct miscdevice imx2_wdt_miscdev = {
242 .minor = WATCHDOG_MINOR,
243 .name = "watchdog",
244 .fops = &imx2_wdt_fops,
245};
246
247static int __init imx2_wdt_probe(struct platform_device *pdev)
248{
249 int ret;
250 int res_size;
251 struct resource *res;
252
253 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
254 if (!res) {
255 dev_err(&pdev->dev, "can't get device resources\n");
256 return -ENODEV;
257 }
258
259 res_size = resource_size(res);
260 if (!devm_request_mem_region(&pdev->dev, res->start, res_size,
261 res->name)) {
262 dev_err(&pdev->dev, "can't allocate %d bytes at %d address\n",
263 res_size, res->start);
264 return -ENOMEM;
265 }
266
267 imx2_wdt.base = devm_ioremap_nocache(&pdev->dev, res->start, res_size);
268 if (!imx2_wdt.base) {
269 dev_err(&pdev->dev, "ioremap failed\n");
270 return -ENOMEM;
271 }
272
273 imx2_wdt.clk = clk_get(&pdev->dev, NULL);
274 if (IS_ERR(imx2_wdt.clk)) {
275 dev_err(&pdev->dev, "can't get Watchdog clock\n");
276 return PTR_ERR(imx2_wdt.clk);
277 }
278
279 imx2_wdt.timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
280 if (imx2_wdt.timeout != timeout)
281 dev_warn(&pdev->dev, "Initial timeout out of range! "
282 "Clamped from %u to %u\n", timeout, imx2_wdt.timeout);
283
284 setup_timer(&imx2_wdt.timer, imx2_wdt_timer_ping, 0);
285
286 imx2_wdt_miscdev.parent = &pdev->dev;
287 ret = misc_register(&imx2_wdt_miscdev);
288 if (ret)
289 goto fail;
290
291 dev_info(&pdev->dev,
292 "IMX2+ Watchdog Timer enabled. timeout=%ds (nowayout=%d)\n",
293 imx2_wdt.timeout, nowayout);
294 return 0;
295
296fail:
297 imx2_wdt_miscdev.parent = NULL;
298 clk_put(imx2_wdt.clk);
299 return ret;
300}
301
302static int __exit imx2_wdt_remove(struct platform_device *pdev)
303{
304 misc_deregister(&imx2_wdt_miscdev);
305
306 if (test_bit(IMX2_WDT_STATUS_STARTED, &imx2_wdt.status)) {
307 del_timer_sync(&imx2_wdt.timer);
308
309 dev_crit(imx2_wdt_miscdev.parent,
310 "Device removed: Expect reboot!\n");
311 } else
312 clk_put(imx2_wdt.clk);
313
314 imx2_wdt_miscdev.parent = NULL;
315 return 0;
316}
317
318static void imx2_wdt_shutdown(struct platform_device *pdev)
319{
320 if (test_bit(IMX2_WDT_STATUS_STARTED, &imx2_wdt.status)) {
321 /* we are running, we need to delete the timer but will give
322 * max timeout before reboot will take place */
323 del_timer_sync(&imx2_wdt.timer);
324 imx2_wdt_set_timeout(IMX2_WDT_MAX_TIME);
325 imx2_wdt_ping();
326
327 dev_crit(imx2_wdt_miscdev.parent,
328 "Device shutdown: Expect reboot!\n");
329 }
330}
331
332static const struct of_device_id imx2_wdt_dt_ids[] = {
333 { .compatible = "fsl,imx21-wdt", },
334 { /* sentinel */ }
335};
336
337static struct platform_driver imx2_wdt_driver = {
338 .remove = __exit_p(imx2_wdt_remove),
339 .shutdown = imx2_wdt_shutdown,
340 .driver = {
341 .name = DRIVER_NAME,
342 .owner = THIS_MODULE,
343 .of_match_table = imx2_wdt_dt_ids,
344 },
345};
346
347static int __init imx2_wdt_init(void)
348{
349 return platform_driver_probe(&imx2_wdt_driver, imx2_wdt_probe);
350}
351module_init(imx2_wdt_init);
352
353static void __exit imx2_wdt_exit(void)
354{
355 platform_driver_unregister(&imx2_wdt_driver);
356}
357module_exit(imx2_wdt_exit);
358
359MODULE_AUTHOR("Wolfram Sang");
360MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
361MODULE_LICENSE("GPL v2");
362MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
363MODULE_ALIAS("platform:" DRIVER_NAME);
1/*
2 * Watchdog driver for IMX2 and later processors
3 *
4 * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
5 * Copyright (C) 2014 Freescale Semiconductor, Inc.
6 *
7 * some parts adapted by similar drivers from Darius Augulis and Vladimir
8 * Zapolskiy, additional improvements by Wim Van Sebroeck.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
15 *
16 * MX1: MX2+:
17 * ---- -----
18 * Registers: 32-bit 16-bit
19 * Stopable timer: Yes No
20 * Need to enable clk: No Yes
21 * Halt on suspend: Manual Can be automatic
22 */
23
24#include <linux/clk.h>
25#include <linux/delay.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/of_address.h>
33#include <linux/platform_device.h>
34#include <linux/regmap.h>
35#include <linux/watchdog.h>
36
37#define DRIVER_NAME "imx2-wdt"
38
39#define IMX2_WDT_WCR 0x00 /* Control Register */
40#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
41#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
42#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
43#define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */
44#define IMX2_WDT_WCR_WDE BIT(2) /* -> Watchdog Enable */
45#define IMX2_WDT_WCR_WDZST BIT(0) /* -> Watchdog timer Suspend */
46
47#define IMX2_WDT_WSR 0x02 /* Service Register */
48#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
49#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
50
51#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
52#define IMX2_WDT_WRSR_TOUT BIT(1) /* -> Reset due to Timeout */
53
54#define IMX2_WDT_WICR 0x06 /* Interrupt Control Register */
55#define IMX2_WDT_WICR_WIE BIT(15) /* -> Interrupt Enable */
56#define IMX2_WDT_WICR_WTIS BIT(14) /* -> Interrupt Status */
57#define IMX2_WDT_WICR_WICT 0xFF /* -> Interrupt Count Timeout */
58
59#define IMX2_WDT_WMCR 0x08 /* Misc Register */
60
61#define IMX2_WDT_MAX_TIME 128
62#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
63
64#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
65
66struct imx2_wdt_device {
67 struct clk *clk;
68 struct regmap *regmap;
69 struct watchdog_device wdog;
70 bool ext_reset;
71};
72
73static bool nowayout = WATCHDOG_NOWAYOUT;
74module_param(nowayout, bool, 0);
75MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
76 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
77
78
79static unsigned timeout;
80module_param(timeout, uint, 0);
81MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
82 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
83
84static const struct watchdog_info imx2_wdt_info = {
85 .identity = "imx2+ watchdog",
86 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
87};
88
89static const struct watchdog_info imx2_wdt_pretimeout_info = {
90 .identity = "imx2+ watchdog",
91 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
92 WDIOF_PRETIMEOUT,
93};
94
95static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
96 void *data)
97{
98 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
99 unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
100
101 /* Use internal reset or external - not both */
102 if (wdev->ext_reset)
103 wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */
104 else
105 wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */
106
107 /* Assert SRS signal */
108 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
109 /*
110 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
111 * written twice), we add another two writes to ensure there must be at
112 * least two writes happen in the same one 32kHz clock period. We save
113 * the target check here, since the writes shouldn't be a huge burden
114 * for other platforms.
115 */
116 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
117 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
118
119 /* wait for reset to assert... */
120 mdelay(500);
121
122 return 0;
123}
124
125static inline void imx2_wdt_setup(struct watchdog_device *wdog)
126{
127 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
128 u32 val;
129
130 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
131
132 /* Suspend timer in low power mode, write once-only */
133 val |= IMX2_WDT_WCR_WDZST;
134 /* Strip the old watchdog Time-Out value */
135 val &= ~IMX2_WDT_WCR_WT;
136 /* Generate internal chip-level reset if WDOG times out */
137 if (!wdev->ext_reset)
138 val &= ~IMX2_WDT_WCR_WRE;
139 /* Or if external-reset assert WDOG_B reset only on time-out */
140 else
141 val |= IMX2_WDT_WCR_WRE;
142 /* Keep Watchdog Disabled */
143 val &= ~IMX2_WDT_WCR_WDE;
144 /* Set the watchdog's Time-Out value */
145 val |= WDOG_SEC_TO_COUNT(wdog->timeout);
146
147 regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
148
149 /* enable the watchdog */
150 val |= IMX2_WDT_WCR_WDE;
151 regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
152}
153
154static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
155{
156 u32 val;
157
158 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
159
160 return val & IMX2_WDT_WCR_WDE;
161}
162
163static int imx2_wdt_ping(struct watchdog_device *wdog)
164{
165 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
166
167 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
168 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
169 return 0;
170}
171
172static void __imx2_wdt_set_timeout(struct watchdog_device *wdog,
173 unsigned int new_timeout)
174{
175 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
176
177 regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
178 WDOG_SEC_TO_COUNT(new_timeout));
179}
180
181static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
182 unsigned int new_timeout)
183{
184 __imx2_wdt_set_timeout(wdog, new_timeout);
185
186 wdog->timeout = new_timeout;
187 return 0;
188}
189
190static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog,
191 unsigned int new_pretimeout)
192{
193 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
194
195 if (new_pretimeout >= IMX2_WDT_MAX_TIME)
196 return -EINVAL;
197
198 wdog->pretimeout = new_pretimeout;
199
200 regmap_update_bits(wdev->regmap, IMX2_WDT_WICR,
201 IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT,
202 IMX2_WDT_WICR_WIE | (new_pretimeout << 1));
203 return 0;
204}
205
206static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg)
207{
208 struct watchdog_device *wdog = wdog_arg;
209 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
210
211 regmap_write_bits(wdev->regmap, IMX2_WDT_WICR,
212 IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS);
213
214 watchdog_notify_pretimeout(wdog);
215
216 return IRQ_HANDLED;
217}
218
219static int imx2_wdt_start(struct watchdog_device *wdog)
220{
221 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
222
223 if (imx2_wdt_is_running(wdev))
224 imx2_wdt_set_timeout(wdog, wdog->timeout);
225 else
226 imx2_wdt_setup(wdog);
227
228 set_bit(WDOG_HW_RUNNING, &wdog->status);
229
230 return imx2_wdt_ping(wdog);
231}
232
233static const struct watchdog_ops imx2_wdt_ops = {
234 .owner = THIS_MODULE,
235 .start = imx2_wdt_start,
236 .ping = imx2_wdt_ping,
237 .set_timeout = imx2_wdt_set_timeout,
238 .set_pretimeout = imx2_wdt_set_pretimeout,
239 .restart = imx2_wdt_restart,
240};
241
242static const struct regmap_config imx2_wdt_regmap_config = {
243 .reg_bits = 16,
244 .reg_stride = 2,
245 .val_bits = 16,
246 .max_register = 0x8,
247};
248
249static int __init imx2_wdt_probe(struct platform_device *pdev)
250{
251 struct imx2_wdt_device *wdev;
252 struct watchdog_device *wdog;
253 struct resource *res;
254 void __iomem *base;
255 int ret;
256 u32 val;
257
258 wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
259 if (!wdev)
260 return -ENOMEM;
261
262 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
263 base = devm_ioremap_resource(&pdev->dev, res);
264 if (IS_ERR(base))
265 return PTR_ERR(base);
266
267 wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
268 &imx2_wdt_regmap_config);
269 if (IS_ERR(wdev->regmap)) {
270 dev_err(&pdev->dev, "regmap init failed\n");
271 return PTR_ERR(wdev->regmap);
272 }
273
274 wdev->clk = devm_clk_get(&pdev->dev, NULL);
275 if (IS_ERR(wdev->clk)) {
276 dev_err(&pdev->dev, "can't get Watchdog clock\n");
277 return PTR_ERR(wdev->clk);
278 }
279
280 wdog = &wdev->wdog;
281 wdog->info = &imx2_wdt_info;
282 wdog->ops = &imx2_wdt_ops;
283 wdog->min_timeout = 1;
284 wdog->timeout = IMX2_WDT_DEFAULT_TIME;
285 wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
286 wdog->parent = &pdev->dev;
287
288 ret = platform_get_irq(pdev, 0);
289 if (ret > 0)
290 if (!devm_request_irq(&pdev->dev, ret, imx2_wdt_isr, 0,
291 dev_name(&pdev->dev), wdog))
292 wdog->info = &imx2_wdt_pretimeout_info;
293
294 ret = clk_prepare_enable(wdev->clk);
295 if (ret)
296 return ret;
297
298 regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
299 wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
300
301 wdev->ext_reset = of_property_read_bool(pdev->dev.of_node,
302 "fsl,ext-reset-output");
303 platform_set_drvdata(pdev, wdog);
304 watchdog_set_drvdata(wdog, wdev);
305 watchdog_set_nowayout(wdog, nowayout);
306 watchdog_set_restart_priority(wdog, 128);
307 watchdog_init_timeout(wdog, timeout, &pdev->dev);
308
309 if (imx2_wdt_is_running(wdev)) {
310 imx2_wdt_set_timeout(wdog, wdog->timeout);
311 set_bit(WDOG_HW_RUNNING, &wdog->status);
312 }
313
314 /*
315 * Disable the watchdog power down counter at boot. Otherwise the power
316 * down counter will pull down the #WDOG interrupt line for one clock
317 * cycle.
318 */
319 regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
320
321 ret = watchdog_register_device(wdog);
322 if (ret) {
323 dev_err(&pdev->dev, "cannot register watchdog device\n");
324 goto disable_clk;
325 }
326
327 dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
328 wdog->timeout, nowayout);
329
330 return 0;
331
332disable_clk:
333 clk_disable_unprepare(wdev->clk);
334 return ret;
335}
336
337static int __exit imx2_wdt_remove(struct platform_device *pdev)
338{
339 struct watchdog_device *wdog = platform_get_drvdata(pdev);
340 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
341
342 watchdog_unregister_device(wdog);
343
344 if (imx2_wdt_is_running(wdev)) {
345 imx2_wdt_ping(wdog);
346 dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
347 }
348 return 0;
349}
350
351static void imx2_wdt_shutdown(struct platform_device *pdev)
352{
353 struct watchdog_device *wdog = platform_get_drvdata(pdev);
354 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
355
356 if (imx2_wdt_is_running(wdev)) {
357 /*
358 * We are running, configure max timeout before reboot
359 * will take place.
360 */
361 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
362 imx2_wdt_ping(wdog);
363 dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
364 }
365}
366
367#ifdef CONFIG_PM_SLEEP
368/* Disable watchdog if it is active or non-active but still running */
369static int imx2_wdt_suspend(struct device *dev)
370{
371 struct watchdog_device *wdog = dev_get_drvdata(dev);
372 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
373
374 /* The watchdog IP block is running */
375 if (imx2_wdt_is_running(wdev)) {
376 /*
377 * Don't update wdog->timeout, we'll restore the current value
378 * during resume.
379 */
380 __imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
381 imx2_wdt_ping(wdog);
382 }
383
384 clk_disable_unprepare(wdev->clk);
385
386 return 0;
387}
388
389/* Enable watchdog and configure it if necessary */
390static int imx2_wdt_resume(struct device *dev)
391{
392 struct watchdog_device *wdog = dev_get_drvdata(dev);
393 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
394 int ret;
395
396 ret = clk_prepare_enable(wdev->clk);
397 if (ret)
398 return ret;
399
400 if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
401 /*
402 * If the watchdog is still active and resumes
403 * from deep sleep state, need to restart the
404 * watchdog again.
405 */
406 imx2_wdt_setup(wdog);
407 }
408 if (imx2_wdt_is_running(wdev)) {
409 imx2_wdt_set_timeout(wdog, wdog->timeout);
410 imx2_wdt_ping(wdog);
411 }
412
413 return 0;
414}
415#endif
416
417static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
418 imx2_wdt_resume);
419
420static const struct of_device_id imx2_wdt_dt_ids[] = {
421 { .compatible = "fsl,imx21-wdt", },
422 { /* sentinel */ }
423};
424MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
425
426static struct platform_driver imx2_wdt_driver = {
427 .remove = __exit_p(imx2_wdt_remove),
428 .shutdown = imx2_wdt_shutdown,
429 .driver = {
430 .name = DRIVER_NAME,
431 .pm = &imx2_wdt_pm_ops,
432 .of_match_table = imx2_wdt_dt_ids,
433 },
434};
435
436module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
437
438MODULE_AUTHOR("Wolfram Sang");
439MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
440MODULE_LICENSE("GPL v2");
441MODULE_ALIAS("platform:" DRIVER_NAME);