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1/*
2 * Watchdog driver for IMX2 and later processors
3 *
4 * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
5 *
6 * some parts adapted by similar drivers from Darius Augulis and Vladimir
7 * Zapolskiy, additional improvements by Wim Van Sebroeck.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
14 *
15 * MX1: MX2+:
16 * ---- -----
17 * Registers: 32-bit 16-bit
18 * Stopable timer: Yes No
19 * Need to enable clk: No Yes
20 * Halt on suspend: Manual Can be automatic
21 */
22
23#include <linux/init.h>
24#include <linux/kernel.h>
25#include <linux/miscdevice.h>
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/platform_device.h>
29#include <linux/watchdog.h>
30#include <linux/clk.h>
31#include <linux/fs.h>
32#include <linux/io.h>
33#include <linux/uaccess.h>
34#include <linux/timer.h>
35#include <linux/jiffies.h>
36#include <mach/hardware.h>
37
38#define DRIVER_NAME "imx2-wdt"
39
40#define IMX2_WDT_WCR 0x00 /* Control Register */
41#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
42#define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
43#define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */
44
45#define IMX2_WDT_WSR 0x02 /* Service Register */
46#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
47#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
48
49#define IMX2_WDT_MAX_TIME 128
50#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
51
52#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
53
54#define IMX2_WDT_STATUS_OPEN 0
55#define IMX2_WDT_STATUS_STARTED 1
56#define IMX2_WDT_EXPECT_CLOSE 2
57
58static struct {
59 struct clk *clk;
60 void __iomem *base;
61 unsigned timeout;
62 unsigned long status;
63 struct timer_list timer; /* Pings the watchdog when closed */
64} imx2_wdt;
65
66static struct miscdevice imx2_wdt_miscdev;
67
68static int nowayout = WATCHDOG_NOWAYOUT;
69module_param(nowayout, int, 0);
70MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
71 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
72
73
74static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
75module_param(timeout, uint, 0);
76MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
77 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
78
79static const struct watchdog_info imx2_wdt_info = {
80 .identity = "imx2+ watchdog",
81 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
82};
83
84static inline void imx2_wdt_setup(void)
85{
86 u16 val = __raw_readw(imx2_wdt.base + IMX2_WDT_WCR);
87
88 /* Strip the old watchdog Time-Out value */
89 val &= ~IMX2_WDT_WCR_WT;
90 /* Generate reset if WDOG times out */
91 val &= ~IMX2_WDT_WCR_WRE;
92 /* Keep Watchdog Disabled */
93 val &= ~IMX2_WDT_WCR_WDE;
94 /* Set the watchdog's Time-Out value */
95 val |= WDOG_SEC_TO_COUNT(imx2_wdt.timeout);
96
97 __raw_writew(val, imx2_wdt.base + IMX2_WDT_WCR);
98
99 /* enable the watchdog */
100 val |= IMX2_WDT_WCR_WDE;
101 __raw_writew(val, imx2_wdt.base + IMX2_WDT_WCR);
102}
103
104static inline void imx2_wdt_ping(void)
105{
106 __raw_writew(IMX2_WDT_SEQ1, imx2_wdt.base + IMX2_WDT_WSR);
107 __raw_writew(IMX2_WDT_SEQ2, imx2_wdt.base + IMX2_WDT_WSR);
108}
109
110static void imx2_wdt_timer_ping(unsigned long arg)
111{
112 /* ping it every imx2_wdt.timeout / 2 seconds to prevent reboot */
113 imx2_wdt_ping();
114 mod_timer(&imx2_wdt.timer, jiffies + imx2_wdt.timeout * HZ / 2);
115}
116
117static void imx2_wdt_start(void)
118{
119 if (!test_and_set_bit(IMX2_WDT_STATUS_STARTED, &imx2_wdt.status)) {
120 /* at our first start we enable clock and do initialisations */
121 clk_enable(imx2_wdt.clk);
122
123 imx2_wdt_setup();
124 } else /* delete the timer that pings the watchdog after close */
125 del_timer_sync(&imx2_wdt.timer);
126
127 /* Watchdog is enabled - time to reload the timeout value */
128 imx2_wdt_ping();
129}
130
131static void imx2_wdt_stop(void)
132{
133 /* we don't need a clk_disable, it cannot be disabled once started.
134 * We use a timer to ping the watchdog while /dev/watchdog is closed */
135 imx2_wdt_timer_ping(0);
136}
137
138static void imx2_wdt_set_timeout(int new_timeout)
139{
140 u16 val = __raw_readw(imx2_wdt.base + IMX2_WDT_WCR);
141
142 /* set the new timeout value in the WSR */
143 val &= ~IMX2_WDT_WCR_WT;
144 val |= WDOG_SEC_TO_COUNT(new_timeout);
145 __raw_writew(val, imx2_wdt.base + IMX2_WDT_WCR);
146}
147
148static int imx2_wdt_open(struct inode *inode, struct file *file)
149{
150 if (test_and_set_bit(IMX2_WDT_STATUS_OPEN, &imx2_wdt.status))
151 return -EBUSY;
152
153 imx2_wdt_start();
154 return nonseekable_open(inode, file);
155}
156
157static int imx2_wdt_close(struct inode *inode, struct file *file)
158{
159 if (test_bit(IMX2_WDT_EXPECT_CLOSE, &imx2_wdt.status) && !nowayout)
160 imx2_wdt_stop();
161 else {
162 dev_crit(imx2_wdt_miscdev.parent,
163 "Unexpected close: Expect reboot!\n");
164 imx2_wdt_ping();
165 }
166
167 clear_bit(IMX2_WDT_EXPECT_CLOSE, &imx2_wdt.status);
168 clear_bit(IMX2_WDT_STATUS_OPEN, &imx2_wdt.status);
169 return 0;
170}
171
172static long imx2_wdt_ioctl(struct file *file, unsigned int cmd,
173 unsigned long arg)
174{
175 void __user *argp = (void __user *)arg;
176 int __user *p = argp;
177 int new_value;
178
179 switch (cmd) {
180 case WDIOC_GETSUPPORT:
181 return copy_to_user(argp, &imx2_wdt_info,
182 sizeof(struct watchdog_info)) ? -EFAULT : 0;
183
184 case WDIOC_GETSTATUS:
185 case WDIOC_GETBOOTSTATUS:
186 return put_user(0, p);
187
188 case WDIOC_KEEPALIVE:
189 imx2_wdt_ping();
190 return 0;
191
192 case WDIOC_SETTIMEOUT:
193 if (get_user(new_value, p))
194 return -EFAULT;
195 if ((new_value < 1) || (new_value > IMX2_WDT_MAX_TIME))
196 return -EINVAL;
197 imx2_wdt_set_timeout(new_value);
198 imx2_wdt.timeout = new_value;
199 imx2_wdt_ping();
200
201 /* Fallthrough to return current value */
202 case WDIOC_GETTIMEOUT:
203 return put_user(imx2_wdt.timeout, p);
204
205 default:
206 return -ENOTTY;
207 }
208}
209
210static ssize_t imx2_wdt_write(struct file *file, const char __user *data,
211 size_t len, loff_t *ppos)
212{
213 size_t i;
214 char c;
215
216 if (len == 0) /* Can we see this even ? */
217 return 0;
218
219 clear_bit(IMX2_WDT_EXPECT_CLOSE, &imx2_wdt.status);
220 /* scan to see whether or not we got the magic character */
221 for (i = 0; i != len; i++) {
222 if (get_user(c, data + i))
223 return -EFAULT;
224 if (c == 'V')
225 set_bit(IMX2_WDT_EXPECT_CLOSE, &imx2_wdt.status);
226 }
227
228 imx2_wdt_ping();
229 return len;
230}
231
232static const struct file_operations imx2_wdt_fops = {
233 .owner = THIS_MODULE,
234 .llseek = no_llseek,
235 .unlocked_ioctl = imx2_wdt_ioctl,
236 .open = imx2_wdt_open,
237 .release = imx2_wdt_close,
238 .write = imx2_wdt_write,
239};
240
241static struct miscdevice imx2_wdt_miscdev = {
242 .minor = WATCHDOG_MINOR,
243 .name = "watchdog",
244 .fops = &imx2_wdt_fops,
245};
246
247static int __init imx2_wdt_probe(struct platform_device *pdev)
248{
249 int ret;
250 int res_size;
251 struct resource *res;
252
253 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
254 if (!res) {
255 dev_err(&pdev->dev, "can't get device resources\n");
256 return -ENODEV;
257 }
258
259 res_size = resource_size(res);
260 if (!devm_request_mem_region(&pdev->dev, res->start, res_size,
261 res->name)) {
262 dev_err(&pdev->dev, "can't allocate %d bytes at %d address\n",
263 res_size, res->start);
264 return -ENOMEM;
265 }
266
267 imx2_wdt.base = devm_ioremap_nocache(&pdev->dev, res->start, res_size);
268 if (!imx2_wdt.base) {
269 dev_err(&pdev->dev, "ioremap failed\n");
270 return -ENOMEM;
271 }
272
273 imx2_wdt.clk = clk_get(&pdev->dev, NULL);
274 if (IS_ERR(imx2_wdt.clk)) {
275 dev_err(&pdev->dev, "can't get Watchdog clock\n");
276 return PTR_ERR(imx2_wdt.clk);
277 }
278
279 imx2_wdt.timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
280 if (imx2_wdt.timeout != timeout)
281 dev_warn(&pdev->dev, "Initial timeout out of range! "
282 "Clamped from %u to %u\n", timeout, imx2_wdt.timeout);
283
284 setup_timer(&imx2_wdt.timer, imx2_wdt_timer_ping, 0);
285
286 imx2_wdt_miscdev.parent = &pdev->dev;
287 ret = misc_register(&imx2_wdt_miscdev);
288 if (ret)
289 goto fail;
290
291 dev_info(&pdev->dev,
292 "IMX2+ Watchdog Timer enabled. timeout=%ds (nowayout=%d)\n",
293 imx2_wdt.timeout, nowayout);
294 return 0;
295
296fail:
297 imx2_wdt_miscdev.parent = NULL;
298 clk_put(imx2_wdt.clk);
299 return ret;
300}
301
302static int __exit imx2_wdt_remove(struct platform_device *pdev)
303{
304 misc_deregister(&imx2_wdt_miscdev);
305
306 if (test_bit(IMX2_WDT_STATUS_STARTED, &imx2_wdt.status)) {
307 del_timer_sync(&imx2_wdt.timer);
308
309 dev_crit(imx2_wdt_miscdev.parent,
310 "Device removed: Expect reboot!\n");
311 } else
312 clk_put(imx2_wdt.clk);
313
314 imx2_wdt_miscdev.parent = NULL;
315 return 0;
316}
317
318static void imx2_wdt_shutdown(struct platform_device *pdev)
319{
320 if (test_bit(IMX2_WDT_STATUS_STARTED, &imx2_wdt.status)) {
321 /* we are running, we need to delete the timer but will give
322 * max timeout before reboot will take place */
323 del_timer_sync(&imx2_wdt.timer);
324 imx2_wdt_set_timeout(IMX2_WDT_MAX_TIME);
325 imx2_wdt_ping();
326
327 dev_crit(imx2_wdt_miscdev.parent,
328 "Device shutdown: Expect reboot!\n");
329 }
330}
331
332static const struct of_device_id imx2_wdt_dt_ids[] = {
333 { .compatible = "fsl,imx21-wdt", },
334 { /* sentinel */ }
335};
336
337static struct platform_driver imx2_wdt_driver = {
338 .remove = __exit_p(imx2_wdt_remove),
339 .shutdown = imx2_wdt_shutdown,
340 .driver = {
341 .name = DRIVER_NAME,
342 .owner = THIS_MODULE,
343 .of_match_table = imx2_wdt_dt_ids,
344 },
345};
346
347static int __init imx2_wdt_init(void)
348{
349 return platform_driver_probe(&imx2_wdt_driver, imx2_wdt_probe);
350}
351module_init(imx2_wdt_init);
352
353static void __exit imx2_wdt_exit(void)
354{
355 platform_driver_unregister(&imx2_wdt_driver);
356}
357module_exit(imx2_wdt_exit);
358
359MODULE_AUTHOR("Wolfram Sang");
360MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
361MODULE_LICENSE("GPL v2");
362MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
363MODULE_ALIAS("platform:" DRIVER_NAME);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Watchdog driver for IMX2 and later processors
4 *
5 * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
6 * Copyright (C) 2014 Freescale Semiconductor, Inc.
7 *
8 * some parts adapted by similar drivers from Darius Augulis and Vladimir
9 * Zapolskiy, additional improvements by Wim Van Sebroeck.
10 *
11 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
12 *
13 * MX1: MX2+:
14 * ---- -----
15 * Registers: 32-bit 16-bit
16 * Stopable timer: Yes No
17 * Need to enable clk: No Yes
18 * Halt on suspend: Manual Can be automatic
19 */
20
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/of_address.h>
30#include <linux/platform_device.h>
31#include <linux/regmap.h>
32#include <linux/watchdog.h>
33
34#define DRIVER_NAME "imx2-wdt"
35
36#define IMX2_WDT_WCR 0x00 /* Control Register */
37#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
38#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
39#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
40#define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */
41#define IMX2_WDT_WCR_WDE BIT(2) /* -> Watchdog Enable */
42#define IMX2_WDT_WCR_WDZST BIT(0) /* -> Watchdog timer Suspend */
43
44#define IMX2_WDT_WSR 0x02 /* Service Register */
45#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
46#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
47
48#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
49#define IMX2_WDT_WRSR_TOUT BIT(1) /* -> Reset due to Timeout */
50
51#define IMX2_WDT_WICR 0x06 /* Interrupt Control Register */
52#define IMX2_WDT_WICR_WIE BIT(15) /* -> Interrupt Enable */
53#define IMX2_WDT_WICR_WTIS BIT(14) /* -> Interrupt Status */
54#define IMX2_WDT_WICR_WICT 0xFF /* -> Interrupt Count Timeout */
55
56#define IMX2_WDT_WMCR 0x08 /* Misc Register */
57
58#define IMX2_WDT_MAX_TIME 128U
59#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
60
61#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
62
63struct imx2_wdt_device {
64 struct clk *clk;
65 struct regmap *regmap;
66 struct watchdog_device wdog;
67 bool ext_reset;
68};
69
70static bool nowayout = WATCHDOG_NOWAYOUT;
71module_param(nowayout, bool, 0);
72MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
73 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
74
75
76static unsigned timeout;
77module_param(timeout, uint, 0);
78MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
79 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
80
81static const struct watchdog_info imx2_wdt_info = {
82 .identity = "imx2+ watchdog",
83 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
84};
85
86static const struct watchdog_info imx2_wdt_pretimeout_info = {
87 .identity = "imx2+ watchdog",
88 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
89 WDIOF_PRETIMEOUT,
90};
91
92static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
93 void *data)
94{
95 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
96 unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
97
98 /* Use internal reset or external - not both */
99 if (wdev->ext_reset)
100 wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */
101 else
102 wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */
103
104 /* Assert SRS signal */
105 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
106 /*
107 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
108 * written twice), we add another two writes to ensure there must be at
109 * least two writes happen in the same one 32kHz clock period. We save
110 * the target check here, since the writes shouldn't be a huge burden
111 * for other platforms.
112 */
113 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
114 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
115
116 /* wait for reset to assert... */
117 mdelay(500);
118
119 return 0;
120}
121
122static inline void imx2_wdt_setup(struct watchdog_device *wdog)
123{
124 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
125 u32 val;
126
127 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
128
129 /* Suspend timer in low power mode, write once-only */
130 val |= IMX2_WDT_WCR_WDZST;
131 /* Strip the old watchdog Time-Out value */
132 val &= ~IMX2_WDT_WCR_WT;
133 /* Generate internal chip-level reset if WDOG times out */
134 if (!wdev->ext_reset)
135 val &= ~IMX2_WDT_WCR_WRE;
136 /* Or if external-reset assert WDOG_B reset only on time-out */
137 else
138 val |= IMX2_WDT_WCR_WRE;
139 /* Keep Watchdog Disabled */
140 val &= ~IMX2_WDT_WCR_WDE;
141 /* Set the watchdog's Time-Out value */
142 val |= WDOG_SEC_TO_COUNT(wdog->timeout);
143
144 regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
145
146 /* enable the watchdog */
147 val |= IMX2_WDT_WCR_WDE;
148 regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
149}
150
151static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
152{
153 u32 val;
154
155 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
156
157 return val & IMX2_WDT_WCR_WDE;
158}
159
160static int imx2_wdt_ping(struct watchdog_device *wdog)
161{
162 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
163
164 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
165 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
166 return 0;
167}
168
169static void __imx2_wdt_set_timeout(struct watchdog_device *wdog,
170 unsigned int new_timeout)
171{
172 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
173
174 regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
175 WDOG_SEC_TO_COUNT(new_timeout));
176}
177
178static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
179 unsigned int new_timeout)
180{
181 unsigned int actual;
182
183 actual = min(new_timeout, IMX2_WDT_MAX_TIME);
184 __imx2_wdt_set_timeout(wdog, actual);
185 wdog->timeout = new_timeout;
186 return 0;
187}
188
189static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog,
190 unsigned int new_pretimeout)
191{
192 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
193
194 if (new_pretimeout >= IMX2_WDT_MAX_TIME)
195 return -EINVAL;
196
197 wdog->pretimeout = new_pretimeout;
198
199 regmap_update_bits(wdev->regmap, IMX2_WDT_WICR,
200 IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT,
201 IMX2_WDT_WICR_WIE | (new_pretimeout << 1));
202 return 0;
203}
204
205static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg)
206{
207 struct watchdog_device *wdog = wdog_arg;
208 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
209
210 regmap_write_bits(wdev->regmap, IMX2_WDT_WICR,
211 IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS);
212
213 watchdog_notify_pretimeout(wdog);
214
215 return IRQ_HANDLED;
216}
217
218static int imx2_wdt_start(struct watchdog_device *wdog)
219{
220 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
221
222 if (imx2_wdt_is_running(wdev))
223 imx2_wdt_set_timeout(wdog, wdog->timeout);
224 else
225 imx2_wdt_setup(wdog);
226
227 set_bit(WDOG_HW_RUNNING, &wdog->status);
228
229 return imx2_wdt_ping(wdog);
230}
231
232static const struct watchdog_ops imx2_wdt_ops = {
233 .owner = THIS_MODULE,
234 .start = imx2_wdt_start,
235 .ping = imx2_wdt_ping,
236 .set_timeout = imx2_wdt_set_timeout,
237 .set_pretimeout = imx2_wdt_set_pretimeout,
238 .restart = imx2_wdt_restart,
239};
240
241static const struct regmap_config imx2_wdt_regmap_config = {
242 .reg_bits = 16,
243 .reg_stride = 2,
244 .val_bits = 16,
245 .max_register = 0x8,
246};
247
248static int __init imx2_wdt_probe(struct platform_device *pdev)
249{
250 struct imx2_wdt_device *wdev;
251 struct watchdog_device *wdog;
252 void __iomem *base;
253 int ret;
254 u32 val;
255
256 wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
257 if (!wdev)
258 return -ENOMEM;
259
260 base = devm_platform_ioremap_resource(pdev, 0);
261 if (IS_ERR(base))
262 return PTR_ERR(base);
263
264 wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
265 &imx2_wdt_regmap_config);
266 if (IS_ERR(wdev->regmap)) {
267 dev_err(&pdev->dev, "regmap init failed\n");
268 return PTR_ERR(wdev->regmap);
269 }
270
271 wdev->clk = devm_clk_get(&pdev->dev, NULL);
272 if (IS_ERR(wdev->clk)) {
273 dev_err(&pdev->dev, "can't get Watchdog clock\n");
274 return PTR_ERR(wdev->clk);
275 }
276
277 wdog = &wdev->wdog;
278 wdog->info = &imx2_wdt_info;
279 wdog->ops = &imx2_wdt_ops;
280 wdog->min_timeout = 1;
281 wdog->timeout = IMX2_WDT_DEFAULT_TIME;
282 wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
283 wdog->parent = &pdev->dev;
284
285 ret = platform_get_irq(pdev, 0);
286 if (ret > 0)
287 if (!devm_request_irq(&pdev->dev, ret, imx2_wdt_isr, 0,
288 dev_name(&pdev->dev), wdog))
289 wdog->info = &imx2_wdt_pretimeout_info;
290
291 ret = clk_prepare_enable(wdev->clk);
292 if (ret)
293 return ret;
294
295 regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
296 wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
297
298 wdev->ext_reset = of_property_read_bool(pdev->dev.of_node,
299 "fsl,ext-reset-output");
300 platform_set_drvdata(pdev, wdog);
301 watchdog_set_drvdata(wdog, wdev);
302 watchdog_set_nowayout(wdog, nowayout);
303 watchdog_set_restart_priority(wdog, 128);
304 watchdog_init_timeout(wdog, timeout, &pdev->dev);
305
306 if (imx2_wdt_is_running(wdev)) {
307 imx2_wdt_set_timeout(wdog, wdog->timeout);
308 set_bit(WDOG_HW_RUNNING, &wdog->status);
309 }
310
311 /*
312 * Disable the watchdog power down counter at boot. Otherwise the power
313 * down counter will pull down the #WDOG interrupt line for one clock
314 * cycle.
315 */
316 regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
317
318 ret = watchdog_register_device(wdog);
319 if (ret)
320 goto disable_clk;
321
322 dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
323 wdog->timeout, nowayout);
324
325 return 0;
326
327disable_clk:
328 clk_disable_unprepare(wdev->clk);
329 return ret;
330}
331
332static int __exit imx2_wdt_remove(struct platform_device *pdev)
333{
334 struct watchdog_device *wdog = platform_get_drvdata(pdev);
335 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
336
337 watchdog_unregister_device(wdog);
338
339 if (imx2_wdt_is_running(wdev)) {
340 imx2_wdt_ping(wdog);
341 dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
342 }
343 return 0;
344}
345
346static void imx2_wdt_shutdown(struct platform_device *pdev)
347{
348 struct watchdog_device *wdog = platform_get_drvdata(pdev);
349 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
350
351 if (imx2_wdt_is_running(wdev)) {
352 /*
353 * We are running, configure max timeout before reboot
354 * will take place.
355 */
356 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
357 imx2_wdt_ping(wdog);
358 dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
359 }
360}
361
362#ifdef CONFIG_PM_SLEEP
363/* Disable watchdog if it is active or non-active but still running */
364static int imx2_wdt_suspend(struct device *dev)
365{
366 struct watchdog_device *wdog = dev_get_drvdata(dev);
367 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
368
369 /* The watchdog IP block is running */
370 if (imx2_wdt_is_running(wdev)) {
371 /*
372 * Don't update wdog->timeout, we'll restore the current value
373 * during resume.
374 */
375 __imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
376 imx2_wdt_ping(wdog);
377 }
378
379 clk_disable_unprepare(wdev->clk);
380
381 return 0;
382}
383
384/* Enable watchdog and configure it if necessary */
385static int imx2_wdt_resume(struct device *dev)
386{
387 struct watchdog_device *wdog = dev_get_drvdata(dev);
388 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
389 int ret;
390
391 ret = clk_prepare_enable(wdev->clk);
392 if (ret)
393 return ret;
394
395 if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
396 /*
397 * If the watchdog is still active and resumes
398 * from deep sleep state, need to restart the
399 * watchdog again.
400 */
401 imx2_wdt_setup(wdog);
402 }
403 if (imx2_wdt_is_running(wdev)) {
404 imx2_wdt_set_timeout(wdog, wdog->timeout);
405 imx2_wdt_ping(wdog);
406 }
407
408 return 0;
409}
410#endif
411
412static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
413 imx2_wdt_resume);
414
415static const struct of_device_id imx2_wdt_dt_ids[] = {
416 { .compatible = "fsl,imx21-wdt", },
417 { /* sentinel */ }
418};
419MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
420
421static struct platform_driver imx2_wdt_driver = {
422 .remove = __exit_p(imx2_wdt_remove),
423 .shutdown = imx2_wdt_shutdown,
424 .driver = {
425 .name = DRIVER_NAME,
426 .pm = &imx2_wdt_pm_ops,
427 .of_match_table = imx2_wdt_dt_ids,
428 },
429};
430
431module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
432
433MODULE_AUTHOR("Wolfram Sang");
434MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
435MODULE_LICENSE("GPL v2");
436MODULE_ALIAS("platform:" DRIVER_NAME);