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1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38/*
39 * This file contains the functions to manage Queue Heads and Queue
40 * Transfer Descriptors for Host mode
41 */
42#include <linux/gcd.h>
43#include <linux/kernel.h>
44#include <linux/module.h>
45#include <linux/spinlock.h>
46#include <linux/interrupt.h>
47#include <linux/dma-mapping.h>
48#include <linux/io.h>
49#include <linux/slab.h>
50#include <linux/usb.h>
51
52#include <linux/usb/hcd.h>
53#include <linux/usb/ch11.h>
54
55#include "core.h"
56#include "hcd.h"
57
58/* Wait this long before releasing periodic reservation */
59#define DWC2_UNRESERVE_DELAY (msecs_to_jiffies(5))
60
61/* If we get a NAK, wait this long before retrying */
62#define DWC2_RETRY_WAIT_DELAY (msecs_to_jiffies(1))
63
64/**
65 * dwc2_periodic_channel_available() - Checks that a channel is available for a
66 * periodic transfer
67 *
68 * @hsotg: The HCD state structure for the DWC OTG controller
69 *
70 * Return: 0 if successful, negative error code otherwise
71 */
72static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg)
73{
74 /*
75 * Currently assuming that there is a dedicated host channel for
76 * each periodic transaction plus at least one host channel for
77 * non-periodic transactions
78 */
79 int status;
80 int num_channels;
81
82 num_channels = hsotg->params.host_channels;
83 if ((hsotg->periodic_channels + hsotg->non_periodic_channels <
84 num_channels) && (hsotg->periodic_channels < num_channels - 1)) {
85 status = 0;
86 } else {
87 dev_dbg(hsotg->dev,
88 "%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
89 __func__, num_channels,
90 hsotg->periodic_channels, hsotg->non_periodic_channels);
91 status = -ENOSPC;
92 }
93
94 return status;
95}
96
97/**
98 * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth
99 * for the specified QH in the periodic schedule
100 *
101 * @hsotg: The HCD state structure for the DWC OTG controller
102 * @qh: QH containing periodic bandwidth required
103 *
104 * Return: 0 if successful, negative error code otherwise
105 *
106 * For simplicity, this calculation assumes that all the transfers in the
107 * periodic schedule may occur in the same (micro)frame
108 */
109static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg,
110 struct dwc2_qh *qh)
111{
112 int status;
113 s16 max_claimed_usecs;
114
115 status = 0;
116
117 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
118 /*
119 * High speed mode
120 * Max periodic usecs is 80% x 125 usec = 100 usec
121 */
122 max_claimed_usecs = 100 - qh->host_us;
123 } else {
124 /*
125 * Full speed mode
126 * Max periodic usecs is 90% x 1000 usec = 900 usec
127 */
128 max_claimed_usecs = 900 - qh->host_us;
129 }
130
131 if (hsotg->periodic_usecs > max_claimed_usecs) {
132 dev_err(hsotg->dev,
133 "%s: already claimed usecs %d, required usecs %d\n",
134 __func__, hsotg->periodic_usecs, qh->host_us);
135 status = -ENOSPC;
136 }
137
138 return status;
139}
140
141/**
142 * pmap_schedule() - Schedule time in a periodic bitmap (pmap).
143 *
144 * @map: The bitmap representing the schedule; will be updated
145 * upon success.
146 * @bits_per_period: The schedule represents several periods. This is how many
147 * bits are in each period. It's assumed that the beginning
148 * of the schedule will repeat after its end.
149 * @periods_in_map: The number of periods in the schedule.
150 * @num_bits: The number of bits we need per period we want to reserve
151 * in this function call.
152 * @interval: How often we need to be scheduled for the reservation this
153 * time. 1 means every period. 2 means every other period.
154 * ...you get the picture?
155 * @start: The bit number to start at. Normally 0. Must be within
156 * the interval or we return failure right away.
157 * @only_one_period: Normally we'll allow picking a start anywhere within the
158 * first interval, since we can still make all repetition
159 * requirements by doing that. However, if you pass true
160 * here then we'll return failure if we can't fit within
161 * the period that "start" is in.
162 *
163 * The idea here is that we want to schedule time for repeating events that all
164 * want the same resource. The resource is divided into fixed-sized periods
165 * and the events want to repeat every "interval" periods. The schedule
166 * granularity is one bit.
167 *
168 * To keep things "simple", we'll represent our schedule with a bitmap that
169 * contains a fixed number of periods. This gets rid of a lot of complexity
170 * but does mean that we need to handle things specially (and non-ideally) if
171 * the number of the periods in the schedule doesn't match well with the
172 * intervals that we're trying to schedule.
173 *
174 * Here's an explanation of the scheme we'll implement, assuming 8 periods.
175 * - If interval is 1, we need to take up space in each of the 8
176 * periods we're scheduling. Easy.
177 * - If interval is 2, we need to take up space in half of the
178 * periods. Again, easy.
179 * - If interval is 3, we actually need to fall back to interval 1.
180 * Why? Because we might need time in any period. AKA for the
181 * first 8 periods, we'll be in slot 0, 3, 6. Then we'll be
182 * in slot 1, 4, 7. Then we'll be in 2, 5. Then we'll be back to
183 * 0, 3, and 6. Since we could be in any frame we need to reserve
184 * for all of them. Sucks, but that's what you gotta do. Note that
185 * if we were instead scheduling 8 * 3 = 24 we'd do much better, but
186 * then we need more memory and time to do scheduling.
187 * - If interval is 4, easy.
188 * - If interval is 5, we again need interval 1. The schedule will be
189 * 0, 5, 2, 7, 4, 1, 6, 3, 0
190 * - If interval is 6, we need interval 2. 0, 6, 4, 2.
191 * - If interval is 7, we need interval 1.
192 * - If interval is 8, we need interval 8.
193 *
194 * If you do the math, you'll see that we need to pretend that interval is
195 * equal to the greatest_common_divisor(interval, periods_in_map).
196 *
197 * Note that at the moment this function tends to front-pack the schedule.
198 * In some cases that's really non-ideal (it's hard to schedule things that
199 * need to repeat every period). In other cases it's perfect (you can easily
200 * schedule bigger, less often repeating things).
201 *
202 * Here's the algorithm in action (8 periods, 5 bits per period):
203 * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0
204 * |*****| ***|*****| ***|*****| ***|*****| ***| OK 3 bits, intv 3 at 2
205 * |*****|* ***|*****| ***|*****|* ***|*****| ***| OK 1 bits, intv 4 at 5
206 * |** |* |** | |** |* |** | | Remv 3 bits, intv 3 at 2
207 * |*** |* |*** | |*** |* |*** | | OK 1 bits, intv 6 at 2
208 * |**** |* * |**** | * |**** |* * |**** | * | OK 1 bits, intv 1 at 3
209 * |**** |**** |**** | *** |**** |**** |**** | *** | OK 2 bits, intv 2 at 6
210 * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 1 at 4
211 * |*****|*****|*****| ****|*****|*****|*****| ****| FAIL 1 bits, intv 1
212 * | ***|*****| ***| ****| ***|*****| ***| ****| Remv 2 bits, intv 2 at 0
213 * | ***| ****| ***| ****| ***| ****| ***| ****| Remv 1 bits, intv 4 at 5
214 * | **| ****| **| ****| **| ****| **| ****| Remv 1 bits, intv 6 at 2
215 * | *| ** *| *| ** *| *| ** *| *| ** *| Remv 1 bits, intv 1 at 3
216 * | *| *| *| *| *| *| *| *| Remv 2 bits, intv 2 at 6
217 * | | | | | | | | | Remv 1 bits, intv 1 at 4
218 * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0
219 * |*** | |** | |*** | |** | | OK 1 bits, intv 4 at 2
220 * |*****| |** **| |*****| |** **| | OK 2 bits, intv 2 at 3
221 * |*****|* |** **| |*****|* |** **| | OK 1 bits, intv 4 at 5
222 * |*****|*** |** **| ** |*****|*** |** **| ** | OK 2 bits, intv 2 at 6
223 * |*****|*****|** **| ****|*****|*****|** **| ****| OK 2 bits, intv 2 at 8
224 * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 4 at 12
225 *
226 * This function is pretty generic and could be easily abstracted if anything
227 * needed similar scheduling.
228 *
229 * Returns either -ENOSPC or a >= 0 start bit which should be passed to the
230 * unschedule routine. The map bitmap will be updated on a non-error result.
231 */
232static int pmap_schedule(unsigned long *map, int bits_per_period,
233 int periods_in_map, int num_bits,
234 int interval, int start, bool only_one_period)
235{
236 int interval_bits;
237 int to_reserve;
238 int first_end;
239 int i;
240
241 if (num_bits > bits_per_period)
242 return -ENOSPC;
243
244 /* Adjust interval as per description */
245 interval = gcd(interval, periods_in_map);
246
247 interval_bits = bits_per_period * interval;
248 to_reserve = periods_in_map / interval;
249
250 /* If start has gotten us past interval then we can't schedule */
251 if (start >= interval_bits)
252 return -ENOSPC;
253
254 if (only_one_period)
255 /* Must fit within same period as start; end at begin of next */
256 first_end = (start / bits_per_period + 1) * bits_per_period;
257 else
258 /* Can fit anywhere in the first interval */
259 first_end = interval_bits;
260
261 /*
262 * We'll try to pick the first repetition, then see if that time
263 * is free for each of the subsequent repetitions. If it's not
264 * we'll adjust the start time for the next search of the first
265 * repetition.
266 */
267 while (start + num_bits <= first_end) {
268 int end;
269
270 /* Need to stay within this period */
271 end = (start / bits_per_period + 1) * bits_per_period;
272
273 /* Look for num_bits us in this microframe starting at start */
274 start = bitmap_find_next_zero_area(map, end, start, num_bits,
275 0);
276
277 /*
278 * We should get start >= end if we fail. We might be
279 * able to check the next microframe depending on the
280 * interval, so continue on (start already updated).
281 */
282 if (start >= end) {
283 start = end;
284 continue;
285 }
286
287 /* At this point we have a valid point for first one */
288 for (i = 1; i < to_reserve; i++) {
289 int ith_start = start + interval_bits * i;
290 int ith_end = end + interval_bits * i;
291 int ret;
292
293 /* Use this as a dumb "check if bits are 0" */
294 ret = bitmap_find_next_zero_area(
295 map, ith_start + num_bits, ith_start, num_bits,
296 0);
297
298 /* We got the right place, continue checking */
299 if (ret == ith_start)
300 continue;
301
302 /* Move start up for next time and exit for loop */
303 ith_start = bitmap_find_next_zero_area(
304 map, ith_end, ith_start, num_bits, 0);
305 if (ith_start >= ith_end)
306 /* Need a while new period next time */
307 start = end;
308 else
309 start = ith_start - interval_bits * i;
310 break;
311 }
312
313 /* If didn't exit the for loop with a break, we have success */
314 if (i == to_reserve)
315 break;
316 }
317
318 if (start + num_bits > first_end)
319 return -ENOSPC;
320
321 for (i = 0; i < to_reserve; i++) {
322 int ith_start = start + interval_bits * i;
323
324 bitmap_set(map, ith_start, num_bits);
325 }
326
327 return start;
328}
329
330/**
331 * pmap_unschedule() - Undo work done by pmap_schedule()
332 *
333 * @map: See pmap_schedule().
334 * @bits_per_period: See pmap_schedule().
335 * @periods_in_map: See pmap_schedule().
336 * @num_bits: The number of bits that was passed to schedule.
337 * @interval: The interval that was passed to schedule.
338 * @start: The return value from pmap_schedule().
339 */
340static void pmap_unschedule(unsigned long *map, int bits_per_period,
341 int periods_in_map, int num_bits,
342 int interval, int start)
343{
344 int interval_bits;
345 int to_release;
346 int i;
347
348 /* Adjust interval as per description in pmap_schedule() */
349 interval = gcd(interval, periods_in_map);
350
351 interval_bits = bits_per_period * interval;
352 to_release = periods_in_map / interval;
353
354 for (i = 0; i < to_release; i++) {
355 int ith_start = start + interval_bits * i;
356
357 bitmap_clear(map, ith_start, num_bits);
358 }
359}
360
361/**
362 * dwc2_get_ls_map() - Get the map used for the given qh
363 *
364 * @hsotg: The HCD state structure for the DWC OTG controller.
365 * @qh: QH for the periodic transfer.
366 *
367 * We'll always get the periodic map out of our TT. Note that even if we're
368 * running the host straight in low speed / full speed mode it appears as if
369 * a TT is allocated for us, so we'll use it. If that ever changes we can
370 * add logic here to get a map out of "hsotg" if !qh->do_split.
371 *
372 * Returns: the map or NULL if a map couldn't be found.
373 */
374static unsigned long *dwc2_get_ls_map(struct dwc2_hsotg *hsotg,
375 struct dwc2_qh *qh)
376{
377 unsigned long *map;
378
379 /* Don't expect to be missing a TT and be doing low speed scheduling */
380 if (WARN_ON(!qh->dwc_tt))
381 return NULL;
382
383 /* Get the map and adjust if this is a multi_tt hub */
384 map = qh->dwc_tt->periodic_bitmaps;
385 if (qh->dwc_tt->usb_tt->multi)
386 map += DWC2_ELEMENTS_PER_LS_BITMAP * qh->ttport;
387
388 return map;
389}
390
391#ifdef DWC2_PRINT_SCHEDULE
392/*
393 * cat_printf() - A printf() + strcat() helper
394 *
395 * This is useful for concatenating a bunch of strings where each string is
396 * constructed using printf.
397 *
398 * @buf: The destination buffer; will be updated to point after the printed
399 * data.
400 * @size: The number of bytes in the buffer (includes space for '\0').
401 * @fmt: The format for printf.
402 * @...: The args for printf.
403 */
404static __printf(3, 4)
405void cat_printf(char **buf, size_t *size, const char *fmt, ...)
406{
407 va_list args;
408 int i;
409
410 if (*size == 0)
411 return;
412
413 va_start(args, fmt);
414 i = vsnprintf(*buf, *size, fmt, args);
415 va_end(args);
416
417 if (i >= *size) {
418 (*buf)[*size - 1] = '\0';
419 *buf += *size;
420 *size = 0;
421 } else {
422 *buf += i;
423 *size -= i;
424 }
425}
426
427/*
428 * pmap_print() - Print the given periodic map
429 *
430 * Will attempt to print out the periodic schedule.
431 *
432 * @map: See pmap_schedule().
433 * @bits_per_period: See pmap_schedule().
434 * @periods_in_map: See pmap_schedule().
435 * @period_name: The name of 1 period, like "uFrame"
436 * @units: The name of the units, like "us".
437 * @print_fn: The function to call for printing.
438 * @print_data: Opaque data to pass to the print function.
439 */
440static void pmap_print(unsigned long *map, int bits_per_period,
441 int periods_in_map, const char *period_name,
442 const char *units,
443 void (*print_fn)(const char *str, void *data),
444 void *print_data)
445{
446 int period;
447
448 for (period = 0; period < periods_in_map; period++) {
449 char tmp[64];
450 char *buf = tmp;
451 size_t buf_size = sizeof(tmp);
452 int period_start = period * bits_per_period;
453 int period_end = period_start + bits_per_period;
454 int start = 0;
455 int count = 0;
456 bool printed = false;
457 int i;
458
459 for (i = period_start; i < period_end + 1; i++) {
460 /* Handle case when ith bit is set */
461 if (i < period_end &&
462 bitmap_find_next_zero_area(map, i + 1,
463 i, 1, 0) != i) {
464 if (count == 0)
465 start = i - period_start;
466 count++;
467 continue;
468 }
469
470 /* ith bit isn't set; don't care if count == 0 */
471 if (count == 0)
472 continue;
473
474 if (!printed)
475 cat_printf(&buf, &buf_size, "%s %d: ",
476 period_name, period);
477 else
478 cat_printf(&buf, &buf_size, ", ");
479 printed = true;
480
481 cat_printf(&buf, &buf_size, "%d %s -%3d %s", start,
482 units, start + count - 1, units);
483 count = 0;
484 }
485
486 if (printed)
487 print_fn(tmp, print_data);
488 }
489}
490
491struct dwc2_qh_print_data {
492 struct dwc2_hsotg *hsotg;
493 struct dwc2_qh *qh;
494};
495
496/**
497 * dwc2_qh_print() - Helper function for dwc2_qh_schedule_print()
498 *
499 * @str: The string to print
500 * @data: A pointer to a struct dwc2_qh_print_data
501 */
502static void dwc2_qh_print(const char *str, void *data)
503{
504 struct dwc2_qh_print_data *print_data = data;
505
506 dwc2_sch_dbg(print_data->hsotg, "QH=%p ...%s\n", print_data->qh, str);
507}
508
509/**
510 * dwc2_qh_schedule_print() - Print the periodic schedule
511 *
512 * @hsotg: The HCD state structure for the DWC OTG controller.
513 * @qh: QH to print.
514 */
515static void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg,
516 struct dwc2_qh *qh)
517{
518 struct dwc2_qh_print_data print_data = { hsotg, qh };
519 int i;
520
521 /*
522 * The printing functions are quite slow and inefficient.
523 * If we don't have tracing turned on, don't run unless the special
524 * define is turned on.
525 */
526
527 if (qh->schedule_low_speed) {
528 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
529
530 dwc2_sch_dbg(hsotg, "QH=%p LS/FS trans: %d=>%d us @ %d us",
531 qh, qh->device_us,
532 DWC2_ROUND_US_TO_SLICE(qh->device_us),
533 DWC2_US_PER_SLICE * qh->ls_start_schedule_slice);
534
535 if (map) {
536 dwc2_sch_dbg(hsotg,
537 "QH=%p Whole low/full speed map %p now:\n",
538 qh, map);
539 pmap_print(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
540 DWC2_LS_SCHEDULE_FRAMES, "Frame ", "slices",
541 dwc2_qh_print, &print_data);
542 }
543 }
544
545 for (i = 0; i < qh->num_hs_transfers; i++) {
546 struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + i;
547 int uframe = trans_time->start_schedule_us /
548 DWC2_HS_PERIODIC_US_PER_UFRAME;
549 int rel_us = trans_time->start_schedule_us %
550 DWC2_HS_PERIODIC_US_PER_UFRAME;
551
552 dwc2_sch_dbg(hsotg,
553 "QH=%p HS trans #%d: %d us @ uFrame %d + %d us\n",
554 qh, i, trans_time->duration_us, uframe, rel_us);
555 }
556 if (qh->num_hs_transfers) {
557 dwc2_sch_dbg(hsotg, "QH=%p Whole high speed map now:\n", qh);
558 pmap_print(hsotg->hs_periodic_bitmap,
559 DWC2_HS_PERIODIC_US_PER_UFRAME,
560 DWC2_HS_SCHEDULE_UFRAMES, "uFrame", "us",
561 dwc2_qh_print, &print_data);
562 }
563}
564#else
565static inline void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg,
566 struct dwc2_qh *qh) {};
567#endif
568
569/**
570 * dwc2_ls_pmap_schedule() - Schedule a low speed QH
571 *
572 * @hsotg: The HCD state structure for the DWC OTG controller.
573 * @qh: QH for the periodic transfer.
574 * @search_slice: We'll start trying to schedule at the passed slice.
575 * Remember that slices are the units of the low speed
576 * schedule (think 25us or so).
577 *
578 * Wraps pmap_schedule() with the right parameters for low speed scheduling.
579 *
580 * Normally we schedule low speed devices on the map associated with the TT.
581 *
582 * Returns: 0 for success or an error code.
583 */
584static int dwc2_ls_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
585 int search_slice)
586{
587 int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE);
588 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
589 int slice;
590
591 if (!map)
592 return -EINVAL;
593
594 /*
595 * Schedule on the proper low speed map with our low speed scheduling
596 * parameters. Note that we use the "device_interval" here since
597 * we want the low speed interval and the only way we'd be in this
598 * function is if the device is low speed.
599 *
600 * If we happen to be doing low speed and high speed scheduling for the
601 * same transaction (AKA we have a split) we always do low speed first.
602 * That means we can always pass "false" for only_one_period (that
603 * parameters is only useful when we're trying to get one schedule to
604 * match what we already planned in the other schedule).
605 */
606 slice = pmap_schedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
607 DWC2_LS_SCHEDULE_FRAMES, slices,
608 qh->device_interval, search_slice, false);
609
610 if (slice < 0)
611 return slice;
612
613 qh->ls_start_schedule_slice = slice;
614 return 0;
615}
616
617/**
618 * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_ls_pmap_schedule()
619 *
620 * @hsotg: The HCD state structure for the DWC OTG controller.
621 * @qh: QH for the periodic transfer.
622 */
623static void dwc2_ls_pmap_unschedule(struct dwc2_hsotg *hsotg,
624 struct dwc2_qh *qh)
625{
626 int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE);
627 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
628
629 /* Schedule should have failed, so no worries about no error code */
630 if (!map)
631 return;
632
633 pmap_unschedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
634 DWC2_LS_SCHEDULE_FRAMES, slices, qh->device_interval,
635 qh->ls_start_schedule_slice);
636}
637
638/**
639 * dwc2_hs_pmap_schedule - Schedule in the main high speed schedule
640 *
641 * This will schedule something on the main dwc2 schedule.
642 *
643 * We'll start looking in qh->hs_transfers[index].start_schedule_us. We'll
644 * update this with the result upon success. We also use the duration from
645 * the same structure.
646 *
647 * @hsotg: The HCD state structure for the DWC OTG controller.
648 * @qh: QH for the periodic transfer.
649 * @only_one_period: If true we will limit ourselves to just looking at
650 * one period (aka one 100us chunk). This is used if we have
651 * already scheduled something on the low speed schedule and
652 * need to find something that matches on the high speed one.
653 * @index: The index into qh->hs_transfers that we're working with.
654 *
655 * Returns: 0 for success or an error code. Upon success the
656 * dwc2_hs_transfer_time specified by "index" will be updated.
657 */
658static int dwc2_hs_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
659 bool only_one_period, int index)
660{
661 struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index;
662 int us;
663
664 us = pmap_schedule(hsotg->hs_periodic_bitmap,
665 DWC2_HS_PERIODIC_US_PER_UFRAME,
666 DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us,
667 qh->host_interval, trans_time->start_schedule_us,
668 only_one_period);
669
670 if (us < 0)
671 return us;
672
673 trans_time->start_schedule_us = us;
674 return 0;
675}
676
677/**
678 * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_hs_pmap_schedule()
679 *
680 * @hsotg: The HCD state structure for the DWC OTG controller.
681 * @qh: QH for the periodic transfer.
682 */
683static void dwc2_hs_pmap_unschedule(struct dwc2_hsotg *hsotg,
684 struct dwc2_qh *qh, int index)
685{
686 struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index;
687
688 pmap_unschedule(hsotg->hs_periodic_bitmap,
689 DWC2_HS_PERIODIC_US_PER_UFRAME,
690 DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us,
691 qh->host_interval, trans_time->start_schedule_us);
692}
693
694/**
695 * dwc2_uframe_schedule_split - Schedule a QH for a periodic split xfer.
696 *
697 * This is the most complicated thing in USB. We have to find matching time
698 * in both the global high speed schedule for the port and the low speed
699 * schedule for the TT associated with the given device.
700 *
701 * Being here means that the host must be running in high speed mode and the
702 * device is in low or full speed mode (and behind a hub).
703 *
704 * @hsotg: The HCD state structure for the DWC OTG controller.
705 * @qh: QH for the periodic transfer.
706 */
707static int dwc2_uframe_schedule_split(struct dwc2_hsotg *hsotg,
708 struct dwc2_qh *qh)
709{
710 int bytecount = dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp);
711 int ls_search_slice;
712 int err = 0;
713 int host_interval_in_sched;
714
715 /*
716 * The interval (how often to repeat) in the actual host schedule.
717 * See pmap_schedule() for gcd() explanation.
718 */
719 host_interval_in_sched = gcd(qh->host_interval,
720 DWC2_HS_SCHEDULE_UFRAMES);
721
722 /*
723 * We always try to find space in the low speed schedule first, then
724 * try to find high speed time that matches. If we don't, we'll bump
725 * up the place we start searching in the low speed schedule and try
726 * again. To start we'll look right at the beginning of the low speed
727 * schedule.
728 *
729 * Note that this will tend to front-load the high speed schedule.
730 * We may eventually want to try to avoid this by either considering
731 * both schedules together or doing some sort of round robin.
732 */
733 ls_search_slice = 0;
734
735 while (ls_search_slice < DWC2_LS_SCHEDULE_SLICES) {
736 int start_s_uframe;
737 int ssplit_s_uframe;
738 int second_s_uframe;
739 int rel_uframe;
740 int first_count;
741 int middle_count;
742 int end_count;
743 int first_data_bytes;
744 int other_data_bytes;
745 int i;
746
747 if (qh->schedule_low_speed) {
748 err = dwc2_ls_pmap_schedule(hsotg, qh, ls_search_slice);
749
750 /*
751 * If we got an error here there's no other magic we
752 * can do, so bail. All the looping above is only
753 * helpful to redo things if we got a low speed slot
754 * and then couldn't find a matching high speed slot.
755 */
756 if (err)
757 return err;
758 } else {
759 /* Must be missing the tt structure? Why? */
760 WARN_ON_ONCE(1);
761 }
762
763 /*
764 * This will give us a number 0 - 7 if
765 * DWC2_LS_SCHEDULE_FRAMES == 1, or 0 - 15 if == 2, or ...
766 */
767 start_s_uframe = qh->ls_start_schedule_slice /
768 DWC2_SLICES_PER_UFRAME;
769
770 /* Get a number that's always 0 - 7 */
771 rel_uframe = (start_s_uframe % 8);
772
773 /*
774 * If we were going to start in uframe 7 then we would need to
775 * issue a start split in uframe 6, which spec says is not OK.
776 * Move on to the next full frame (assuming there is one).
777 *
778 * See 11.18.4 Host Split Transaction Scheduling Requirements
779 * bullet 1.
780 */
781 if (rel_uframe == 7) {
782 if (qh->schedule_low_speed)
783 dwc2_ls_pmap_unschedule(hsotg, qh);
784 ls_search_slice =
785 (qh->ls_start_schedule_slice /
786 DWC2_LS_PERIODIC_SLICES_PER_FRAME + 1) *
787 DWC2_LS_PERIODIC_SLICES_PER_FRAME;
788 continue;
789 }
790
791 /*
792 * For ISOC in:
793 * - start split (frame -1)
794 * - complete split w/ data (frame +1)
795 * - complete split w/ data (frame +2)
796 * - ...
797 * - complete split w/ data (frame +num_data_packets)
798 * - complete split w/ data (frame +num_data_packets+1)
799 * - complete split w/ data (frame +num_data_packets+2, max 8)
800 * ...though if frame was "0" then max is 7...
801 *
802 * For ISOC out we might need to do:
803 * - start split w/ data (frame -1)
804 * - start split w/ data (frame +0)
805 * - ...
806 * - start split w/ data (frame +num_data_packets-2)
807 *
808 * For INTERRUPT in we might need to do:
809 * - start split (frame -1)
810 * - complete split w/ data (frame +1)
811 * - complete split w/ data (frame +2)
812 * - complete split w/ data (frame +3, max 8)
813 *
814 * For INTERRUPT out we might need to do:
815 * - start split w/ data (frame -1)
816 * - complete split (frame +1)
817 * - complete split (frame +2)
818 * - complete split (frame +3, max 8)
819 *
820 * Start adjusting!
821 */
822 ssplit_s_uframe = (start_s_uframe +
823 host_interval_in_sched - 1) %
824 host_interval_in_sched;
825 if (qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in)
826 second_s_uframe = start_s_uframe;
827 else
828 second_s_uframe = start_s_uframe + 1;
829
830 /* First data transfer might not be all 188 bytes. */
831 first_data_bytes = 188 -
832 DIV_ROUND_UP(188 * (qh->ls_start_schedule_slice %
833 DWC2_SLICES_PER_UFRAME),
834 DWC2_SLICES_PER_UFRAME);
835 if (first_data_bytes > bytecount)
836 first_data_bytes = bytecount;
837 other_data_bytes = bytecount - first_data_bytes;
838
839 /*
840 * For now, skip OUT xfers where first xfer is partial
841 *
842 * Main dwc2 code assumes:
843 * - INT transfers never get split in two.
844 * - ISOC transfers can always transfer 188 bytes the first
845 * time.
846 *
847 * Until that code is fixed, try again if the first transfer
848 * couldn't transfer everything.
849 *
850 * This code can be removed if/when the rest of dwc2 handles
851 * the above cases. Until it's fixed we just won't be able
852 * to schedule quite as tightly.
853 */
854 if (!qh->ep_is_in &&
855 (first_data_bytes != min_t(int, 188, bytecount))) {
856 dwc2_sch_dbg(hsotg,
857 "QH=%p avoiding broken 1st xfer (%d, %d)\n",
858 qh, first_data_bytes, bytecount);
859 if (qh->schedule_low_speed)
860 dwc2_ls_pmap_unschedule(hsotg, qh);
861 ls_search_slice = (start_s_uframe + 1) *
862 DWC2_SLICES_PER_UFRAME;
863 continue;
864 }
865
866 /* Start by assuming transfers for the bytes */
867 qh->num_hs_transfers = 1 + DIV_ROUND_UP(other_data_bytes, 188);
868
869 /*
870 * Everything except ISOC OUT has extra transfers. Rules are
871 * complicated. See 11.18.4 Host Split Transaction Scheduling
872 * Requirements bullet 3.
873 */
874 if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
875 if (rel_uframe == 6)
876 qh->num_hs_transfers += 2;
877 else
878 qh->num_hs_transfers += 3;
879
880 if (qh->ep_is_in) {
881 /*
882 * First is start split, middle/end is data.
883 * Allocate full data bytes for all data.
884 */
885 first_count = 4;
886 middle_count = bytecount;
887 end_count = bytecount;
888 } else {
889 /*
890 * First is data, middle/end is complete.
891 * First transfer and second can have data.
892 * Rest should just have complete split.
893 */
894 first_count = first_data_bytes;
895 middle_count = max_t(int, 4, other_data_bytes);
896 end_count = 4;
897 }
898 } else {
899 if (qh->ep_is_in) {
900 int last;
901
902 /* Account for the start split */
903 qh->num_hs_transfers++;
904
905 /* Calculate "L" value from spec */
906 last = rel_uframe + qh->num_hs_transfers + 1;
907
908 /* Start with basic case */
909 if (last <= 6)
910 qh->num_hs_transfers += 2;
911 else
912 qh->num_hs_transfers += 1;
913
914 /* Adjust downwards */
915 if (last >= 6 && rel_uframe == 0)
916 qh->num_hs_transfers--;
917
918 /* 1st = start; rest can contain data */
919 first_count = 4;
920 middle_count = min_t(int, 188, bytecount);
921 end_count = middle_count;
922 } else {
923 /* All contain data, last might be smaller */
924 first_count = first_data_bytes;
925 middle_count = min_t(int, 188,
926 other_data_bytes);
927 end_count = other_data_bytes % 188;
928 }
929 }
930
931 /* Assign durations per uFrame */
932 qh->hs_transfers[0].duration_us = HS_USECS_ISO(first_count);
933 for (i = 1; i < qh->num_hs_transfers - 1; i++)
934 qh->hs_transfers[i].duration_us =
935 HS_USECS_ISO(middle_count);
936 if (qh->num_hs_transfers > 1)
937 qh->hs_transfers[qh->num_hs_transfers - 1].duration_us =
938 HS_USECS_ISO(end_count);
939
940 /*
941 * Assign start us. The call below to dwc2_hs_pmap_schedule()
942 * will start with these numbers but may adjust within the same
943 * microframe.
944 */
945 qh->hs_transfers[0].start_schedule_us =
946 ssplit_s_uframe * DWC2_HS_PERIODIC_US_PER_UFRAME;
947 for (i = 1; i < qh->num_hs_transfers; i++)
948 qh->hs_transfers[i].start_schedule_us =
949 ((second_s_uframe + i - 1) %
950 DWC2_HS_SCHEDULE_UFRAMES) *
951 DWC2_HS_PERIODIC_US_PER_UFRAME;
952
953 /* Try to schedule with filled in hs_transfers above */
954 for (i = 0; i < qh->num_hs_transfers; i++) {
955 err = dwc2_hs_pmap_schedule(hsotg, qh, true, i);
956 if (err)
957 break;
958 }
959
960 /* If we scheduled all w/out breaking out then we're all good */
961 if (i == qh->num_hs_transfers)
962 break;
963
964 for (; i >= 0; i--)
965 dwc2_hs_pmap_unschedule(hsotg, qh, i);
966
967 if (qh->schedule_low_speed)
968 dwc2_ls_pmap_unschedule(hsotg, qh);
969
970 /* Try again starting in the next microframe */
971 ls_search_slice = (start_s_uframe + 1) * DWC2_SLICES_PER_UFRAME;
972 }
973
974 if (ls_search_slice >= DWC2_LS_SCHEDULE_SLICES)
975 return -ENOSPC;
976
977 return 0;
978}
979
980/**
981 * dwc2_uframe_schedule_hs - Schedule a QH for a periodic high speed xfer.
982 *
983 * Basically this just wraps dwc2_hs_pmap_schedule() to provide a clean
984 * interface.
985 *
986 * @hsotg: The HCD state structure for the DWC OTG controller.
987 * @qh: QH for the periodic transfer.
988 */
989static int dwc2_uframe_schedule_hs(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
990{
991 /* In non-split host and device time are the same */
992 WARN_ON(qh->host_us != qh->device_us);
993 WARN_ON(qh->host_interval != qh->device_interval);
994 WARN_ON(qh->num_hs_transfers != 1);
995
996 /* We'll have one transfer; init start to 0 before calling scheduler */
997 qh->hs_transfers[0].start_schedule_us = 0;
998 qh->hs_transfers[0].duration_us = qh->host_us;
999
1000 return dwc2_hs_pmap_schedule(hsotg, qh, false, 0);
1001}
1002
1003/**
1004 * dwc2_uframe_schedule_ls - Schedule a QH for a periodic low/full speed xfer.
1005 *
1006 * Basically this just wraps dwc2_ls_pmap_schedule() to provide a clean
1007 * interface.
1008 *
1009 * @hsotg: The HCD state structure for the DWC OTG controller.
1010 * @qh: QH for the periodic transfer.
1011 */
1012static int dwc2_uframe_schedule_ls(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1013{
1014 /* In non-split host and device time are the same */
1015 WARN_ON(qh->host_us != qh->device_us);
1016 WARN_ON(qh->host_interval != qh->device_interval);
1017 WARN_ON(!qh->schedule_low_speed);
1018
1019 /* Run on the main low speed schedule (no split = no hub = no TT) */
1020 return dwc2_ls_pmap_schedule(hsotg, qh, 0);
1021}
1022
1023/**
1024 * dwc2_uframe_schedule - Schedule a QH for a periodic xfer.
1025 *
1026 * Calls one of the 3 sub-function depending on what type of transfer this QH
1027 * is for. Also adds some printing.
1028 *
1029 * @hsotg: The HCD state structure for the DWC OTG controller.
1030 * @qh: QH for the periodic transfer.
1031 */
1032static int dwc2_uframe_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1033{
1034 int ret;
1035
1036 if (qh->dev_speed == USB_SPEED_HIGH)
1037 ret = dwc2_uframe_schedule_hs(hsotg, qh);
1038 else if (!qh->do_split)
1039 ret = dwc2_uframe_schedule_ls(hsotg, qh);
1040 else
1041 ret = dwc2_uframe_schedule_split(hsotg, qh);
1042
1043 if (ret)
1044 dwc2_sch_dbg(hsotg, "QH=%p Failed to schedule %d\n", qh, ret);
1045 else
1046 dwc2_qh_schedule_print(hsotg, qh);
1047
1048 return ret;
1049}
1050
1051/**
1052 * dwc2_uframe_unschedule - Undoes dwc2_uframe_schedule().
1053 *
1054 * @hsotg: The HCD state structure for the DWC OTG controller.
1055 * @qh: QH for the periodic transfer.
1056 */
1057static void dwc2_uframe_unschedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1058{
1059 int i;
1060
1061 for (i = 0; i < qh->num_hs_transfers; i++)
1062 dwc2_hs_pmap_unschedule(hsotg, qh, i);
1063
1064 if (qh->schedule_low_speed)
1065 dwc2_ls_pmap_unschedule(hsotg, qh);
1066
1067 dwc2_sch_dbg(hsotg, "QH=%p Unscheduled\n", qh);
1068}
1069
1070/**
1071 * dwc2_pick_first_frame() - Choose 1st frame for qh that's already scheduled
1072 *
1073 * Takes a qh that has already been scheduled (which means we know we have the
1074 * bandwdith reserved for us) and set the next_active_frame and the
1075 * start_active_frame.
1076 *
1077 * This is expected to be called on qh's that weren't previously actively
1078 * running. It just picks the next frame that we can fit into without any
1079 * thought about the past.
1080 *
1081 * @hsotg: The HCD state structure for the DWC OTG controller
1082 * @qh: QH for a periodic endpoint
1083 *
1084 */
1085static void dwc2_pick_first_frame(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1086{
1087 u16 frame_number;
1088 u16 earliest_frame;
1089 u16 next_active_frame;
1090 u16 relative_frame;
1091 u16 interval;
1092
1093 /*
1094 * Use the real frame number rather than the cached value as of the
1095 * last SOF to give us a little extra slop.
1096 */
1097 frame_number = dwc2_hcd_get_frame_number(hsotg);
1098
1099 /*
1100 * We wouldn't want to start any earlier than the next frame just in
1101 * case the frame number ticks as we're doing this calculation.
1102 *
1103 * NOTE: if we could quantify how long till we actually get scheduled
1104 * we might be able to avoid the "+ 1" by looking at the upper part of
1105 * HFNUM (the FRREM field). For now we'll just use the + 1 though.
1106 */
1107 earliest_frame = dwc2_frame_num_inc(frame_number, 1);
1108 next_active_frame = earliest_frame;
1109
1110 /* Get the "no microframe schduler" out of the way... */
1111 if (!hsotg->params.uframe_sched) {
1112 if (qh->do_split)
1113 /* Splits are active at microframe 0 minus 1 */
1114 next_active_frame |= 0x7;
1115 goto exit;
1116 }
1117
1118 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
1119 /*
1120 * We're either at high speed or we're doing a split (which
1121 * means we're talking high speed to a hub). In any case
1122 * the first frame should be based on when the first scheduled
1123 * event is.
1124 */
1125 WARN_ON(qh->num_hs_transfers < 1);
1126
1127 relative_frame = qh->hs_transfers[0].start_schedule_us /
1128 DWC2_HS_PERIODIC_US_PER_UFRAME;
1129
1130 /* Adjust interval as per high speed schedule */
1131 interval = gcd(qh->host_interval, DWC2_HS_SCHEDULE_UFRAMES);
1132
1133 } else {
1134 /*
1135 * Low or full speed directly on dwc2. Just about the same
1136 * as high speed but on a different schedule and with slightly
1137 * different adjustments. Note that this works because when
1138 * the host and device are both low speed then frames in the
1139 * controller tick at low speed.
1140 */
1141 relative_frame = qh->ls_start_schedule_slice /
1142 DWC2_LS_PERIODIC_SLICES_PER_FRAME;
1143 interval = gcd(qh->host_interval, DWC2_LS_SCHEDULE_FRAMES);
1144 }
1145
1146 /* Scheduler messed up if frame is past interval */
1147 WARN_ON(relative_frame >= interval);
1148
1149 /*
1150 * We know interval must divide (HFNUM_MAX_FRNUM + 1) now that we've
1151 * done the gcd(), so it's safe to move to the beginning of the current
1152 * interval like this.
1153 *
1154 * After this we might be before earliest_frame, but don't worry,
1155 * we'll fix it...
1156 */
1157 next_active_frame = (next_active_frame / interval) * interval;
1158
1159 /*
1160 * Actually choose to start at the frame number we've been
1161 * scheduled for.
1162 */
1163 next_active_frame = dwc2_frame_num_inc(next_active_frame,
1164 relative_frame);
1165
1166 /*
1167 * We actually need 1 frame before since the next_active_frame is
1168 * the frame number we'll be put on the ready list and we won't be on
1169 * the bus until 1 frame later.
1170 */
1171 next_active_frame = dwc2_frame_num_dec(next_active_frame, 1);
1172
1173 /*
1174 * By now we might actually be before the earliest_frame. Let's move
1175 * up intervals until we're not.
1176 */
1177 while (dwc2_frame_num_gt(earliest_frame, next_active_frame))
1178 next_active_frame = dwc2_frame_num_inc(next_active_frame,
1179 interval);
1180
1181exit:
1182 qh->next_active_frame = next_active_frame;
1183 qh->start_active_frame = next_active_frame;
1184
1185 dwc2_sch_vdbg(hsotg, "QH=%p First fn=%04x nxt=%04x\n",
1186 qh, frame_number, qh->next_active_frame);
1187}
1188
1189/**
1190 * dwc2_do_reserve() - Make a periodic reservation
1191 *
1192 * Try to allocate space in the periodic schedule. Depending on parameters
1193 * this might use the microframe scheduler or the dumb scheduler.
1194 *
1195 * @hsotg: The HCD state structure for the DWC OTG controller
1196 * @qh: QH for the periodic transfer.
1197 *
1198 * Returns: 0 upon success; error upon failure.
1199 */
1200static int dwc2_do_reserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1201{
1202 int status;
1203
1204 if (hsotg->params.uframe_sched) {
1205 status = dwc2_uframe_schedule(hsotg, qh);
1206 } else {
1207 status = dwc2_periodic_channel_available(hsotg);
1208 if (status) {
1209 dev_info(hsotg->dev,
1210 "%s: No host channel available for periodic transfer\n",
1211 __func__);
1212 return status;
1213 }
1214
1215 status = dwc2_check_periodic_bandwidth(hsotg, qh);
1216 }
1217
1218 if (status) {
1219 dev_dbg(hsotg->dev,
1220 "%s: Insufficient periodic bandwidth for periodic transfer\n",
1221 __func__);
1222 return status;
1223 }
1224
1225 if (!hsotg->params.uframe_sched)
1226 /* Reserve periodic channel */
1227 hsotg->periodic_channels++;
1228
1229 /* Update claimed usecs per (micro)frame */
1230 hsotg->periodic_usecs += qh->host_us;
1231
1232 dwc2_pick_first_frame(hsotg, qh);
1233
1234 return 0;
1235}
1236
1237/**
1238 * dwc2_do_unreserve() - Actually release the periodic reservation
1239 *
1240 * This function actually releases the periodic bandwidth that was reserved
1241 * by the given qh.
1242 *
1243 * @hsotg: The HCD state structure for the DWC OTG controller
1244 * @qh: QH for the periodic transfer.
1245 */
1246static void dwc2_do_unreserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1247{
1248 assert_spin_locked(&hsotg->lock);
1249
1250 WARN_ON(!qh->unreserve_pending);
1251
1252 /* No more unreserve pending--we're doing it */
1253 qh->unreserve_pending = false;
1254
1255 if (WARN_ON(!list_empty(&qh->qh_list_entry)))
1256 list_del_init(&qh->qh_list_entry);
1257
1258 /* Update claimed usecs per (micro)frame */
1259 hsotg->periodic_usecs -= qh->host_us;
1260
1261 if (hsotg->params.uframe_sched) {
1262 dwc2_uframe_unschedule(hsotg, qh);
1263 } else {
1264 /* Release periodic channel reservation */
1265 hsotg->periodic_channels--;
1266 }
1267}
1268
1269/**
1270 * dwc2_unreserve_timer_fn() - Timer function to release periodic reservation
1271 *
1272 * According to the kernel doc for usb_submit_urb() (specifically the part about
1273 * "Reserved Bandwidth Transfers"), we need to keep a reservation active as
1274 * long as a device driver keeps submitting. Since we're using HCD_BH to give
1275 * back the URB we need to give the driver a little bit of time before we
1276 * release the reservation. This worker is called after the appropriate
1277 * delay.
1278 *
1279 * @work: Pointer to a qh unreserve_work.
1280 */
1281static void dwc2_unreserve_timer_fn(struct timer_list *t)
1282{
1283 struct dwc2_qh *qh = from_timer(qh, t, unreserve_timer);
1284 struct dwc2_hsotg *hsotg = qh->hsotg;
1285 unsigned long flags;
1286
1287 /*
1288 * Wait for the lock, or for us to be scheduled again. We
1289 * could be scheduled again if:
1290 * - We started executing but didn't get the lock yet.
1291 * - A new reservation came in, but cancel didn't take effect
1292 * because we already started executing.
1293 * - The timer has been kicked again.
1294 * In that case cancel and wait for the next call.
1295 */
1296 while (!spin_trylock_irqsave(&hsotg->lock, flags)) {
1297 if (timer_pending(&qh->unreserve_timer))
1298 return;
1299 }
1300
1301 /*
1302 * Might be no more unreserve pending if:
1303 * - We started executing but didn't get the lock yet.
1304 * - A new reservation came in, but cancel didn't take effect
1305 * because we already started executing.
1306 *
1307 * We can't put this in the loop above because unreserve_pending needs
1308 * to be accessed under lock, so we can only check it once we got the
1309 * lock.
1310 */
1311 if (qh->unreserve_pending)
1312 dwc2_do_unreserve(hsotg, qh);
1313
1314 spin_unlock_irqrestore(&hsotg->lock, flags);
1315}
1316
1317/**
1318 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a
1319 * host channel is large enough to handle the maximum data transfer in a single
1320 * (micro)frame for a periodic transfer
1321 *
1322 * @hsotg: The HCD state structure for the DWC OTG controller
1323 * @qh: QH for a periodic endpoint
1324 *
1325 * Return: 0 if successful, negative error code otherwise
1326 */
1327static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg,
1328 struct dwc2_qh *qh)
1329{
1330 u32 max_xfer_size;
1331 u32 max_channel_xfer_size;
1332 int status = 0;
1333
1334 max_xfer_size = dwc2_max_packet(qh->maxp) * dwc2_hb_mult(qh->maxp);
1335 max_channel_xfer_size = hsotg->params.max_transfer_size;
1336
1337 if (max_xfer_size > max_channel_xfer_size) {
1338 dev_err(hsotg->dev,
1339 "%s: Periodic xfer length %d > max xfer length for channel %d\n",
1340 __func__, max_xfer_size, max_channel_xfer_size);
1341 status = -ENOSPC;
1342 }
1343
1344 return status;
1345}
1346
1347/**
1348 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in
1349 * the periodic schedule
1350 *
1351 * @hsotg: The HCD state structure for the DWC OTG controller
1352 * @qh: QH for the periodic transfer. The QH should already contain the
1353 * scheduling information.
1354 *
1355 * Return: 0 if successful, negative error code otherwise
1356 */
1357static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1358{
1359 int status;
1360
1361 status = dwc2_check_max_xfer_size(hsotg, qh);
1362 if (status) {
1363 dev_dbg(hsotg->dev,
1364 "%s: Channel max transfer size too small for periodic transfer\n",
1365 __func__);
1366 return status;
1367 }
1368
1369 /* Cancel pending unreserve; if canceled OK, unreserve was pending */
1370 if (del_timer(&qh->unreserve_timer))
1371 WARN_ON(!qh->unreserve_pending);
1372
1373 /*
1374 * Only need to reserve if there's not an unreserve pending, since if an
1375 * unreserve is pending then by definition our old reservation is still
1376 * valid. Unreserve might still be pending even if we didn't cancel if
1377 * dwc2_unreserve_timer_fn() already started. Code in the timer handles
1378 * that case.
1379 */
1380 if (!qh->unreserve_pending) {
1381 status = dwc2_do_reserve(hsotg, qh);
1382 if (status)
1383 return status;
1384 } else {
1385 /*
1386 * It might have been a while, so make sure that frame_number
1387 * is still good. Note: we could also try to use the similar
1388 * dwc2_next_periodic_start() but that schedules much more
1389 * tightly and we might need to hurry and queue things up.
1390 */
1391 if (dwc2_frame_num_le(qh->next_active_frame,
1392 hsotg->frame_number))
1393 dwc2_pick_first_frame(hsotg, qh);
1394 }
1395
1396 qh->unreserve_pending = 0;
1397
1398 if (hsotg->params.dma_desc_enable)
1399 /* Don't rely on SOF and start in ready schedule */
1400 list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
1401 else
1402 /* Always start in inactive schedule */
1403 list_add_tail(&qh->qh_list_entry,
1404 &hsotg->periodic_sched_inactive);
1405
1406 return 0;
1407}
1408
1409/**
1410 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer
1411 * from the periodic schedule
1412 *
1413 * @hsotg: The HCD state structure for the DWC OTG controller
1414 * @qh: QH for the periodic transfer
1415 */
1416static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg,
1417 struct dwc2_qh *qh)
1418{
1419 bool did_modify;
1420
1421 assert_spin_locked(&hsotg->lock);
1422
1423 /*
1424 * Schedule the unreserve to happen in a little bit. Cases here:
1425 * - Unreserve worker might be sitting there waiting to grab the lock.
1426 * In this case it will notice it's been schedule again and will
1427 * quit.
1428 * - Unreserve worker might not be scheduled.
1429 *
1430 * We should never already be scheduled since dwc2_schedule_periodic()
1431 * should have canceled the scheduled unreserve timer (hence the
1432 * warning on did_modify).
1433 *
1434 * We add + 1 to the timer to guarantee that at least 1 jiffy has
1435 * passed (otherwise if the jiffy counter might tick right after we
1436 * read it and we'll get no delay).
1437 */
1438 did_modify = mod_timer(&qh->unreserve_timer,
1439 jiffies + DWC2_UNRESERVE_DELAY + 1);
1440 WARN_ON(did_modify);
1441 qh->unreserve_pending = 1;
1442
1443 list_del_init(&qh->qh_list_entry);
1444}
1445
1446/**
1447 * dwc2_wait_timer_fn() - Timer function to re-queue after waiting
1448 *
1449 * As per the spec, a NAK indicates that "a function is temporarily unable to
1450 * transmit or receive data, but will eventually be able to do so without need
1451 * of host intervention".
1452 *
1453 * That means that when we encounter a NAK we're supposed to retry.
1454 *
1455 * ...but if we retry right away (from the interrupt handler that saw the NAK)
1456 * then we can end up with an interrupt storm (if the other side keeps NAKing
1457 * us) because on slow enough CPUs it could take us longer to get out of the
1458 * interrupt routine than it takes for the device to send another NAK. That
1459 * leads to a constant stream of NAK interrupts and the CPU locks.
1460 *
1461 * ...so instead of retrying right away in the case of a NAK we'll set a timer
1462 * to retry some time later. This function handles that timer and moves the
1463 * qh back to the "inactive" list, then queues transactions.
1464 *
1465 * @t: Pointer to wait_timer in a qh.
1466 */
1467static void dwc2_wait_timer_fn(struct timer_list *t)
1468{
1469 struct dwc2_qh *qh = from_timer(qh, t, wait_timer);
1470 struct dwc2_hsotg *hsotg = qh->hsotg;
1471 unsigned long flags;
1472
1473 spin_lock_irqsave(&hsotg->lock, flags);
1474
1475 /*
1476 * We'll set wait_timer_cancel to true if we want to cancel this
1477 * operation in dwc2_hcd_qh_unlink().
1478 */
1479 if (!qh->wait_timer_cancel) {
1480 enum dwc2_transaction_type tr_type;
1481
1482 qh->want_wait = false;
1483
1484 list_move(&qh->qh_list_entry,
1485 &hsotg->non_periodic_sched_inactive);
1486
1487 tr_type = dwc2_hcd_select_transactions(hsotg);
1488 if (tr_type != DWC2_TRANSACTION_NONE)
1489 dwc2_hcd_queue_transactions(hsotg, tr_type);
1490 }
1491
1492 spin_unlock_irqrestore(&hsotg->lock, flags);
1493}
1494
1495/**
1496 * dwc2_qh_init() - Initializes a QH structure
1497 *
1498 * @hsotg: The HCD state structure for the DWC OTG controller
1499 * @qh: The QH to init
1500 * @urb: Holds the information about the device/endpoint needed to initialize
1501 * the QH
1502 * @mem_flags: Flags for allocating memory.
1503 */
1504static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1505 struct dwc2_hcd_urb *urb, gfp_t mem_flags)
1506{
1507 int dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
1508 u8 ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1509 bool ep_is_in = !!dwc2_hcd_is_pipe_in(&urb->pipe_info);
1510 bool ep_is_isoc = (ep_type == USB_ENDPOINT_XFER_ISOC);
1511 bool ep_is_int = (ep_type == USB_ENDPOINT_XFER_INT);
1512 u32 hprt = dwc2_readl(hsotg->regs + HPRT0);
1513 u32 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1514 bool do_split = (prtspd == HPRT0_SPD_HIGH_SPEED &&
1515 dev_speed != USB_SPEED_HIGH);
1516 int maxp = dwc2_hcd_get_mps(&urb->pipe_info);
1517 int bytecount = dwc2_hb_mult(maxp) * dwc2_max_packet(maxp);
1518 char *speed, *type;
1519
1520 /* Initialize QH */
1521 qh->hsotg = hsotg;
1522 timer_setup(&qh->unreserve_timer, dwc2_unreserve_timer_fn, 0);
1523 timer_setup(&qh->wait_timer, dwc2_wait_timer_fn, 0);
1524 qh->ep_type = ep_type;
1525 qh->ep_is_in = ep_is_in;
1526
1527 qh->data_toggle = DWC2_HC_PID_DATA0;
1528 qh->maxp = maxp;
1529 INIT_LIST_HEAD(&qh->qtd_list);
1530 INIT_LIST_HEAD(&qh->qh_list_entry);
1531
1532 qh->do_split = do_split;
1533 qh->dev_speed = dev_speed;
1534
1535 if (ep_is_int || ep_is_isoc) {
1536 /* Compute scheduling parameters once and save them */
1537 int host_speed = do_split ? USB_SPEED_HIGH : dev_speed;
1538 struct dwc2_tt *dwc_tt = dwc2_host_get_tt_info(hsotg, urb->priv,
1539 mem_flags,
1540 &qh->ttport);
1541 int device_ns;
1542
1543 qh->dwc_tt = dwc_tt;
1544
1545 qh->host_us = NS_TO_US(usb_calc_bus_time(host_speed, ep_is_in,
1546 ep_is_isoc, bytecount));
1547 device_ns = usb_calc_bus_time(dev_speed, ep_is_in,
1548 ep_is_isoc, bytecount);
1549
1550 if (do_split && dwc_tt)
1551 device_ns += dwc_tt->usb_tt->think_time;
1552 qh->device_us = NS_TO_US(device_ns);
1553
1554 qh->device_interval = urb->interval;
1555 qh->host_interval = urb->interval * (do_split ? 8 : 1);
1556
1557 /*
1558 * Schedule low speed if we're running the host in low or
1559 * full speed OR if we've got a "TT" to deal with to access this
1560 * device.
1561 */
1562 qh->schedule_low_speed = prtspd != HPRT0_SPD_HIGH_SPEED ||
1563 dwc_tt;
1564
1565 if (do_split) {
1566 /* We won't know num transfers until we schedule */
1567 qh->num_hs_transfers = -1;
1568 } else if (dev_speed == USB_SPEED_HIGH) {
1569 qh->num_hs_transfers = 1;
1570 } else {
1571 qh->num_hs_transfers = 0;
1572 }
1573
1574 /* We'll schedule later when we have something to do */
1575 }
1576
1577 switch (dev_speed) {
1578 case USB_SPEED_LOW:
1579 speed = "low";
1580 break;
1581 case USB_SPEED_FULL:
1582 speed = "full";
1583 break;
1584 case USB_SPEED_HIGH:
1585 speed = "high";
1586 break;
1587 default:
1588 speed = "?";
1589 break;
1590 }
1591
1592 switch (qh->ep_type) {
1593 case USB_ENDPOINT_XFER_ISOC:
1594 type = "isochronous";
1595 break;
1596 case USB_ENDPOINT_XFER_INT:
1597 type = "interrupt";
1598 break;
1599 case USB_ENDPOINT_XFER_CONTROL:
1600 type = "control";
1601 break;
1602 case USB_ENDPOINT_XFER_BULK:
1603 type = "bulk";
1604 break;
1605 default:
1606 type = "?";
1607 break;
1608 }
1609
1610 dwc2_sch_dbg(hsotg, "QH=%p Init %s, %s speed, %d bytes:\n", qh, type,
1611 speed, bytecount);
1612 dwc2_sch_dbg(hsotg, "QH=%p ...addr=%d, ep=%d, %s\n", qh,
1613 dwc2_hcd_get_dev_addr(&urb->pipe_info),
1614 dwc2_hcd_get_ep_num(&urb->pipe_info),
1615 ep_is_in ? "IN" : "OUT");
1616 if (ep_is_int || ep_is_isoc) {
1617 dwc2_sch_dbg(hsotg,
1618 "QH=%p ...duration: host=%d us, device=%d us\n",
1619 qh, qh->host_us, qh->device_us);
1620 dwc2_sch_dbg(hsotg, "QH=%p ...interval: host=%d, device=%d\n",
1621 qh, qh->host_interval, qh->device_interval);
1622 if (qh->schedule_low_speed)
1623 dwc2_sch_dbg(hsotg, "QH=%p ...low speed schedule=%p\n",
1624 qh, dwc2_get_ls_map(hsotg, qh));
1625 }
1626}
1627
1628/**
1629 * dwc2_hcd_qh_create() - Allocates and initializes a QH
1630 *
1631 * @hsotg: The HCD state structure for the DWC OTG controller
1632 * @urb: Holds the information about the device/endpoint needed
1633 * to initialize the QH
1634 * @atomic_alloc: Flag to do atomic allocation if needed
1635 *
1636 * Return: Pointer to the newly allocated QH, or NULL on error
1637 */
1638struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
1639 struct dwc2_hcd_urb *urb,
1640 gfp_t mem_flags)
1641{
1642 struct dwc2_qh *qh;
1643
1644 if (!urb->priv)
1645 return NULL;
1646
1647 /* Allocate memory */
1648 qh = kzalloc(sizeof(*qh), mem_flags);
1649 if (!qh)
1650 return NULL;
1651
1652 dwc2_qh_init(hsotg, qh, urb, mem_flags);
1653
1654 if (hsotg->params.dma_desc_enable &&
1655 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) {
1656 dwc2_hcd_qh_free(hsotg, qh);
1657 return NULL;
1658 }
1659
1660 return qh;
1661}
1662
1663/**
1664 * dwc2_hcd_qh_free() - Frees the QH
1665 *
1666 * @hsotg: HCD instance
1667 * @qh: The QH to free
1668 *
1669 * QH should already be removed from the list. QTD list should already be empty
1670 * if called from URB Dequeue.
1671 *
1672 * Must NOT be called with interrupt disabled or spinlock held
1673 */
1674void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1675{
1676 /* Make sure any unreserve work is finished. */
1677 if (del_timer_sync(&qh->unreserve_timer)) {
1678 unsigned long flags;
1679
1680 spin_lock_irqsave(&hsotg->lock, flags);
1681 dwc2_do_unreserve(hsotg, qh);
1682 spin_unlock_irqrestore(&hsotg->lock, flags);
1683 }
1684
1685 /*
1686 * We don't have the lock so we can safely wait until the wait timer
1687 * finishes. Of course, at this point in time we'd better have set
1688 * wait_timer_active to false so if this timer was still pending it
1689 * won't do anything anyway, but we want it to finish before we free
1690 * memory.
1691 */
1692 del_timer_sync(&qh->wait_timer);
1693
1694 dwc2_host_put_tt_info(hsotg, qh->dwc_tt);
1695
1696 if (qh->desc_list)
1697 dwc2_hcd_qh_free_ddma(hsotg, qh);
1698 kfree(qh);
1699}
1700
1701/**
1702 * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic
1703 * schedule if it is not already in the schedule. If the QH is already in
1704 * the schedule, no action is taken.
1705 *
1706 * @hsotg: The HCD state structure for the DWC OTG controller
1707 * @qh: The QH to add
1708 *
1709 * Return: 0 if successful, negative error code otherwise
1710 */
1711int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1712{
1713 int status;
1714 u32 intr_mask;
1715
1716 if (dbg_qh(qh))
1717 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1718
1719 if (!list_empty(&qh->qh_list_entry))
1720 /* QH already in a schedule */
1721 return 0;
1722
1723 /* Add the new QH to the appropriate schedule */
1724 if (dwc2_qh_is_non_per(qh)) {
1725 /* Schedule right away */
1726 qh->start_active_frame = hsotg->frame_number;
1727 qh->next_active_frame = qh->start_active_frame;
1728
1729 if (qh->want_wait) {
1730 list_add_tail(&qh->qh_list_entry,
1731 &hsotg->non_periodic_sched_waiting);
1732 qh->wait_timer_cancel = false;
1733 mod_timer(&qh->wait_timer,
1734 jiffies + DWC2_RETRY_WAIT_DELAY + 1);
1735 } else {
1736 list_add_tail(&qh->qh_list_entry,
1737 &hsotg->non_periodic_sched_inactive);
1738 }
1739 return 0;
1740 }
1741
1742 status = dwc2_schedule_periodic(hsotg, qh);
1743 if (status)
1744 return status;
1745 if (!hsotg->periodic_qh_count) {
1746 intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
1747 intr_mask |= GINTSTS_SOF;
1748 dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
1749 }
1750 hsotg->periodic_qh_count++;
1751
1752 return 0;
1753}
1754
1755/**
1756 * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic
1757 * schedule. Memory is not freed.
1758 *
1759 * @hsotg: The HCD state structure
1760 * @qh: QH to remove from schedule
1761 */
1762void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1763{
1764 u32 intr_mask;
1765
1766 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1767
1768 /* If the wait_timer is pending, this will stop it from acting */
1769 qh->wait_timer_cancel = true;
1770
1771 if (list_empty(&qh->qh_list_entry))
1772 /* QH is not in a schedule */
1773 return;
1774
1775 if (dwc2_qh_is_non_per(qh)) {
1776 if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry)
1777 hsotg->non_periodic_qh_ptr =
1778 hsotg->non_periodic_qh_ptr->next;
1779 list_del_init(&qh->qh_list_entry);
1780 return;
1781 }
1782
1783 dwc2_deschedule_periodic(hsotg, qh);
1784 hsotg->periodic_qh_count--;
1785 if (!hsotg->periodic_qh_count &&
1786 !hsotg->params.dma_desc_enable) {
1787 intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
1788 intr_mask &= ~GINTSTS_SOF;
1789 dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
1790 }
1791}
1792
1793/**
1794 * dwc2_next_for_periodic_split() - Set next_active_frame midway thru a split.
1795 *
1796 * This is called for setting next_active_frame for periodic splits for all but
1797 * the first packet of the split. Confusing? I thought so...
1798 *
1799 * Periodic splits are single low/full speed transfers that we end up splitting
1800 * up into several high speed transfers. They always fit into one full (1 ms)
1801 * frame but might be split over several microframes (125 us each). We to put
1802 * each of the parts on a very specific high speed frame.
1803 *
1804 * This function figures out where the next active uFrame needs to be.
1805 *
1806 * @hsotg: The HCD state structure
1807 * @qh: QH for the periodic transfer.
1808 * @frame_number: The current frame number.
1809 *
1810 * Return: number missed by (or 0 if we didn't miss).
1811 */
1812static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg,
1813 struct dwc2_qh *qh, u16 frame_number)
1814{
1815 u16 old_frame = qh->next_active_frame;
1816 u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1);
1817 int missed = 0;
1818 u16 incr;
1819
1820 /*
1821 * See dwc2_uframe_schedule_split() for split scheduling.
1822 *
1823 * Basically: increment 1 normally, but 2 right after the start split
1824 * (except for ISOC out).
1825 */
1826 if (old_frame == qh->start_active_frame &&
1827 !(qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in))
1828 incr = 2;
1829 else
1830 incr = 1;
1831
1832 qh->next_active_frame = dwc2_frame_num_inc(old_frame, incr);
1833
1834 /*
1835 * Note that it's OK for frame_number to be 1 frame past
1836 * next_active_frame. Remember that next_active_frame is supposed to
1837 * be 1 frame _before_ when we want to be scheduled. If we're 1 frame
1838 * past it just means schedule ASAP.
1839 *
1840 * It's _not_ OK, however, if we're more than one frame past.
1841 */
1842 if (dwc2_frame_num_gt(prev_frame_number, qh->next_active_frame)) {
1843 /*
1844 * OOPS, we missed. That's actually pretty bad since
1845 * the hub will be unhappy; try ASAP I guess.
1846 */
1847 missed = dwc2_frame_num_dec(prev_frame_number,
1848 qh->next_active_frame);
1849 qh->next_active_frame = frame_number;
1850 }
1851
1852 return missed;
1853}
1854
1855/**
1856 * dwc2_next_periodic_start() - Set next_active_frame for next transfer start
1857 *
1858 * This is called for setting next_active_frame for a periodic transfer for
1859 * all cases other than midway through a periodic split. This will also update
1860 * start_active_frame.
1861 *
1862 * Since we _always_ keep start_active_frame as the start of the previous
1863 * transfer this is normally pretty easy: we just add our interval to
1864 * start_active_frame and we've got our answer.
1865 *
1866 * The tricks come into play if we miss. In that case we'll look for the next
1867 * slot we can fit into.
1868 *
1869 * @hsotg: The HCD state structure
1870 * @qh: QH for the periodic transfer.
1871 * @frame_number: The current frame number.
1872 *
1873 * Return: number missed by (or 0 if we didn't miss).
1874 */
1875static int dwc2_next_periodic_start(struct dwc2_hsotg *hsotg,
1876 struct dwc2_qh *qh, u16 frame_number)
1877{
1878 int missed = 0;
1879 u16 interval = qh->host_interval;
1880 u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1);
1881
1882 qh->start_active_frame = dwc2_frame_num_inc(qh->start_active_frame,
1883 interval);
1884
1885 /*
1886 * The dwc2_frame_num_gt() function used below won't work terribly well
1887 * with if we just incremented by a really large intervals since the
1888 * frame counter only goes to 0x3fff. It's terribly unlikely that we
1889 * will have missed in this case anyway. Just go to exit. If we want
1890 * to try to do better we'll need to keep track of a bigger counter
1891 * somewhere in the driver and handle overflows.
1892 */
1893 if (interval >= 0x1000)
1894 goto exit;
1895
1896 /*
1897 * Test for misses, which is when it's too late to schedule.
1898 *
1899 * A few things to note:
1900 * - We compare against prev_frame_number since start_active_frame
1901 * and next_active_frame are always 1 frame before we want things
1902 * to be active and we assume we can still get scheduled in the
1903 * current frame number.
1904 * - It's possible for start_active_frame (now incremented) to be
1905 * next_active_frame if we got an EO MISS (even_odd miss) which
1906 * basically means that we detected there wasn't enough time for
1907 * the last packet and dwc2_hc_set_even_odd_frame() rescheduled us
1908 * at the last second. We want to make sure we don't schedule
1909 * another transfer for the same frame. My test webcam doesn't seem
1910 * terribly upset by missing a transfer but really doesn't like when
1911 * we do two transfers in the same frame.
1912 * - Some misses are expected. Specifically, in order to work
1913 * perfectly dwc2 really needs quite spectacular interrupt latency
1914 * requirements. It needs to be able to handle its interrupts
1915 * completely within 125 us of them being asserted. That not only
1916 * means that the dwc2 interrupt handler needs to be fast but it
1917 * means that nothing else in the system has to block dwc2 for a long
1918 * time. We can help with the dwc2 parts of this, but it's hard to
1919 * guarantee that a system will have interrupt latency < 125 us, so
1920 * we have to be robust to some misses.
1921 */
1922 if (qh->start_active_frame == qh->next_active_frame ||
1923 dwc2_frame_num_gt(prev_frame_number, qh->start_active_frame)) {
1924 u16 ideal_start = qh->start_active_frame;
1925 int periods_in_map;
1926
1927 /*
1928 * Adjust interval as per gcd with map size.
1929 * See pmap_schedule() for more details here.
1930 */
1931 if (qh->do_split || qh->dev_speed == USB_SPEED_HIGH)
1932 periods_in_map = DWC2_HS_SCHEDULE_UFRAMES;
1933 else
1934 periods_in_map = DWC2_LS_SCHEDULE_FRAMES;
1935 interval = gcd(interval, periods_in_map);
1936
1937 do {
1938 qh->start_active_frame = dwc2_frame_num_inc(
1939 qh->start_active_frame, interval);
1940 } while (dwc2_frame_num_gt(prev_frame_number,
1941 qh->start_active_frame));
1942
1943 missed = dwc2_frame_num_dec(qh->start_active_frame,
1944 ideal_start);
1945 }
1946
1947exit:
1948 qh->next_active_frame = qh->start_active_frame;
1949
1950 return missed;
1951}
1952
1953/*
1954 * Deactivates a QH. For non-periodic QHs, removes the QH from the active
1955 * non-periodic schedule. The QH is added to the inactive non-periodic
1956 * schedule if any QTDs are still attached to the QH.
1957 *
1958 * For periodic QHs, the QH is removed from the periodic queued schedule. If
1959 * there are any QTDs still attached to the QH, the QH is added to either the
1960 * periodic inactive schedule or the periodic ready schedule and its next
1961 * scheduled frame is calculated. The QH is placed in the ready schedule if
1962 * the scheduled frame has been reached already. Otherwise it's placed in the
1963 * inactive schedule. If there are no QTDs attached to the QH, the QH is
1964 * completely removed from the periodic schedule.
1965 */
1966void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1967 int sched_next_periodic_split)
1968{
1969 u16 old_frame = qh->next_active_frame;
1970 u16 frame_number;
1971 int missed;
1972
1973 if (dbg_qh(qh))
1974 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1975
1976 if (dwc2_qh_is_non_per(qh)) {
1977 dwc2_hcd_qh_unlink(hsotg, qh);
1978 if (!list_empty(&qh->qtd_list))
1979 /* Add back to inactive/waiting non-periodic schedule */
1980 dwc2_hcd_qh_add(hsotg, qh);
1981 return;
1982 }
1983
1984 /*
1985 * Use the real frame number rather than the cached value as of the
1986 * last SOF just to get us a little closer to reality. Note that
1987 * means we don't actually know if we've already handled the SOF
1988 * interrupt for this frame.
1989 */
1990 frame_number = dwc2_hcd_get_frame_number(hsotg);
1991
1992 if (sched_next_periodic_split)
1993 missed = dwc2_next_for_periodic_split(hsotg, qh, frame_number);
1994 else
1995 missed = dwc2_next_periodic_start(hsotg, qh, frame_number);
1996
1997 dwc2_sch_vdbg(hsotg,
1998 "QH=%p next(%d) fn=%04x, sch=%04x=>%04x (%+d) miss=%d %s\n",
1999 qh, sched_next_periodic_split, frame_number, old_frame,
2000 qh->next_active_frame,
2001 dwc2_frame_num_dec(qh->next_active_frame, old_frame),
2002 missed, missed ? "MISS" : "");
2003
2004 if (list_empty(&qh->qtd_list)) {
2005 dwc2_hcd_qh_unlink(hsotg, qh);
2006 return;
2007 }
2008
2009 /*
2010 * Remove from periodic_sched_queued and move to
2011 * appropriate queue
2012 *
2013 * Note: we purposely use the frame_number from the "hsotg" structure
2014 * since we know SOF interrupt will handle future frames.
2015 */
2016 if (dwc2_frame_num_le(qh->next_active_frame, hsotg->frame_number))
2017 list_move_tail(&qh->qh_list_entry,
2018 &hsotg->periodic_sched_ready);
2019 else
2020 list_move_tail(&qh->qh_list_entry,
2021 &hsotg->periodic_sched_inactive);
2022}
2023
2024/**
2025 * dwc2_hcd_qtd_init() - Initializes a QTD structure
2026 *
2027 * @qtd: The QTD to initialize
2028 * @urb: The associated URB
2029 */
2030void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2031{
2032 qtd->urb = urb;
2033 if (dwc2_hcd_get_pipe_type(&urb->pipe_info) ==
2034 USB_ENDPOINT_XFER_CONTROL) {
2035 /*
2036 * The only time the QTD data toggle is used is on the data
2037 * phase of control transfers. This phase always starts with
2038 * DATA1.
2039 */
2040 qtd->data_toggle = DWC2_HC_PID_DATA1;
2041 qtd->control_phase = DWC2_CONTROL_SETUP;
2042 }
2043
2044 /* Start split */
2045 qtd->complete_split = 0;
2046 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
2047 qtd->isoc_split_offset = 0;
2048 qtd->in_process = 0;
2049
2050 /* Store the qtd ptr in the urb to reference the QTD */
2051 urb->qtd = qtd;
2052}
2053
2054/**
2055 * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH
2056 * Caller must hold driver lock.
2057 *
2058 * @hsotg: The DWC HCD structure
2059 * @qtd: The QTD to add
2060 * @qh: Queue head to add qtd to
2061 *
2062 * Return: 0 if successful, negative error code otherwise
2063 *
2064 * If the QH to which the QTD is added is not currently scheduled, it is placed
2065 * into the proper schedule based on its EP type.
2066 */
2067int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2068 struct dwc2_qh *qh)
2069{
2070 int retval;
2071
2072 if (unlikely(!qh)) {
2073 dev_err(hsotg->dev, "%s: Invalid QH\n", __func__);
2074 retval = -EINVAL;
2075 goto fail;
2076 }
2077
2078 retval = dwc2_hcd_qh_add(hsotg, qh);
2079 if (retval)
2080 goto fail;
2081
2082 qtd->qh = qh;
2083 list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);
2084
2085 return 0;
2086fail:
2087 return retval;
2088}