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1/*
2 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37/*
38 * This file contains the functions to manage Queue Heads and Queue
39 * Transfer Descriptors for Host mode
40 */
41#include <linux/gcd.h>
42#include <linux/kernel.h>
43#include <linux/module.h>
44#include <linux/spinlock.h>
45#include <linux/interrupt.h>
46#include <linux/dma-mapping.h>
47#include <linux/io.h>
48#include <linux/slab.h>
49#include <linux/usb.h>
50
51#include <linux/usb/hcd.h>
52#include <linux/usb/ch11.h>
53
54#include "core.h"
55#include "hcd.h"
56
57/* Wait this long before releasing periodic reservation */
58#define DWC2_UNRESERVE_DELAY (msecs_to_jiffies(5))
59
60/**
61 * dwc2_periodic_channel_available() - Checks that a channel is available for a
62 * periodic transfer
63 *
64 * @hsotg: The HCD state structure for the DWC OTG controller
65 *
66 * Return: 0 if successful, negative error code otherwise
67 */
68static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg)
69{
70 /*
71 * Currently assuming that there is a dedicated host channel for
72 * each periodic transaction plus at least one host channel for
73 * non-periodic transactions
74 */
75 int status;
76 int num_channels;
77
78 num_channels = hsotg->params.host_channels;
79 if (hsotg->periodic_channels + hsotg->non_periodic_channels <
80 num_channels
81 && hsotg->periodic_channels < num_channels - 1) {
82 status = 0;
83 } else {
84 dev_dbg(hsotg->dev,
85 "%s: Total channels: %d, Periodic: %d, "
86 "Non-periodic: %d\n", __func__, num_channels,
87 hsotg->periodic_channels, hsotg->non_periodic_channels);
88 status = -ENOSPC;
89 }
90
91 return status;
92}
93
94/**
95 * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth
96 * for the specified QH in the periodic schedule
97 *
98 * @hsotg: The HCD state structure for the DWC OTG controller
99 * @qh: QH containing periodic bandwidth required
100 *
101 * Return: 0 if successful, negative error code otherwise
102 *
103 * For simplicity, this calculation assumes that all the transfers in the
104 * periodic schedule may occur in the same (micro)frame
105 */
106static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg,
107 struct dwc2_qh *qh)
108{
109 int status;
110 s16 max_claimed_usecs;
111
112 status = 0;
113
114 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
115 /*
116 * High speed mode
117 * Max periodic usecs is 80% x 125 usec = 100 usec
118 */
119 max_claimed_usecs = 100 - qh->host_us;
120 } else {
121 /*
122 * Full speed mode
123 * Max periodic usecs is 90% x 1000 usec = 900 usec
124 */
125 max_claimed_usecs = 900 - qh->host_us;
126 }
127
128 if (hsotg->periodic_usecs > max_claimed_usecs) {
129 dev_err(hsotg->dev,
130 "%s: already claimed usecs %d, required usecs %d\n",
131 __func__, hsotg->periodic_usecs, qh->host_us);
132 status = -ENOSPC;
133 }
134
135 return status;
136}
137
138/**
139 * pmap_schedule() - Schedule time in a periodic bitmap (pmap).
140 *
141 * @map: The bitmap representing the schedule; will be updated
142 * upon success.
143 * @bits_per_period: The schedule represents several periods. This is how many
144 * bits are in each period. It's assumed that the beginning
145 * of the schedule will repeat after its end.
146 * @periods_in_map: The number of periods in the schedule.
147 * @num_bits: The number of bits we need per period we want to reserve
148 * in this function call.
149 * @interval: How often we need to be scheduled for the reservation this
150 * time. 1 means every period. 2 means every other period.
151 * ...you get the picture?
152 * @start: The bit number to start at. Normally 0. Must be within
153 * the interval or we return failure right away.
154 * @only_one_period: Normally we'll allow picking a start anywhere within the
155 * first interval, since we can still make all repetition
156 * requirements by doing that. However, if you pass true
157 * here then we'll return failure if we can't fit within
158 * the period that "start" is in.
159 *
160 * The idea here is that we want to schedule time for repeating events that all
161 * want the same resource. The resource is divided into fixed-sized periods
162 * and the events want to repeat every "interval" periods. The schedule
163 * granularity is one bit.
164 *
165 * To keep things "simple", we'll represent our schedule with a bitmap that
166 * contains a fixed number of periods. This gets rid of a lot of complexity
167 * but does mean that we need to handle things specially (and non-ideally) if
168 * the number of the periods in the schedule doesn't match well with the
169 * intervals that we're trying to schedule.
170 *
171 * Here's an explanation of the scheme we'll implement, assuming 8 periods.
172 * - If interval is 1, we need to take up space in each of the 8
173 * periods we're scheduling. Easy.
174 * - If interval is 2, we need to take up space in half of the
175 * periods. Again, easy.
176 * - If interval is 3, we actually need to fall back to interval 1.
177 * Why? Because we might need time in any period. AKA for the
178 * first 8 periods, we'll be in slot 0, 3, 6. Then we'll be
179 * in slot 1, 4, 7. Then we'll be in 2, 5. Then we'll be back to
180 * 0, 3, and 6. Since we could be in any frame we need to reserve
181 * for all of them. Sucks, but that's what you gotta do. Note that
182 * if we were instead scheduling 8 * 3 = 24 we'd do much better, but
183 * then we need more memory and time to do scheduling.
184 * - If interval is 4, easy.
185 * - If interval is 5, we again need interval 1. The schedule will be
186 * 0, 5, 2, 7, 4, 1, 6, 3, 0
187 * - If interval is 6, we need interval 2. 0, 6, 4, 2.
188 * - If interval is 7, we need interval 1.
189 * - If interval is 8, we need interval 8.
190 *
191 * If you do the math, you'll see that we need to pretend that interval is
192 * equal to the greatest_common_divisor(interval, periods_in_map).
193 *
194 * Note that at the moment this function tends to front-pack the schedule.
195 * In some cases that's really non-ideal (it's hard to schedule things that
196 * need to repeat every period). In other cases it's perfect (you can easily
197 * schedule bigger, less often repeating things).
198 *
199 * Here's the algorithm in action (8 periods, 5 bits per period):
200 * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0
201 * |*****| ***|*****| ***|*****| ***|*****| ***| OK 3 bits, intv 3 at 2
202 * |*****|* ***|*****| ***|*****|* ***|*****| ***| OK 1 bits, intv 4 at 5
203 * |** |* |** | |** |* |** | | Remv 3 bits, intv 3 at 2
204 * |*** |* |*** | |*** |* |*** | | OK 1 bits, intv 6 at 2
205 * |**** |* * |**** | * |**** |* * |**** | * | OK 1 bits, intv 1 at 3
206 * |**** |**** |**** | *** |**** |**** |**** | *** | OK 2 bits, intv 2 at 6
207 * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 1 at 4
208 * |*****|*****|*****| ****|*****|*****|*****| ****| FAIL 1 bits, intv 1
209 * | ***|*****| ***| ****| ***|*****| ***| ****| Remv 2 bits, intv 2 at 0
210 * | ***| ****| ***| ****| ***| ****| ***| ****| Remv 1 bits, intv 4 at 5
211 * | **| ****| **| ****| **| ****| **| ****| Remv 1 bits, intv 6 at 2
212 * | *| ** *| *| ** *| *| ** *| *| ** *| Remv 1 bits, intv 1 at 3
213 * | *| *| *| *| *| *| *| *| Remv 2 bits, intv 2 at 6
214 * | | | | | | | | | Remv 1 bits, intv 1 at 4
215 * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0
216 * |*** | |** | |*** | |** | | OK 1 bits, intv 4 at 2
217 * |*****| |** **| |*****| |** **| | OK 2 bits, intv 2 at 3
218 * |*****|* |** **| |*****|* |** **| | OK 1 bits, intv 4 at 5
219 * |*****|*** |** **| ** |*****|*** |** **| ** | OK 2 bits, intv 2 at 6
220 * |*****|*****|** **| ****|*****|*****|** **| ****| OK 2 bits, intv 2 at 8
221 * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 4 at 12
222 *
223 * This function is pretty generic and could be easily abstracted if anything
224 * needed similar scheduling.
225 *
226 * Returns either -ENOSPC or a >= 0 start bit which should be passed to the
227 * unschedule routine. The map bitmap will be updated on a non-error result.
228 */
229static int pmap_schedule(unsigned long *map, int bits_per_period,
230 int periods_in_map, int num_bits,
231 int interval, int start, bool only_one_period)
232{
233 int interval_bits;
234 int to_reserve;
235 int first_end;
236 int i;
237
238 if (num_bits > bits_per_period)
239 return -ENOSPC;
240
241 /* Adjust interval as per description */
242 interval = gcd(interval, periods_in_map);
243
244 interval_bits = bits_per_period * interval;
245 to_reserve = periods_in_map / interval;
246
247 /* If start has gotten us past interval then we can't schedule */
248 if (start >= interval_bits)
249 return -ENOSPC;
250
251 if (only_one_period)
252 /* Must fit within same period as start; end at begin of next */
253 first_end = (start / bits_per_period + 1) * bits_per_period;
254 else
255 /* Can fit anywhere in the first interval */
256 first_end = interval_bits;
257
258 /*
259 * We'll try to pick the first repetition, then see if that time
260 * is free for each of the subsequent repetitions. If it's not
261 * we'll adjust the start time for the next search of the first
262 * repetition.
263 */
264 while (start + num_bits <= first_end) {
265 int end;
266
267 /* Need to stay within this period */
268 end = (start / bits_per_period + 1) * bits_per_period;
269
270 /* Look for num_bits us in this microframe starting at start */
271 start = bitmap_find_next_zero_area(map, end, start, num_bits,
272 0);
273
274 /*
275 * We should get start >= end if we fail. We might be
276 * able to check the next microframe depending on the
277 * interval, so continue on (start already updated).
278 */
279 if (start >= end) {
280 start = end;
281 continue;
282 }
283
284 /* At this point we have a valid point for first one */
285 for (i = 1; i < to_reserve; i++) {
286 int ith_start = start + interval_bits * i;
287 int ith_end = end + interval_bits * i;
288 int ret;
289
290 /* Use this as a dumb "check if bits are 0" */
291 ret = bitmap_find_next_zero_area(
292 map, ith_start + num_bits, ith_start, num_bits,
293 0);
294
295 /* We got the right place, continue checking */
296 if (ret == ith_start)
297 continue;
298
299 /* Move start up for next time and exit for loop */
300 ith_start = bitmap_find_next_zero_area(
301 map, ith_end, ith_start, num_bits, 0);
302 if (ith_start >= ith_end)
303 /* Need a while new period next time */
304 start = end;
305 else
306 start = ith_start - interval_bits * i;
307 break;
308 }
309
310 /* If didn't exit the for loop with a break, we have success */
311 if (i == to_reserve)
312 break;
313 }
314
315 if (start + num_bits > first_end)
316 return -ENOSPC;
317
318 for (i = 0; i < to_reserve; i++) {
319 int ith_start = start + interval_bits * i;
320
321 bitmap_set(map, ith_start, num_bits);
322 }
323
324 return start;
325}
326
327/**
328 * pmap_unschedule() - Undo work done by pmap_schedule()
329 *
330 * @map: See pmap_schedule().
331 * @bits_per_period: See pmap_schedule().
332 * @periods_in_map: See pmap_schedule().
333 * @num_bits: The number of bits that was passed to schedule.
334 * @interval: The interval that was passed to schedule.
335 * @start: The return value from pmap_schedule().
336 */
337static void pmap_unschedule(unsigned long *map, int bits_per_period,
338 int periods_in_map, int num_bits,
339 int interval, int start)
340{
341 int interval_bits;
342 int to_release;
343 int i;
344
345 /* Adjust interval as per description in pmap_schedule() */
346 interval = gcd(interval, periods_in_map);
347
348 interval_bits = bits_per_period * interval;
349 to_release = periods_in_map / interval;
350
351 for (i = 0; i < to_release; i++) {
352 int ith_start = start + interval_bits * i;
353
354 bitmap_clear(map, ith_start, num_bits);
355 }
356}
357
358/**
359 * dwc2_get_ls_map() - Get the map used for the given qh
360 *
361 * @hsotg: The HCD state structure for the DWC OTG controller.
362 * @qh: QH for the periodic transfer.
363 *
364 * We'll always get the periodic map out of our TT. Note that even if we're
365 * running the host straight in low speed / full speed mode it appears as if
366 * a TT is allocated for us, so we'll use it. If that ever changes we can
367 * add logic here to get a map out of "hsotg" if !qh->do_split.
368 *
369 * Returns: the map or NULL if a map couldn't be found.
370 */
371static unsigned long *dwc2_get_ls_map(struct dwc2_hsotg *hsotg,
372 struct dwc2_qh *qh)
373{
374 unsigned long *map;
375
376 /* Don't expect to be missing a TT and be doing low speed scheduling */
377 if (WARN_ON(!qh->dwc_tt))
378 return NULL;
379
380 /* Get the map and adjust if this is a multi_tt hub */
381 map = qh->dwc_tt->periodic_bitmaps;
382 if (qh->dwc_tt->usb_tt->multi)
383 map += DWC2_ELEMENTS_PER_LS_BITMAP * qh->ttport;
384
385 return map;
386}
387
388#ifdef DWC2_PRINT_SCHEDULE
389/*
390 * cat_printf() - A printf() + strcat() helper
391 *
392 * This is useful for concatenating a bunch of strings where each string is
393 * constructed using printf.
394 *
395 * @buf: The destination buffer; will be updated to point after the printed
396 * data.
397 * @size: The number of bytes in the buffer (includes space for '\0').
398 * @fmt: The format for printf.
399 * @...: The args for printf.
400 */
401static __printf(3, 4)
402void cat_printf(char **buf, size_t *size, const char *fmt, ...)
403{
404 va_list args;
405 int i;
406
407 if (*size == 0)
408 return;
409
410 va_start(args, fmt);
411 i = vsnprintf(*buf, *size, fmt, args);
412 va_end(args);
413
414 if (i >= *size) {
415 (*buf)[*size - 1] = '\0';
416 *buf += *size;
417 *size = 0;
418 } else {
419 *buf += i;
420 *size -= i;
421 }
422}
423
424/*
425 * pmap_print() - Print the given periodic map
426 *
427 * Will attempt to print out the periodic schedule.
428 *
429 * @map: See pmap_schedule().
430 * @bits_per_period: See pmap_schedule().
431 * @periods_in_map: See pmap_schedule().
432 * @period_name: The name of 1 period, like "uFrame"
433 * @units: The name of the units, like "us".
434 * @print_fn: The function to call for printing.
435 * @print_data: Opaque data to pass to the print function.
436 */
437static void pmap_print(unsigned long *map, int bits_per_period,
438 int periods_in_map, const char *period_name,
439 const char *units,
440 void (*print_fn)(const char *str, void *data),
441 void *print_data)
442{
443 int period;
444
445 for (period = 0; period < periods_in_map; period++) {
446 char tmp[64];
447 char *buf = tmp;
448 size_t buf_size = sizeof(tmp);
449 int period_start = period * bits_per_period;
450 int period_end = period_start + bits_per_period;
451 int start = 0;
452 int count = 0;
453 bool printed = false;
454 int i;
455
456 for (i = period_start; i < period_end + 1; i++) {
457 /* Handle case when ith bit is set */
458 if (i < period_end &&
459 bitmap_find_next_zero_area(map, i + 1,
460 i, 1, 0) != i) {
461 if (count == 0)
462 start = i - period_start;
463 count++;
464 continue;
465 }
466
467 /* ith bit isn't set; don't care if count == 0 */
468 if (count == 0)
469 continue;
470
471 if (!printed)
472 cat_printf(&buf, &buf_size, "%s %d: ",
473 period_name, period);
474 else
475 cat_printf(&buf, &buf_size, ", ");
476 printed = true;
477
478 cat_printf(&buf, &buf_size, "%d %s -%3d %s", start,
479 units, start + count - 1, units);
480 count = 0;
481 }
482
483 if (printed)
484 print_fn(tmp, print_data);
485 }
486}
487
488
489struct dwc2_qh_print_data {
490 struct dwc2_hsotg *hsotg;
491 struct dwc2_qh *qh;
492};
493
494/**
495 * dwc2_qh_print() - Helper function for dwc2_qh_schedule_print()
496 *
497 * @str: The string to print
498 * @data: A pointer to a struct dwc2_qh_print_data
499 */
500static void dwc2_qh_print(const char *str, void *data)
501{
502 struct dwc2_qh_print_data *print_data = data;
503
504 dwc2_sch_dbg(print_data->hsotg, "QH=%p ...%s\n", print_data->qh, str);
505}
506
507/**
508 * dwc2_qh_schedule_print() - Print the periodic schedule
509 *
510 * @hsotg: The HCD state structure for the DWC OTG controller.
511 * @qh: QH to print.
512 */
513static void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg,
514 struct dwc2_qh *qh)
515{
516 struct dwc2_qh_print_data print_data = { hsotg, qh };
517 int i;
518
519 /*
520 * The printing functions are quite slow and inefficient.
521 * If we don't have tracing turned on, don't run unless the special
522 * define is turned on.
523 */
524
525 if (qh->schedule_low_speed) {
526 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
527
528 dwc2_sch_dbg(hsotg, "QH=%p LS/FS trans: %d=>%d us @ %d us",
529 qh, qh->device_us,
530 DWC2_ROUND_US_TO_SLICE(qh->device_us),
531 DWC2_US_PER_SLICE * qh->ls_start_schedule_slice);
532
533 if (map) {
534 dwc2_sch_dbg(hsotg,
535 "QH=%p Whole low/full speed map %p now:\n",
536 qh, map);
537 pmap_print(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
538 DWC2_LS_SCHEDULE_FRAMES, "Frame ", "slices",
539 dwc2_qh_print, &print_data);
540 }
541 }
542
543 for (i = 0; i < qh->num_hs_transfers; i++) {
544 struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + i;
545 int uframe = trans_time->start_schedule_us /
546 DWC2_HS_PERIODIC_US_PER_UFRAME;
547 int rel_us = trans_time->start_schedule_us %
548 DWC2_HS_PERIODIC_US_PER_UFRAME;
549
550 dwc2_sch_dbg(hsotg,
551 "QH=%p HS trans #%d: %d us @ uFrame %d + %d us\n",
552 qh, i, trans_time->duration_us, uframe, rel_us);
553 }
554 if (qh->num_hs_transfers) {
555 dwc2_sch_dbg(hsotg, "QH=%p Whole high speed map now:\n", qh);
556 pmap_print(hsotg->hs_periodic_bitmap,
557 DWC2_HS_PERIODIC_US_PER_UFRAME,
558 DWC2_HS_SCHEDULE_UFRAMES, "uFrame", "us",
559 dwc2_qh_print, &print_data);
560 }
561 return;
562}
563#else
564static inline void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg,
565 struct dwc2_qh *qh) {};
566#endif
567
568/**
569 * dwc2_ls_pmap_schedule() - Schedule a low speed QH
570 *
571 * @hsotg: The HCD state structure for the DWC OTG controller.
572 * @qh: QH for the periodic transfer.
573 * @search_slice: We'll start trying to schedule at the passed slice.
574 * Remember that slices are the units of the low speed
575 * schedule (think 25us or so).
576 *
577 * Wraps pmap_schedule() with the right parameters for low speed scheduling.
578 *
579 * Normally we schedule low speed devices on the map associated with the TT.
580 *
581 * Returns: 0 for success or an error code.
582 */
583static int dwc2_ls_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
584 int search_slice)
585{
586 int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE);
587 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
588 int slice;
589
590 if (map == NULL)
591 return -EINVAL;
592
593 /*
594 * Schedule on the proper low speed map with our low speed scheduling
595 * parameters. Note that we use the "device_interval" here since
596 * we want the low speed interval and the only way we'd be in this
597 * function is if the device is low speed.
598 *
599 * If we happen to be doing low speed and high speed scheduling for the
600 * same transaction (AKA we have a split) we always do low speed first.
601 * That means we can always pass "false" for only_one_period (that
602 * parameters is only useful when we're trying to get one schedule to
603 * match what we already planned in the other schedule).
604 */
605 slice = pmap_schedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
606 DWC2_LS_SCHEDULE_FRAMES, slices,
607 qh->device_interval, search_slice, false);
608
609 if (slice < 0)
610 return slice;
611
612 qh->ls_start_schedule_slice = slice;
613 return 0;
614}
615
616/**
617 * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_ls_pmap_schedule()
618 *
619 * @hsotg: The HCD state structure for the DWC OTG controller.
620 * @qh: QH for the periodic transfer.
621 */
622static void dwc2_ls_pmap_unschedule(struct dwc2_hsotg *hsotg,
623 struct dwc2_qh *qh)
624{
625 int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE);
626 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
627
628 /* Schedule should have failed, so no worries about no error code */
629 if (map == NULL)
630 return;
631
632 pmap_unschedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
633 DWC2_LS_SCHEDULE_FRAMES, slices, qh->device_interval,
634 qh->ls_start_schedule_slice);
635}
636
637/**
638 * dwc2_hs_pmap_schedule - Schedule in the main high speed schedule
639 *
640 * This will schedule something on the main dwc2 schedule.
641 *
642 * We'll start looking in qh->hs_transfers[index].start_schedule_us. We'll
643 * update this with the result upon success. We also use the duration from
644 * the same structure.
645 *
646 * @hsotg: The HCD state structure for the DWC OTG controller.
647 * @qh: QH for the periodic transfer.
648 * @only_one_period: If true we will limit ourselves to just looking at
649 * one period (aka one 100us chunk). This is used if we have
650 * already scheduled something on the low speed schedule and
651 * need to find something that matches on the high speed one.
652 * @index: The index into qh->hs_transfers that we're working with.
653 *
654 * Returns: 0 for success or an error code. Upon success the
655 * dwc2_hs_transfer_time specified by "index" will be updated.
656 */
657static int dwc2_hs_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
658 bool only_one_period, int index)
659{
660 struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index;
661 int us;
662
663 us = pmap_schedule(hsotg->hs_periodic_bitmap,
664 DWC2_HS_PERIODIC_US_PER_UFRAME,
665 DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us,
666 qh->host_interval, trans_time->start_schedule_us,
667 only_one_period);
668
669 if (us < 0)
670 return us;
671
672 trans_time->start_schedule_us = us;
673 return 0;
674}
675
676/**
677 * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_hs_pmap_schedule()
678 *
679 * @hsotg: The HCD state structure for the DWC OTG controller.
680 * @qh: QH for the periodic transfer.
681 */
682static void dwc2_hs_pmap_unschedule(struct dwc2_hsotg *hsotg,
683 struct dwc2_qh *qh, int index)
684{
685 struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index;
686
687 pmap_unschedule(hsotg->hs_periodic_bitmap,
688 DWC2_HS_PERIODIC_US_PER_UFRAME,
689 DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us,
690 qh->host_interval, trans_time->start_schedule_us);
691}
692
693/**
694 * dwc2_uframe_schedule_split - Schedule a QH for a periodic split xfer.
695 *
696 * This is the most complicated thing in USB. We have to find matching time
697 * in both the global high speed schedule for the port and the low speed
698 * schedule for the TT associated with the given device.
699 *
700 * Being here means that the host must be running in high speed mode and the
701 * device is in low or full speed mode (and behind a hub).
702 *
703 * @hsotg: The HCD state structure for the DWC OTG controller.
704 * @qh: QH for the periodic transfer.
705 */
706static int dwc2_uframe_schedule_split(struct dwc2_hsotg *hsotg,
707 struct dwc2_qh *qh)
708{
709 int bytecount = dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp);
710 int ls_search_slice;
711 int err = 0;
712 int host_interval_in_sched;
713
714 /*
715 * The interval (how often to repeat) in the actual host schedule.
716 * See pmap_schedule() for gcd() explanation.
717 */
718 host_interval_in_sched = gcd(qh->host_interval,
719 DWC2_HS_SCHEDULE_UFRAMES);
720
721 /*
722 * We always try to find space in the low speed schedule first, then
723 * try to find high speed time that matches. If we don't, we'll bump
724 * up the place we start searching in the low speed schedule and try
725 * again. To start we'll look right at the beginning of the low speed
726 * schedule.
727 *
728 * Note that this will tend to front-load the high speed schedule.
729 * We may eventually want to try to avoid this by either considering
730 * both schedules together or doing some sort of round robin.
731 */
732 ls_search_slice = 0;
733
734 while (ls_search_slice < DWC2_LS_SCHEDULE_SLICES) {
735 int start_s_uframe;
736 int ssplit_s_uframe;
737 int second_s_uframe;
738 int rel_uframe;
739 int first_count;
740 int middle_count;
741 int end_count;
742 int first_data_bytes;
743 int other_data_bytes;
744 int i;
745
746 if (qh->schedule_low_speed) {
747 err = dwc2_ls_pmap_schedule(hsotg, qh, ls_search_slice);
748
749 /*
750 * If we got an error here there's no other magic we
751 * can do, so bail. All the looping above is only
752 * helpful to redo things if we got a low speed slot
753 * and then couldn't find a matching high speed slot.
754 */
755 if (err)
756 return err;
757 } else {
758 /* Must be missing the tt structure? Why? */
759 WARN_ON_ONCE(1);
760 }
761
762 /*
763 * This will give us a number 0 - 7 if
764 * DWC2_LS_SCHEDULE_FRAMES == 1, or 0 - 15 if == 2, or ...
765 */
766 start_s_uframe = qh->ls_start_schedule_slice /
767 DWC2_SLICES_PER_UFRAME;
768
769 /* Get a number that's always 0 - 7 */
770 rel_uframe = (start_s_uframe % 8);
771
772 /*
773 * If we were going to start in uframe 7 then we would need to
774 * issue a start split in uframe 6, which spec says is not OK.
775 * Move on to the next full frame (assuming there is one).
776 *
777 * See 11.18.4 Host Split Transaction Scheduling Requirements
778 * bullet 1.
779 */
780 if (rel_uframe == 7) {
781 if (qh->schedule_low_speed)
782 dwc2_ls_pmap_unschedule(hsotg, qh);
783 ls_search_slice =
784 (qh->ls_start_schedule_slice /
785 DWC2_LS_PERIODIC_SLICES_PER_FRAME + 1) *
786 DWC2_LS_PERIODIC_SLICES_PER_FRAME;
787 continue;
788 }
789
790 /*
791 * For ISOC in:
792 * - start split (frame -1)
793 * - complete split w/ data (frame +1)
794 * - complete split w/ data (frame +2)
795 * - ...
796 * - complete split w/ data (frame +num_data_packets)
797 * - complete split w/ data (frame +num_data_packets+1)
798 * - complete split w/ data (frame +num_data_packets+2, max 8)
799 * ...though if frame was "0" then max is 7...
800 *
801 * For ISOC out we might need to do:
802 * - start split w/ data (frame -1)
803 * - start split w/ data (frame +0)
804 * - ...
805 * - start split w/ data (frame +num_data_packets-2)
806 *
807 * For INTERRUPT in we might need to do:
808 * - start split (frame -1)
809 * - complete split w/ data (frame +1)
810 * - complete split w/ data (frame +2)
811 * - complete split w/ data (frame +3, max 8)
812 *
813 * For INTERRUPT out we might need to do:
814 * - start split w/ data (frame -1)
815 * - complete split (frame +1)
816 * - complete split (frame +2)
817 * - complete split (frame +3, max 8)
818 *
819 * Start adjusting!
820 */
821 ssplit_s_uframe = (start_s_uframe +
822 host_interval_in_sched - 1) %
823 host_interval_in_sched;
824 if (qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in)
825 second_s_uframe = start_s_uframe;
826 else
827 second_s_uframe = start_s_uframe + 1;
828
829 /* First data transfer might not be all 188 bytes. */
830 first_data_bytes = 188 -
831 DIV_ROUND_UP(188 * (qh->ls_start_schedule_slice %
832 DWC2_SLICES_PER_UFRAME),
833 DWC2_SLICES_PER_UFRAME);
834 if (first_data_bytes > bytecount)
835 first_data_bytes = bytecount;
836 other_data_bytes = bytecount - first_data_bytes;
837
838 /*
839 * For now, skip OUT xfers where first xfer is partial
840 *
841 * Main dwc2 code assumes:
842 * - INT transfers never get split in two.
843 * - ISOC transfers can always transfer 188 bytes the first
844 * time.
845 *
846 * Until that code is fixed, try again if the first transfer
847 * couldn't transfer everything.
848 *
849 * This code can be removed if/when the rest of dwc2 handles
850 * the above cases. Until it's fixed we just won't be able
851 * to schedule quite as tightly.
852 */
853 if (!qh->ep_is_in &&
854 (first_data_bytes != min_t(int, 188, bytecount))) {
855 dwc2_sch_dbg(hsotg,
856 "QH=%p avoiding broken 1st xfer (%d, %d)\n",
857 qh, first_data_bytes, bytecount);
858 if (qh->schedule_low_speed)
859 dwc2_ls_pmap_unschedule(hsotg, qh);
860 ls_search_slice = (start_s_uframe + 1) *
861 DWC2_SLICES_PER_UFRAME;
862 continue;
863 }
864
865 /* Start by assuming transfers for the bytes */
866 qh->num_hs_transfers = 1 + DIV_ROUND_UP(other_data_bytes, 188);
867
868 /*
869 * Everything except ISOC OUT has extra transfers. Rules are
870 * complicated. See 11.18.4 Host Split Transaction Scheduling
871 * Requirements bullet 3.
872 */
873 if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
874 if (rel_uframe == 6)
875 qh->num_hs_transfers += 2;
876 else
877 qh->num_hs_transfers += 3;
878
879 if (qh->ep_is_in) {
880 /*
881 * First is start split, middle/end is data.
882 * Allocate full data bytes for all data.
883 */
884 first_count = 4;
885 middle_count = bytecount;
886 end_count = bytecount;
887 } else {
888 /*
889 * First is data, middle/end is complete.
890 * First transfer and second can have data.
891 * Rest should just have complete split.
892 */
893 first_count = first_data_bytes;
894 middle_count = max_t(int, 4, other_data_bytes);
895 end_count = 4;
896 }
897 } else {
898 if (qh->ep_is_in) {
899 int last;
900
901 /* Account for the start split */
902 qh->num_hs_transfers++;
903
904 /* Calculate "L" value from spec */
905 last = rel_uframe + qh->num_hs_transfers + 1;
906
907 /* Start with basic case */
908 if (last <= 6)
909 qh->num_hs_transfers += 2;
910 else
911 qh->num_hs_transfers += 1;
912
913 /* Adjust downwards */
914 if (last >= 6 && rel_uframe == 0)
915 qh->num_hs_transfers--;
916
917 /* 1st = start; rest can contain data */
918 first_count = 4;
919 middle_count = min_t(int, 188, bytecount);
920 end_count = middle_count;
921 } else {
922 /* All contain data, last might be smaller */
923 first_count = first_data_bytes;
924 middle_count = min_t(int, 188,
925 other_data_bytes);
926 end_count = other_data_bytes % 188;
927 }
928 }
929
930 /* Assign durations per uFrame */
931 qh->hs_transfers[0].duration_us = HS_USECS_ISO(first_count);
932 for (i = 1; i < qh->num_hs_transfers - 1; i++)
933 qh->hs_transfers[i].duration_us =
934 HS_USECS_ISO(middle_count);
935 if (qh->num_hs_transfers > 1)
936 qh->hs_transfers[qh->num_hs_transfers - 1].duration_us =
937 HS_USECS_ISO(end_count);
938
939 /*
940 * Assign start us. The call below to dwc2_hs_pmap_schedule()
941 * will start with these numbers but may adjust within the same
942 * microframe.
943 */
944 qh->hs_transfers[0].start_schedule_us =
945 ssplit_s_uframe * DWC2_HS_PERIODIC_US_PER_UFRAME;
946 for (i = 1; i < qh->num_hs_transfers; i++)
947 qh->hs_transfers[i].start_schedule_us =
948 ((second_s_uframe + i - 1) %
949 DWC2_HS_SCHEDULE_UFRAMES) *
950 DWC2_HS_PERIODIC_US_PER_UFRAME;
951
952 /* Try to schedule with filled in hs_transfers above */
953 for (i = 0; i < qh->num_hs_transfers; i++) {
954 err = dwc2_hs_pmap_schedule(hsotg, qh, true, i);
955 if (err)
956 break;
957 }
958
959 /* If we scheduled all w/out breaking out then we're all good */
960 if (i == qh->num_hs_transfers)
961 break;
962
963 for (; i >= 0; i--)
964 dwc2_hs_pmap_unschedule(hsotg, qh, i);
965
966 if (qh->schedule_low_speed)
967 dwc2_ls_pmap_unschedule(hsotg, qh);
968
969 /* Try again starting in the next microframe */
970 ls_search_slice = (start_s_uframe + 1) * DWC2_SLICES_PER_UFRAME;
971 }
972
973 if (ls_search_slice >= DWC2_LS_SCHEDULE_SLICES)
974 return -ENOSPC;
975
976 return 0;
977}
978
979/**
980 * dwc2_uframe_schedule_hs - Schedule a QH for a periodic high speed xfer.
981 *
982 * Basically this just wraps dwc2_hs_pmap_schedule() to provide a clean
983 * interface.
984 *
985 * @hsotg: The HCD state structure for the DWC OTG controller.
986 * @qh: QH for the periodic transfer.
987 */
988static int dwc2_uframe_schedule_hs(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
989{
990 /* In non-split host and device time are the same */
991 WARN_ON(qh->host_us != qh->device_us);
992 WARN_ON(qh->host_interval != qh->device_interval);
993 WARN_ON(qh->num_hs_transfers != 1);
994
995 /* We'll have one transfer; init start to 0 before calling scheduler */
996 qh->hs_transfers[0].start_schedule_us = 0;
997 qh->hs_transfers[0].duration_us = qh->host_us;
998
999 return dwc2_hs_pmap_schedule(hsotg, qh, false, 0);
1000}
1001
1002/**
1003 * dwc2_uframe_schedule_ls - Schedule a QH for a periodic low/full speed xfer.
1004 *
1005 * Basically this just wraps dwc2_ls_pmap_schedule() to provide a clean
1006 * interface.
1007 *
1008 * @hsotg: The HCD state structure for the DWC OTG controller.
1009 * @qh: QH for the periodic transfer.
1010 */
1011static int dwc2_uframe_schedule_ls(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1012{
1013 /* In non-split host and device time are the same */
1014 WARN_ON(qh->host_us != qh->device_us);
1015 WARN_ON(qh->host_interval != qh->device_interval);
1016 WARN_ON(!qh->schedule_low_speed);
1017
1018 /* Run on the main low speed schedule (no split = no hub = no TT) */
1019 return dwc2_ls_pmap_schedule(hsotg, qh, 0);
1020}
1021
1022/**
1023 * dwc2_uframe_schedule - Schedule a QH for a periodic xfer.
1024 *
1025 * Calls one of the 3 sub-function depending on what type of transfer this QH
1026 * is for. Also adds some printing.
1027 *
1028 * @hsotg: The HCD state structure for the DWC OTG controller.
1029 * @qh: QH for the periodic transfer.
1030 */
1031static int dwc2_uframe_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1032{
1033 int ret;
1034
1035 if (qh->dev_speed == USB_SPEED_HIGH)
1036 ret = dwc2_uframe_schedule_hs(hsotg, qh);
1037 else if (!qh->do_split)
1038 ret = dwc2_uframe_schedule_ls(hsotg, qh);
1039 else
1040 ret = dwc2_uframe_schedule_split(hsotg, qh);
1041
1042 if (ret)
1043 dwc2_sch_dbg(hsotg, "QH=%p Failed to schedule %d\n", qh, ret);
1044 else
1045 dwc2_qh_schedule_print(hsotg, qh);
1046
1047 return ret;
1048}
1049
1050/**
1051 * dwc2_uframe_unschedule - Undoes dwc2_uframe_schedule().
1052 *
1053 * @hsotg: The HCD state structure for the DWC OTG controller.
1054 * @qh: QH for the periodic transfer.
1055 */
1056static void dwc2_uframe_unschedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1057{
1058 int i;
1059
1060 for (i = 0; i < qh->num_hs_transfers; i++)
1061 dwc2_hs_pmap_unschedule(hsotg, qh, i);
1062
1063 if (qh->schedule_low_speed)
1064 dwc2_ls_pmap_unschedule(hsotg, qh);
1065
1066 dwc2_sch_dbg(hsotg, "QH=%p Unscheduled\n", qh);
1067}
1068
1069/**
1070 * dwc2_pick_first_frame() - Choose 1st frame for qh that's already scheduled
1071 *
1072 * Takes a qh that has already been scheduled (which means we know we have the
1073 * bandwdith reserved for us) and set the next_active_frame and the
1074 * start_active_frame.
1075 *
1076 * This is expected to be called on qh's that weren't previously actively
1077 * running. It just picks the next frame that we can fit into without any
1078 * thought about the past.
1079 *
1080 * @hsotg: The HCD state structure for the DWC OTG controller
1081 * @qh: QH for a periodic endpoint
1082 *
1083 */
1084static void dwc2_pick_first_frame(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1085{
1086 u16 frame_number;
1087 u16 earliest_frame;
1088 u16 next_active_frame;
1089 u16 relative_frame;
1090 u16 interval;
1091
1092 /*
1093 * Use the real frame number rather than the cached value as of the
1094 * last SOF to give us a little extra slop.
1095 */
1096 frame_number = dwc2_hcd_get_frame_number(hsotg);
1097
1098 /*
1099 * We wouldn't want to start any earlier than the next frame just in
1100 * case the frame number ticks as we're doing this calculation.
1101 *
1102 * NOTE: if we could quantify how long till we actually get scheduled
1103 * we might be able to avoid the "+ 1" by looking at the upper part of
1104 * HFNUM (the FRREM field). For now we'll just use the + 1 though.
1105 */
1106 earliest_frame = dwc2_frame_num_inc(frame_number, 1);
1107 next_active_frame = earliest_frame;
1108
1109 /* Get the "no microframe schduler" out of the way... */
1110 if (hsotg->params.uframe_sched <= 0) {
1111 if (qh->do_split)
1112 /* Splits are active at microframe 0 minus 1 */
1113 next_active_frame |= 0x7;
1114 goto exit;
1115 }
1116
1117 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
1118 /*
1119 * We're either at high speed or we're doing a split (which
1120 * means we're talking high speed to a hub). In any case
1121 * the first frame should be based on when the first scheduled
1122 * event is.
1123 */
1124 WARN_ON(qh->num_hs_transfers < 1);
1125
1126 relative_frame = qh->hs_transfers[0].start_schedule_us /
1127 DWC2_HS_PERIODIC_US_PER_UFRAME;
1128
1129 /* Adjust interval as per high speed schedule */
1130 interval = gcd(qh->host_interval, DWC2_HS_SCHEDULE_UFRAMES);
1131
1132 } else {
1133 /*
1134 * Low or full speed directly on dwc2. Just about the same
1135 * as high speed but on a different schedule and with slightly
1136 * different adjustments. Note that this works because when
1137 * the host and device are both low speed then frames in the
1138 * controller tick at low speed.
1139 */
1140 relative_frame = qh->ls_start_schedule_slice /
1141 DWC2_LS_PERIODIC_SLICES_PER_FRAME;
1142 interval = gcd(qh->host_interval, DWC2_LS_SCHEDULE_FRAMES);
1143 }
1144
1145 /* Scheduler messed up if frame is past interval */
1146 WARN_ON(relative_frame >= interval);
1147
1148 /*
1149 * We know interval must divide (HFNUM_MAX_FRNUM + 1) now that we've
1150 * done the gcd(), so it's safe to move to the beginning of the current
1151 * interval like this.
1152 *
1153 * After this we might be before earliest_frame, but don't worry,
1154 * we'll fix it...
1155 */
1156 next_active_frame = (next_active_frame / interval) * interval;
1157
1158 /*
1159 * Actually choose to start at the frame number we've been
1160 * scheduled for.
1161 */
1162 next_active_frame = dwc2_frame_num_inc(next_active_frame,
1163 relative_frame);
1164
1165 /*
1166 * We actually need 1 frame before since the next_active_frame is
1167 * the frame number we'll be put on the ready list and we won't be on
1168 * the bus until 1 frame later.
1169 */
1170 next_active_frame = dwc2_frame_num_dec(next_active_frame, 1);
1171
1172 /*
1173 * By now we might actually be before the earliest_frame. Let's move
1174 * up intervals until we're not.
1175 */
1176 while (dwc2_frame_num_gt(earliest_frame, next_active_frame))
1177 next_active_frame = dwc2_frame_num_inc(next_active_frame,
1178 interval);
1179
1180exit:
1181 qh->next_active_frame = next_active_frame;
1182 qh->start_active_frame = next_active_frame;
1183
1184 dwc2_sch_vdbg(hsotg, "QH=%p First fn=%04x nxt=%04x\n",
1185 qh, frame_number, qh->next_active_frame);
1186}
1187
1188/**
1189 * dwc2_do_reserve() - Make a periodic reservation
1190 *
1191 * Try to allocate space in the periodic schedule. Depending on parameters
1192 * this might use the microframe scheduler or the dumb scheduler.
1193 *
1194 * @hsotg: The HCD state structure for the DWC OTG controller
1195 * @qh: QH for the periodic transfer.
1196 *
1197 * Returns: 0 upon success; error upon failure.
1198 */
1199static int dwc2_do_reserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1200{
1201 int status;
1202
1203 if (hsotg->params.uframe_sched > 0) {
1204 status = dwc2_uframe_schedule(hsotg, qh);
1205 } else {
1206 status = dwc2_periodic_channel_available(hsotg);
1207 if (status) {
1208 dev_info(hsotg->dev,
1209 "%s: No host channel available for periodic transfer\n",
1210 __func__);
1211 return status;
1212 }
1213
1214 status = dwc2_check_periodic_bandwidth(hsotg, qh);
1215 }
1216
1217 if (status) {
1218 dev_dbg(hsotg->dev,
1219 "%s: Insufficient periodic bandwidth for periodic transfer\n",
1220 __func__);
1221 return status;
1222 }
1223
1224 if (hsotg->params.uframe_sched <= 0)
1225 /* Reserve periodic channel */
1226 hsotg->periodic_channels++;
1227
1228 /* Update claimed usecs per (micro)frame */
1229 hsotg->periodic_usecs += qh->host_us;
1230
1231 dwc2_pick_first_frame(hsotg, qh);
1232
1233 return 0;
1234}
1235
1236/**
1237 * dwc2_do_unreserve() - Actually release the periodic reservation
1238 *
1239 * This function actually releases the periodic bandwidth that was reserved
1240 * by the given qh.
1241 *
1242 * @hsotg: The HCD state structure for the DWC OTG controller
1243 * @qh: QH for the periodic transfer.
1244 */
1245static void dwc2_do_unreserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1246{
1247 assert_spin_locked(&hsotg->lock);
1248
1249 WARN_ON(!qh->unreserve_pending);
1250
1251 /* No more unreserve pending--we're doing it */
1252 qh->unreserve_pending = false;
1253
1254 if (WARN_ON(!list_empty(&qh->qh_list_entry)))
1255 list_del_init(&qh->qh_list_entry);
1256
1257 /* Update claimed usecs per (micro)frame */
1258 hsotg->periodic_usecs -= qh->host_us;
1259
1260 if (hsotg->params.uframe_sched > 0) {
1261 dwc2_uframe_unschedule(hsotg, qh);
1262 } else {
1263 /* Release periodic channel reservation */
1264 hsotg->periodic_channels--;
1265 }
1266}
1267
1268/**
1269 * dwc2_unreserve_timer_fn() - Timer function to release periodic reservation
1270 *
1271 * According to the kernel doc for usb_submit_urb() (specifically the part about
1272 * "Reserved Bandwidth Transfers"), we need to keep a reservation active as
1273 * long as a device driver keeps submitting. Since we're using HCD_BH to give
1274 * back the URB we need to give the driver a little bit of time before we
1275 * release the reservation. This worker is called after the appropriate
1276 * delay.
1277 *
1278 * @work: Pointer to a qh unreserve_work.
1279 */
1280static void dwc2_unreserve_timer_fn(unsigned long data)
1281{
1282 struct dwc2_qh *qh = (struct dwc2_qh *)data;
1283 struct dwc2_hsotg *hsotg = qh->hsotg;
1284 unsigned long flags;
1285
1286 /*
1287 * Wait for the lock, or for us to be scheduled again. We
1288 * could be scheduled again if:
1289 * - We started executing but didn't get the lock yet.
1290 * - A new reservation came in, but cancel didn't take effect
1291 * because we already started executing.
1292 * - The timer has been kicked again.
1293 * In that case cancel and wait for the next call.
1294 */
1295 while (!spin_trylock_irqsave(&hsotg->lock, flags)) {
1296 if (timer_pending(&qh->unreserve_timer))
1297 return;
1298 }
1299
1300 /*
1301 * Might be no more unreserve pending if:
1302 * - We started executing but didn't get the lock yet.
1303 * - A new reservation came in, but cancel didn't take effect
1304 * because we already started executing.
1305 *
1306 * We can't put this in the loop above because unreserve_pending needs
1307 * to be accessed under lock, so we can only check it once we got the
1308 * lock.
1309 */
1310 if (qh->unreserve_pending)
1311 dwc2_do_unreserve(hsotg, qh);
1312
1313 spin_unlock_irqrestore(&hsotg->lock, flags);
1314}
1315
1316/**
1317 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a
1318 * host channel is large enough to handle the maximum data transfer in a single
1319 * (micro)frame for a periodic transfer
1320 *
1321 * @hsotg: The HCD state structure for the DWC OTG controller
1322 * @qh: QH for a periodic endpoint
1323 *
1324 * Return: 0 if successful, negative error code otherwise
1325 */
1326static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg,
1327 struct dwc2_qh *qh)
1328{
1329 u32 max_xfer_size;
1330 u32 max_channel_xfer_size;
1331 int status = 0;
1332
1333 max_xfer_size = dwc2_max_packet(qh->maxp) * dwc2_hb_mult(qh->maxp);
1334 max_channel_xfer_size = hsotg->params.max_transfer_size;
1335
1336 if (max_xfer_size > max_channel_xfer_size) {
1337 dev_err(hsotg->dev,
1338 "%s: Periodic xfer length %d > max xfer length for channel %d\n",
1339 __func__, max_xfer_size, max_channel_xfer_size);
1340 status = -ENOSPC;
1341 }
1342
1343 return status;
1344}
1345
1346/**
1347 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in
1348 * the periodic schedule
1349 *
1350 * @hsotg: The HCD state structure for the DWC OTG controller
1351 * @qh: QH for the periodic transfer. The QH should already contain the
1352 * scheduling information.
1353 *
1354 * Return: 0 if successful, negative error code otherwise
1355 */
1356static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1357{
1358 int status;
1359
1360 status = dwc2_check_max_xfer_size(hsotg, qh);
1361 if (status) {
1362 dev_dbg(hsotg->dev,
1363 "%s: Channel max transfer size too small for periodic transfer\n",
1364 __func__);
1365 return status;
1366 }
1367
1368 /* Cancel pending unreserve; if canceled OK, unreserve was pending */
1369 if (del_timer(&qh->unreserve_timer))
1370 WARN_ON(!qh->unreserve_pending);
1371
1372 /*
1373 * Only need to reserve if there's not an unreserve pending, since if an
1374 * unreserve is pending then by definition our old reservation is still
1375 * valid. Unreserve might still be pending even if we didn't cancel if
1376 * dwc2_unreserve_timer_fn() already started. Code in the timer handles
1377 * that case.
1378 */
1379 if (!qh->unreserve_pending) {
1380 status = dwc2_do_reserve(hsotg, qh);
1381 if (status)
1382 return status;
1383 } else {
1384 /*
1385 * It might have been a while, so make sure that frame_number
1386 * is still good. Note: we could also try to use the similar
1387 * dwc2_next_periodic_start() but that schedules much more
1388 * tightly and we might need to hurry and queue things up.
1389 */
1390 if (dwc2_frame_num_le(qh->next_active_frame,
1391 hsotg->frame_number))
1392 dwc2_pick_first_frame(hsotg, qh);
1393 }
1394
1395 qh->unreserve_pending = 0;
1396
1397 if (hsotg->params.dma_desc_enable > 0)
1398 /* Don't rely on SOF and start in ready schedule */
1399 list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
1400 else
1401 /* Always start in inactive schedule */
1402 list_add_tail(&qh->qh_list_entry,
1403 &hsotg->periodic_sched_inactive);
1404
1405 return 0;
1406}
1407
1408/**
1409 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer
1410 * from the periodic schedule
1411 *
1412 * @hsotg: The HCD state structure for the DWC OTG controller
1413 * @qh: QH for the periodic transfer
1414 */
1415static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg,
1416 struct dwc2_qh *qh)
1417{
1418 bool did_modify;
1419
1420 assert_spin_locked(&hsotg->lock);
1421
1422 /*
1423 * Schedule the unreserve to happen in a little bit. Cases here:
1424 * - Unreserve worker might be sitting there waiting to grab the lock.
1425 * In this case it will notice it's been schedule again and will
1426 * quit.
1427 * - Unreserve worker might not be scheduled.
1428 *
1429 * We should never already be scheduled since dwc2_schedule_periodic()
1430 * should have canceled the scheduled unreserve timer (hence the
1431 * warning on did_modify).
1432 *
1433 * We add + 1 to the timer to guarantee that at least 1 jiffy has
1434 * passed (otherwise if the jiffy counter might tick right after we
1435 * read it and we'll get no delay).
1436 */
1437 did_modify = mod_timer(&qh->unreserve_timer,
1438 jiffies + DWC2_UNRESERVE_DELAY + 1);
1439 WARN_ON(did_modify);
1440 qh->unreserve_pending = 1;
1441
1442 list_del_init(&qh->qh_list_entry);
1443}
1444
1445/**
1446 * dwc2_qh_init() - Initializes a QH structure
1447 *
1448 * @hsotg: The HCD state structure for the DWC OTG controller
1449 * @qh: The QH to init
1450 * @urb: Holds the information about the device/endpoint needed to initialize
1451 * the QH
1452 * @mem_flags: Flags for allocating memory.
1453 */
1454static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1455 struct dwc2_hcd_urb *urb, gfp_t mem_flags)
1456{
1457 int dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
1458 u8 ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1459 bool ep_is_in = !!dwc2_hcd_is_pipe_in(&urb->pipe_info);
1460 bool ep_is_isoc = (ep_type == USB_ENDPOINT_XFER_ISOC);
1461 bool ep_is_int = (ep_type == USB_ENDPOINT_XFER_INT);
1462 u32 hprt = dwc2_readl(hsotg->regs + HPRT0);
1463 u32 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1464 bool do_split = (prtspd == HPRT0_SPD_HIGH_SPEED &&
1465 dev_speed != USB_SPEED_HIGH);
1466 int maxp = dwc2_hcd_get_mps(&urb->pipe_info);
1467 int bytecount = dwc2_hb_mult(maxp) * dwc2_max_packet(maxp);
1468 char *speed, *type;
1469
1470 /* Initialize QH */
1471 qh->hsotg = hsotg;
1472 setup_timer(&qh->unreserve_timer, dwc2_unreserve_timer_fn,
1473 (unsigned long)qh);
1474 qh->ep_type = ep_type;
1475 qh->ep_is_in = ep_is_in;
1476
1477 qh->data_toggle = DWC2_HC_PID_DATA0;
1478 qh->maxp = maxp;
1479 INIT_LIST_HEAD(&qh->qtd_list);
1480 INIT_LIST_HEAD(&qh->qh_list_entry);
1481
1482 qh->do_split = do_split;
1483 qh->dev_speed = dev_speed;
1484
1485 if (ep_is_int || ep_is_isoc) {
1486 /* Compute scheduling parameters once and save them */
1487 int host_speed = do_split ? USB_SPEED_HIGH : dev_speed;
1488 struct dwc2_tt *dwc_tt = dwc2_host_get_tt_info(hsotg, urb->priv,
1489 mem_flags,
1490 &qh->ttport);
1491 int device_ns;
1492
1493 qh->dwc_tt = dwc_tt;
1494
1495 qh->host_us = NS_TO_US(usb_calc_bus_time(host_speed, ep_is_in,
1496 ep_is_isoc, bytecount));
1497 device_ns = usb_calc_bus_time(dev_speed, ep_is_in,
1498 ep_is_isoc, bytecount);
1499
1500 if (do_split && dwc_tt)
1501 device_ns += dwc_tt->usb_tt->think_time;
1502 qh->device_us = NS_TO_US(device_ns);
1503
1504
1505 qh->device_interval = urb->interval;
1506 qh->host_interval = urb->interval * (do_split ? 8 : 1);
1507
1508 /*
1509 * Schedule low speed if we're running the host in low or
1510 * full speed OR if we've got a "TT" to deal with to access this
1511 * device.
1512 */
1513 qh->schedule_low_speed = prtspd != HPRT0_SPD_HIGH_SPEED ||
1514 dwc_tt;
1515
1516 if (do_split) {
1517 /* We won't know num transfers until we schedule */
1518 qh->num_hs_transfers = -1;
1519 } else if (dev_speed == USB_SPEED_HIGH) {
1520 qh->num_hs_transfers = 1;
1521 } else {
1522 qh->num_hs_transfers = 0;
1523 }
1524
1525 /* We'll schedule later when we have something to do */
1526 }
1527
1528 switch (dev_speed) {
1529 case USB_SPEED_LOW:
1530 speed = "low";
1531 break;
1532 case USB_SPEED_FULL:
1533 speed = "full";
1534 break;
1535 case USB_SPEED_HIGH:
1536 speed = "high";
1537 break;
1538 default:
1539 speed = "?";
1540 break;
1541 }
1542
1543 switch (qh->ep_type) {
1544 case USB_ENDPOINT_XFER_ISOC:
1545 type = "isochronous";
1546 break;
1547 case USB_ENDPOINT_XFER_INT:
1548 type = "interrupt";
1549 break;
1550 case USB_ENDPOINT_XFER_CONTROL:
1551 type = "control";
1552 break;
1553 case USB_ENDPOINT_XFER_BULK:
1554 type = "bulk";
1555 break;
1556 default:
1557 type = "?";
1558 break;
1559 }
1560
1561 dwc2_sch_dbg(hsotg, "QH=%p Init %s, %s speed, %d bytes:\n", qh, type,
1562 speed, bytecount);
1563 dwc2_sch_dbg(hsotg, "QH=%p ...addr=%d, ep=%d, %s\n", qh,
1564 dwc2_hcd_get_dev_addr(&urb->pipe_info),
1565 dwc2_hcd_get_ep_num(&urb->pipe_info),
1566 ep_is_in ? "IN" : "OUT");
1567 if (ep_is_int || ep_is_isoc) {
1568 dwc2_sch_dbg(hsotg,
1569 "QH=%p ...duration: host=%d us, device=%d us\n",
1570 qh, qh->host_us, qh->device_us);
1571 dwc2_sch_dbg(hsotg, "QH=%p ...interval: host=%d, device=%d\n",
1572 qh, qh->host_interval, qh->device_interval);
1573 if (qh->schedule_low_speed)
1574 dwc2_sch_dbg(hsotg, "QH=%p ...low speed schedule=%p\n",
1575 qh, dwc2_get_ls_map(hsotg, qh));
1576 }
1577}
1578
1579/**
1580 * dwc2_hcd_qh_create() - Allocates and initializes a QH
1581 *
1582 * @hsotg: The HCD state structure for the DWC OTG controller
1583 * @urb: Holds the information about the device/endpoint needed
1584 * to initialize the QH
1585 * @atomic_alloc: Flag to do atomic allocation if needed
1586 *
1587 * Return: Pointer to the newly allocated QH, or NULL on error
1588 */
1589struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
1590 struct dwc2_hcd_urb *urb,
1591 gfp_t mem_flags)
1592{
1593 struct dwc2_qh *qh;
1594
1595 if (!urb->priv)
1596 return NULL;
1597
1598 /* Allocate memory */
1599 qh = kzalloc(sizeof(*qh), mem_flags);
1600 if (!qh)
1601 return NULL;
1602
1603 dwc2_qh_init(hsotg, qh, urb, mem_flags);
1604
1605 if (hsotg->params.dma_desc_enable > 0 &&
1606 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) {
1607 dwc2_hcd_qh_free(hsotg, qh);
1608 return NULL;
1609 }
1610
1611 return qh;
1612}
1613
1614/**
1615 * dwc2_hcd_qh_free() - Frees the QH
1616 *
1617 * @hsotg: HCD instance
1618 * @qh: The QH to free
1619 *
1620 * QH should already be removed from the list. QTD list should already be empty
1621 * if called from URB Dequeue.
1622 *
1623 * Must NOT be called with interrupt disabled or spinlock held
1624 */
1625void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1626{
1627 /* Make sure any unreserve work is finished. */
1628 if (del_timer_sync(&qh->unreserve_timer)) {
1629 unsigned long flags;
1630
1631 spin_lock_irqsave(&hsotg->lock, flags);
1632 dwc2_do_unreserve(hsotg, qh);
1633 spin_unlock_irqrestore(&hsotg->lock, flags);
1634 }
1635 dwc2_host_put_tt_info(hsotg, qh->dwc_tt);
1636
1637 if (qh->desc_list)
1638 dwc2_hcd_qh_free_ddma(hsotg, qh);
1639 kfree(qh);
1640}
1641
1642/**
1643 * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic
1644 * schedule if it is not already in the schedule. If the QH is already in
1645 * the schedule, no action is taken.
1646 *
1647 * @hsotg: The HCD state structure for the DWC OTG controller
1648 * @qh: The QH to add
1649 *
1650 * Return: 0 if successful, negative error code otherwise
1651 */
1652int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1653{
1654 int status;
1655 u32 intr_mask;
1656
1657 if (dbg_qh(qh))
1658 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1659
1660 if (!list_empty(&qh->qh_list_entry))
1661 /* QH already in a schedule */
1662 return 0;
1663
1664 /* Add the new QH to the appropriate schedule */
1665 if (dwc2_qh_is_non_per(qh)) {
1666 /* Schedule right away */
1667 qh->start_active_frame = hsotg->frame_number;
1668 qh->next_active_frame = qh->start_active_frame;
1669
1670 /* Always start in inactive schedule */
1671 list_add_tail(&qh->qh_list_entry,
1672 &hsotg->non_periodic_sched_inactive);
1673 return 0;
1674 }
1675
1676 status = dwc2_schedule_periodic(hsotg, qh);
1677 if (status)
1678 return status;
1679 if (!hsotg->periodic_qh_count) {
1680 intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
1681 intr_mask |= GINTSTS_SOF;
1682 dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
1683 }
1684 hsotg->periodic_qh_count++;
1685
1686 return 0;
1687}
1688
1689/**
1690 * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic
1691 * schedule. Memory is not freed.
1692 *
1693 * @hsotg: The HCD state structure
1694 * @qh: QH to remove from schedule
1695 */
1696void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1697{
1698 u32 intr_mask;
1699
1700 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1701
1702 if (list_empty(&qh->qh_list_entry))
1703 /* QH is not in a schedule */
1704 return;
1705
1706 if (dwc2_qh_is_non_per(qh)) {
1707 if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry)
1708 hsotg->non_periodic_qh_ptr =
1709 hsotg->non_periodic_qh_ptr->next;
1710 list_del_init(&qh->qh_list_entry);
1711 return;
1712 }
1713
1714 dwc2_deschedule_periodic(hsotg, qh);
1715 hsotg->periodic_qh_count--;
1716 if (!hsotg->periodic_qh_count &&
1717 hsotg->params.dma_desc_enable <= 0) {
1718 intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
1719 intr_mask &= ~GINTSTS_SOF;
1720 dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
1721 }
1722}
1723
1724/**
1725 * dwc2_next_for_periodic_split() - Set next_active_frame midway thru a split.
1726 *
1727 * This is called for setting next_active_frame for periodic splits for all but
1728 * the first packet of the split. Confusing? I thought so...
1729 *
1730 * Periodic splits are single low/full speed transfers that we end up splitting
1731 * up into several high speed transfers. They always fit into one full (1 ms)
1732 * frame but might be split over several microframes (125 us each). We to put
1733 * each of the parts on a very specific high speed frame.
1734 *
1735 * This function figures out where the next active uFrame needs to be.
1736 *
1737 * @hsotg: The HCD state structure
1738 * @qh: QH for the periodic transfer.
1739 * @frame_number: The current frame number.
1740 *
1741 * Return: number missed by (or 0 if we didn't miss).
1742 */
1743static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg,
1744 struct dwc2_qh *qh, u16 frame_number)
1745{
1746 u16 old_frame = qh->next_active_frame;
1747 u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1);
1748 int missed = 0;
1749 u16 incr;
1750
1751 /*
1752 * See dwc2_uframe_schedule_split() for split scheduling.
1753 *
1754 * Basically: increment 1 normally, but 2 right after the start split
1755 * (except for ISOC out).
1756 */
1757 if (old_frame == qh->start_active_frame &&
1758 !(qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in))
1759 incr = 2;
1760 else
1761 incr = 1;
1762
1763 qh->next_active_frame = dwc2_frame_num_inc(old_frame, incr);
1764
1765 /*
1766 * Note that it's OK for frame_number to be 1 frame past
1767 * next_active_frame. Remember that next_active_frame is supposed to
1768 * be 1 frame _before_ when we want to be scheduled. If we're 1 frame
1769 * past it just means schedule ASAP.
1770 *
1771 * It's _not_ OK, however, if we're more than one frame past.
1772 */
1773 if (dwc2_frame_num_gt(prev_frame_number, qh->next_active_frame)) {
1774 /*
1775 * OOPS, we missed. That's actually pretty bad since
1776 * the hub will be unhappy; try ASAP I guess.
1777 */
1778 missed = dwc2_frame_num_dec(prev_frame_number,
1779 qh->next_active_frame);
1780 qh->next_active_frame = frame_number;
1781 }
1782
1783 return missed;
1784}
1785
1786/**
1787 * dwc2_next_periodic_start() - Set next_active_frame for next transfer start
1788 *
1789 * This is called for setting next_active_frame for a periodic transfer for
1790 * all cases other than midway through a periodic split. This will also update
1791 * start_active_frame.
1792 *
1793 * Since we _always_ keep start_active_frame as the start of the previous
1794 * transfer this is normally pretty easy: we just add our interval to
1795 * start_active_frame and we've got our answer.
1796 *
1797 * The tricks come into play if we miss. In that case we'll look for the next
1798 * slot we can fit into.
1799 *
1800 * @hsotg: The HCD state structure
1801 * @qh: QH for the periodic transfer.
1802 * @frame_number: The current frame number.
1803 *
1804 * Return: number missed by (or 0 if we didn't miss).
1805 */
1806static int dwc2_next_periodic_start(struct dwc2_hsotg *hsotg,
1807 struct dwc2_qh *qh, u16 frame_number)
1808{
1809 int missed = 0;
1810 u16 interval = qh->host_interval;
1811 u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1);
1812
1813 qh->start_active_frame = dwc2_frame_num_inc(qh->start_active_frame,
1814 interval);
1815
1816 /*
1817 * The dwc2_frame_num_gt() function used below won't work terribly well
1818 * with if we just incremented by a really large intervals since the
1819 * frame counter only goes to 0x3fff. It's terribly unlikely that we
1820 * will have missed in this case anyway. Just go to exit. If we want
1821 * to try to do better we'll need to keep track of a bigger counter
1822 * somewhere in the driver and handle overflows.
1823 */
1824 if (interval >= 0x1000)
1825 goto exit;
1826
1827 /*
1828 * Test for misses, which is when it's too late to schedule.
1829 *
1830 * A few things to note:
1831 * - We compare against prev_frame_number since start_active_frame
1832 * and next_active_frame are always 1 frame before we want things
1833 * to be active and we assume we can still get scheduled in the
1834 * current frame number.
1835 * - It's possible for start_active_frame (now incremented) to be
1836 * next_active_frame if we got an EO MISS (even_odd miss) which
1837 * basically means that we detected there wasn't enough time for
1838 * the last packet and dwc2_hc_set_even_odd_frame() rescheduled us
1839 * at the last second. We want to make sure we don't schedule
1840 * another transfer for the same frame. My test webcam doesn't seem
1841 * terribly upset by missing a transfer but really doesn't like when
1842 * we do two transfers in the same frame.
1843 * - Some misses are expected. Specifically, in order to work
1844 * perfectly dwc2 really needs quite spectacular interrupt latency
1845 * requirements. It needs to be able to handle its interrupts
1846 * completely within 125 us of them being asserted. That not only
1847 * means that the dwc2 interrupt handler needs to be fast but it
1848 * means that nothing else in the system has to block dwc2 for a long
1849 * time. We can help with the dwc2 parts of this, but it's hard to
1850 * guarantee that a system will have interrupt latency < 125 us, so
1851 * we have to be robust to some misses.
1852 */
1853 if (qh->start_active_frame == qh->next_active_frame ||
1854 dwc2_frame_num_gt(prev_frame_number, qh->start_active_frame)) {
1855 u16 ideal_start = qh->start_active_frame;
1856 int periods_in_map;
1857
1858 /*
1859 * Adjust interval as per gcd with map size.
1860 * See pmap_schedule() for more details here.
1861 */
1862 if (qh->do_split || qh->dev_speed == USB_SPEED_HIGH)
1863 periods_in_map = DWC2_HS_SCHEDULE_UFRAMES;
1864 else
1865 periods_in_map = DWC2_LS_SCHEDULE_FRAMES;
1866 interval = gcd(interval, periods_in_map);
1867
1868 do {
1869 qh->start_active_frame = dwc2_frame_num_inc(
1870 qh->start_active_frame, interval);
1871 } while (dwc2_frame_num_gt(prev_frame_number,
1872 qh->start_active_frame));
1873
1874 missed = dwc2_frame_num_dec(qh->start_active_frame,
1875 ideal_start);
1876 }
1877
1878exit:
1879 qh->next_active_frame = qh->start_active_frame;
1880
1881 return missed;
1882}
1883
1884/*
1885 * Deactivates a QH. For non-periodic QHs, removes the QH from the active
1886 * non-periodic schedule. The QH is added to the inactive non-periodic
1887 * schedule if any QTDs are still attached to the QH.
1888 *
1889 * For periodic QHs, the QH is removed from the periodic queued schedule. If
1890 * there are any QTDs still attached to the QH, the QH is added to either the
1891 * periodic inactive schedule or the periodic ready schedule and its next
1892 * scheduled frame is calculated. The QH is placed in the ready schedule if
1893 * the scheduled frame has been reached already. Otherwise it's placed in the
1894 * inactive schedule. If there are no QTDs attached to the QH, the QH is
1895 * completely removed from the periodic schedule.
1896 */
1897void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1898 int sched_next_periodic_split)
1899{
1900 u16 old_frame = qh->next_active_frame;
1901 u16 frame_number;
1902 int missed;
1903
1904 if (dbg_qh(qh))
1905 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1906
1907 if (dwc2_qh_is_non_per(qh)) {
1908 dwc2_hcd_qh_unlink(hsotg, qh);
1909 if (!list_empty(&qh->qtd_list))
1910 /* Add back to inactive non-periodic schedule */
1911 dwc2_hcd_qh_add(hsotg, qh);
1912 return;
1913 }
1914
1915 /*
1916 * Use the real frame number rather than the cached value as of the
1917 * last SOF just to get us a little closer to reality. Note that
1918 * means we don't actually know if we've already handled the SOF
1919 * interrupt for this frame.
1920 */
1921 frame_number = dwc2_hcd_get_frame_number(hsotg);
1922
1923 if (sched_next_periodic_split)
1924 missed = dwc2_next_for_periodic_split(hsotg, qh, frame_number);
1925 else
1926 missed = dwc2_next_periodic_start(hsotg, qh, frame_number);
1927
1928 dwc2_sch_vdbg(hsotg,
1929 "QH=%p next(%d) fn=%04x, sch=%04x=>%04x (%+d) miss=%d %s\n",
1930 qh, sched_next_periodic_split, frame_number, old_frame,
1931 qh->next_active_frame,
1932 dwc2_frame_num_dec(qh->next_active_frame, old_frame),
1933 missed, missed ? "MISS" : "");
1934
1935 if (list_empty(&qh->qtd_list)) {
1936 dwc2_hcd_qh_unlink(hsotg, qh);
1937 return;
1938 }
1939
1940 /*
1941 * Remove from periodic_sched_queued and move to
1942 * appropriate queue
1943 *
1944 * Note: we purposely use the frame_number from the "hsotg" structure
1945 * since we know SOF interrupt will handle future frames.
1946 */
1947 if (dwc2_frame_num_le(qh->next_active_frame, hsotg->frame_number))
1948 list_move_tail(&qh->qh_list_entry,
1949 &hsotg->periodic_sched_ready);
1950 else
1951 list_move_tail(&qh->qh_list_entry,
1952 &hsotg->periodic_sched_inactive);
1953}
1954
1955/**
1956 * dwc2_hcd_qtd_init() - Initializes a QTD structure
1957 *
1958 * @qtd: The QTD to initialize
1959 * @urb: The associated URB
1960 */
1961void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
1962{
1963 qtd->urb = urb;
1964 if (dwc2_hcd_get_pipe_type(&urb->pipe_info) ==
1965 USB_ENDPOINT_XFER_CONTROL) {
1966 /*
1967 * The only time the QTD data toggle is used is on the data
1968 * phase of control transfers. This phase always starts with
1969 * DATA1.
1970 */
1971 qtd->data_toggle = DWC2_HC_PID_DATA1;
1972 qtd->control_phase = DWC2_CONTROL_SETUP;
1973 }
1974
1975 /* Start split */
1976 qtd->complete_split = 0;
1977 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1978 qtd->isoc_split_offset = 0;
1979 qtd->in_process = 0;
1980
1981 /* Store the qtd ptr in the urb to reference the QTD */
1982 urb->qtd = qtd;
1983}
1984
1985/**
1986 * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH
1987 * Caller must hold driver lock.
1988 *
1989 * @hsotg: The DWC HCD structure
1990 * @qtd: The QTD to add
1991 * @qh: Queue head to add qtd to
1992 *
1993 * Return: 0 if successful, negative error code otherwise
1994 *
1995 * If the QH to which the QTD is added is not currently scheduled, it is placed
1996 * into the proper schedule based on its EP type.
1997 */
1998int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
1999 struct dwc2_qh *qh)
2000{
2001 int retval;
2002
2003 if (unlikely(!qh)) {
2004 dev_err(hsotg->dev, "%s: Invalid QH\n", __func__);
2005 retval = -EINVAL;
2006 goto fail;
2007 }
2008
2009 retval = dwc2_hcd_qh_add(hsotg, qh);
2010 if (retval)
2011 goto fail;
2012
2013 qtd->qh = qh;
2014 list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);
2015
2016 return 0;
2017fail:
2018 return retval;
2019}