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1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * hcd.h - DesignWare HS OTG Controller host-mode declarations
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37#ifndef __DWC2_HCD_H__
38#define __DWC2_HCD_H__
39
40/*
41 * This file contains the structures, constants, and interfaces for the
42 * Host Contoller Driver (HCD)
43 *
44 * The Host Controller Driver (HCD) is responsible for translating requests
45 * from the USB Driver into the appropriate actions on the DWC_otg controller.
46 * It isolates the USBD from the specifics of the controller by providing an
47 * API to the USBD.
48 */
49
50struct dwc2_qh;
51
52/**
53 * struct dwc2_host_chan - Software host channel descriptor
54 *
55 * @hc_num: Host channel number, used for register address lookup
56 * @dev_addr: Address of the device
57 * @ep_num: Endpoint of the device
58 * @ep_is_in: Endpoint direction
59 * @speed: Device speed. One of the following values:
60 * - USB_SPEED_LOW
61 * - USB_SPEED_FULL
62 * - USB_SPEED_HIGH
63 * @ep_type: Endpoint type. One of the following values:
64 * - USB_ENDPOINT_XFER_CONTROL: 0
65 * - USB_ENDPOINT_XFER_ISOC: 1
66 * - USB_ENDPOINT_XFER_BULK: 2
67 * - USB_ENDPOINT_XFER_INTR: 3
68 * @max_packet: Max packet size in bytes
69 * @data_pid_start: PID for initial transaction.
70 * 0: DATA0
71 * 1: DATA2
72 * 2: DATA1
73 * 3: MDATA (non-Control EP),
74 * SETUP (Control EP)
75 * @multi_count: Number of additional periodic transactions per
76 * (micro)frame
77 * @xfer_buf: Pointer to current transfer buffer position
78 * @xfer_dma: DMA address of xfer_buf
79 * @xfer_len: Total number of bytes to transfer
80 * @xfer_count: Number of bytes transferred so far
81 * @start_pkt_count: Packet count at start of transfer
82 * @xfer_started: True if the transfer has been started
83 * @ping: True if a PING request should be issued on this channel
84 * @error_state: True if the error count for this transaction is non-zero
85 * @halt_on_queue: True if this channel should be halted the next time a
86 * request is queued for the channel. This is necessary in
87 * slave mode if no request queue space is available when
88 * an attempt is made to halt the channel.
89 * @halt_pending: True if the host channel has been halted, but the core
90 * is not finished flushing queued requests
91 * @do_split: Enable split for the channel
92 * @complete_split: Enable complete split
93 * @hub_addr: Address of high speed hub for the split
94 * @hub_port: Port of the low/full speed device for the split
95 * @xact_pos: Split transaction position. One of the following values:
96 * - DWC2_HCSPLT_XACTPOS_MID
97 * - DWC2_HCSPLT_XACTPOS_BEGIN
98 * - DWC2_HCSPLT_XACTPOS_END
99 * - DWC2_HCSPLT_XACTPOS_ALL
100 * @requests: Number of requests issued for this channel since it was
101 * assigned to the current transfer (not counting PINGs)
102 * @schinfo: Scheduling micro-frame bitmap
103 * @ntd: Number of transfer descriptors for the transfer
104 * @halt_status: Reason for halting the host channel
105 * @hcint Contents of the HCINT register when the interrupt came
106 * @qh: QH for the transfer being processed by this channel
107 * @hc_list_entry: For linking to list of host channels
108 * @desc_list_addr: Current QH's descriptor list DMA address
109 * @desc_list_sz: Current QH's descriptor list size
110 * @split_order_list_entry: List entry for keeping track of the order of splits
111 *
112 * This structure represents the state of a single host channel when acting in
113 * host mode. It contains the data items needed to transfer packets to an
114 * endpoint via a host channel.
115 */
116struct dwc2_host_chan {
117 u8 hc_num;
118
119 unsigned dev_addr:7;
120 unsigned ep_num:4;
121 unsigned ep_is_in:1;
122 unsigned speed:4;
123 unsigned ep_type:2;
124 unsigned max_packet:11;
125 unsigned data_pid_start:2;
126#define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0
127#define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2
128#define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1
129#define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA
130#define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP
131
132 unsigned multi_count:2;
133
134 u8 *xfer_buf;
135 dma_addr_t xfer_dma;
136 u32 xfer_len;
137 u32 xfer_count;
138 u16 start_pkt_count;
139 u8 xfer_started;
140 u8 do_ping;
141 u8 error_state;
142 u8 halt_on_queue;
143 u8 halt_pending;
144 u8 do_split;
145 u8 complete_split;
146 u8 hub_addr;
147 u8 hub_port;
148 u8 xact_pos;
149#define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID
150#define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END
151#define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN
152#define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL
153
154 u8 requests;
155 u8 schinfo;
156 u16 ntd;
157 enum dwc2_halt_status halt_status;
158 u32 hcint;
159 struct dwc2_qh *qh;
160 struct list_head hc_list_entry;
161 dma_addr_t desc_list_addr;
162 u32 desc_list_sz;
163 struct list_head split_order_list_entry;
164};
165
166struct dwc2_hcd_pipe_info {
167 u8 dev_addr;
168 u8 ep_num;
169 u8 pipe_type;
170 u8 pipe_dir;
171 u16 mps;
172};
173
174struct dwc2_hcd_iso_packet_desc {
175 u32 offset;
176 u32 length;
177 u32 actual_length;
178 u32 status;
179};
180
181struct dwc2_qtd;
182
183struct dwc2_hcd_urb {
184 void *priv;
185 struct dwc2_qtd *qtd;
186 void *buf;
187 dma_addr_t dma;
188 void *setup_packet;
189 dma_addr_t setup_dma;
190 u32 length;
191 u32 actual_length;
192 u32 status;
193 u32 error_count;
194 u32 packet_count;
195 u32 flags;
196 u16 interval;
197 struct dwc2_hcd_pipe_info pipe_info;
198 struct dwc2_hcd_iso_packet_desc iso_descs[0];
199};
200
201/* Phases for control transfers */
202enum dwc2_control_phase {
203 DWC2_CONTROL_SETUP,
204 DWC2_CONTROL_DATA,
205 DWC2_CONTROL_STATUS,
206};
207
208/* Transaction types */
209enum dwc2_transaction_type {
210 DWC2_TRANSACTION_NONE,
211 DWC2_TRANSACTION_PERIODIC,
212 DWC2_TRANSACTION_NON_PERIODIC,
213 DWC2_TRANSACTION_ALL,
214};
215
216/* The number of elements per LS bitmap (per port on multi_tt) */
217#define DWC2_ELEMENTS_PER_LS_BITMAP DIV_ROUND_UP(DWC2_LS_SCHEDULE_SLICES, \
218 BITS_PER_LONG)
219
220/**
221 * struct dwc2_tt - dwc2 data associated with a usb_tt
222 *
223 * @refcount: Number of Queue Heads (QHs) holding a reference.
224 * @usb_tt: Pointer back to the official usb_tt.
225 * @periodic_bitmaps: Bitmap for which parts of the 1ms frame are accounted
226 * for already. Each is DWC2_ELEMENTS_PER_LS_BITMAP
227 * elements (so sizeof(long) times that in bytes).
228 *
229 * This structure is stored in the hcpriv of the official usb_tt.
230 */
231struct dwc2_tt {
232 int refcount;
233 struct usb_tt *usb_tt;
234 unsigned long periodic_bitmaps[];
235};
236
237/**
238 * struct dwc2_hs_transfer_time - Info about a transfer on the high speed bus.
239 *
240 * @start_schedule_usecs: The start time on the main bus schedule. Note that
241 * the main bus schedule is tightly packed and this
242 * time should be interpreted as tightly packed (so
243 * uFrame 0 starts at 0 us, uFrame 1 starts at 100 us
244 * instead of 125 us).
245 * @duration_us: How long this transfer goes.
246 */
247
248struct dwc2_hs_transfer_time {
249 u32 start_schedule_us;
250 u16 duration_us;
251};
252
253/**
254 * struct dwc2_qh - Software queue head structure
255 *
256 * @hsotg: The HCD state structure for the DWC OTG controller
257 * @ep_type: Endpoint type. One of the following values:
258 * - USB_ENDPOINT_XFER_CONTROL
259 * - USB_ENDPOINT_XFER_BULK
260 * - USB_ENDPOINT_XFER_INT
261 * - USB_ENDPOINT_XFER_ISOC
262 * @ep_is_in: Endpoint direction
263 * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor
264 * @dev_speed: Device speed. One of the following values:
265 * - USB_SPEED_LOW
266 * - USB_SPEED_FULL
267 * - USB_SPEED_HIGH
268 * @data_toggle: Determines the PID of the next data packet for
269 * non-controltransfers. Ignored for control transfers.
270 * One of the following values:
271 * - DWC2_HC_PID_DATA0
272 * - DWC2_HC_PID_DATA1
273 * @ping_state: Ping state
274 * @do_split: Full/low speed endpoint on high-speed hub requires split
275 * @td_first: Index of first activated isochronous transfer descriptor
276 * @td_last: Index of last activated isochronous transfer descriptor
277 * @host_us: Bandwidth in microseconds per transfer as seen by host
278 * @device_us: Bandwidth in microseconds per transfer as seen by device
279 * @host_interval: Interval between transfers as seen by the host. If
280 * the host is high speed and the device is low speed this
281 * will be 8 times device interval.
282 * @device_interval: Interval between transfers as seen by the device.
283 * interval.
284 * @next_active_frame: (Micro)frame _before_ we next need to put something on
285 * the bus. We'll move the qh to active here. If the
286 * host is in high speed mode this will be a uframe. If
287 * the host is in low speed mode this will be a full frame.
288 * @start_active_frame: If we are partway through a split transfer, this will be
289 * what next_active_frame was when we started. Otherwise
290 * it should always be the same as next_active_frame.
291 * @num_hs_transfers: Number of transfers in hs_transfers.
292 * Normally this is 1 but can be more than one for splits.
293 * Always >= 1 unless the host is in low/full speed mode.
294 * @hs_transfers: Transfers that are scheduled as seen by the high speed
295 * bus. Not used if host is in low or full speed mode (but
296 * note that it IS USED if the device is low or full speed
297 * as long as the HOST is in high speed mode).
298 * @ls_start_schedule_slice: Start time (in slices) on the low speed bus
299 * schedule that's being used by this device. This
300 * will be on the periodic_bitmap in a
301 * "struct dwc2_tt". Not used if this device is high
302 * speed. Note that this is in "schedule slice" which
303 * is tightly packed.
304 * @ls_duration_us: Duration on the low speed bus schedule.
305 * @ntd: Actual number of transfer descriptors in a list
306 * @qtd_list: List of QTDs for this QH
307 * @channel: Host channel currently processing transfers for this QH
308 * @qh_list_entry: Entry for QH in either the periodic or non-periodic
309 * schedule
310 * @desc_list: List of transfer descriptors
311 * @desc_list_dma: Physical address of desc_list
312 * @desc_list_sz: Size of descriptors list
313 * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer
314 * descriptor and indicates original XferSize value for the
315 * descriptor
316 * @unreserve_timer: Timer for releasing periodic reservation.
317 * @wait_timer: Timer used to wait before re-queuing.
318 * @dwc2_tt: Pointer to our tt info (or NULL if no tt).
319 * @ttport: Port number within our tt.
320 * @tt_buffer_dirty True if clear_tt_buffer_complete is pending
321 * @unreserve_pending: True if we planned to unreserve but haven't yet.
322 * @schedule_low_speed: True if we have a low/full speed component (either the
323 * host is in low/full speed mode or do_split).
324 * @want_wait: We should wait before re-queuing; only matters for non-
325 * periodic transfers and is ignored for periodic ones.
326 * @wait_timer_cancel: Set to true to cancel the wait_timer.
327 *
328 * A Queue Head (QH) holds the static characteristics of an endpoint and
329 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
330 * be entered in either the non-periodic or periodic schedule.
331 */
332struct dwc2_qh {
333 struct dwc2_hsotg *hsotg;
334 u8 ep_type;
335 u8 ep_is_in;
336 u16 maxp;
337 u8 dev_speed;
338 u8 data_toggle;
339 u8 ping_state;
340 u8 do_split;
341 u8 td_first;
342 u8 td_last;
343 u16 host_us;
344 u16 device_us;
345 u16 host_interval;
346 u16 device_interval;
347 u16 next_active_frame;
348 u16 start_active_frame;
349 s16 num_hs_transfers;
350 struct dwc2_hs_transfer_time hs_transfers[DWC2_HS_SCHEDULE_UFRAMES];
351 u32 ls_start_schedule_slice;
352 u16 ntd;
353 struct list_head qtd_list;
354 struct dwc2_host_chan *channel;
355 struct list_head qh_list_entry;
356 struct dwc2_dma_desc *desc_list;
357 dma_addr_t desc_list_dma;
358 u32 desc_list_sz;
359 u32 *n_bytes;
360 struct timer_list unreserve_timer;
361 struct timer_list wait_timer;
362 struct dwc2_tt *dwc_tt;
363 int ttport;
364 unsigned tt_buffer_dirty:1;
365 unsigned unreserve_pending:1;
366 unsigned schedule_low_speed:1;
367 unsigned want_wait:1;
368 unsigned wait_timer_cancel:1;
369};
370
371/**
372 * struct dwc2_qtd - Software queue transfer descriptor (QTD)
373 *
374 * @control_phase: Current phase for control transfers (Setup, Data, or
375 * Status)
376 * @in_process: Indicates if this QTD is currently processed by HW
377 * @data_toggle: Determines the PID of the next data packet for the
378 * data phase of control transfers. Ignored for other
379 * transfer types. One of the following values:
380 * - DWC2_HC_PID_DATA0
381 * - DWC2_HC_PID_DATA1
382 * @complete_split: Keeps track of the current split type for FS/LS
383 * endpoints on a HS Hub
384 * @isoc_split_pos: Position of the ISOC split in full/low speed
385 * @isoc_frame_index: Index of the next frame descriptor for an isochronous
386 * transfer. A frame descriptor describes the buffer
387 * position and length of the data to be transferred in the
388 * next scheduled (micro)frame of an isochronous transfer.
389 * It also holds status for that transaction. The frame
390 * index starts at 0.
391 * @isoc_split_offset: Position of the ISOC split in the buffer for the
392 * current frame
393 * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT
394 * @error_count: Holds the number of bus errors that have occurred for
395 * a transaction within this transfer
396 * @n_desc: Number of DMA descriptors for this QTD
397 * @isoc_frame_index_last: Last activated frame (packet) index, used in
398 * descriptor DMA mode only
399 * @num_naks: Number of NAKs received on this QTD.
400 * @urb: URB for this transfer
401 * @qh: Queue head for this QTD
402 * @qtd_list_entry: For linking to the QH's list of QTDs
403 *
404 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
405 * interrupt, or isochronous transfer. A single QTD is created for each URB
406 * (of one of these types) submitted to the HCD. The transfer associated with
407 * a QTD may require one or multiple transactions.
408 *
409 * A QTD is linked to a Queue Head, which is entered in either the
410 * non-periodic or periodic schedule for execution. When a QTD is chosen for
411 * execution, some or all of its transactions may be executed. After
412 * execution, the state of the QTD is updated. The QTD may be retired if all
413 * its transactions are complete or if an error occurred. Otherwise, it
414 * remains in the schedule so more transactions can be executed later.
415 */
416struct dwc2_qtd {
417 enum dwc2_control_phase control_phase;
418 u8 in_process;
419 u8 data_toggle;
420 u8 complete_split;
421 u8 isoc_split_pos;
422 u16 isoc_frame_index;
423 u16 isoc_split_offset;
424 u16 isoc_td_last;
425 u16 isoc_td_first;
426 u32 ssplit_out_xfer_count;
427 u8 error_count;
428 u8 n_desc;
429 u16 isoc_frame_index_last;
430 u16 num_naks;
431 struct dwc2_hcd_urb *urb;
432 struct dwc2_qh *qh;
433 struct list_head qtd_list_entry;
434};
435
436#ifdef DEBUG
437struct hc_xfer_info {
438 struct dwc2_hsotg *hsotg;
439 struct dwc2_host_chan *chan;
440};
441#endif
442
443u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg);
444
445/* Gets the struct usb_hcd that contains a struct dwc2_hsotg */
446static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg)
447{
448 return (struct usb_hcd *)hsotg->priv;
449}
450
451/*
452 * Inline used to disable one channel interrupt. Channel interrupts are
453 * disabled when the channel is halted or released by the interrupt handler.
454 * There is no need to handle further interrupts of that type until the
455 * channel is re-assigned. In fact, subsequent handling may cause crashes
456 * because the channel structures are cleaned up when the channel is released.
457 */
458static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr)
459{
460 u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
461
462 mask &= ~intr;
463 dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum));
464}
465
466void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan);
467void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
468 enum dwc2_halt_status halt_status);
469void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
470 struct dwc2_host_chan *chan);
471
472/*
473 * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they
474 * are read as 1, they won't clear when written back.
475 */
476static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg)
477{
478 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
479
480 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG);
481 return hprt0;
482}
483
484static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe)
485{
486 return pipe->ep_num;
487}
488
489static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe)
490{
491 return pipe->pipe_type;
492}
493
494static inline u16 dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info *pipe)
495{
496 return pipe->mps;
497}
498
499static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe)
500{
501 return pipe->dev_addr;
502}
503
504static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe)
505{
506 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC;
507}
508
509static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe)
510{
511 return pipe->pipe_type == USB_ENDPOINT_XFER_INT;
512}
513
514static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe)
515{
516 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK;
517}
518
519static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe)
520{
521 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL;
522}
523
524static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe)
525{
526 return pipe->pipe_dir == USB_DIR_IN;
527}
528
529static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe)
530{
531 return !dwc2_hcd_is_pipe_in(pipe);
532}
533
534int dwc2_hcd_init(struct dwc2_hsotg *hsotg);
535void dwc2_hcd_remove(struct dwc2_hsotg *hsotg);
536
537/* Transaction Execution Functions */
538enum dwc2_transaction_type dwc2_hcd_select_transactions(
539 struct dwc2_hsotg *hsotg);
540void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
541 enum dwc2_transaction_type tr_type);
542
543/* Schedule Queue Functions */
544/* Implemented in hcd_queue.c */
545struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
546 struct dwc2_hcd_urb *urb,
547 gfp_t mem_flags);
548void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
549int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
550void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
551void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
552 int sched_csplit);
553
554void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb);
555int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
556 struct dwc2_qh *qh);
557
558/* Unlinks and frees a QTD */
559static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg,
560 struct dwc2_qtd *qtd,
561 struct dwc2_qh *qh)
562{
563 list_del(&qtd->qtd_list_entry);
564 kfree(qtd);
565 qtd = NULL;
566}
567
568/* Descriptor DMA support functions */
569void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg,
570 struct dwc2_qh *qh);
571void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg,
572 struct dwc2_host_chan *chan, int chnum,
573 enum dwc2_halt_status halt_status);
574
575int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
576 gfp_t mem_flags);
577void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
578
579/* Check if QH is non-periodic */
580#define dwc2_qh_is_non_per(_qh_ptr_) \
581 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \
582 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL)
583
584#ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC
585static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; }
586static inline bool dbg_qh(struct dwc2_qh *qh) { return true; }
587static inline bool dbg_urb(struct urb *urb) { return true; }
588static inline bool dbg_perio(void) { return true; }
589#else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */
590static inline bool dbg_hc(struct dwc2_host_chan *hc)
591{
592 return hc->ep_type == USB_ENDPOINT_XFER_BULK ||
593 hc->ep_type == USB_ENDPOINT_XFER_CONTROL;
594}
595
596static inline bool dbg_qh(struct dwc2_qh *qh)
597{
598 return qh->ep_type == USB_ENDPOINT_XFER_BULK ||
599 qh->ep_type == USB_ENDPOINT_XFER_CONTROL;
600}
601
602static inline bool dbg_urb(struct urb *urb)
603{
604 return usb_pipetype(urb->pipe) == PIPE_BULK ||
605 usb_pipetype(urb->pipe) == PIPE_CONTROL;
606}
607
608static inline bool dbg_perio(void) { return false; }
609#endif
610
611/* High bandwidth multiplier as encoded in highspeed endpoint descriptors */
612#define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03))
613
614/* Packet size for any kind of endpoint descriptor */
615#define dwc2_max_packet(wmaxpacketsize) ((wmaxpacketsize) & 0x07ff)
616
617/*
618 * Returns true if frame1 index is greater than frame2 index. The comparison
619 * is done modulo FRLISTEN_64_SIZE. This accounts for the rollover of the
620 * frame number when the max index frame number is reached.
621 */
622static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2)
623{
624 u16 diff = fr_idx1 - fr_idx2;
625 u16 sign = diff & (FRLISTEN_64_SIZE >> 1);
626
627 return diff && !sign;
628}
629
630/*
631 * Returns true if frame1 is less than or equal to frame2. The comparison is
632 * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the
633 * frame number when the max frame number is reached.
634 */
635static inline int dwc2_frame_num_le(u16 frame1, u16 frame2)
636{
637 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1);
638}
639
640/*
641 * Returns true if frame1 is greater than frame2. The comparison is done
642 * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
643 * number when the max frame number is reached.
644 */
645static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2)
646{
647 return (frame1 != frame2) &&
648 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1);
649}
650
651/*
652 * Increments frame by the amount specified by inc. The addition is done
653 * modulo HFNUM_MAX_FRNUM. Returns the incremented value.
654 */
655static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc)
656{
657 return (frame + inc) & HFNUM_MAX_FRNUM;
658}
659
660static inline u16 dwc2_frame_num_dec(u16 frame, u16 dec)
661{
662 return (frame + HFNUM_MAX_FRNUM + 1 - dec) & HFNUM_MAX_FRNUM;
663}
664
665static inline u16 dwc2_full_frame_num(u16 frame)
666{
667 return (frame & HFNUM_MAX_FRNUM) >> 3;
668}
669
670static inline u16 dwc2_micro_frame_num(u16 frame)
671{
672 return frame & 0x7;
673}
674
675/*
676 * Returns the Core Interrupt Status register contents, ANDed with the Core
677 * Interrupt Mask register contents
678 */
679static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg)
680{
681 return dwc2_readl(hsotg->regs + GINTSTS) &
682 dwc2_readl(hsotg->regs + GINTMSK);
683}
684
685static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb)
686{
687 return dwc2_urb->status;
688}
689
690static inline u32 dwc2_hcd_urb_get_actual_length(
691 struct dwc2_hcd_urb *dwc2_urb)
692{
693 return dwc2_urb->actual_length;
694}
695
696static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb)
697{
698 return dwc2_urb->error_count;
699}
700
701static inline void dwc2_hcd_urb_set_iso_desc_params(
702 struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset,
703 u32 length)
704{
705 dwc2_urb->iso_descs[desc_num].offset = offset;
706 dwc2_urb->iso_descs[desc_num].length = length;
707}
708
709static inline u32 dwc2_hcd_urb_get_iso_desc_status(
710 struct dwc2_hcd_urb *dwc2_urb, int desc_num)
711{
712 return dwc2_urb->iso_descs[desc_num].status;
713}
714
715static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length(
716 struct dwc2_hcd_urb *dwc2_urb, int desc_num)
717{
718 return dwc2_urb->iso_descs[desc_num].actual_length;
719}
720
721static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg,
722 struct usb_host_endpoint *ep)
723{
724 struct dwc2_qh *qh = ep->hcpriv;
725
726 if (qh && !list_empty(&qh->qh_list_entry))
727 return 1;
728
729 return 0;
730}
731
732static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg,
733 struct usb_host_endpoint *ep)
734{
735 struct dwc2_qh *qh = ep->hcpriv;
736
737 if (!qh) {
738 WARN_ON(1);
739 return 0;
740 }
741
742 return qh->host_us;
743}
744
745void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
746 struct dwc2_host_chan *chan, int chnum,
747 struct dwc2_qtd *qtd);
748
749/* HCD Core API */
750
751/**
752 * dwc2_handle_hcd_intr() - Called on every hardware interrupt
753 *
754 * @hsotg: The DWC2 HCD
755 *
756 * Returns IRQ_HANDLED if interrupt is handled
757 * Return IRQ_NONE if interrupt is not handled
758 */
759irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg);
760
761/**
762 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation
763 *
764 * @hsotg: The DWC2 HCD
765 */
766void dwc2_hcd_stop(struct dwc2_hsotg *hsotg);
767
768/**
769 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host,
770 * and 0 otherwise
771 *
772 * @hsotg: The DWC2 HCD
773 */
774int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg);
775
776/**
777 * dwc2_hcd_dump_state() - Dumps hsotg state
778 *
779 * @hsotg: The DWC2 HCD
780 *
781 * NOTE: This function will be removed once the peripheral controller code
782 * is integrated and the driver is stable
783 */
784void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg);
785
786/* URB interface */
787
788/* Transfer flags */
789#define URB_GIVEBACK_ASAP 0x1
790#define URB_SEND_ZERO_PACKET 0x2
791
792/* Host driver callbacks */
793struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg,
794 void *context, gfp_t mem_flags,
795 int *ttport);
796
797void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg,
798 struct dwc2_tt *dwc_tt);
799int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context);
800void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
801 int status);
802
803#endif /* __DWC2_HCD_H__ */