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1/*
2 * hcd.h - DesignWare HS OTG Controller host-mode declarations
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36#ifndef __DWC2_HCD_H__
37#define __DWC2_HCD_H__
38
39/*
40 * This file contains the structures, constants, and interfaces for the
41 * Host Contoller Driver (HCD)
42 *
43 * The Host Controller Driver (HCD) is responsible for translating requests
44 * from the USB Driver into the appropriate actions on the DWC_otg controller.
45 * It isolates the USBD from the specifics of the controller by providing an
46 * API to the USBD.
47 */
48
49struct dwc2_qh;
50
51/**
52 * struct dwc2_host_chan - Software host channel descriptor
53 *
54 * @hc_num: Host channel number, used for register address lookup
55 * @dev_addr: Address of the device
56 * @ep_num: Endpoint of the device
57 * @ep_is_in: Endpoint direction
58 * @speed: Device speed. One of the following values:
59 * - USB_SPEED_LOW
60 * - USB_SPEED_FULL
61 * - USB_SPEED_HIGH
62 * @ep_type: Endpoint type. One of the following values:
63 * - USB_ENDPOINT_XFER_CONTROL: 0
64 * - USB_ENDPOINT_XFER_ISOC: 1
65 * - USB_ENDPOINT_XFER_BULK: 2
66 * - USB_ENDPOINT_XFER_INTR: 3
67 * @max_packet: Max packet size in bytes
68 * @data_pid_start: PID for initial transaction.
69 * 0: DATA0
70 * 1: DATA2
71 * 2: DATA1
72 * 3: MDATA (non-Control EP),
73 * SETUP (Control EP)
74 * @multi_count: Number of additional periodic transactions per
75 * (micro)frame
76 * @xfer_buf: Pointer to current transfer buffer position
77 * @xfer_dma: DMA address of xfer_buf
78 * @xfer_len: Total number of bytes to transfer
79 * @xfer_count: Number of bytes transferred so far
80 * @start_pkt_count: Packet count at start of transfer
81 * @xfer_started: True if the transfer has been started
82 * @ping: True if a PING request should be issued on this channel
83 * @error_state: True if the error count for this transaction is non-zero
84 * @halt_on_queue: True if this channel should be halted the next time a
85 * request is queued for the channel. This is necessary in
86 * slave mode if no request queue space is available when
87 * an attempt is made to halt the channel.
88 * @halt_pending: True if the host channel has been halted, but the core
89 * is not finished flushing queued requests
90 * @do_split: Enable split for the channel
91 * @complete_split: Enable complete split
92 * @hub_addr: Address of high speed hub for the split
93 * @hub_port: Port of the low/full speed device for the split
94 * @xact_pos: Split transaction position. One of the following values:
95 * - DWC2_HCSPLT_XACTPOS_MID
96 * - DWC2_HCSPLT_XACTPOS_BEGIN
97 * - DWC2_HCSPLT_XACTPOS_END
98 * - DWC2_HCSPLT_XACTPOS_ALL
99 * @requests: Number of requests issued for this channel since it was
100 * assigned to the current transfer (not counting PINGs)
101 * @schinfo: Scheduling micro-frame bitmap
102 * @ntd: Number of transfer descriptors for the transfer
103 * @halt_status: Reason for halting the host channel
104 * @hcint Contents of the HCINT register when the interrupt came
105 * @qh: QH for the transfer being processed by this channel
106 * @hc_list_entry: For linking to list of host channels
107 * @desc_list_addr: Current QH's descriptor list DMA address
108 * @desc_list_sz: Current QH's descriptor list size
109 * @split_order_list_entry: List entry for keeping track of the order of splits
110 *
111 * This structure represents the state of a single host channel when acting in
112 * host mode. It contains the data items needed to transfer packets to an
113 * endpoint via a host channel.
114 */
115struct dwc2_host_chan {
116 u8 hc_num;
117
118 unsigned dev_addr:7;
119 unsigned ep_num:4;
120 unsigned ep_is_in:1;
121 unsigned speed:4;
122 unsigned ep_type:2;
123 unsigned max_packet:11;
124 unsigned data_pid_start:2;
125#define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0
126#define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2
127#define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1
128#define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA
129#define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP
130
131 unsigned multi_count:2;
132
133 u8 *xfer_buf;
134 dma_addr_t xfer_dma;
135 u32 xfer_len;
136 u32 xfer_count;
137 u16 start_pkt_count;
138 u8 xfer_started;
139 u8 do_ping;
140 u8 error_state;
141 u8 halt_on_queue;
142 u8 halt_pending;
143 u8 do_split;
144 u8 complete_split;
145 u8 hub_addr;
146 u8 hub_port;
147 u8 xact_pos;
148#define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID
149#define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END
150#define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN
151#define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL
152
153 u8 requests;
154 u8 schinfo;
155 u16 ntd;
156 enum dwc2_halt_status halt_status;
157 u32 hcint;
158 struct dwc2_qh *qh;
159 struct list_head hc_list_entry;
160 dma_addr_t desc_list_addr;
161 u32 desc_list_sz;
162 struct list_head split_order_list_entry;
163};
164
165struct dwc2_hcd_pipe_info {
166 u8 dev_addr;
167 u8 ep_num;
168 u8 pipe_type;
169 u8 pipe_dir;
170 u16 mps;
171};
172
173struct dwc2_hcd_iso_packet_desc {
174 u32 offset;
175 u32 length;
176 u32 actual_length;
177 u32 status;
178};
179
180struct dwc2_qtd;
181
182struct dwc2_hcd_urb {
183 void *priv;
184 struct dwc2_qtd *qtd;
185 void *buf;
186 dma_addr_t dma;
187 void *setup_packet;
188 dma_addr_t setup_dma;
189 u32 length;
190 u32 actual_length;
191 u32 status;
192 u32 error_count;
193 u32 packet_count;
194 u32 flags;
195 u16 interval;
196 struct dwc2_hcd_pipe_info pipe_info;
197 struct dwc2_hcd_iso_packet_desc iso_descs[0];
198};
199
200/* Phases for control transfers */
201enum dwc2_control_phase {
202 DWC2_CONTROL_SETUP,
203 DWC2_CONTROL_DATA,
204 DWC2_CONTROL_STATUS,
205};
206
207/* Transaction types */
208enum dwc2_transaction_type {
209 DWC2_TRANSACTION_NONE,
210 DWC2_TRANSACTION_PERIODIC,
211 DWC2_TRANSACTION_NON_PERIODIC,
212 DWC2_TRANSACTION_ALL,
213};
214
215/* The number of elements per LS bitmap (per port on multi_tt) */
216#define DWC2_ELEMENTS_PER_LS_BITMAP DIV_ROUND_UP(DWC2_LS_SCHEDULE_SLICES, \
217 BITS_PER_LONG)
218
219/**
220 * struct dwc2_tt - dwc2 data associated with a usb_tt
221 *
222 * @refcount: Number of Queue Heads (QHs) holding a reference.
223 * @usb_tt: Pointer back to the official usb_tt.
224 * @periodic_bitmaps: Bitmap for which parts of the 1ms frame are accounted
225 * for already. Each is DWC2_ELEMENTS_PER_LS_BITMAP
226 * elements (so sizeof(long) times that in bytes).
227 *
228 * This structure is stored in the hcpriv of the official usb_tt.
229 */
230struct dwc2_tt {
231 int refcount;
232 struct usb_tt *usb_tt;
233 unsigned long periodic_bitmaps[];
234};
235
236/**
237 * struct dwc2_hs_transfer_time - Info about a transfer on the high speed bus.
238 *
239 * @start_schedule_usecs: The start time on the main bus schedule. Note that
240 * the main bus schedule is tightly packed and this
241 * time should be interpreted as tightly packed (so
242 * uFrame 0 starts at 0 us, uFrame 1 starts at 100 us
243 * instead of 125 us).
244 * @duration_us: How long this transfer goes.
245 */
246
247struct dwc2_hs_transfer_time {
248 u32 start_schedule_us;
249 u16 duration_us;
250};
251
252/**
253 * struct dwc2_qh - Software queue head structure
254 *
255 * @hsotg: The HCD state structure for the DWC OTG controller
256 * @ep_type: Endpoint type. One of the following values:
257 * - USB_ENDPOINT_XFER_CONTROL
258 * - USB_ENDPOINT_XFER_BULK
259 * - USB_ENDPOINT_XFER_INT
260 * - USB_ENDPOINT_XFER_ISOC
261 * @ep_is_in: Endpoint direction
262 * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor
263 * @dev_speed: Device speed. One of the following values:
264 * - USB_SPEED_LOW
265 * - USB_SPEED_FULL
266 * - USB_SPEED_HIGH
267 * @data_toggle: Determines the PID of the next data packet for
268 * non-controltransfers. Ignored for control transfers.
269 * One of the following values:
270 * - DWC2_HC_PID_DATA0
271 * - DWC2_HC_PID_DATA1
272 * @ping_state: Ping state
273 * @do_split: Full/low speed endpoint on high-speed hub requires split
274 * @td_first: Index of first activated isochronous transfer descriptor
275 * @td_last: Index of last activated isochronous transfer descriptor
276 * @host_us: Bandwidth in microseconds per transfer as seen by host
277 * @device_us: Bandwidth in microseconds per transfer as seen by device
278 * @host_interval: Interval between transfers as seen by the host. If
279 * the host is high speed and the device is low speed this
280 * will be 8 times device interval.
281 * @device_interval: Interval between transfers as seen by the device.
282 * interval.
283 * @next_active_frame: (Micro)frame _before_ we next need to put something on
284 * the bus. We'll move the qh to active here. If the
285 * host is in high speed mode this will be a uframe. If
286 * the host is in low speed mode this will be a full frame.
287 * @start_active_frame: If we are partway through a split transfer, this will be
288 * what next_active_frame was when we started. Otherwise
289 * it should always be the same as next_active_frame.
290 * @num_hs_transfers: Number of transfers in hs_transfers.
291 * Normally this is 1 but can be more than one for splits.
292 * Always >= 1 unless the host is in low/full speed mode.
293 * @hs_transfers: Transfers that are scheduled as seen by the high speed
294 * bus. Not used if host is in low or full speed mode (but
295 * note that it IS USED if the device is low or full speed
296 * as long as the HOST is in high speed mode).
297 * @ls_start_schedule_slice: Start time (in slices) on the low speed bus
298 * schedule that's being used by this device. This
299 * will be on the periodic_bitmap in a
300 * "struct dwc2_tt". Not used if this device is high
301 * speed. Note that this is in "schedule slice" which
302 * is tightly packed.
303 * @ls_duration_us: Duration on the low speed bus schedule.
304 * @ntd: Actual number of transfer descriptors in a list
305 * @qtd_list: List of QTDs for this QH
306 * @channel: Host channel currently processing transfers for this QH
307 * @qh_list_entry: Entry for QH in either the periodic or non-periodic
308 * schedule
309 * @desc_list: List of transfer descriptors
310 * @desc_list_dma: Physical address of desc_list
311 * @desc_list_sz: Size of descriptors list
312 * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer
313 * descriptor and indicates original XferSize value for the
314 * descriptor
315 * @unreserve_timer: Timer for releasing periodic reservation.
316 * @dwc2_tt: Pointer to our tt info (or NULL if no tt).
317 * @ttport: Port number within our tt.
318 * @tt_buffer_dirty True if clear_tt_buffer_complete is pending
319 * @unreserve_pending: True if we planned to unreserve but haven't yet.
320 * @schedule_low_speed: True if we have a low/full speed component (either the
321 * host is in low/full speed mode or do_split).
322 *
323 * A Queue Head (QH) holds the static characteristics of an endpoint and
324 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
325 * be entered in either the non-periodic or periodic schedule.
326 */
327struct dwc2_qh {
328 struct dwc2_hsotg *hsotg;
329 u8 ep_type;
330 u8 ep_is_in;
331 u16 maxp;
332 u8 dev_speed;
333 u8 data_toggle;
334 u8 ping_state;
335 u8 do_split;
336 u8 td_first;
337 u8 td_last;
338 u16 host_us;
339 u16 device_us;
340 u16 host_interval;
341 u16 device_interval;
342 u16 next_active_frame;
343 u16 start_active_frame;
344 s16 num_hs_transfers;
345 struct dwc2_hs_transfer_time hs_transfers[DWC2_HS_SCHEDULE_UFRAMES];
346 u32 ls_start_schedule_slice;
347 u16 ntd;
348 struct list_head qtd_list;
349 struct dwc2_host_chan *channel;
350 struct list_head qh_list_entry;
351 struct dwc2_hcd_dma_desc *desc_list;
352 dma_addr_t desc_list_dma;
353 u32 desc_list_sz;
354 u32 *n_bytes;
355 struct timer_list unreserve_timer;
356 struct dwc2_tt *dwc_tt;
357 int ttport;
358 unsigned tt_buffer_dirty:1;
359 unsigned unreserve_pending:1;
360 unsigned schedule_low_speed:1;
361};
362
363/**
364 * struct dwc2_qtd - Software queue transfer descriptor (QTD)
365 *
366 * @control_phase: Current phase for control transfers (Setup, Data, or
367 * Status)
368 * @in_process: Indicates if this QTD is currently processed by HW
369 * @data_toggle: Determines the PID of the next data packet for the
370 * data phase of control transfers. Ignored for other
371 * transfer types. One of the following values:
372 * - DWC2_HC_PID_DATA0
373 * - DWC2_HC_PID_DATA1
374 * @complete_split: Keeps track of the current split type for FS/LS
375 * endpoints on a HS Hub
376 * @isoc_split_pos: Position of the ISOC split in full/low speed
377 * @isoc_frame_index: Index of the next frame descriptor for an isochronous
378 * transfer. A frame descriptor describes the buffer
379 * position and length of the data to be transferred in the
380 * next scheduled (micro)frame of an isochronous transfer.
381 * It also holds status for that transaction. The frame
382 * index starts at 0.
383 * @isoc_split_offset: Position of the ISOC split in the buffer for the
384 * current frame
385 * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT
386 * @error_count: Holds the number of bus errors that have occurred for
387 * a transaction within this transfer
388 * @n_desc: Number of DMA descriptors for this QTD
389 * @isoc_frame_index_last: Last activated frame (packet) index, used in
390 * descriptor DMA mode only
391 * @urb: URB for this transfer
392 * @qh: Queue head for this QTD
393 * @qtd_list_entry: For linking to the QH's list of QTDs
394 *
395 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
396 * interrupt, or isochronous transfer. A single QTD is created for each URB
397 * (of one of these types) submitted to the HCD. The transfer associated with
398 * a QTD may require one or multiple transactions.
399 *
400 * A QTD is linked to a Queue Head, which is entered in either the
401 * non-periodic or periodic schedule for execution. When a QTD is chosen for
402 * execution, some or all of its transactions may be executed. After
403 * execution, the state of the QTD is updated. The QTD may be retired if all
404 * its transactions are complete or if an error occurred. Otherwise, it
405 * remains in the schedule so more transactions can be executed later.
406 */
407struct dwc2_qtd {
408 enum dwc2_control_phase control_phase;
409 u8 in_process;
410 u8 data_toggle;
411 u8 complete_split;
412 u8 isoc_split_pos;
413 u16 isoc_frame_index;
414 u16 isoc_split_offset;
415 u16 isoc_td_last;
416 u16 isoc_td_first;
417 u32 ssplit_out_xfer_count;
418 u8 error_count;
419 u8 n_desc;
420 u16 isoc_frame_index_last;
421 struct dwc2_hcd_urb *urb;
422 struct dwc2_qh *qh;
423 struct list_head qtd_list_entry;
424};
425
426#ifdef DEBUG
427struct hc_xfer_info {
428 struct dwc2_hsotg *hsotg;
429 struct dwc2_host_chan *chan;
430};
431#endif
432
433u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg);
434
435/* Gets the struct usb_hcd that contains a struct dwc2_hsotg */
436static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg)
437{
438 return (struct usb_hcd *)hsotg->priv;
439}
440
441/*
442 * Inline used to disable one channel interrupt. Channel interrupts are
443 * disabled when the channel is halted or released by the interrupt handler.
444 * There is no need to handle further interrupts of that type until the
445 * channel is re-assigned. In fact, subsequent handling may cause crashes
446 * because the channel structures are cleaned up when the channel is released.
447 */
448static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr)
449{
450 u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
451
452 mask &= ~intr;
453 dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum));
454}
455
456void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan);
457void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
458 enum dwc2_halt_status halt_status);
459void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
460 struct dwc2_host_chan *chan);
461
462/*
463 * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they
464 * are read as 1, they won't clear when written back.
465 */
466static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg)
467{
468 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
469
470 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG);
471 return hprt0;
472}
473
474static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe)
475{
476 return pipe->ep_num;
477}
478
479static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe)
480{
481 return pipe->pipe_type;
482}
483
484static inline u16 dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info *pipe)
485{
486 return pipe->mps;
487}
488
489static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe)
490{
491 return pipe->dev_addr;
492}
493
494static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe)
495{
496 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC;
497}
498
499static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe)
500{
501 return pipe->pipe_type == USB_ENDPOINT_XFER_INT;
502}
503
504static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe)
505{
506 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK;
507}
508
509static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe)
510{
511 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL;
512}
513
514static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe)
515{
516 return pipe->pipe_dir == USB_DIR_IN;
517}
518
519static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe)
520{
521 return !dwc2_hcd_is_pipe_in(pipe);
522}
523
524extern int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq);
525extern void dwc2_hcd_remove(struct dwc2_hsotg *hsotg);
526
527/* Transaction Execution Functions */
528extern enum dwc2_transaction_type dwc2_hcd_select_transactions(
529 struct dwc2_hsotg *hsotg);
530extern void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
531 enum dwc2_transaction_type tr_type);
532
533/* Schedule Queue Functions */
534/* Implemented in hcd_queue.c */
535extern struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
536 struct dwc2_hcd_urb *urb,
537 gfp_t mem_flags);
538extern void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
539extern int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
540extern void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
541extern void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
542 int sched_csplit);
543
544extern void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb);
545extern int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
546 struct dwc2_qh *qh);
547
548/* Unlinks and frees a QTD */
549static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg,
550 struct dwc2_qtd *qtd,
551 struct dwc2_qh *qh)
552{
553 list_del(&qtd->qtd_list_entry);
554 kfree(qtd);
555}
556
557/* Descriptor DMA support functions */
558extern void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg,
559 struct dwc2_qh *qh);
560extern void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg,
561 struct dwc2_host_chan *chan, int chnum,
562 enum dwc2_halt_status halt_status);
563
564extern int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
565 gfp_t mem_flags);
566extern void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
567
568/* Check if QH is non-periodic */
569#define dwc2_qh_is_non_per(_qh_ptr_) \
570 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \
571 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL)
572
573#ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC
574static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; }
575static inline bool dbg_qh(struct dwc2_qh *qh) { return true; }
576static inline bool dbg_urb(struct urb *urb) { return true; }
577static inline bool dbg_perio(void) { return true; }
578#else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */
579static inline bool dbg_hc(struct dwc2_host_chan *hc)
580{
581 return hc->ep_type == USB_ENDPOINT_XFER_BULK ||
582 hc->ep_type == USB_ENDPOINT_XFER_CONTROL;
583}
584
585static inline bool dbg_qh(struct dwc2_qh *qh)
586{
587 return qh->ep_type == USB_ENDPOINT_XFER_BULK ||
588 qh->ep_type == USB_ENDPOINT_XFER_CONTROL;
589}
590
591static inline bool dbg_urb(struct urb *urb)
592{
593 return usb_pipetype(urb->pipe) == PIPE_BULK ||
594 usb_pipetype(urb->pipe) == PIPE_CONTROL;
595}
596
597static inline bool dbg_perio(void) { return false; }
598#endif
599
600/* High bandwidth multiplier as encoded in highspeed endpoint descriptors */
601#define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03))
602
603/* Packet size for any kind of endpoint descriptor */
604#define dwc2_max_packet(wmaxpacketsize) ((wmaxpacketsize) & 0x07ff)
605
606/*
607 * Returns true if frame1 index is greater than frame2 index. The comparison
608 * is done modulo FRLISTEN_64_SIZE. This accounts for the rollover of the
609 * frame number when the max index frame number is reached.
610 */
611static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2)
612{
613 u16 diff = fr_idx1 - fr_idx2;
614 u16 sign = diff & (FRLISTEN_64_SIZE >> 1);
615
616 return diff && !sign;
617}
618
619/*
620 * Returns true if frame1 is less than or equal to frame2. The comparison is
621 * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the
622 * frame number when the max frame number is reached.
623 */
624static inline int dwc2_frame_num_le(u16 frame1, u16 frame2)
625{
626 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1);
627}
628
629/*
630 * Returns true if frame1 is greater than frame2. The comparison is done
631 * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
632 * number when the max frame number is reached.
633 */
634static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2)
635{
636 return (frame1 != frame2) &&
637 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1);
638}
639
640/*
641 * Increments frame by the amount specified by inc. The addition is done
642 * modulo HFNUM_MAX_FRNUM. Returns the incremented value.
643 */
644static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc)
645{
646 return (frame + inc) & HFNUM_MAX_FRNUM;
647}
648
649static inline u16 dwc2_frame_num_dec(u16 frame, u16 dec)
650{
651 return (frame + HFNUM_MAX_FRNUM + 1 - dec) & HFNUM_MAX_FRNUM;
652}
653
654static inline u16 dwc2_full_frame_num(u16 frame)
655{
656 return (frame & HFNUM_MAX_FRNUM) >> 3;
657}
658
659static inline u16 dwc2_micro_frame_num(u16 frame)
660{
661 return frame & 0x7;
662}
663
664/*
665 * Returns the Core Interrupt Status register contents, ANDed with the Core
666 * Interrupt Mask register contents
667 */
668static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg)
669{
670 return dwc2_readl(hsotg->regs + GINTSTS) &
671 dwc2_readl(hsotg->regs + GINTMSK);
672}
673
674static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb)
675{
676 return dwc2_urb->status;
677}
678
679static inline u32 dwc2_hcd_urb_get_actual_length(
680 struct dwc2_hcd_urb *dwc2_urb)
681{
682 return dwc2_urb->actual_length;
683}
684
685static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb)
686{
687 return dwc2_urb->error_count;
688}
689
690static inline void dwc2_hcd_urb_set_iso_desc_params(
691 struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset,
692 u32 length)
693{
694 dwc2_urb->iso_descs[desc_num].offset = offset;
695 dwc2_urb->iso_descs[desc_num].length = length;
696}
697
698static inline u32 dwc2_hcd_urb_get_iso_desc_status(
699 struct dwc2_hcd_urb *dwc2_urb, int desc_num)
700{
701 return dwc2_urb->iso_descs[desc_num].status;
702}
703
704static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length(
705 struct dwc2_hcd_urb *dwc2_urb, int desc_num)
706{
707 return dwc2_urb->iso_descs[desc_num].actual_length;
708}
709
710static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg,
711 struct usb_host_endpoint *ep)
712{
713 struct dwc2_qh *qh = ep->hcpriv;
714
715 if (qh && !list_empty(&qh->qh_list_entry))
716 return 1;
717
718 return 0;
719}
720
721static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg,
722 struct usb_host_endpoint *ep)
723{
724 struct dwc2_qh *qh = ep->hcpriv;
725
726 if (!qh) {
727 WARN_ON(1);
728 return 0;
729 }
730
731 return qh->host_us;
732}
733
734extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
735 struct dwc2_host_chan *chan, int chnum,
736 struct dwc2_qtd *qtd);
737
738/* HCD Core API */
739
740/**
741 * dwc2_handle_hcd_intr() - Called on every hardware interrupt
742 *
743 * @hsotg: The DWC2 HCD
744 *
745 * Returns IRQ_HANDLED if interrupt is handled
746 * Return IRQ_NONE if interrupt is not handled
747 */
748extern irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg);
749
750/**
751 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation
752 *
753 * @hsotg: The DWC2 HCD
754 */
755extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg);
756
757/**
758 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host,
759 * and 0 otherwise
760 *
761 * @hsotg: The DWC2 HCD
762 */
763extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg);
764
765/**
766 * dwc2_hcd_dump_state() - Dumps hsotg state
767 *
768 * @hsotg: The DWC2 HCD
769 *
770 * NOTE: This function will be removed once the peripheral controller code
771 * is integrated and the driver is stable
772 */
773extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg);
774
775/**
776 * dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF
777 *
778 * @hsotg: The DWC2 HCD
779 *
780 * This can be used to determine average interrupt latency. Frame remaining is
781 * also shown for start transfer and two additional sample points.
782 *
783 * NOTE: This function will be removed once the peripheral controller code
784 * is integrated and the driver is stable
785 */
786extern void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg);
787
788/* URB interface */
789
790/* Transfer flags */
791#define URB_GIVEBACK_ASAP 0x1
792#define URB_SEND_ZERO_PACKET 0x2
793
794/* Host driver callbacks */
795
796extern void dwc2_host_start(struct dwc2_hsotg *hsotg);
797extern void dwc2_host_disconnect(struct dwc2_hsotg *hsotg);
798extern void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
799 int *hub_addr, int *hub_port);
800extern struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg,
801 void *context, gfp_t mem_flags,
802 int *ttport);
803
804extern void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg,
805 struct dwc2_tt *dwc_tt);
806extern int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context);
807extern void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
808 int status);
809
810#ifdef DEBUG
811/*
812 * Macro to sample the remaining PHY clocks left in the current frame. This
813 * may be used during debugging to determine the average time it takes to
814 * execute sections of code. There are two possible sample points, "a" and
815 * "b", so the _letter_ argument must be one of these values.
816 *
817 * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
818 * example, "cat /sys/devices/lm0/hcd_frrem".
819 */
820#define dwc2_sample_frrem(_hcd_, _qh_, _letter_) \
821do { \
822 struct hfnum_data _hfnum_; \
823 struct dwc2_qtd *_qtd_; \
824 \
825 _qtd_ = list_entry((_qh_)->qtd_list.next, struct dwc2_qtd, \
826 qtd_list_entry); \
827 if (usb_pipeint(_qtd_->urb->pipe) && \
828 (_qh_)->start_active_frame != 0 && !_qtd_->complete_split) { \
829 _hfnum_.d32 = dwc2_readl((_hcd_)->regs + HFNUM); \
830 switch (_hfnum_.b.frnum & 0x7) { \
831 case 7: \
832 (_hcd_)->hfnum_7_samples_##_letter_++; \
833 (_hcd_)->hfnum_7_frrem_accum_##_letter_ += \
834 _hfnum_.b.frrem; \
835 break; \
836 case 0: \
837 (_hcd_)->hfnum_0_samples_##_letter_++; \
838 (_hcd_)->hfnum_0_frrem_accum_##_letter_ += \
839 _hfnum_.b.frrem; \
840 break; \
841 default: \
842 (_hcd_)->hfnum_other_samples_##_letter_++; \
843 (_hcd_)->hfnum_other_frrem_accum_##_letter_ += \
844 _hfnum_.b.frrem; \
845 break; \
846 } \
847 } \
848} while (0)
849#else
850#define dwc2_sample_frrem(_hcd_, _qh_, _letter_) do {} while (0)
851#endif
852
853#endif /* __DWC2_HCD_H__ */