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1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * core_intr.c - DesignWare HS OTG Controller common interrupt handling
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38/*
39 * This file contains the common interrupt handlers
40 */
41#include <linux/kernel.h>
42#include <linux/module.h>
43#include <linux/moduleparam.h>
44#include <linux/spinlock.h>
45#include <linux/interrupt.h>
46#include <linux/dma-mapping.h>
47#include <linux/io.h>
48#include <linux/slab.h>
49#include <linux/usb.h>
50
51#include <linux/usb/hcd.h>
52#include <linux/usb/ch11.h>
53
54#include "core.h"
55#include "hcd.h"
56
57static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg)
58{
59 switch (hsotg->op_state) {
60 case OTG_STATE_A_HOST:
61 return "a_host";
62 case OTG_STATE_A_SUSPEND:
63 return "a_suspend";
64 case OTG_STATE_A_PERIPHERAL:
65 return "a_peripheral";
66 case OTG_STATE_B_PERIPHERAL:
67 return "b_peripheral";
68 case OTG_STATE_B_HOST:
69 return "b_host";
70 default:
71 return "unknown";
72 }
73}
74
75/**
76 * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts.
77 * When the PRTINT interrupt fires, there are certain status bits in the Host
78 * Port that needs to get cleared.
79 *
80 * @hsotg: Programming view of DWC_otg controller
81 */
82static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
83{
84 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
85
86 if (hprt0 & HPRT0_ENACHG) {
87 hprt0 &= ~HPRT0_ENA;
88 dwc2_writel(hprt0, hsotg->regs + HPRT0);
89 }
90}
91
92/**
93 * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message
94 *
95 * @hsotg: Programming view of DWC_otg controller
96 */
97static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
98{
99 /* Clear interrupt */
100 dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
101
102 dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n",
103 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
104}
105
106/**
107 * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG
108 * Interrupt Register (GOTGINT) to determine what interrupt has occurred.
109 *
110 * @hsotg: Programming view of DWC_otg controller
111 */
112static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
113{
114 u32 gotgint;
115 u32 gotgctl;
116 u32 gintmsk;
117
118 gotgint = dwc2_readl(hsotg->regs + GOTGINT);
119 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
120 dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
121 dwc2_op_state_str(hsotg));
122
123 if (gotgint & GOTGINT_SES_END_DET) {
124 dev_dbg(hsotg->dev,
125 " ++OTG Interrupt: Session End Detected++ (%s)\n",
126 dwc2_op_state_str(hsotg));
127 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
128
129 if (dwc2_is_device_mode(hsotg))
130 dwc2_hsotg_disconnect(hsotg);
131
132 if (hsotg->op_state == OTG_STATE_B_HOST) {
133 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
134 } else {
135 /*
136 * If not B_HOST and Device HNP still set, HNP did
137 * not succeed!
138 */
139 if (gotgctl & GOTGCTL_DEVHNPEN) {
140 dev_dbg(hsotg->dev, "Session End Detected\n");
141 dev_err(hsotg->dev,
142 "Device Not Connected/Responding!\n");
143 }
144
145 /*
146 * If Session End Detected the B-Cable has been
147 * disconnected
148 */
149 /* Reset to a clean state */
150 hsotg->lx_state = DWC2_L0;
151 }
152
153 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
154 gotgctl &= ~GOTGCTL_DEVHNPEN;
155 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
156 }
157
158 if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
159 dev_dbg(hsotg->dev,
160 " ++OTG Interrupt: Session Request Success Status Change++\n");
161 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
162 if (gotgctl & GOTGCTL_SESREQSCS) {
163 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
164 hsotg->params.i2c_enable) {
165 hsotg->srp_success = 1;
166 } else {
167 /* Clear Session Request */
168 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
169 gotgctl &= ~GOTGCTL_SESREQ;
170 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
171 }
172 }
173 }
174
175 if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) {
176 /*
177 * Print statements during the HNP interrupt handling
178 * can cause it to fail
179 */
180 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
181 /*
182 * WA for 3.00a- HW is not setting cur_mode, even sometimes
183 * this does not help
184 */
185 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)
186 udelay(100);
187 if (gotgctl & GOTGCTL_HSTNEGSCS) {
188 if (dwc2_is_host_mode(hsotg)) {
189 hsotg->op_state = OTG_STATE_B_HOST;
190 /*
191 * Need to disable SOF interrupt immediately.
192 * When switching from device to host, the PCD
193 * interrupt handler won't handle the interrupt
194 * if host mode is already set. The HCD
195 * interrupt handler won't get called if the
196 * HCD state is HALT. This means that the
197 * interrupt does not get handled and Linux
198 * complains loudly.
199 */
200 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
201 gintmsk &= ~GINTSTS_SOF;
202 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
203
204 /*
205 * Call callback function with spin lock
206 * released
207 */
208 spin_unlock(&hsotg->lock);
209
210 /* Initialize the Core for Host mode */
211 dwc2_hcd_start(hsotg);
212 spin_lock(&hsotg->lock);
213 hsotg->op_state = OTG_STATE_B_HOST;
214 }
215 } else {
216 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
217 gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
218 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
219 dev_dbg(hsotg->dev, "HNP Failed\n");
220 dev_err(hsotg->dev,
221 "Device Not Connected/Responding\n");
222 }
223 }
224
225 if (gotgint & GOTGINT_HST_NEG_DET) {
226 /*
227 * The disconnect interrupt is set at the same time as
228 * Host Negotiation Detected. During the mode switch all
229 * interrupts are cleared so the disconnect interrupt
230 * handler will not get executed.
231 */
232 dev_dbg(hsotg->dev,
233 " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n",
234 (dwc2_is_host_mode(hsotg) ? "Host" : "Device"));
235 if (dwc2_is_device_mode(hsotg)) {
236 dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n",
237 hsotg->op_state);
238 spin_unlock(&hsotg->lock);
239 dwc2_hcd_disconnect(hsotg, false);
240 spin_lock(&hsotg->lock);
241 hsotg->op_state = OTG_STATE_A_PERIPHERAL;
242 } else {
243 /* Need to disable SOF interrupt immediately */
244 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
245 gintmsk &= ~GINTSTS_SOF;
246 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
247 spin_unlock(&hsotg->lock);
248 dwc2_hcd_start(hsotg);
249 spin_lock(&hsotg->lock);
250 hsotg->op_state = OTG_STATE_A_HOST;
251 }
252 }
253
254 if (gotgint & GOTGINT_A_DEV_TOUT_CHG)
255 dev_dbg(hsotg->dev,
256 " ++OTG Interrupt: A-Device Timeout Change++\n");
257 if (gotgint & GOTGINT_DBNCE_DONE)
258 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
259
260 /* Clear GOTGINT */
261 dwc2_writel(gotgint, hsotg->regs + GOTGINT);
262}
263
264/**
265 * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status
266 * Change Interrupt
267 *
268 * @hsotg: Programming view of DWC_otg controller
269 *
270 * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a
271 * Device to Host Mode transition or a Host to Device Mode transition. This only
272 * occurs when the cable is connected/removed from the PHY connector.
273 */
274static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
275{
276 u32 gintmsk;
277
278 /* Clear interrupt */
279 dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
280
281 /* Need to disable SOF interrupt immediately */
282 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
283 gintmsk &= ~GINTSTS_SOF;
284 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
285
286 dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n",
287 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
288
289 /*
290 * Need to schedule a work, as there are possible DELAY function calls.
291 * Release lock before scheduling workq as it holds spinlock during
292 * scheduling.
293 */
294 if (hsotg->wq_otg) {
295 spin_unlock(&hsotg->lock);
296 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
297 spin_lock(&hsotg->lock);
298 }
299}
300
301/**
302 * dwc2_handle_session_req_intr() - This interrupt indicates that a device is
303 * initiating the Session Request Protocol to request the host to turn on bus
304 * power so a new session can begin
305 *
306 * @hsotg: Programming view of DWC_otg controller
307 *
308 * This handler responds by turning on bus power. If the DWC_otg controller is
309 * in low power mode, this handler brings the controller out of low power mode
310 * before turning on bus power.
311 */
312static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
313{
314 int ret;
315
316 /* Clear interrupt */
317 dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
318
319 dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
320 hsotg->lx_state);
321
322 if (dwc2_is_device_mode(hsotg)) {
323 if (hsotg->lx_state == DWC2_L2) {
324 ret = dwc2_exit_partial_power_down(hsotg, true);
325 if (ret && (ret != -ENOTSUPP))
326 dev_err(hsotg->dev,
327 "exit power_down failed\n");
328 }
329
330 /*
331 * Report disconnect if there is any previous session
332 * established
333 */
334 dwc2_hsotg_disconnect(hsotg);
335 }
336}
337
338/**
339 * dwc2_wakeup_from_lpm_l1 - Exit the device from LPM L1 state
340 *
341 * @hsotg: Programming view of DWC_otg controller
342 *
343 */
344static void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg)
345{
346 u32 glpmcfg;
347 u32 i = 0;
348
349 if (hsotg->lx_state != DWC2_L1) {
350 dev_err(hsotg->dev, "Core isn't in DWC2_L1 state\n");
351 return;
352 }
353
354 glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG);
355 if (dwc2_is_device_mode(hsotg)) {
356 dev_dbg(hsotg->dev, "Exit from L1 state\n");
357 glpmcfg &= ~GLPMCFG_ENBLSLPM;
358 glpmcfg &= ~GLPMCFG_HIRD_THRES_EN;
359 dwc2_writel(glpmcfg, hsotg->regs + GLPMCFG);
360
361 do {
362 glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG);
363
364 if (!(glpmcfg & (GLPMCFG_COREL1RES_MASK |
365 GLPMCFG_L1RESUMEOK | GLPMCFG_SLPSTS)))
366 break;
367
368 udelay(1);
369 } while (++i < 200);
370
371 if (i == 200) {
372 dev_err(hsotg->dev, "Failed to exit L1 sleep state in 200us.\n");
373 return;
374 }
375 dwc2_gadget_init_lpm(hsotg);
376 } else {
377 /* TODO */
378 dev_err(hsotg->dev, "Host side LPM is not supported.\n");
379 return;
380 }
381
382 /* Change to L0 state */
383 hsotg->lx_state = DWC2_L0;
384
385 /* Inform gadget to exit from L1 */
386 call_gadget(hsotg, resume);
387}
388
389/*
390 * This interrupt indicates that the DWC_otg controller has detected a
391 * resume or remote wakeup sequence. If the DWC_otg controller is in
392 * low power mode, the handler must brings the controller out of low
393 * power mode. The controller automatically begins resume signaling.
394 * The handler schedules a time to stop resume signaling.
395 */
396static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
397{
398 int ret;
399
400 /* Clear interrupt */
401 dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
402
403 dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n");
404 dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
405
406 if (hsotg->lx_state == DWC2_L1) {
407 dwc2_wakeup_from_lpm_l1(hsotg);
408 return;
409 }
410
411 if (dwc2_is_device_mode(hsotg)) {
412 dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
413 dwc2_readl(hsotg->regs + DSTS));
414 if (hsotg->lx_state == DWC2_L2) {
415 u32 dctl = dwc2_readl(hsotg->regs + DCTL);
416
417 /* Clear Remote Wakeup Signaling */
418 dctl &= ~DCTL_RMTWKUPSIG;
419 dwc2_writel(dctl, hsotg->regs + DCTL);
420 ret = dwc2_exit_partial_power_down(hsotg, true);
421 if (ret && (ret != -ENOTSUPP))
422 dev_err(hsotg->dev, "exit power_down failed\n");
423
424 call_gadget(hsotg, resume);
425 }
426 /* Change to L0 state */
427 hsotg->lx_state = DWC2_L0;
428 } else {
429 if (hsotg->params.power_down)
430 return;
431
432 if (hsotg->lx_state != DWC2_L1) {
433 u32 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
434
435 /* Restart the Phy Clock */
436 pcgcctl &= ~PCGCTL_STOPPCLK;
437 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
438 mod_timer(&hsotg->wkp_timer,
439 jiffies + msecs_to_jiffies(71));
440 } else {
441 /* Change to L0 state */
442 hsotg->lx_state = DWC2_L0;
443 }
444 }
445}
446
447/*
448 * This interrupt indicates that a device has been disconnected from the
449 * root port
450 */
451static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
452{
453 dwc2_writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS);
454
455 dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n",
456 dwc2_is_host_mode(hsotg) ? "Host" : "Device",
457 dwc2_op_state_str(hsotg));
458
459 if (hsotg->op_state == OTG_STATE_A_HOST)
460 dwc2_hcd_disconnect(hsotg, false);
461}
462
463/*
464 * This interrupt indicates that SUSPEND state has been detected on the USB.
465 *
466 * For HNP the USB Suspend interrupt signals the change from "a_peripheral"
467 * to "a_host".
468 *
469 * When power management is enabled the core will be put in low power mode.
470 */
471static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
472{
473 u32 dsts;
474 int ret;
475
476 /* Clear interrupt */
477 dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
478
479 dev_dbg(hsotg->dev, "USB SUSPEND\n");
480
481 if (dwc2_is_device_mode(hsotg)) {
482 /*
483 * Check the Device status register to determine if the Suspend
484 * state is active
485 */
486 dsts = dwc2_readl(hsotg->regs + DSTS);
487 dev_dbg(hsotg->dev, "%s: DSTS=0x%0x\n", __func__, dsts);
488 dev_dbg(hsotg->dev,
489 "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d HWCFG4.Hibernation=%d\n",
490 !!(dsts & DSTS_SUSPSTS),
491 hsotg->hw_params.power_optimized,
492 hsotg->hw_params.hibernation);
493
494 /* Ignore suspend request before enumeration */
495 if (!dwc2_is_device_connected(hsotg)) {
496 dev_dbg(hsotg->dev,
497 "ignore suspend request before enumeration\n");
498 return;
499 }
500 if (dsts & DSTS_SUSPSTS) {
501 if (hsotg->hw_params.power_optimized) {
502 ret = dwc2_enter_partial_power_down(hsotg);
503 if (ret) {
504 if (ret != -ENOTSUPP)
505 dev_err(hsotg->dev,
506 "%s: enter partial_power_down failed\n",
507 __func__);
508 goto skip_power_saving;
509 }
510
511 udelay(100);
512
513 /* Ask phy to be suspended */
514 if (!IS_ERR_OR_NULL(hsotg->uphy))
515 usb_phy_set_suspend(hsotg->uphy, true);
516 }
517
518 if (hsotg->hw_params.hibernation) {
519 ret = dwc2_enter_hibernation(hsotg, 0);
520 if (ret && ret != -ENOTSUPP)
521 dev_err(hsotg->dev,
522 "%s: enter hibernation failed\n",
523 __func__);
524 }
525skip_power_saving:
526 /*
527 * Change to L2 (suspend) state before releasing
528 * spinlock
529 */
530 hsotg->lx_state = DWC2_L2;
531
532 /* Call gadget suspend callback */
533 call_gadget(hsotg, suspend);
534 }
535 } else {
536 if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) {
537 dev_dbg(hsotg->dev, "a_peripheral->a_host\n");
538
539 /* Change to L2 (suspend) state */
540 hsotg->lx_state = DWC2_L2;
541 /* Clear the a_peripheral flag, back to a_host */
542 spin_unlock(&hsotg->lock);
543 dwc2_hcd_start(hsotg);
544 spin_lock(&hsotg->lock);
545 hsotg->op_state = OTG_STATE_A_HOST;
546 }
547 }
548}
549
550/**
551 * dwc2_handle_lpm_intr - GINTSTS_LPMTRANRCVD Interrupt handler
552 *
553 * @hsotg: Programming view of DWC_otg controller
554 *
555 */
556static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg)
557{
558 u32 glpmcfg;
559 u32 pcgcctl;
560 u32 hird;
561 u32 hird_thres;
562 u32 hird_thres_en;
563 u32 enslpm;
564
565 /* Clear interrupt */
566 dwc2_writel(GINTSTS_LPMTRANRCVD, hsotg->regs + GINTSTS);
567
568 glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG);
569
570 if (!(glpmcfg & GLPMCFG_LPMCAP)) {
571 dev_err(hsotg->dev, "Unexpected LPM interrupt\n");
572 return;
573 }
574
575 hird = (glpmcfg & GLPMCFG_HIRD_MASK) >> GLPMCFG_HIRD_SHIFT;
576 hird_thres = (glpmcfg & GLPMCFG_HIRD_THRES_MASK &
577 ~GLPMCFG_HIRD_THRES_EN) >> GLPMCFG_HIRD_THRES_SHIFT;
578 hird_thres_en = glpmcfg & GLPMCFG_HIRD_THRES_EN;
579 enslpm = glpmcfg & GLPMCFG_ENBLSLPM;
580
581 if (dwc2_is_device_mode(hsotg)) {
582 dev_dbg(hsotg->dev, "HIRD_THRES_EN = %d\n", hird_thres_en);
583
584 if (hird_thres_en && hird >= hird_thres) {
585 dev_dbg(hsotg->dev, "L1 with utmi_l1_suspend_n\n");
586 } else if (enslpm) {
587 dev_dbg(hsotg->dev, "L1 with utmi_sleep_n\n");
588 } else {
589 dev_dbg(hsotg->dev, "Entering Sleep with L1 Gating\n");
590
591 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
592 pcgcctl |= PCGCTL_ENBL_SLEEP_GATING;
593 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
594 }
595 /**
596 * Examine prt_sleep_sts after TL1TokenTetry period max (10 us)
597 */
598 udelay(10);
599
600 glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG);
601
602 if (glpmcfg & GLPMCFG_SLPSTS) {
603 /* Save the current state */
604 hsotg->lx_state = DWC2_L1;
605 dev_dbg(hsotg->dev,
606 "Core is in L1 sleep glpmcfg=%08x\n", glpmcfg);
607
608 /* Inform gadget that we are in L1 state */
609 call_gadget(hsotg, suspend);
610 }
611 }
612}
613
614#define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \
615 GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT | \
616 GINTSTS_MODEMIS | GINTSTS_DISCONNINT | \
617 GINTSTS_USBSUSP | GINTSTS_PRTINT | \
618 GINTSTS_LPMTRANRCVD)
619
620/*
621 * This function returns the Core Interrupt register
622 */
623static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
624{
625 u32 gintsts;
626 u32 gintmsk;
627 u32 gahbcfg;
628 u32 gintmsk_common = GINTMSK_COMMON;
629
630 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
631 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
632 gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
633
634 /* If any common interrupts set */
635 if (gintsts & gintmsk_common)
636 dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n",
637 gintsts, gintmsk);
638
639 if (gahbcfg & GAHBCFG_GLBL_INTR_EN)
640 return gintsts & gintmsk & gintmsk_common;
641 else
642 return 0;
643}
644
645/*
646 * GPWRDN interrupt handler.
647 *
648 * The GPWRDN interrupts are those that occur in both Host and
649 * Device mode while core is in hibernated state.
650 */
651static void dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg)
652{
653 u32 gpwrdn;
654 int linestate;
655
656 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
657 /* clear all interrupt */
658 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
659 linestate = (gpwrdn & GPWRDN_LINESTATE_MASK) >> GPWRDN_LINESTATE_SHIFT;
660 dev_dbg(hsotg->dev,
661 "%s: dwc2_handle_gpwrdwn_intr called gpwrdn= %08x\n", __func__,
662 gpwrdn);
663
664 if ((gpwrdn & GPWRDN_DISCONN_DET) &&
665 (gpwrdn & GPWRDN_DISCONN_DET_MSK) && !linestate) {
666 u32 gpwrdn_tmp;
667
668 dev_dbg(hsotg->dev, "%s: GPWRDN_DISCONN_DET\n", __func__);
669
670 /* Switch-on voltage to the core */
671 gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN);
672 gpwrdn_tmp &= ~GPWRDN_PWRDNSWTCH;
673 dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN);
674 udelay(10);
675
676 /* Reset core */
677 gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN);
678 gpwrdn_tmp &= ~GPWRDN_PWRDNRSTN;
679 dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN);
680 udelay(10);
681
682 /* Disable Power Down Clamp */
683 gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN);
684 gpwrdn_tmp &= ~GPWRDN_PWRDNCLMP;
685 dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN);
686 udelay(10);
687
688 /* Deassert reset core */
689 gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN);
690 gpwrdn_tmp |= GPWRDN_PWRDNRSTN;
691 dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN);
692 udelay(10);
693
694 /* Disable PMU interrupt */
695 gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN);
696 gpwrdn_tmp &= ~GPWRDN_PMUINTSEL;
697 dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN);
698
699 /* De-assert Wakeup Logic */
700 gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN);
701 gpwrdn_tmp &= ~GPWRDN_PMUACTV;
702 dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN);
703
704 hsotg->hibernated = 0;
705
706 if (gpwrdn & GPWRDN_IDSTS) {
707 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
708 dwc2_core_init(hsotg, false);
709 dwc2_enable_global_interrupts(hsotg);
710 dwc2_hsotg_core_init_disconnected(hsotg, false);
711 dwc2_hsotg_core_connect(hsotg);
712 } else {
713 hsotg->op_state = OTG_STATE_A_HOST;
714
715 /* Initialize the Core for Host mode */
716 dwc2_core_init(hsotg, false);
717 dwc2_enable_global_interrupts(hsotg);
718 dwc2_hcd_start(hsotg);
719 }
720 }
721
722 if ((gpwrdn & GPWRDN_LNSTSCHG) &&
723 (gpwrdn & GPWRDN_LNSTSCHG_MSK) && linestate) {
724 dev_dbg(hsotg->dev, "%s: GPWRDN_LNSTSCHG\n", __func__);
725 if (hsotg->hw_params.hibernation &&
726 hsotg->hibernated) {
727 if (gpwrdn & GPWRDN_IDSTS) {
728 dwc2_exit_hibernation(hsotg, 0, 0, 0);
729 call_gadget(hsotg, resume);
730 } else {
731 dwc2_exit_hibernation(hsotg, 1, 0, 1);
732 }
733 }
734 }
735 if ((gpwrdn & GPWRDN_RST_DET) && (gpwrdn & GPWRDN_RST_DET_MSK)) {
736 dev_dbg(hsotg->dev, "%s: GPWRDN_RST_DET\n", __func__);
737 if (!linestate && (gpwrdn & GPWRDN_BSESSVLD))
738 dwc2_exit_hibernation(hsotg, 0, 1, 0);
739 }
740 if ((gpwrdn & GPWRDN_STS_CHGINT) &&
741 (gpwrdn & GPWRDN_STS_CHGINT_MSK) && linestate) {
742 dev_dbg(hsotg->dev, "%s: GPWRDN_STS_CHGINT\n", __func__);
743 if (hsotg->hw_params.hibernation &&
744 hsotg->hibernated) {
745 if (gpwrdn & GPWRDN_IDSTS) {
746 dwc2_exit_hibernation(hsotg, 0, 0, 0);
747 call_gadget(hsotg, resume);
748 } else {
749 dwc2_exit_hibernation(hsotg, 1, 0, 1);
750 }
751 }
752 }
753}
754
755/*
756 * Common interrupt handler
757 *
758 * The common interrupts are those that occur in both Host and Device mode.
759 * This handler handles the following interrupts:
760 * - Mode Mismatch Interrupt
761 * - OTG Interrupt
762 * - Connector ID Status Change Interrupt
763 * - Disconnect Interrupt
764 * - Session Request Interrupt
765 * - Resume / Remote Wakeup Detected Interrupt
766 * - Suspend Interrupt
767 */
768irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
769{
770 struct dwc2_hsotg *hsotg = dev;
771 u32 gintsts;
772 irqreturn_t retval = IRQ_NONE;
773
774 spin_lock(&hsotg->lock);
775
776 if (!dwc2_is_controller_alive(hsotg)) {
777 dev_warn(hsotg->dev, "Controller is dead\n");
778 goto out;
779 }
780
781 gintsts = dwc2_read_common_intr(hsotg);
782 if (gintsts & ~GINTSTS_PRTINT)
783 retval = IRQ_HANDLED;
784
785 /* In case of hibernated state gintsts must not work */
786 if (hsotg->hibernated) {
787 dwc2_handle_gpwrdn_intr(hsotg);
788 retval = IRQ_HANDLED;
789 goto out;
790 }
791
792 if (gintsts & GINTSTS_MODEMIS)
793 dwc2_handle_mode_mismatch_intr(hsotg);
794 if (gintsts & GINTSTS_OTGINT)
795 dwc2_handle_otg_intr(hsotg);
796 if (gintsts & GINTSTS_CONIDSTSCHNG)
797 dwc2_handle_conn_id_status_change_intr(hsotg);
798 if (gintsts & GINTSTS_DISCONNINT)
799 dwc2_handle_disconnect_intr(hsotg);
800 if (gintsts & GINTSTS_SESSREQINT)
801 dwc2_handle_session_req_intr(hsotg);
802 if (gintsts & GINTSTS_WKUPINT)
803 dwc2_handle_wakeup_detected_intr(hsotg);
804 if (gintsts & GINTSTS_USBSUSP)
805 dwc2_handle_usb_suspend_intr(hsotg);
806 if (gintsts & GINTSTS_LPMTRANRCVD)
807 dwc2_handle_lpm_intr(hsotg);
808
809 if (gintsts & GINTSTS_PRTINT) {
810 /*
811 * The port interrupt occurs while in device mode with HPRT0
812 * Port Enable/Disable
813 */
814 if (dwc2_is_device_mode(hsotg)) {
815 dev_dbg(hsotg->dev,
816 " --Port interrupt received in Device mode--\n");
817 dwc2_handle_usb_port_intr(hsotg);
818 retval = IRQ_HANDLED;
819 }
820 }
821
822out:
823 spin_unlock(&hsotg->lock);
824 return retval;
825}