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1/*****************************************************************************/
2/* ips.c -- driver for the Adaptec / IBM ServeRAID controller */
3/* */
4/* Written By: Keith Mitchell, IBM Corporation */
5/* Jack Hammer, Adaptec, Inc. */
6/* David Jeffery, Adaptec, Inc. */
7/* */
8/* Copyright (C) 2000 IBM Corporation */
9/* Copyright (C) 2002,2003 Adaptec, Inc. */
10/* */
11/* This program is free software; you can redistribute it and/or modify */
12/* it under the terms of the GNU General Public License as published by */
13/* the Free Software Foundation; either version 2 of the License, or */
14/* (at your option) any later version. */
15/* */
16/* This program is distributed in the hope that it will be useful, */
17/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19/* GNU General Public License for more details. */
20/* */
21/* NO WARRANTY */
22/* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23/* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24/* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25/* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26/* solely responsible for determining the appropriateness of using and */
27/* distributing the Program and assumes all risks associated with its */
28/* exercise of rights under this Agreement, including but not limited to */
29/* the risks and costs of program errors, damage to or loss of data, */
30/* programs or equipment, and unavailability or interruption of operations. */
31/* */
32/* DISCLAIMER OF LIABILITY */
33/* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34/* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35/* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37/* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38/* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39/* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
40/* */
41/* You should have received a copy of the GNU General Public License */
42/* along with this program; if not, write to the Free Software */
43/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
44/* */
45/* Bugs/Comments/Suggestions about this driver should be mailed to: */
46/* ipslinux@adaptec.com */
47/* */
48/* For system support issues, contact your local IBM Customer support. */
49/* Directions to find IBM Customer Support for each country can be found at: */
50/* http://www.ibm.com/planetwide/ */
51/* */
52/*****************************************************************************/
53
54/*****************************************************************************/
55/* Change Log */
56/* */
57/* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */
58/* 0.99.03 - Make interrupt routine handle all completed request on the */
59/* adapter not just the first one */
60/* - Make sure passthru commands get woken up if we run out of */
61/* SCBs */
62/* - Send all of the commands on the queue at once rather than */
63/* one at a time since the card will support it. */
64/* 0.99.04 - Fix race condition in the passthru mechanism -- this required */
65/* the interface to the utilities to change */
66/* - Fix error recovery code */
67/* 0.99.05 - Fix an oops when we get certain passthru commands */
68/* 1.00.00 - Initial Public Release */
69/* Functionally equivalent to 0.99.05 */
70/* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */
71/* - Change version to 3.60 to coincide with release numbering. */
72/* 3.60.01 - Remove bogus error check in passthru routine */
73/* 3.60.02 - Make DCDB direction based on lookup table */
74/* - Only allow one DCDB command to a SCSI ID at a time */
75/* 4.00.00 - Add support for ServeRAID 4 */
76/* 4.00.01 - Add support for First Failure Data Capture */
77/* 4.00.02 - Fix problem with PT DCDB with no buffer */
78/* 4.00.03 - Add alternative passthru interface */
79/* - Add ability to flash BIOS */
80/* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */
81/* 4.00.05 - Remove wish_block from init routine */
82/* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */
83/* 2.3.18 and later */
84/* - Sync with other changes from the 2.3 kernels */
85/* 4.00.06 - Fix timeout with initial FFDC command */
86/* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */
87/* 4.10.00 - Add support for ServeRAID 4M/4L */
88/* 4.10.13 - Fix for dynamic unload and proc file system */
89/* 4.20.03 - Rename version to coincide with new release schedules */
90/* Performance fixes */
91/* Fix truncation of /proc files with cat */
92/* Merge in changes through kernel 2.4.0test1ac21 */
93/* 4.20.13 - Fix some failure cases / reset code */
94/* - Hook into the reboot_notifier to flush the controller cache */
95/* 4.50.01 - Fix problem when there is a hole in logical drive numbering */
96/* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */
97/* - Add IPSSEND Flash Support */
98/* - Set Sense Data for Unknown SCSI Command */
99/* - Use Slot Number from NVRAM Page 5 */
100/* - Restore caller's DCDB Structure */
101/* 4.70.12 - Corrective actions for bad controller ( during initialization )*/
102/* 4.70.13 - Don't Send CDB's if we already know the device is not present */
103/* - Don't release HA Lock in ips_next() until SC taken off queue */
104/* - Unregister SCSI device in ips_release() */
105/* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */
106/* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */
107/* Code Clean-Up for 2.4.x kernel */
108/* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */
109/* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */
110/* - Don't Issue Internal FFDC Command if there are Active Commands */
111/* - Close Window for getting too many IOCTL's active */
112/* 4.80.00 - Make ia64 Safe */
113/* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */
114/* - Adjustments to Device Queue Depth */
115/* 4.80.14 - Take all semaphores off stack */
116/* - Clean Up New_IOCTL path */
117/* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */
118/* - 5 second delay needed after resetting an i960 adapter */
119/* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */
120/* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */
121/* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */
122/* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */
123/* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */
124/* 4.90.11 - Don't actually RESET unless it's physically required */
125/* - Remove unused compile options */
126/* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */
127/* - Get rid on IOCTL_NEW_COMMAND code */
128/* - Add Extended DCDB Commands for Tape Support in 5I */
129/* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */
130/* 5.10.15 - remove unused code (sem, macros, etc.) */
131/* 5.30.00 - use __devexit_p() */
132/* 6.00.00 - Add 6x Adapters and Battery Flash */
133/* 6.10.00 - Remove 1G Addressing Limitations */
134/* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */
135/* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */
136/* 7.10.18 - Add highmem_io flag in SCSI Templete for 2.4 kernels */
137/* - Fix path/name for scsi_hosts.h include for 2.6 kernels */
138/* - Fix sort order of 7k */
139/* - Remove 3 unused "inline" functions */
140/* 7.12.xx - Use STATIC functions wherever possible */
141/* - Clean up deprecated MODULE_PARM calls */
142/* 7.12.05 - Remove Version Matching per IBM request */
143/*****************************************************************************/
144
145/*
146 * Conditional Compilation directives for this driver:
147 *
148 * IPS_DEBUG - Turn on debugging info
149 *
150 * Parameters:
151 *
152 * debug:<number> - Set debug level to <number>
153 * NOTE: only works when IPS_DEBUG compile directive is used.
154 * 1 - Normal debug messages
155 * 2 - Verbose debug messages
156 * 11 - Method trace (non interrupt)
157 * 12 - Method trace (includes interrupt)
158 *
159 * noi2o - Don't use I2O Queues (ServeRAID 4 only)
160 * nommap - Don't use memory mapped I/O
161 * ioctlsize - Initial size of the IOCTL buffer
162 */
163
164#include <asm/io.h>
165#include <asm/byteorder.h>
166#include <asm/page.h>
167#include <linux/stddef.h>
168#include <linux/string.h>
169#include <linux/errno.h>
170#include <linux/kernel.h>
171#include <linux/ioport.h>
172#include <linux/slab.h>
173#include <linux/delay.h>
174#include <linux/pci.h>
175#include <linux/proc_fs.h>
176#include <linux/reboot.h>
177#include <linux/interrupt.h>
178
179#include <linux/blkdev.h>
180#include <linux/types.h>
181#include <linux/dma-mapping.h>
182
183#include <scsi/sg.h>
184#include "scsi.h"
185#include <scsi/scsi_host.h>
186
187#include "ips.h"
188
189#include <linux/module.h>
190
191#include <linux/stat.h>
192
193#include <linux/spinlock.h>
194#include <linux/init.h>
195
196#include <linux/smp.h>
197
198#ifdef MODULE
199static char *ips = NULL;
200module_param(ips, charp, 0);
201#endif
202
203/*
204 * DRIVER_VER
205 */
206#define IPS_VERSION_HIGH IPS_VER_MAJOR_STRING "." IPS_VER_MINOR_STRING
207#define IPS_VERSION_LOW "." IPS_VER_BUILD_STRING " "
208
209#if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__)
210#warning "This driver has only been tested on the x86/ia64/x86_64 platforms"
211#endif
212
213#define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \
214 DMA_NONE == scb->scsi_cmd->sc_data_direction) ? \
215 PCI_DMA_BIDIRECTIONAL : \
216 scb->scsi_cmd->sc_data_direction)
217
218#ifdef IPS_DEBUG
219#define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n");
220#define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n");
221#define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v);
222#else
223#define METHOD_TRACE(s, i)
224#define DEBUG(i, s)
225#define DEBUG_VAR(i, s, v...)
226#endif
227
228/*
229 * Function prototypes
230 */
231static int ips_detect(struct scsi_host_template *);
232static int ips_release(struct Scsi_Host *);
233static int ips_eh_abort(struct scsi_cmnd *);
234static int ips_eh_reset(struct scsi_cmnd *);
235static int ips_queue(struct Scsi_Host *, struct scsi_cmnd *);
236static const char *ips_info(struct Scsi_Host *);
237static irqreturn_t do_ipsintr(int, void *);
238static int ips_hainit(ips_ha_t *);
239static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *);
240static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int);
241static int ips_send_cmd(ips_ha_t *, ips_scb_t *);
242static int ips_online(ips_ha_t *, ips_scb_t *);
243static int ips_inquiry(ips_ha_t *, ips_scb_t *);
244static int ips_rdcap(ips_ha_t *, ips_scb_t *);
245static int ips_msense(ips_ha_t *, ips_scb_t *);
246static int ips_reqsen(ips_ha_t *, ips_scb_t *);
247static int ips_deallocatescbs(ips_ha_t *, int);
248static int ips_allocatescbs(ips_ha_t *);
249static int ips_reset_copperhead(ips_ha_t *);
250static int ips_reset_copperhead_memio(ips_ha_t *);
251static int ips_reset_morpheus(ips_ha_t *);
252static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *);
253static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *);
254static int ips_issue_i2o(ips_ha_t *, ips_scb_t *);
255static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *);
256static int ips_isintr_copperhead(ips_ha_t *);
257static int ips_isintr_copperhead_memio(ips_ha_t *);
258static int ips_isintr_morpheus(ips_ha_t *);
259static int ips_wait(ips_ha_t *, int, int);
260static int ips_write_driver_status(ips_ha_t *, int);
261static int ips_read_adapter_status(ips_ha_t *, int);
262static int ips_read_subsystem_parameters(ips_ha_t *, int);
263static int ips_read_config(ips_ha_t *, int);
264static int ips_clear_adapter(ips_ha_t *, int);
265static int ips_readwrite_page5(ips_ha_t *, int, int);
266static int ips_init_copperhead(ips_ha_t *);
267static int ips_init_copperhead_memio(ips_ha_t *);
268static int ips_init_morpheus(ips_ha_t *);
269static int ips_isinit_copperhead(ips_ha_t *);
270static int ips_isinit_copperhead_memio(ips_ha_t *);
271static int ips_isinit_morpheus(ips_ha_t *);
272static int ips_erase_bios(ips_ha_t *);
273static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t);
274static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t);
275static int ips_erase_bios_memio(ips_ha_t *);
276static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
277static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
278static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
279static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
280static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
281static void ips_free_flash_copperhead(ips_ha_t * ha);
282static void ips_get_bios_version(ips_ha_t *, int);
283static void ips_identify_controller(ips_ha_t *);
284static void ips_chkstatus(ips_ha_t *, IPS_STATUS *);
285static void ips_enable_int_copperhead(ips_ha_t *);
286static void ips_enable_int_copperhead_memio(ips_ha_t *);
287static void ips_enable_int_morpheus(ips_ha_t *);
288static int ips_intr_copperhead(ips_ha_t *);
289static int ips_intr_morpheus(ips_ha_t *);
290static void ips_next(ips_ha_t *, int);
291static void ipsintr_blocking(ips_ha_t *, struct ips_scb *);
292static void ipsintr_done(ips_ha_t *, struct ips_scb *);
293static void ips_done(ips_ha_t *, ips_scb_t *);
294static void ips_free(ips_ha_t *);
295static void ips_init_scb(ips_ha_t *, ips_scb_t *);
296static void ips_freescb(ips_ha_t *, ips_scb_t *);
297static void ips_setup_funclist(ips_ha_t *);
298static void ips_statinit(ips_ha_t *);
299static void ips_statinit_memio(ips_ha_t *);
300static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time_t);
301static void ips_ffdc_reset(ips_ha_t *, int);
302static void ips_ffdc_time(ips_ha_t *);
303static uint32_t ips_statupd_copperhead(ips_ha_t *);
304static uint32_t ips_statupd_copperhead_memio(ips_ha_t *);
305static uint32_t ips_statupd_morpheus(ips_ha_t *);
306static ips_scb_t *ips_getscb(ips_ha_t *);
307static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *);
308static void ips_putq_wait_tail(ips_wait_queue_t *, struct scsi_cmnd *);
309static void ips_putq_copp_tail(ips_copp_queue_t *,
310 ips_copp_wait_item_t *);
311static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *);
312static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *);
313static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_t *);
314static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_t *,
315 struct scsi_cmnd *);
316static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *,
317 ips_copp_wait_item_t *);
318static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *);
319
320static int ips_is_passthru(struct scsi_cmnd *);
321static int ips_make_passthru(ips_ha_t *, struct scsi_cmnd *, ips_scb_t *, int);
322static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
323static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *);
324static void ips_scmd_buf_write(struct scsi_cmnd * scmd, void *data,
325 unsigned int count);
326static void ips_scmd_buf_read(struct scsi_cmnd * scmd, void *data,
327 unsigned int count);
328
329static int ips_proc_info(struct Scsi_Host *, char *, char **, off_t, int, int);
330static int ips_host_info(ips_ha_t *, char *, off_t, int);
331static void copy_mem_info(IPS_INFOSTR *, char *, int);
332static int copy_info(IPS_INFOSTR *, char *, ...);
333static int ips_abort_init(ips_ha_t * ha, int index);
334static int ips_init_phase2(int index);
335
336static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr);
337static int ips_register_scsi(int index);
338
339static int ips_poll_for_flush_complete(ips_ha_t * ha);
340static void ips_flush_and_reset(ips_ha_t *ha);
341
342/*
343 * global variables
344 */
345static const char ips_name[] = "ips";
346static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */
347static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */
348static unsigned int ips_next_controller;
349static unsigned int ips_num_controllers;
350static unsigned int ips_released_controllers;
351static int ips_hotplug;
352static int ips_cmd_timeout = 60;
353static int ips_reset_timeout = 60 * 5;
354static int ips_force_memio = 1; /* Always use Memory Mapped I/O */
355static int ips_force_i2o = 1; /* Always use I2O command delivery */
356static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */
357static int ips_cd_boot; /* Booting from Manager CD */
358static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */
359static dma_addr_t ips_flashbusaddr;
360static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */
361static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */
362static struct scsi_host_template ips_driver_template = {
363 .detect = ips_detect,
364 .release = ips_release,
365 .info = ips_info,
366 .queuecommand = ips_queue,
367 .eh_abort_handler = ips_eh_abort,
368 .eh_host_reset_handler = ips_eh_reset,
369 .proc_name = "ips",
370 .proc_info = ips_proc_info,
371 .slave_configure = ips_slave_configure,
372 .bios_param = ips_biosparam,
373 .this_id = -1,
374 .sg_tablesize = IPS_MAX_SG,
375 .cmd_per_lun = 3,
376 .use_clustering = ENABLE_CLUSTERING,
377};
378
379
380/* This table describes all ServeRAID Adapters */
381static struct pci_device_id ips_pci_table[] = {
382 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
383 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
384 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
385 { 0, }
386};
387
388MODULE_DEVICE_TABLE( pci, ips_pci_table );
389
390static char ips_hot_plug_name[] = "ips";
391
392static int __devinit ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent);
393static void __devexit ips_remove_device(struct pci_dev *pci_dev);
394
395static struct pci_driver ips_pci_driver = {
396 .name = ips_hot_plug_name,
397 .id_table = ips_pci_table,
398 .probe = ips_insert_device,
399 .remove = __devexit_p(ips_remove_device),
400};
401
402
403/*
404 * Necessary forward function protoypes
405 */
406static int ips_halt(struct notifier_block *nb, ulong event, void *buf);
407
408#define MAX_ADAPTER_NAME 15
409
410static char ips_adapter_name[][30] = {
411 "ServeRAID",
412 "ServeRAID II",
413 "ServeRAID on motherboard",
414 "ServeRAID on motherboard",
415 "ServeRAID 3H",
416 "ServeRAID 3L",
417 "ServeRAID 4H",
418 "ServeRAID 4M",
419 "ServeRAID 4L",
420 "ServeRAID 4Mx",
421 "ServeRAID 4Lx",
422 "ServeRAID 5i",
423 "ServeRAID 5i",
424 "ServeRAID 6M",
425 "ServeRAID 6i",
426 "ServeRAID 7t",
427 "ServeRAID 7k",
428 "ServeRAID 7M"
429};
430
431static struct notifier_block ips_notifier = {
432 ips_halt, NULL, 0
433};
434
435/*
436 * Direction table
437 */
438static char ips_command_direction[] = {
439 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT,
440 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK,
441 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
442 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
443 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT,
444 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
445 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN,
446 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
447 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK,
448 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
449 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE,
450 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
451 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT,
452 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE,
453 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK,
454 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
455 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
456 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
457 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
458 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
459 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
460 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
461 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
462 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
463 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
464 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
465 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
466 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
467 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
468 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
469 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
470 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
471 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
472 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE,
473 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT,
474 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE,
475 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN,
476 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
477 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
478 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
479 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
480 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
481 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
482 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
483 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
484 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
485 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT,
486 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
487 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
488 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
489 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK
490};
491
492
493/****************************************************************************/
494/* */
495/* Routine Name: ips_setup */
496/* */
497/* Routine Description: */
498/* */
499/* setup parameters to the driver */
500/* */
501/****************************************************************************/
502static int
503ips_setup(char *ips_str)
504{
505
506 int i;
507 char *key;
508 char *value;
509 IPS_OPTION options[] = {
510 {"noi2o", &ips_force_i2o, 0},
511 {"nommap", &ips_force_memio, 0},
512 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE},
513 {"cdboot", &ips_cd_boot, 0},
514 {"maxcmds", &MaxLiteCmds, 32},
515 };
516
517 /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */
518 /* Search for value */
519 while ((key = strsep(&ips_str, ",."))) {
520 if (!*key)
521 continue;
522 value = strchr(key, ':');
523 if (value)
524 *value++ = '\0';
525 /*
526 * We now have key/value pairs.
527 * Update the variables
528 */
529 for (i = 0; i < ARRAY_SIZE(options); i++) {
530 if (strnicmp
531 (key, options[i].option_name,
532 strlen(options[i].option_name)) == 0) {
533 if (value)
534 *options[i].option_flag =
535 simple_strtoul(value, NULL, 0);
536 else
537 *options[i].option_flag =
538 options[i].option_value;
539 break;
540 }
541 }
542 }
543
544 return (1);
545}
546
547__setup("ips=", ips_setup);
548
549/****************************************************************************/
550/* */
551/* Routine Name: ips_detect */
552/* */
553/* Routine Description: */
554/* */
555/* Detect and initialize the driver */
556/* */
557/* NOTE: this routine is called under the io_request_lock spinlock */
558/* */
559/****************************************************************************/
560static int
561ips_detect(struct scsi_host_template * SHT)
562{
563 int i;
564
565 METHOD_TRACE("ips_detect", 1);
566
567#ifdef MODULE
568 if (ips)
569 ips_setup(ips);
570#endif
571
572 for (i = 0; i < ips_num_controllers; i++) {
573 if (ips_register_scsi(i))
574 ips_free(ips_ha[i]);
575 ips_released_controllers++;
576 }
577 ips_hotplug = 1;
578 return (ips_num_controllers);
579}
580
581/****************************************************************************/
582/* configure the function pointers to use the functions that will work */
583/* with the found version of the adapter */
584/****************************************************************************/
585static void
586ips_setup_funclist(ips_ha_t * ha)
587{
588
589 /*
590 * Setup Functions
591 */
592 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
593 /* morpheus / marco / sebring */
594 ha->func.isintr = ips_isintr_morpheus;
595 ha->func.isinit = ips_isinit_morpheus;
596 ha->func.issue = ips_issue_i2o_memio;
597 ha->func.init = ips_init_morpheus;
598 ha->func.statupd = ips_statupd_morpheus;
599 ha->func.reset = ips_reset_morpheus;
600 ha->func.intr = ips_intr_morpheus;
601 ha->func.enableint = ips_enable_int_morpheus;
602 } else if (IPS_USE_MEMIO(ha)) {
603 /* copperhead w/MEMIO */
604 ha->func.isintr = ips_isintr_copperhead_memio;
605 ha->func.isinit = ips_isinit_copperhead_memio;
606 ha->func.init = ips_init_copperhead_memio;
607 ha->func.statupd = ips_statupd_copperhead_memio;
608 ha->func.statinit = ips_statinit_memio;
609 ha->func.reset = ips_reset_copperhead_memio;
610 ha->func.intr = ips_intr_copperhead;
611 ha->func.erasebios = ips_erase_bios_memio;
612 ha->func.programbios = ips_program_bios_memio;
613 ha->func.verifybios = ips_verify_bios_memio;
614 ha->func.enableint = ips_enable_int_copperhead_memio;
615 if (IPS_USE_I2O_DELIVER(ha))
616 ha->func.issue = ips_issue_i2o_memio;
617 else
618 ha->func.issue = ips_issue_copperhead_memio;
619 } else {
620 /* copperhead */
621 ha->func.isintr = ips_isintr_copperhead;
622 ha->func.isinit = ips_isinit_copperhead;
623 ha->func.init = ips_init_copperhead;
624 ha->func.statupd = ips_statupd_copperhead;
625 ha->func.statinit = ips_statinit;
626 ha->func.reset = ips_reset_copperhead;
627 ha->func.intr = ips_intr_copperhead;
628 ha->func.erasebios = ips_erase_bios;
629 ha->func.programbios = ips_program_bios;
630 ha->func.verifybios = ips_verify_bios;
631 ha->func.enableint = ips_enable_int_copperhead;
632
633 if (IPS_USE_I2O_DELIVER(ha))
634 ha->func.issue = ips_issue_i2o;
635 else
636 ha->func.issue = ips_issue_copperhead;
637 }
638}
639
640/****************************************************************************/
641/* */
642/* Routine Name: ips_release */
643/* */
644/* Routine Description: */
645/* */
646/* Remove a driver */
647/* */
648/****************************************************************************/
649static int
650ips_release(struct Scsi_Host *sh)
651{
652 ips_scb_t *scb;
653 ips_ha_t *ha;
654 int i;
655
656 METHOD_TRACE("ips_release", 1);
657
658 scsi_remove_host(sh);
659
660 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ;
661
662 if (i == IPS_MAX_ADAPTERS) {
663 printk(KERN_WARNING
664 "(%s) release, invalid Scsi_Host pointer.\n", ips_name);
665 BUG();
666 return (FALSE);
667 }
668
669 ha = IPS_HA(sh);
670
671 if (!ha)
672 return (FALSE);
673
674 /* flush the cache on the controller */
675 scb = &ha->scbs[ha->max_cmds - 1];
676
677 ips_init_scb(ha, scb);
678
679 scb->timeout = ips_cmd_timeout;
680 scb->cdb[0] = IPS_CMD_FLUSH;
681
682 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
683 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
684 scb->cmd.flush_cache.state = IPS_NORM_STATE;
685 scb->cmd.flush_cache.reserved = 0;
686 scb->cmd.flush_cache.reserved2 = 0;
687 scb->cmd.flush_cache.reserved3 = 0;
688 scb->cmd.flush_cache.reserved4 = 0;
689
690 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
691
692 /* send command */
693 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE)
694 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n");
695
696 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n");
697
698 ips_sh[i] = NULL;
699 ips_ha[i] = NULL;
700
701 /* free extra memory */
702 ips_free(ha);
703
704 /* free IRQ */
705 free_irq(ha->pcidev->irq, ha);
706
707 scsi_host_put(sh);
708
709 ips_released_controllers++;
710
711 return (FALSE);
712}
713
714/****************************************************************************/
715/* */
716/* Routine Name: ips_halt */
717/* */
718/* Routine Description: */
719/* */
720/* Perform cleanup when the system reboots */
721/* */
722/****************************************************************************/
723static int
724ips_halt(struct notifier_block *nb, ulong event, void *buf)
725{
726 ips_scb_t *scb;
727 ips_ha_t *ha;
728 int i;
729
730 if ((event != SYS_RESTART) && (event != SYS_HALT) &&
731 (event != SYS_POWER_OFF))
732 return (NOTIFY_DONE);
733
734 for (i = 0; i < ips_next_controller; i++) {
735 ha = (ips_ha_t *) ips_ha[i];
736
737 if (!ha)
738 continue;
739
740 if (!ha->active)
741 continue;
742
743 /* flush the cache on the controller */
744 scb = &ha->scbs[ha->max_cmds - 1];
745
746 ips_init_scb(ha, scb);
747
748 scb->timeout = ips_cmd_timeout;
749 scb->cdb[0] = IPS_CMD_FLUSH;
750
751 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
752 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
753 scb->cmd.flush_cache.state = IPS_NORM_STATE;
754 scb->cmd.flush_cache.reserved = 0;
755 scb->cmd.flush_cache.reserved2 = 0;
756 scb->cmd.flush_cache.reserved3 = 0;
757 scb->cmd.flush_cache.reserved4 = 0;
758
759 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
760
761 /* send command */
762 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) ==
763 IPS_FAILURE)
764 IPS_PRINTK(KERN_WARNING, ha->pcidev,
765 "Incomplete Flush.\n");
766 else
767 IPS_PRINTK(KERN_WARNING, ha->pcidev,
768 "Flushing Complete.\n");
769 }
770
771 return (NOTIFY_OK);
772}
773
774/****************************************************************************/
775/* */
776/* Routine Name: ips_eh_abort */
777/* */
778/* Routine Description: */
779/* */
780/* Abort a command (using the new error code stuff) */
781/* Note: this routine is called under the io_request_lock */
782/****************************************************************************/
783int ips_eh_abort(struct scsi_cmnd *SC)
784{
785 ips_ha_t *ha;
786 ips_copp_wait_item_t *item;
787 int ret;
788 struct Scsi_Host *host;
789
790 METHOD_TRACE("ips_eh_abort", 1);
791
792 if (!SC)
793 return (FAILED);
794
795 host = SC->device->host;
796 ha = (ips_ha_t *) SC->device->host->hostdata;
797
798 if (!ha)
799 return (FAILED);
800
801 if (!ha->active)
802 return (FAILED);
803
804 spin_lock(host->host_lock);
805
806 /* See if the command is on the copp queue */
807 item = ha->copp_waitlist.head;
808 while ((item) && (item->scsi_cmd != SC))
809 item = item->next;
810
811 if (item) {
812 /* Found it */
813 ips_removeq_copp(&ha->copp_waitlist, item);
814 ret = (SUCCESS);
815
816 /* See if the command is on the wait queue */
817 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
818 /* command not sent yet */
819 ret = (SUCCESS);
820 } else {
821 /* command must have already been sent */
822 ret = (FAILED);
823 }
824
825 spin_unlock(host->host_lock);
826 return ret;
827}
828
829/****************************************************************************/
830/* */
831/* Routine Name: ips_eh_reset */
832/* */
833/* Routine Description: */
834/* */
835/* Reset the controller (with new eh error code) */
836/* */
837/* NOTE: this routine is called under the io_request_lock spinlock */
838/* */
839/****************************************************************************/
840static int __ips_eh_reset(struct scsi_cmnd *SC)
841{
842 int ret;
843 int i;
844 ips_ha_t *ha;
845 ips_scb_t *scb;
846 ips_copp_wait_item_t *item;
847
848 METHOD_TRACE("ips_eh_reset", 1);
849
850#ifdef NO_IPS_RESET
851 return (FAILED);
852#else
853
854 if (!SC) {
855 DEBUG(1, "Reset called with NULL scsi command");
856
857 return (FAILED);
858 }
859
860 ha = (ips_ha_t *) SC->device->host->hostdata;
861
862 if (!ha) {
863 DEBUG(1, "Reset called with NULL ha struct");
864
865 return (FAILED);
866 }
867
868 if (!ha->active)
869 return (FAILED);
870
871 /* See if the command is on the copp queue */
872 item = ha->copp_waitlist.head;
873 while ((item) && (item->scsi_cmd != SC))
874 item = item->next;
875
876 if (item) {
877 /* Found it */
878 ips_removeq_copp(&ha->copp_waitlist, item);
879 return (SUCCESS);
880 }
881
882 /* See if the command is on the wait queue */
883 if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
884 /* command not sent yet */
885 return (SUCCESS);
886 }
887
888 /* An explanation for the casual observer: */
889 /* Part of the function of a RAID controller is automatic error */
890 /* detection and recovery. As such, the only problem that physically */
891 /* resetting an adapter will ever fix is when, for some reason, */
892 /* the driver is not successfully communicating with the adapter. */
893 /* Therefore, we will attempt to flush this adapter. If that succeeds, */
894 /* then there's no real purpose in a physical reset. This will complete */
895 /* much faster and avoids any problems that might be caused by a */
896 /* physical reset ( such as having to fail all the outstanding I/O's ). */
897
898 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */
899 scb = &ha->scbs[ha->max_cmds - 1];
900
901 ips_init_scb(ha, scb);
902
903 scb->timeout = ips_cmd_timeout;
904 scb->cdb[0] = IPS_CMD_FLUSH;
905
906 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
907 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
908 scb->cmd.flush_cache.state = IPS_NORM_STATE;
909 scb->cmd.flush_cache.reserved = 0;
910 scb->cmd.flush_cache.reserved2 = 0;
911 scb->cmd.flush_cache.reserved3 = 0;
912 scb->cmd.flush_cache.reserved4 = 0;
913
914 /* Attempt the flush command */
915 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL);
916 if (ret == IPS_SUCCESS) {
917 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
918 "Reset Request - Flushed Cache\n");
919 return (SUCCESS);
920 }
921 }
922
923 /* Either we can't communicate with the adapter or it's an IOCTL request */
924 /* from a utility. A physical reset is needed at this point. */
925
926 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */
927
928 /*
929 * command must have already been sent
930 * reset the controller
931 */
932 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n");
933 ret = (*ha->func.reset) (ha);
934
935 if (!ret) {
936 struct scsi_cmnd *scsi_cmd;
937
938 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
939 "Controller reset failed - controller now offline.\n");
940
941 /* Now fail all of the active commands */
942 DEBUG_VAR(1, "(%s%d) Failing active commands",
943 ips_name, ha->host_num);
944
945 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
946 scb->scsi_cmd->result = DID_ERROR << 16;
947 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
948 ips_freescb(ha, scb);
949 }
950
951 /* Now fail all of the pending commands */
952 DEBUG_VAR(1, "(%s%d) Failing pending commands",
953 ips_name, ha->host_num);
954
955 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
956 scsi_cmd->result = DID_ERROR;
957 scsi_cmd->scsi_done(scsi_cmd);
958 }
959
960 ha->active = FALSE;
961 return (FAILED);
962 }
963
964 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) {
965 struct scsi_cmnd *scsi_cmd;
966
967 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
968 "Controller reset failed - controller now offline.\n");
969
970 /* Now fail all of the active commands */
971 DEBUG_VAR(1, "(%s%d) Failing active commands",
972 ips_name, ha->host_num);
973
974 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
975 scb->scsi_cmd->result = DID_ERROR << 16;
976 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
977 ips_freescb(ha, scb);
978 }
979
980 /* Now fail all of the pending commands */
981 DEBUG_VAR(1, "(%s%d) Failing pending commands",
982 ips_name, ha->host_num);
983
984 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
985 scsi_cmd->result = DID_ERROR << 16;
986 scsi_cmd->scsi_done(scsi_cmd);
987 }
988
989 ha->active = FALSE;
990 return (FAILED);
991 }
992
993 /* FFDC */
994 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) {
995 struct timeval tv;
996
997 do_gettimeofday(&tv);
998 ha->last_ffdc = tv.tv_sec;
999 ha->reset_count++;
1000 ips_ffdc_reset(ha, IPS_INTR_IORL);
1001 }
1002
1003 /* Now fail all of the active commands */
1004 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num);
1005
1006 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
1007 scb->scsi_cmd->result = DID_RESET << 16;
1008 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
1009 ips_freescb(ha, scb);
1010 }
1011
1012 /* Reset DCDB active command bits */
1013 for (i = 1; i < ha->nbus; i++)
1014 ha->dcdb_active[i - 1] = 0;
1015
1016 /* Reset the number of active IOCTLs */
1017 ha->num_ioctl = 0;
1018
1019 ips_next(ha, IPS_INTR_IORL);
1020
1021 return (SUCCESS);
1022#endif /* NO_IPS_RESET */
1023
1024}
1025
1026static int ips_eh_reset(struct scsi_cmnd *SC)
1027{
1028 int rc;
1029
1030 spin_lock_irq(SC->device->host->host_lock);
1031 rc = __ips_eh_reset(SC);
1032 spin_unlock_irq(SC->device->host->host_lock);
1033
1034 return rc;
1035}
1036
1037/****************************************************************************/
1038/* */
1039/* Routine Name: ips_queue */
1040/* */
1041/* Routine Description: */
1042/* */
1043/* Send a command to the controller */
1044/* */
1045/* NOTE: */
1046/* Linux obtains io_request_lock before calling this function */
1047/* */
1048/****************************************************************************/
1049static int ips_queue_lck(struct scsi_cmnd *SC, void (*done) (struct scsi_cmnd *))
1050{
1051 ips_ha_t *ha;
1052 ips_passthru_t *pt;
1053
1054 METHOD_TRACE("ips_queue", 1);
1055
1056 ha = (ips_ha_t *) SC->device->host->hostdata;
1057
1058 if (!ha)
1059 return (1);
1060
1061 if (!ha->active)
1062 return (DID_ERROR);
1063
1064 if (ips_is_passthru(SC)) {
1065 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) {
1066 SC->result = DID_BUS_BUSY << 16;
1067 done(SC);
1068
1069 return (0);
1070 }
1071 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) {
1072 SC->result = DID_BUS_BUSY << 16;
1073 done(SC);
1074
1075 return (0);
1076 }
1077
1078 SC->scsi_done = done;
1079
1080 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)",
1081 ips_name,
1082 ha->host_num,
1083 SC->cmnd[0],
1084 SC->device->channel, SC->device->id, SC->device->lun);
1085
1086 /* Check for command to initiator IDs */
1087 if ((scmd_channel(SC) > 0)
1088 && (scmd_id(SC) == ha->ha_id[scmd_channel(SC)])) {
1089 SC->result = DID_NO_CONNECT << 16;
1090 done(SC);
1091
1092 return (0);
1093 }
1094
1095 if (ips_is_passthru(SC)) {
1096
1097 ips_copp_wait_item_t *scratch;
1098
1099 /* A Reset IOCTL is only sent by the boot CD in extreme cases. */
1100 /* There can never be any system activity ( network or disk ), but check */
1101 /* anyway just as a good practice. */
1102 pt = (ips_passthru_t *) scsi_sglist(SC);
1103 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) &&
1104 (pt->CoppCP.cmd.reset.adapter_flag == 1)) {
1105 if (ha->scb_activelist.count != 0) {
1106 SC->result = DID_BUS_BUSY << 16;
1107 done(SC);
1108 return (0);
1109 }
1110 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */
1111 __ips_eh_reset(SC);
1112 SC->result = DID_OK << 16;
1113 SC->scsi_done(SC);
1114 return (0);
1115 }
1116
1117 /* allocate space for the scribble */
1118 scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC);
1119
1120 if (!scratch) {
1121 SC->result = DID_ERROR << 16;
1122 done(SC);
1123
1124 return (0);
1125 }
1126
1127 scratch->scsi_cmd = SC;
1128 scratch->next = NULL;
1129
1130 ips_putq_copp_tail(&ha->copp_waitlist, scratch);
1131 } else {
1132 ips_putq_wait_tail(&ha->scb_waitlist, SC);
1133 }
1134
1135 ips_next(ha, IPS_INTR_IORL);
1136
1137 return (0);
1138}
1139
1140static DEF_SCSI_QCMD(ips_queue)
1141
1142/****************************************************************************/
1143/* */
1144/* Routine Name: ips_biosparam */
1145/* */
1146/* Routine Description: */
1147/* */
1148/* Set bios geometry for the controller */
1149/* */
1150/****************************************************************************/
1151static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
1152 sector_t capacity, int geom[])
1153{
1154 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata;
1155 int heads;
1156 int sectors;
1157 int cylinders;
1158
1159 METHOD_TRACE("ips_biosparam", 1);
1160
1161 if (!ha)
1162 /* ?!?! host adater info invalid */
1163 return (0);
1164
1165 if (!ha->active)
1166 return (0);
1167
1168 if (!ips_read_adapter_status(ha, IPS_INTR_ON))
1169 /* ?!?! Enquiry command failed */
1170 return (0);
1171
1172 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) {
1173 heads = IPS_NORM_HEADS;
1174 sectors = IPS_NORM_SECTORS;
1175 } else {
1176 heads = IPS_COMP_HEADS;
1177 sectors = IPS_COMP_SECTORS;
1178 }
1179
1180 cylinders = (unsigned long) capacity / (heads * sectors);
1181
1182 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d",
1183 heads, sectors, cylinders);
1184
1185 geom[0] = heads;
1186 geom[1] = sectors;
1187 geom[2] = cylinders;
1188
1189 return (0);
1190}
1191
1192/****************************************************************************/
1193/* */
1194/* Routine Name: ips_slave_configure */
1195/* */
1196/* Routine Description: */
1197/* */
1198/* Set queue depths on devices once scan is complete */
1199/* */
1200/****************************************************************************/
1201static int
1202ips_slave_configure(struct scsi_device * SDptr)
1203{
1204 ips_ha_t *ha;
1205 int min;
1206
1207 ha = IPS_HA(SDptr->host);
1208 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) {
1209 min = ha->max_cmds / 2;
1210 if (ha->enq->ucLogDriveCount <= 2)
1211 min = ha->max_cmds - 1;
1212 scsi_adjust_queue_depth(SDptr, MSG_ORDERED_TAG, min);
1213 }
1214
1215 SDptr->skip_ms_page_8 = 1;
1216 SDptr->skip_ms_page_3f = 1;
1217 return 0;
1218}
1219
1220/****************************************************************************/
1221/* */
1222/* Routine Name: do_ipsintr */
1223/* */
1224/* Routine Description: */
1225/* */
1226/* Wrapper for the interrupt handler */
1227/* */
1228/****************************************************************************/
1229static irqreturn_t
1230do_ipsintr(int irq, void *dev_id)
1231{
1232 ips_ha_t *ha;
1233 struct Scsi_Host *host;
1234 int irqstatus;
1235
1236 METHOD_TRACE("do_ipsintr", 2);
1237
1238 ha = (ips_ha_t *) dev_id;
1239 if (!ha)
1240 return IRQ_NONE;
1241 host = ips_sh[ha->host_num];
1242 /* interrupt during initialization */
1243 if (!host) {
1244 (*ha->func.intr) (ha);
1245 return IRQ_HANDLED;
1246 }
1247
1248 spin_lock(host->host_lock);
1249
1250 if (!ha->active) {
1251 spin_unlock(host->host_lock);
1252 return IRQ_HANDLED;
1253 }
1254
1255 irqstatus = (*ha->func.intr) (ha);
1256
1257 spin_unlock(host->host_lock);
1258
1259 /* start the next command */
1260 ips_next(ha, IPS_INTR_ON);
1261 return IRQ_RETVAL(irqstatus);
1262}
1263
1264/****************************************************************************/
1265/* */
1266/* Routine Name: ips_intr_copperhead */
1267/* */
1268/* Routine Description: */
1269/* */
1270/* Polling interrupt handler */
1271/* */
1272/* ASSUMES interrupts are disabled */
1273/* */
1274/****************************************************************************/
1275int
1276ips_intr_copperhead(ips_ha_t * ha)
1277{
1278 ips_stat_t *sp;
1279 ips_scb_t *scb;
1280 IPS_STATUS cstatus;
1281 int intrstatus;
1282
1283 METHOD_TRACE("ips_intr", 2);
1284
1285 if (!ha)
1286 return 0;
1287
1288 if (!ha->active)
1289 return 0;
1290
1291 intrstatus = (*ha->func.isintr) (ha);
1292
1293 if (!intrstatus) {
1294 /*
1295 * Unexpected/Shared interrupt
1296 */
1297
1298 return 0;
1299 }
1300
1301 while (TRUE) {
1302 sp = &ha->sp;
1303
1304 intrstatus = (*ha->func.isintr) (ha);
1305
1306 if (!intrstatus)
1307 break;
1308 else
1309 cstatus.value = (*ha->func.statupd) (ha);
1310
1311 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1312 /* Spurious Interrupt ? */
1313 continue;
1314 }
1315
1316 ips_chkstatus(ha, &cstatus);
1317 scb = (ips_scb_t *) sp->scb_addr;
1318
1319 /*
1320 * use the callback function to finish things up
1321 * NOTE: interrupts are OFF for this
1322 */
1323 (*scb->callback) (ha, scb);
1324 } /* end while */
1325 return 1;
1326}
1327
1328/****************************************************************************/
1329/* */
1330/* Routine Name: ips_intr_morpheus */
1331/* */
1332/* Routine Description: */
1333/* */
1334/* Polling interrupt handler */
1335/* */
1336/* ASSUMES interrupts are disabled */
1337/* */
1338/****************************************************************************/
1339int
1340ips_intr_morpheus(ips_ha_t * ha)
1341{
1342 ips_stat_t *sp;
1343 ips_scb_t *scb;
1344 IPS_STATUS cstatus;
1345 int intrstatus;
1346
1347 METHOD_TRACE("ips_intr_morpheus", 2);
1348
1349 if (!ha)
1350 return 0;
1351
1352 if (!ha->active)
1353 return 0;
1354
1355 intrstatus = (*ha->func.isintr) (ha);
1356
1357 if (!intrstatus) {
1358 /*
1359 * Unexpected/Shared interrupt
1360 */
1361
1362 return 0;
1363 }
1364
1365 while (TRUE) {
1366 sp = &ha->sp;
1367
1368 intrstatus = (*ha->func.isintr) (ha);
1369
1370 if (!intrstatus)
1371 break;
1372 else
1373 cstatus.value = (*ha->func.statupd) (ha);
1374
1375 if (cstatus.value == 0xffffffff)
1376 /* No more to process */
1377 break;
1378
1379 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1380 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1381 "Spurious interrupt; no ccb.\n");
1382
1383 continue;
1384 }
1385
1386 ips_chkstatus(ha, &cstatus);
1387 scb = (ips_scb_t *) sp->scb_addr;
1388
1389 /*
1390 * use the callback function to finish things up
1391 * NOTE: interrupts are OFF for this
1392 */
1393 (*scb->callback) (ha, scb);
1394 } /* end while */
1395 return 1;
1396}
1397
1398/****************************************************************************/
1399/* */
1400/* Routine Name: ips_info */
1401/* */
1402/* Routine Description: */
1403/* */
1404/* Return info about the driver */
1405/* */
1406/****************************************************************************/
1407static const char *
1408ips_info(struct Scsi_Host *SH)
1409{
1410 static char buffer[256];
1411 char *bp;
1412 ips_ha_t *ha;
1413
1414 METHOD_TRACE("ips_info", 1);
1415
1416 ha = IPS_HA(SH);
1417
1418 if (!ha)
1419 return (NULL);
1420
1421 bp = &buffer[0];
1422 memset(bp, 0, sizeof (buffer));
1423
1424 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ",
1425 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT);
1426
1427 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) {
1428 strcat(bp, " <");
1429 strcat(bp, ips_adapter_name[ha->ad_type - 1]);
1430 strcat(bp, ">");
1431 }
1432
1433 return (bp);
1434}
1435
1436/****************************************************************************/
1437/* */
1438/* Routine Name: ips_proc_info */
1439/* */
1440/* Routine Description: */
1441/* */
1442/* The passthru interface for the driver */
1443/* */
1444/****************************************************************************/
1445static int
1446ips_proc_info(struct Scsi_Host *host, char *buffer, char **start, off_t offset,
1447 int length, int func)
1448{
1449 int i;
1450 int ret;
1451 ips_ha_t *ha = NULL;
1452
1453 METHOD_TRACE("ips_proc_info", 1);
1454
1455 /* Find our host structure */
1456 for (i = 0; i < ips_next_controller; i++) {
1457 if (ips_sh[i]) {
1458 if (ips_sh[i] == host) {
1459 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1460 break;
1461 }
1462 }
1463 }
1464
1465 if (!ha)
1466 return (-EINVAL);
1467
1468 if (func) {
1469 /* write */
1470 return (0);
1471 } else {
1472 /* read */
1473 if (start)
1474 *start = buffer;
1475
1476 ret = ips_host_info(ha, buffer, offset, length);
1477
1478 return (ret);
1479 }
1480}
1481
1482/*--------------------------------------------------------------------------*/
1483/* Helper Functions */
1484/*--------------------------------------------------------------------------*/
1485
1486/****************************************************************************/
1487/* */
1488/* Routine Name: ips_is_passthru */
1489/* */
1490/* Routine Description: */
1491/* */
1492/* Determine if the specified SCSI command is really a passthru command */
1493/* */
1494/****************************************************************************/
1495static int ips_is_passthru(struct scsi_cmnd *SC)
1496{
1497 unsigned long flags;
1498
1499 METHOD_TRACE("ips_is_passthru", 1);
1500
1501 if (!SC)
1502 return (0);
1503
1504 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) &&
1505 (SC->device->channel == 0) &&
1506 (SC->device->id == IPS_ADAPTER_ID) &&
1507 (SC->device->lun == 0) && scsi_sglist(SC)) {
1508 struct scatterlist *sg = scsi_sglist(SC);
1509 char *buffer;
1510
1511 /* kmap_atomic() ensures addressability of the user buffer.*/
1512 /* local_irq_save() protects the KM_IRQ0 address slot. */
1513 local_irq_save(flags);
1514 buffer = kmap_atomic(sg_page(sg), KM_IRQ0) + sg->offset;
1515 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' &&
1516 buffer[2] == 'P' && buffer[3] == 'P') {
1517 kunmap_atomic(buffer - sg->offset, KM_IRQ0);
1518 local_irq_restore(flags);
1519 return 1;
1520 }
1521 kunmap_atomic(buffer - sg->offset, KM_IRQ0);
1522 local_irq_restore(flags);
1523 }
1524 return 0;
1525}
1526
1527/****************************************************************************/
1528/* */
1529/* Routine Name: ips_alloc_passthru_buffer */
1530/* */
1531/* Routine Description: */
1532/* allocate a buffer large enough for the ioctl data if the ioctl buffer */
1533/* is too small or doesn't exist */
1534/****************************************************************************/
1535static int
1536ips_alloc_passthru_buffer(ips_ha_t * ha, int length)
1537{
1538 void *bigger_buf;
1539 dma_addr_t dma_busaddr;
1540
1541 if (ha->ioctl_data && length <= ha->ioctl_len)
1542 return 0;
1543 /* there is no buffer or it's not big enough, allocate a new one */
1544 bigger_buf = pci_alloc_consistent(ha->pcidev, length, &dma_busaddr);
1545 if (bigger_buf) {
1546 /* free the old memory */
1547 pci_free_consistent(ha->pcidev, ha->ioctl_len, ha->ioctl_data,
1548 ha->ioctl_busaddr);
1549 /* use the new memory */
1550 ha->ioctl_data = (char *) bigger_buf;
1551 ha->ioctl_len = length;
1552 ha->ioctl_busaddr = dma_busaddr;
1553 } else {
1554 return -1;
1555 }
1556 return 0;
1557}
1558
1559/****************************************************************************/
1560/* */
1561/* Routine Name: ips_make_passthru */
1562/* */
1563/* Routine Description: */
1564/* */
1565/* Make a passthru command out of the info in the Scsi block */
1566/* */
1567/****************************************************************************/
1568static int
1569ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr)
1570{
1571 ips_passthru_t *pt;
1572 int length = 0;
1573 int i, ret;
1574 struct scatterlist *sg = scsi_sglist(SC);
1575
1576 METHOD_TRACE("ips_make_passthru", 1);
1577
1578 scsi_for_each_sg(SC, sg, scsi_sg_count(SC), i)
1579 length += sg->length;
1580
1581 if (length < sizeof (ips_passthru_t)) {
1582 /* wrong size */
1583 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size",
1584 ips_name, ha->host_num);
1585 return (IPS_FAILURE);
1586 }
1587 if (ips_alloc_passthru_buffer(ha, length)) {
1588 /* allocation failure! If ha->ioctl_data exists, use it to return
1589 some error codes. Return a failed command to the scsi layer. */
1590 if (ha->ioctl_data) {
1591 pt = (ips_passthru_t *) ha->ioctl_data;
1592 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t));
1593 pt->BasicStatus = 0x0B;
1594 pt->ExtendedStatus = 0x00;
1595 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t));
1596 }
1597 return IPS_FAILURE;
1598 }
1599 ha->ioctl_datasize = length;
1600
1601 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize);
1602 pt = (ips_passthru_t *) ha->ioctl_data;
1603
1604 /*
1605 * Some notes about the passthru interface used
1606 *
1607 * IF the scsi op_code == 0x0d then we assume
1608 * that the data came along with/goes with the
1609 * packet we received from the sg driver. In this
1610 * case the CmdBSize field of the pt structure is
1611 * used for the size of the buffer.
1612 */
1613
1614 switch (pt->CoppCmd) {
1615 case IPS_NUMCTRLS:
1616 memcpy(ha->ioctl_data + sizeof (ips_passthru_t),
1617 &ips_num_controllers, sizeof (int));
1618 ips_scmd_buf_write(SC, ha->ioctl_data,
1619 sizeof (ips_passthru_t) + sizeof (int));
1620 SC->result = DID_OK << 16;
1621
1622 return (IPS_SUCCESS_IMM);
1623
1624 case IPS_COPPUSRCMD:
1625 case IPS_COPPIOCCMD:
1626 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) {
1627 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) {
1628 /* wrong size */
1629 DEBUG_VAR(1,
1630 "(%s%d) Passthru structure wrong size",
1631 ips_name, ha->host_num);
1632
1633 return (IPS_FAILURE);
1634 }
1635
1636 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
1637 pt->CoppCP.cmd.flashfw.op_code ==
1638 IPS_CMD_RW_BIOSFW) {
1639 ret = ips_flash_copperhead(ha, pt, scb);
1640 ips_scmd_buf_write(SC, ha->ioctl_data,
1641 sizeof (ips_passthru_t));
1642 return ret;
1643 }
1644 if (ips_usrcmd(ha, pt, scb))
1645 return (IPS_SUCCESS);
1646 else
1647 return (IPS_FAILURE);
1648 }
1649
1650 break;
1651
1652 } /* end switch */
1653
1654 return (IPS_FAILURE);
1655}
1656
1657/****************************************************************************/
1658/* Routine Name: ips_flash_copperhead */
1659/* Routine Description: */
1660/* Flash the BIOS/FW on a Copperhead style controller */
1661/****************************************************************************/
1662static int
1663ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1664{
1665 int datasize;
1666
1667 /* Trombone is the only copperhead that can do packet flash, but only
1668 * for firmware. No one said it had to make sense. */
1669 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) {
1670 if (ips_usrcmd(ha, pt, scb))
1671 return IPS_SUCCESS;
1672 else
1673 return IPS_FAILURE;
1674 }
1675 pt->BasicStatus = 0x0B;
1676 pt->ExtendedStatus = 0;
1677 scb->scsi_cmd->result = DID_OK << 16;
1678 /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */
1679 /* avoid allocating a huge buffer per adapter ( which can fail ). */
1680 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1681 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1682 pt->BasicStatus = 0;
1683 return ips_flash_bios(ha, pt, scb);
1684 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) {
1685 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){
1686 ha->flash_data = ips_FlashData;
1687 ha->flash_busaddr = ips_flashbusaddr;
1688 ha->flash_len = PAGE_SIZE << 7;
1689 ha->flash_datasize = 0;
1690 } else if (!ha->flash_data) {
1691 datasize = pt->CoppCP.cmd.flashfw.total_packets *
1692 pt->CoppCP.cmd.flashfw.count;
1693 ha->flash_data = pci_alloc_consistent(ha->pcidev,
1694 datasize,
1695 &ha->flash_busaddr);
1696 if (!ha->flash_data){
1697 printk(KERN_WARNING "Unable to allocate a flash buffer\n");
1698 return IPS_FAILURE;
1699 }
1700 ha->flash_datasize = 0;
1701 ha->flash_len = datasize;
1702 } else
1703 return IPS_FAILURE;
1704 } else {
1705 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize >
1706 ha->flash_len) {
1707 ips_free_flash_copperhead(ha);
1708 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1709 "failed size sanity check\n");
1710 return IPS_FAILURE;
1711 }
1712 }
1713 if (!ha->flash_data)
1714 return IPS_FAILURE;
1715 pt->BasicStatus = 0;
1716 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1,
1717 pt->CoppCP.cmd.flashfw.count);
1718 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count;
1719 if (pt->CoppCP.cmd.flashfw.packet_num ==
1720 pt->CoppCP.cmd.flashfw.total_packets - 1) {
1721 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE)
1722 return ips_flash_bios(ha, pt, scb);
1723 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE)
1724 return ips_flash_firmware(ha, pt, scb);
1725 }
1726 return IPS_SUCCESS_IMM;
1727}
1728
1729/****************************************************************************/
1730/* Routine Name: ips_flash_bios */
1731/* Routine Description: */
1732/* flashes the bios of a copperhead adapter */
1733/****************************************************************************/
1734static int
1735ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1736{
1737
1738 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1739 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) {
1740 if ((!ha->func.programbios) || (!ha->func.erasebios) ||
1741 (!ha->func.verifybios))
1742 goto error;
1743 if ((*ha->func.erasebios) (ha)) {
1744 DEBUG_VAR(1,
1745 "(%s%d) flash bios failed - unable to erase flash",
1746 ips_name, ha->host_num);
1747 goto error;
1748 } else
1749 if ((*ha->func.programbios) (ha,
1750 ha->flash_data +
1751 IPS_BIOS_HEADER,
1752 ha->flash_datasize -
1753 IPS_BIOS_HEADER, 0)) {
1754 DEBUG_VAR(1,
1755 "(%s%d) flash bios failed - unable to flash",
1756 ips_name, ha->host_num);
1757 goto error;
1758 } else
1759 if ((*ha->func.verifybios) (ha,
1760 ha->flash_data +
1761 IPS_BIOS_HEADER,
1762 ha->flash_datasize -
1763 IPS_BIOS_HEADER, 0)) {
1764 DEBUG_VAR(1,
1765 "(%s%d) flash bios failed - unable to verify flash",
1766 ips_name, ha->host_num);
1767 goto error;
1768 }
1769 ips_free_flash_copperhead(ha);
1770 return IPS_SUCCESS_IMM;
1771 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1772 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1773 if (!ha->func.erasebios)
1774 goto error;
1775 if ((*ha->func.erasebios) (ha)) {
1776 DEBUG_VAR(1,
1777 "(%s%d) flash bios failed - unable to erase flash",
1778 ips_name, ha->host_num);
1779 goto error;
1780 }
1781 return IPS_SUCCESS_IMM;
1782 }
1783 error:
1784 pt->BasicStatus = 0x0B;
1785 pt->ExtendedStatus = 0x00;
1786 ips_free_flash_copperhead(ha);
1787 return IPS_FAILURE;
1788}
1789
1790/****************************************************************************/
1791/* */
1792/* Routine Name: ips_fill_scb_sg_single */
1793/* */
1794/* Routine Description: */
1795/* Fill in a single scb sg_list element from an address */
1796/* return a -1 if a breakup occurred */
1797/****************************************************************************/
1798static int
1799ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr,
1800 ips_scb_t * scb, int indx, unsigned int e_len)
1801{
1802
1803 int ret_val = 0;
1804
1805 if ((scb->data_len + e_len) > ha->max_xfer) {
1806 e_len = ha->max_xfer - scb->data_len;
1807 scb->breakup = indx;
1808 ++scb->sg_break;
1809 ret_val = -1;
1810 } else {
1811 scb->breakup = 0;
1812 scb->sg_break = 0;
1813 }
1814 if (IPS_USE_ENH_SGLIST(ha)) {
1815 scb->sg_list.enh_list[indx].address_lo =
1816 cpu_to_le32(pci_dma_lo32(busaddr));
1817 scb->sg_list.enh_list[indx].address_hi =
1818 cpu_to_le32(pci_dma_hi32(busaddr));
1819 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len);
1820 } else {
1821 scb->sg_list.std_list[indx].address =
1822 cpu_to_le32(pci_dma_lo32(busaddr));
1823 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len);
1824 }
1825
1826 ++scb->sg_len;
1827 scb->data_len += e_len;
1828 return ret_val;
1829}
1830
1831/****************************************************************************/
1832/* Routine Name: ips_flash_firmware */
1833/* Routine Description: */
1834/* flashes the firmware of a copperhead adapter */
1835/****************************************************************************/
1836static int
1837ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1838{
1839 IPS_SG_LIST sg_list;
1840 uint32_t cmd_busaddr;
1841
1842 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE &&
1843 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) {
1844 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND));
1845 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD;
1846 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize);
1847 } else {
1848 pt->BasicStatus = 0x0B;
1849 pt->ExtendedStatus = 0x00;
1850 ips_free_flash_copperhead(ha);
1851 return IPS_FAILURE;
1852 }
1853 /* Save the S/G list pointer so it doesn't get clobbered */
1854 sg_list.list = scb->sg_list.list;
1855 cmd_busaddr = scb->scb_busaddr;
1856 /* copy in the CP */
1857 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1858 /* FIX stuff that might be wrong */
1859 scb->sg_list.list = sg_list.list;
1860 scb->scb_busaddr = cmd_busaddr;
1861 scb->bus = scb->scsi_cmd->device->channel;
1862 scb->target_id = scb->scsi_cmd->device->id;
1863 scb->lun = scb->scsi_cmd->device->lun;
1864 scb->sg_len = 0;
1865 scb->data_len = 0;
1866 scb->flags = 0;
1867 scb->op_code = 0;
1868 scb->callback = ipsintr_done;
1869 scb->timeout = ips_cmd_timeout;
1870
1871 scb->data_len = ha->flash_datasize;
1872 scb->data_busaddr =
1873 pci_map_single(ha->pcidev, ha->flash_data, scb->data_len,
1874 IPS_DMA_DIR(scb));
1875 scb->flags |= IPS_SCB_MAP_SINGLE;
1876 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
1877 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr);
1878 if (pt->TimeOut)
1879 scb->timeout = pt->TimeOut;
1880 scb->scsi_cmd->result = DID_OK << 16;
1881 return IPS_SUCCESS;
1882}
1883
1884/****************************************************************************/
1885/* Routine Name: ips_free_flash_copperhead */
1886/* Routine Description: */
1887/* release the memory resources used to hold the flash image */
1888/****************************************************************************/
1889static void
1890ips_free_flash_copperhead(ips_ha_t * ha)
1891{
1892 if (ha->flash_data == ips_FlashData)
1893 test_and_clear_bit(0, &ips_FlashDataInUse);
1894 else if (ha->flash_data)
1895 pci_free_consistent(ha->pcidev, ha->flash_len, ha->flash_data,
1896 ha->flash_busaddr);
1897 ha->flash_data = NULL;
1898}
1899
1900/****************************************************************************/
1901/* */
1902/* Routine Name: ips_usrcmd */
1903/* */
1904/* Routine Description: */
1905/* */
1906/* Process a user command and make it ready to send */
1907/* */
1908/****************************************************************************/
1909static int
1910ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1911{
1912 IPS_SG_LIST sg_list;
1913 uint32_t cmd_busaddr;
1914
1915 METHOD_TRACE("ips_usrcmd", 1);
1916
1917 if ((!scb) || (!pt) || (!ha))
1918 return (0);
1919
1920 /* Save the S/G list pointer so it doesn't get clobbered */
1921 sg_list.list = scb->sg_list.list;
1922 cmd_busaddr = scb->scb_busaddr;
1923 /* copy in the CP */
1924 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1925 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE));
1926
1927 /* FIX stuff that might be wrong */
1928 scb->sg_list.list = sg_list.list;
1929 scb->scb_busaddr = cmd_busaddr;
1930 scb->bus = scb->scsi_cmd->device->channel;
1931 scb->target_id = scb->scsi_cmd->device->id;
1932 scb->lun = scb->scsi_cmd->device->lun;
1933 scb->sg_len = 0;
1934 scb->data_len = 0;
1935 scb->flags = 0;
1936 scb->op_code = 0;
1937 scb->callback = ipsintr_done;
1938 scb->timeout = ips_cmd_timeout;
1939 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
1940
1941 /* we don't support DCDB/READ/WRITE Scatter Gather */
1942 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) ||
1943 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) ||
1944 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG))
1945 return (0);
1946
1947 if (pt->CmdBSize) {
1948 scb->data_len = pt->CmdBSize;
1949 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t);
1950 } else {
1951 scb->data_busaddr = 0L;
1952 }
1953
1954 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1955 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
1956 (unsigned long) &scb->
1957 dcdb -
1958 (unsigned long) scb);
1959
1960 if (pt->CmdBSize) {
1961 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1962 scb->dcdb.buffer_pointer =
1963 cpu_to_le32(scb->data_busaddr);
1964 else
1965 scb->cmd.basic_io.sg_addr =
1966 cpu_to_le32(scb->data_busaddr);
1967 }
1968
1969 /* set timeouts */
1970 if (pt->TimeOut) {
1971 scb->timeout = pt->TimeOut;
1972
1973 if (pt->TimeOut <= 10)
1974 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10;
1975 else if (pt->TimeOut <= 60)
1976 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60;
1977 else
1978 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M;
1979 }
1980
1981 /* assume success */
1982 scb->scsi_cmd->result = DID_OK << 16;
1983
1984 /* success */
1985 return (1);
1986}
1987
1988/****************************************************************************/
1989/* */
1990/* Routine Name: ips_cleanup_passthru */
1991/* */
1992/* Routine Description: */
1993/* */
1994/* Cleanup after a passthru command */
1995/* */
1996/****************************************************************************/
1997static void
1998ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
1999{
2000 ips_passthru_t *pt;
2001
2002 METHOD_TRACE("ips_cleanup_passthru", 1);
2003
2004 if ((!scb) || (!scb->scsi_cmd) || (!scsi_sglist(scb->scsi_cmd))) {
2005 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru",
2006 ips_name, ha->host_num);
2007
2008 return;
2009 }
2010 pt = (ips_passthru_t *) ha->ioctl_data;
2011
2012 /* Copy data back to the user */
2013 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */
2014 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE));
2015
2016 pt->BasicStatus = scb->basic_status;
2017 pt->ExtendedStatus = scb->extended_status;
2018 pt->AdapterType = ha->ad_type;
2019
2020 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
2021 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD ||
2022 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW))
2023 ips_free_flash_copperhead(ha);
2024
2025 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize);
2026}
2027
2028/****************************************************************************/
2029/* */
2030/* Routine Name: ips_host_info */
2031/* */
2032/* Routine Description: */
2033/* */
2034/* The passthru interface for the driver */
2035/* */
2036/****************************************************************************/
2037static int
2038ips_host_info(ips_ha_t * ha, char *ptr, off_t offset, int len)
2039{
2040 IPS_INFOSTR info;
2041
2042 METHOD_TRACE("ips_host_info", 1);
2043
2044 info.buffer = ptr;
2045 info.length = len;
2046 info.offset = offset;
2047 info.pos = 0;
2048 info.localpos = 0;
2049
2050 copy_info(&info, "\nIBM ServeRAID General Information:\n\n");
2051
2052 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) &&
2053 (le16_to_cpu(ha->nvram->adapter_type) != 0))
2054 copy_info(&info, "\tController Type : %s\n",
2055 ips_adapter_name[ha->ad_type - 1]);
2056 else
2057 copy_info(&info,
2058 "\tController Type : Unknown\n");
2059
2060 if (ha->io_addr)
2061 copy_info(&info,
2062 "\tIO region : 0x%lx (%d bytes)\n",
2063 ha->io_addr, ha->io_len);
2064
2065 if (ha->mem_addr) {
2066 copy_info(&info,
2067 "\tMemory region : 0x%lx (%d bytes)\n",
2068 ha->mem_addr, ha->mem_len);
2069 copy_info(&info,
2070 "\tShared memory address : 0x%lx\n",
2071 ha->mem_ptr);
2072 }
2073
2074 copy_info(&info, "\tIRQ number : %d\n", ha->pcidev->irq);
2075
2076 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */
2077 /* That keeps everything happy for "text" operations on the proc file. */
2078
2079 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) {
2080 if (ha->nvram->bios_low[3] == 0) {
2081 copy_info(&info,
2082 "\tBIOS Version : %c%c%c%c%c%c%c\n",
2083 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2084 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2085 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2086 ha->nvram->bios_low[2]);
2087
2088 } else {
2089 copy_info(&info,
2090 "\tBIOS Version : %c%c%c%c%c%c%c%c\n",
2091 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2092 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2093 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2094 ha->nvram->bios_low[2], ha->nvram->bios_low[3]);
2095 }
2096
2097 }
2098
2099 if (ha->enq->CodeBlkVersion[7] == 0) {
2100 copy_info(&info,
2101 "\tFirmware Version : %c%c%c%c%c%c%c\n",
2102 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2103 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2104 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2105 ha->enq->CodeBlkVersion[6]);
2106 } else {
2107 copy_info(&info,
2108 "\tFirmware Version : %c%c%c%c%c%c%c%c\n",
2109 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2110 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2111 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2112 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]);
2113 }
2114
2115 if (ha->enq->BootBlkVersion[7] == 0) {
2116 copy_info(&info,
2117 "\tBoot Block Version : %c%c%c%c%c%c%c\n",
2118 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2119 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2120 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2121 ha->enq->BootBlkVersion[6]);
2122 } else {
2123 copy_info(&info,
2124 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n",
2125 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2126 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2127 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2128 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]);
2129 }
2130
2131 copy_info(&info, "\tDriver Version : %s%s\n",
2132 IPS_VERSION_HIGH, IPS_VERSION_LOW);
2133
2134 copy_info(&info, "\tDriver Build : %d\n",
2135 IPS_BUILD_IDENT);
2136
2137 copy_info(&info, "\tMax Physical Devices : %d\n",
2138 ha->enq->ucMaxPhysicalDevices);
2139 copy_info(&info, "\tMax Active Commands : %d\n",
2140 ha->max_cmds);
2141 copy_info(&info, "\tCurrent Queued Commands : %d\n",
2142 ha->scb_waitlist.count);
2143 copy_info(&info, "\tCurrent Active Commands : %d\n",
2144 ha->scb_activelist.count - ha->num_ioctl);
2145 copy_info(&info, "\tCurrent Queued PT Commands : %d\n",
2146 ha->copp_waitlist.count);
2147 copy_info(&info, "\tCurrent Active PT Commands : %d\n",
2148 ha->num_ioctl);
2149
2150 copy_info(&info, "\n");
2151
2152 return (info.localpos);
2153}
2154
2155/****************************************************************************/
2156/* */
2157/* Routine Name: copy_mem_info */
2158/* */
2159/* Routine Description: */
2160/* */
2161/* Copy data into an IPS_INFOSTR structure */
2162/* */
2163/****************************************************************************/
2164static void
2165copy_mem_info(IPS_INFOSTR * info, char *data, int len)
2166{
2167 METHOD_TRACE("copy_mem_info", 1);
2168
2169 if (info->pos + len < info->offset) {
2170 info->pos += len;
2171 return;
2172 }
2173
2174 if (info->pos < info->offset) {
2175 data += (info->offset - info->pos);
2176 len -= (info->offset - info->pos);
2177 info->pos += (info->offset - info->pos);
2178 }
2179
2180 if (info->localpos + len > info->length)
2181 len = info->length - info->localpos;
2182
2183 if (len > 0) {
2184 memcpy(info->buffer + info->localpos, data, len);
2185 info->pos += len;
2186 info->localpos += len;
2187 }
2188}
2189
2190/****************************************************************************/
2191/* */
2192/* Routine Name: copy_info */
2193/* */
2194/* Routine Description: */
2195/* */
2196/* printf style wrapper for an info structure */
2197/* */
2198/****************************************************************************/
2199static int
2200copy_info(IPS_INFOSTR * info, char *fmt, ...)
2201{
2202 va_list args;
2203 char buf[128];
2204 int len;
2205
2206 METHOD_TRACE("copy_info", 1);
2207
2208 va_start(args, fmt);
2209 len = vsprintf(buf, fmt, args);
2210 va_end(args);
2211
2212 copy_mem_info(info, buf, len);
2213
2214 return (len);
2215}
2216
2217/****************************************************************************/
2218/* */
2219/* Routine Name: ips_identify_controller */
2220/* */
2221/* Routine Description: */
2222/* */
2223/* Identify this controller */
2224/* */
2225/****************************************************************************/
2226static void
2227ips_identify_controller(ips_ha_t * ha)
2228{
2229 METHOD_TRACE("ips_identify_controller", 1);
2230
2231 switch (ha->pcidev->device) {
2232 case IPS_DEVICEID_COPPERHEAD:
2233 if (ha->pcidev->revision <= IPS_REVID_SERVERAID) {
2234 ha->ad_type = IPS_ADTYPE_SERVERAID;
2235 } else if (ha->pcidev->revision == IPS_REVID_SERVERAID2) {
2236 ha->ad_type = IPS_ADTYPE_SERVERAID2;
2237 } else if (ha->pcidev->revision == IPS_REVID_NAVAJO) {
2238 ha->ad_type = IPS_ADTYPE_NAVAJO;
2239 } else if ((ha->pcidev->revision == IPS_REVID_SERVERAID2)
2240 && (ha->slot_num == 0)) {
2241 ha->ad_type = IPS_ADTYPE_KIOWA;
2242 } else if ((ha->pcidev->revision >= IPS_REVID_CLARINETP1) &&
2243 (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) {
2244 if (ha->enq->ucMaxPhysicalDevices == 15)
2245 ha->ad_type = IPS_ADTYPE_SERVERAID3L;
2246 else
2247 ha->ad_type = IPS_ADTYPE_SERVERAID3;
2248 } else if ((ha->pcidev->revision >= IPS_REVID_TROMBONE32) &&
2249 (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) {
2250 ha->ad_type = IPS_ADTYPE_SERVERAID4H;
2251 }
2252 break;
2253
2254 case IPS_DEVICEID_MORPHEUS:
2255 switch (ha->pcidev->subsystem_device) {
2256 case IPS_SUBDEVICEID_4L:
2257 ha->ad_type = IPS_ADTYPE_SERVERAID4L;
2258 break;
2259
2260 case IPS_SUBDEVICEID_4M:
2261 ha->ad_type = IPS_ADTYPE_SERVERAID4M;
2262 break;
2263
2264 case IPS_SUBDEVICEID_4MX:
2265 ha->ad_type = IPS_ADTYPE_SERVERAID4MX;
2266 break;
2267
2268 case IPS_SUBDEVICEID_4LX:
2269 ha->ad_type = IPS_ADTYPE_SERVERAID4LX;
2270 break;
2271
2272 case IPS_SUBDEVICEID_5I2:
2273 ha->ad_type = IPS_ADTYPE_SERVERAID5I2;
2274 break;
2275
2276 case IPS_SUBDEVICEID_5I1:
2277 ha->ad_type = IPS_ADTYPE_SERVERAID5I1;
2278 break;
2279 }
2280
2281 break;
2282
2283 case IPS_DEVICEID_MARCO:
2284 switch (ha->pcidev->subsystem_device) {
2285 case IPS_SUBDEVICEID_6M:
2286 ha->ad_type = IPS_ADTYPE_SERVERAID6M;
2287 break;
2288 case IPS_SUBDEVICEID_6I:
2289 ha->ad_type = IPS_ADTYPE_SERVERAID6I;
2290 break;
2291 case IPS_SUBDEVICEID_7k:
2292 ha->ad_type = IPS_ADTYPE_SERVERAID7k;
2293 break;
2294 case IPS_SUBDEVICEID_7M:
2295 ha->ad_type = IPS_ADTYPE_SERVERAID7M;
2296 break;
2297 }
2298 break;
2299 }
2300}
2301
2302/****************************************************************************/
2303/* */
2304/* Routine Name: ips_get_bios_version */
2305/* */
2306/* Routine Description: */
2307/* */
2308/* Get the BIOS revision number */
2309/* */
2310/****************************************************************************/
2311static void
2312ips_get_bios_version(ips_ha_t * ha, int intr)
2313{
2314 ips_scb_t *scb;
2315 int ret;
2316 uint8_t major;
2317 uint8_t minor;
2318 uint8_t subminor;
2319 uint8_t *buffer;
2320 char hexDigits[] =
2321 { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C',
2322 'D', 'E', 'F' };
2323
2324 METHOD_TRACE("ips_get_bios_version", 1);
2325
2326 major = 0;
2327 minor = 0;
2328
2329 strncpy(ha->bios_version, " ?", 8);
2330
2331 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) {
2332 if (IPS_USE_MEMIO(ha)) {
2333 /* Memory Mapped I/O */
2334
2335 /* test 1st byte */
2336 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2337 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2338 udelay(25); /* 25 us */
2339
2340 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2341 return;
2342
2343 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2344 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2345 udelay(25); /* 25 us */
2346
2347 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2348 return;
2349
2350 /* Get Major version */
2351 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2352 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2353 udelay(25); /* 25 us */
2354
2355 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2356
2357 /* Get Minor version */
2358 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2359 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2360 udelay(25); /* 25 us */
2361 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2362
2363 /* Get SubMinor version */
2364 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2365 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2366 udelay(25); /* 25 us */
2367 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
2368
2369 } else {
2370 /* Programmed I/O */
2371
2372 /* test 1st byte */
2373 outl(0, ha->io_addr + IPS_REG_FLAP);
2374 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2375 udelay(25); /* 25 us */
2376
2377 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2378 return;
2379
2380 outl(1, ha->io_addr + IPS_REG_FLAP);
2381 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2382 udelay(25); /* 25 us */
2383
2384 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
2385 return;
2386
2387 /* Get Major version */
2388 outl(0x1FF, ha->io_addr + IPS_REG_FLAP);
2389 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2390 udelay(25); /* 25 us */
2391
2392 major = inb(ha->io_addr + IPS_REG_FLDP);
2393
2394 /* Get Minor version */
2395 outl(0x1FE, ha->io_addr + IPS_REG_FLAP);
2396 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2397 udelay(25); /* 25 us */
2398
2399 minor = inb(ha->io_addr + IPS_REG_FLDP);
2400
2401 /* Get SubMinor version */
2402 outl(0x1FD, ha->io_addr + IPS_REG_FLAP);
2403 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2404 udelay(25); /* 25 us */
2405
2406 subminor = inb(ha->io_addr + IPS_REG_FLDP);
2407
2408 }
2409 } else {
2410 /* Morpheus Family - Send Command to the card */
2411
2412 buffer = ha->ioctl_data;
2413
2414 memset(buffer, 0, 0x1000);
2415
2416 scb = &ha->scbs[ha->max_cmds - 1];
2417
2418 ips_init_scb(ha, scb);
2419
2420 scb->timeout = ips_cmd_timeout;
2421 scb->cdb[0] = IPS_CMD_RW_BIOSFW;
2422
2423 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW;
2424 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
2425 scb->cmd.flashfw.type = 1;
2426 scb->cmd.flashfw.direction = 0;
2427 scb->cmd.flashfw.count = cpu_to_le32(0x800);
2428 scb->cmd.flashfw.total_packets = 1;
2429 scb->cmd.flashfw.packet_num = 0;
2430 scb->data_len = 0x1000;
2431 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr;
2432
2433 /* issue the command */
2434 if (((ret =
2435 ips_send_wait(ha, scb, ips_cmd_timeout,
2436 intr)) == IPS_FAILURE)
2437 || (ret == IPS_SUCCESS_IMM)
2438 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
2439 /* Error occurred */
2440
2441 return;
2442 }
2443
2444 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) {
2445 major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */
2446 minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */
2447 subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */
2448 } else {
2449 return;
2450 }
2451 }
2452
2453 ha->bios_version[0] = hexDigits[(major & 0xF0) >> 4];
2454 ha->bios_version[1] = '.';
2455 ha->bios_version[2] = hexDigits[major & 0x0F];
2456 ha->bios_version[3] = hexDigits[subminor];
2457 ha->bios_version[4] = '.';
2458 ha->bios_version[5] = hexDigits[(minor & 0xF0) >> 4];
2459 ha->bios_version[6] = hexDigits[minor & 0x0F];
2460 ha->bios_version[7] = 0;
2461}
2462
2463/****************************************************************************/
2464/* */
2465/* Routine Name: ips_hainit */
2466/* */
2467/* Routine Description: */
2468/* */
2469/* Initialize the controller */
2470/* */
2471/* NOTE: Assumes to be called from with a lock */
2472/* */
2473/****************************************************************************/
2474static int
2475ips_hainit(ips_ha_t * ha)
2476{
2477 int i;
2478 struct timeval tv;
2479
2480 METHOD_TRACE("ips_hainit", 1);
2481
2482 if (!ha)
2483 return (0);
2484
2485 if (ha->func.statinit)
2486 (*ha->func.statinit) (ha);
2487
2488 if (ha->func.enableint)
2489 (*ha->func.enableint) (ha);
2490
2491 /* Send FFDC */
2492 ha->reset_count = 1;
2493 do_gettimeofday(&tv);
2494 ha->last_ffdc = tv.tv_sec;
2495 ips_ffdc_reset(ha, IPS_INTR_IORL);
2496
2497 if (!ips_read_config(ha, IPS_INTR_IORL)) {
2498 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2499 "unable to read config from controller.\n");
2500
2501 return (0);
2502 }
2503 /* end if */
2504 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) {
2505 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2506 "unable to read controller status.\n");
2507
2508 return (0);
2509 }
2510
2511 /* Identify this controller */
2512 ips_identify_controller(ha);
2513
2514 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) {
2515 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2516 "unable to read subsystem parameters.\n");
2517
2518 return (0);
2519 }
2520
2521 /* write nvram user page 5 */
2522 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) {
2523 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2524 "unable to write driver info to controller.\n");
2525
2526 return (0);
2527 }
2528
2529 /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */
2530 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1))
2531 ips_clear_adapter(ha, IPS_INTR_IORL);
2532
2533 /* set limits on SID, LUN, BUS */
2534 ha->ntargets = IPS_MAX_TARGETS + 1;
2535 ha->nlun = 1;
2536 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1;
2537
2538 switch (ha->conf->logical_drive[0].ucStripeSize) {
2539 case 4:
2540 ha->max_xfer = 0x10000;
2541 break;
2542
2543 case 5:
2544 ha->max_xfer = 0x20000;
2545 break;
2546
2547 case 6:
2548 ha->max_xfer = 0x40000;
2549 break;
2550
2551 case 7:
2552 default:
2553 ha->max_xfer = 0x80000;
2554 break;
2555 }
2556
2557 /* setup max concurrent commands */
2558 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) {
2559 /* Use the new method */
2560 ha->max_cmds = ha->enq->ucConcurrentCmdCount;
2561 } else {
2562 /* use the old method */
2563 switch (ha->conf->logical_drive[0].ucStripeSize) {
2564 case 4:
2565 ha->max_cmds = 32;
2566 break;
2567
2568 case 5:
2569 ha->max_cmds = 16;
2570 break;
2571
2572 case 6:
2573 ha->max_cmds = 8;
2574 break;
2575
2576 case 7:
2577 default:
2578 ha->max_cmds = 4;
2579 break;
2580 }
2581 }
2582
2583 /* Limit the Active Commands on a Lite Adapter */
2584 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) ||
2585 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) ||
2586 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) {
2587 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds))
2588 ha->max_cmds = MaxLiteCmds;
2589 }
2590
2591 /* set controller IDs */
2592 ha->ha_id[0] = IPS_ADAPTER_ID;
2593 for (i = 1; i < ha->nbus; i++) {
2594 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f;
2595 ha->dcdb_active[i - 1] = 0;
2596 }
2597
2598 return (1);
2599}
2600
2601/****************************************************************************/
2602/* */
2603/* Routine Name: ips_next */
2604/* */
2605/* Routine Description: */
2606/* */
2607/* Take the next command off the queue and send it to the controller */
2608/* */
2609/****************************************************************************/
2610static void
2611ips_next(ips_ha_t * ha, int intr)
2612{
2613 ips_scb_t *scb;
2614 struct scsi_cmnd *SC;
2615 struct scsi_cmnd *p;
2616 struct scsi_cmnd *q;
2617 ips_copp_wait_item_t *item;
2618 int ret;
2619 struct Scsi_Host *host;
2620 METHOD_TRACE("ips_next", 1);
2621
2622 if (!ha)
2623 return;
2624 host = ips_sh[ha->host_num];
2625 /*
2626 * Block access to the queue function so
2627 * this command won't time out
2628 */
2629 if (intr == IPS_INTR_ON)
2630 spin_lock(host->host_lock);
2631
2632 if ((ha->subsys->param[3] & 0x300000)
2633 && (ha->scb_activelist.count == 0)) {
2634 struct timeval tv;
2635
2636 do_gettimeofday(&tv);
2637
2638 if (tv.tv_sec - ha->last_ffdc > IPS_SECS_8HOURS) {
2639 ha->last_ffdc = tv.tv_sec;
2640 ips_ffdc_time(ha);
2641 }
2642 }
2643
2644 /*
2645 * Send passthru commands
2646 * These have priority over normal I/O
2647 * but shouldn't affect performance too much
2648 * since we limit the number that can be active
2649 * on the card at any one time
2650 */
2651 while ((ha->num_ioctl < IPS_MAX_IOCTL) &&
2652 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) {
2653
2654 item = ips_removeq_copp_head(&ha->copp_waitlist);
2655 ha->num_ioctl++;
2656 if (intr == IPS_INTR_ON)
2657 spin_unlock(host->host_lock);
2658 scb->scsi_cmd = item->scsi_cmd;
2659 kfree(item);
2660
2661 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr);
2662
2663 if (intr == IPS_INTR_ON)
2664 spin_lock(host->host_lock);
2665 switch (ret) {
2666 case IPS_FAILURE:
2667 if (scb->scsi_cmd) {
2668 scb->scsi_cmd->result = DID_ERROR << 16;
2669 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2670 }
2671
2672 ips_freescb(ha, scb);
2673 break;
2674 case IPS_SUCCESS_IMM:
2675 if (scb->scsi_cmd) {
2676 scb->scsi_cmd->result = DID_OK << 16;
2677 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2678 }
2679
2680 ips_freescb(ha, scb);
2681 break;
2682 default:
2683 break;
2684 } /* end case */
2685
2686 if (ret != IPS_SUCCESS) {
2687 ha->num_ioctl--;
2688 continue;
2689 }
2690
2691 ret = ips_send_cmd(ha, scb);
2692
2693 if (ret == IPS_SUCCESS)
2694 ips_putq_scb_head(&ha->scb_activelist, scb);
2695 else
2696 ha->num_ioctl--;
2697
2698 switch (ret) {
2699 case IPS_FAILURE:
2700 if (scb->scsi_cmd) {
2701 scb->scsi_cmd->result = DID_ERROR << 16;
2702 }
2703
2704 ips_freescb(ha, scb);
2705 break;
2706 case IPS_SUCCESS_IMM:
2707 ips_freescb(ha, scb);
2708 break;
2709 default:
2710 break;
2711 } /* end case */
2712
2713 }
2714
2715 /*
2716 * Send "Normal" I/O commands
2717 */
2718
2719 p = ha->scb_waitlist.head;
2720 while ((p) && (scb = ips_getscb(ha))) {
2721 if ((scmd_channel(p) > 0)
2722 && (ha->
2723 dcdb_active[scmd_channel(p) -
2724 1] & (1 << scmd_id(p)))) {
2725 ips_freescb(ha, scb);
2726 p = (struct scsi_cmnd *) p->host_scribble;
2727 continue;
2728 }
2729
2730 q = p;
2731 SC = ips_removeq_wait(&ha->scb_waitlist, q);
2732
2733 if (intr == IPS_INTR_ON)
2734 spin_unlock(host->host_lock); /* Unlock HA after command is taken off queue */
2735
2736 SC->result = DID_OK;
2737 SC->host_scribble = NULL;
2738
2739 scb->target_id = SC->device->id;
2740 scb->lun = SC->device->lun;
2741 scb->bus = SC->device->channel;
2742 scb->scsi_cmd = SC;
2743 scb->breakup = 0;
2744 scb->data_len = 0;
2745 scb->callback = ipsintr_done;
2746 scb->timeout = ips_cmd_timeout;
2747 memset(&scb->cmd, 0, 16);
2748
2749 /* copy in the CDB */
2750 memcpy(scb->cdb, SC->cmnd, SC->cmd_len);
2751
2752 scb->sg_count = scsi_dma_map(SC);
2753 BUG_ON(scb->sg_count < 0);
2754 if (scb->sg_count) {
2755 struct scatterlist *sg;
2756 int i;
2757
2758 scb->flags |= IPS_SCB_MAP_SG;
2759
2760 scsi_for_each_sg(SC, sg, scb->sg_count, i) {
2761 if (ips_fill_scb_sg_single
2762 (ha, sg_dma_address(sg), scb, i,
2763 sg_dma_len(sg)) < 0)
2764 break;
2765 }
2766 scb->dcdb.transfer_length = scb->data_len;
2767 } else {
2768 scb->data_busaddr = 0L;
2769 scb->sg_len = 0;
2770 scb->data_len = 0;
2771 scb->dcdb.transfer_length = 0;
2772 }
2773
2774 scb->dcdb.cmd_attribute =
2775 ips_command_direction[scb->scsi_cmd->cmnd[0]];
2776
2777 /* Allow a WRITE BUFFER Command to Have no Data */
2778 /* This is Used by Tape Flash Utilites */
2779 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) &&
2780 (scb->data_len == 0))
2781 scb->dcdb.cmd_attribute = 0;
2782
2783 if (!(scb->dcdb.cmd_attribute & 0x3))
2784 scb->dcdb.transfer_length = 0;
2785
2786 if (scb->data_len >= IPS_MAX_XFER) {
2787 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
2788 scb->dcdb.transfer_length = 0;
2789 }
2790 if (intr == IPS_INTR_ON)
2791 spin_lock(host->host_lock);
2792
2793 ret = ips_send_cmd(ha, scb);
2794
2795 switch (ret) {
2796 case IPS_SUCCESS:
2797 ips_putq_scb_head(&ha->scb_activelist, scb);
2798 break;
2799 case IPS_FAILURE:
2800 if (scb->scsi_cmd) {
2801 scb->scsi_cmd->result = DID_ERROR << 16;
2802 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2803 }
2804
2805 if (scb->bus)
2806 ha->dcdb_active[scb->bus - 1] &=
2807 ~(1 << scb->target_id);
2808
2809 ips_freescb(ha, scb);
2810 break;
2811 case IPS_SUCCESS_IMM:
2812 if (scb->scsi_cmd)
2813 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2814
2815 if (scb->bus)
2816 ha->dcdb_active[scb->bus - 1] &=
2817 ~(1 << scb->target_id);
2818
2819 ips_freescb(ha, scb);
2820 break;
2821 default:
2822 break;
2823 } /* end case */
2824
2825 p = (struct scsi_cmnd *) p->host_scribble;
2826
2827 } /* end while */
2828
2829 if (intr == IPS_INTR_ON)
2830 spin_unlock(host->host_lock);
2831}
2832
2833/****************************************************************************/
2834/* */
2835/* Routine Name: ips_putq_scb_head */
2836/* */
2837/* Routine Description: */
2838/* */
2839/* Add an item to the head of the queue */
2840/* */
2841/* ASSUMED to be called from within the HA lock */
2842/* */
2843/****************************************************************************/
2844static void
2845ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item)
2846{
2847 METHOD_TRACE("ips_putq_scb_head", 1);
2848
2849 if (!item)
2850 return;
2851
2852 item->q_next = queue->head;
2853 queue->head = item;
2854
2855 if (!queue->tail)
2856 queue->tail = item;
2857
2858 queue->count++;
2859}
2860
2861/****************************************************************************/
2862/* */
2863/* Routine Name: ips_removeq_scb_head */
2864/* */
2865/* Routine Description: */
2866/* */
2867/* Remove the head of the queue */
2868/* */
2869/* ASSUMED to be called from within the HA lock */
2870/* */
2871/****************************************************************************/
2872static ips_scb_t *
2873ips_removeq_scb_head(ips_scb_queue_t * queue)
2874{
2875 ips_scb_t *item;
2876
2877 METHOD_TRACE("ips_removeq_scb_head", 1);
2878
2879 item = queue->head;
2880
2881 if (!item) {
2882 return (NULL);
2883 }
2884
2885 queue->head = item->q_next;
2886 item->q_next = NULL;
2887
2888 if (queue->tail == item)
2889 queue->tail = NULL;
2890
2891 queue->count--;
2892
2893 return (item);
2894}
2895
2896/****************************************************************************/
2897/* */
2898/* Routine Name: ips_removeq_scb */
2899/* */
2900/* Routine Description: */
2901/* */
2902/* Remove an item from a queue */
2903/* */
2904/* ASSUMED to be called from within the HA lock */
2905/* */
2906/****************************************************************************/
2907static ips_scb_t *
2908ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item)
2909{
2910 ips_scb_t *p;
2911
2912 METHOD_TRACE("ips_removeq_scb", 1);
2913
2914 if (!item)
2915 return (NULL);
2916
2917 if (item == queue->head) {
2918 return (ips_removeq_scb_head(queue));
2919 }
2920
2921 p = queue->head;
2922
2923 while ((p) && (item != p->q_next))
2924 p = p->q_next;
2925
2926 if (p) {
2927 /* found a match */
2928 p->q_next = item->q_next;
2929
2930 if (!item->q_next)
2931 queue->tail = p;
2932
2933 item->q_next = NULL;
2934 queue->count--;
2935
2936 return (item);
2937 }
2938
2939 return (NULL);
2940}
2941
2942/****************************************************************************/
2943/* */
2944/* Routine Name: ips_putq_wait_tail */
2945/* */
2946/* Routine Description: */
2947/* */
2948/* Add an item to the tail of the queue */
2949/* */
2950/* ASSUMED to be called from within the HA lock */
2951/* */
2952/****************************************************************************/
2953static void ips_putq_wait_tail(ips_wait_queue_t *queue, struct scsi_cmnd *item)
2954{
2955 METHOD_TRACE("ips_putq_wait_tail", 1);
2956
2957 if (!item)
2958 return;
2959
2960 item->host_scribble = NULL;
2961
2962 if (queue->tail)
2963 queue->tail->host_scribble = (char *) item;
2964
2965 queue->tail = item;
2966
2967 if (!queue->head)
2968 queue->head = item;
2969
2970 queue->count++;
2971}
2972
2973/****************************************************************************/
2974/* */
2975/* Routine Name: ips_removeq_wait_head */
2976/* */
2977/* Routine Description: */
2978/* */
2979/* Remove the head of the queue */
2980/* */
2981/* ASSUMED to be called from within the HA lock */
2982/* */
2983/****************************************************************************/
2984static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_t *queue)
2985{
2986 struct scsi_cmnd *item;
2987
2988 METHOD_TRACE("ips_removeq_wait_head", 1);
2989
2990 item = queue->head;
2991
2992 if (!item) {
2993 return (NULL);
2994 }
2995
2996 queue->head = (struct scsi_cmnd *) item->host_scribble;
2997 item->host_scribble = NULL;
2998
2999 if (queue->tail == item)
3000 queue->tail = NULL;
3001
3002 queue->count--;
3003
3004 return (item);
3005}
3006
3007/****************************************************************************/
3008/* */
3009/* Routine Name: ips_removeq_wait */
3010/* */
3011/* Routine Description: */
3012/* */
3013/* Remove an item from a queue */
3014/* */
3015/* ASSUMED to be called from within the HA lock */
3016/* */
3017/****************************************************************************/
3018static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_t *queue,
3019 struct scsi_cmnd *item)
3020{
3021 struct scsi_cmnd *p;
3022
3023 METHOD_TRACE("ips_removeq_wait", 1);
3024
3025 if (!item)
3026 return (NULL);
3027
3028 if (item == queue->head) {
3029 return (ips_removeq_wait_head(queue));
3030 }
3031
3032 p = queue->head;
3033
3034 while ((p) && (item != (struct scsi_cmnd *) p->host_scribble))
3035 p = (struct scsi_cmnd *) p->host_scribble;
3036
3037 if (p) {
3038 /* found a match */
3039 p->host_scribble = item->host_scribble;
3040
3041 if (!item->host_scribble)
3042 queue->tail = p;
3043
3044 item->host_scribble = NULL;
3045 queue->count--;
3046
3047 return (item);
3048 }
3049
3050 return (NULL);
3051}
3052
3053/****************************************************************************/
3054/* */
3055/* Routine Name: ips_putq_copp_tail */
3056/* */
3057/* Routine Description: */
3058/* */
3059/* Add an item to the tail of the queue */
3060/* */
3061/* ASSUMED to be called from within the HA lock */
3062/* */
3063/****************************************************************************/
3064static void
3065ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3066{
3067 METHOD_TRACE("ips_putq_copp_tail", 1);
3068
3069 if (!item)
3070 return;
3071
3072 item->next = NULL;
3073
3074 if (queue->tail)
3075 queue->tail->next = item;
3076
3077 queue->tail = item;
3078
3079 if (!queue->head)
3080 queue->head = item;
3081
3082 queue->count++;
3083}
3084
3085/****************************************************************************/
3086/* */
3087/* Routine Name: ips_removeq_copp_head */
3088/* */
3089/* Routine Description: */
3090/* */
3091/* Remove the head of the queue */
3092/* */
3093/* ASSUMED to be called from within the HA lock */
3094/* */
3095/****************************************************************************/
3096static ips_copp_wait_item_t *
3097ips_removeq_copp_head(ips_copp_queue_t * queue)
3098{
3099 ips_copp_wait_item_t *item;
3100
3101 METHOD_TRACE("ips_removeq_copp_head", 1);
3102
3103 item = queue->head;
3104
3105 if (!item) {
3106 return (NULL);
3107 }
3108
3109 queue->head = item->next;
3110 item->next = NULL;
3111
3112 if (queue->tail == item)
3113 queue->tail = NULL;
3114
3115 queue->count--;
3116
3117 return (item);
3118}
3119
3120/****************************************************************************/
3121/* */
3122/* Routine Name: ips_removeq_copp */
3123/* */
3124/* Routine Description: */
3125/* */
3126/* Remove an item from a queue */
3127/* */
3128/* ASSUMED to be called from within the HA lock */
3129/* */
3130/****************************************************************************/
3131static ips_copp_wait_item_t *
3132ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3133{
3134 ips_copp_wait_item_t *p;
3135
3136 METHOD_TRACE("ips_removeq_copp", 1);
3137
3138 if (!item)
3139 return (NULL);
3140
3141 if (item == queue->head) {
3142 return (ips_removeq_copp_head(queue));
3143 }
3144
3145 p = queue->head;
3146
3147 while ((p) && (item != p->next))
3148 p = p->next;
3149
3150 if (p) {
3151 /* found a match */
3152 p->next = item->next;
3153
3154 if (!item->next)
3155 queue->tail = p;
3156
3157 item->next = NULL;
3158 queue->count--;
3159
3160 return (item);
3161 }
3162
3163 return (NULL);
3164}
3165
3166/****************************************************************************/
3167/* */
3168/* Routine Name: ipsintr_blocking */
3169/* */
3170/* Routine Description: */
3171/* */
3172/* Finalize an interrupt for internal commands */
3173/* */
3174/****************************************************************************/
3175static void
3176ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb)
3177{
3178 METHOD_TRACE("ipsintr_blocking", 2);
3179
3180 ips_freescb(ha, scb);
3181 if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) {
3182 ha->waitflag = FALSE;
3183
3184 return;
3185 }
3186}
3187
3188/****************************************************************************/
3189/* */
3190/* Routine Name: ipsintr_done */
3191/* */
3192/* Routine Description: */
3193/* */
3194/* Finalize an interrupt for non-internal commands */
3195/* */
3196/****************************************************************************/
3197static void
3198ipsintr_done(ips_ha_t * ha, ips_scb_t * scb)
3199{
3200 METHOD_TRACE("ipsintr_done", 2);
3201
3202 if (!scb) {
3203 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3204 "Spurious interrupt; scb NULL.\n");
3205
3206 return;
3207 }
3208
3209 if (scb->scsi_cmd == NULL) {
3210 /* unexpected interrupt */
3211 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3212 "Spurious interrupt; scsi_cmd not set.\n");
3213
3214 return;
3215 }
3216
3217 ips_done(ha, scb);
3218}
3219
3220/****************************************************************************/
3221/* */
3222/* Routine Name: ips_done */
3223/* */
3224/* Routine Description: */
3225/* */
3226/* Do housekeeping on completed commands */
3227/* ASSUMED to be called form within the request lock */
3228/****************************************************************************/
3229static void
3230ips_done(ips_ha_t * ha, ips_scb_t * scb)
3231{
3232 int ret;
3233
3234 METHOD_TRACE("ips_done", 1);
3235
3236 if (!scb)
3237 return;
3238
3239 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) {
3240 ips_cleanup_passthru(ha, scb);
3241 ha->num_ioctl--;
3242 } else {
3243 /*
3244 * Check to see if this command had too much
3245 * data and had to be broke up. If so, queue
3246 * the rest of the data and continue.
3247 */
3248 if ((scb->breakup) || (scb->sg_break)) {
3249 struct scatterlist *sg;
3250 int i, sg_dma_index, ips_sg_index = 0;
3251
3252 /* we had a data breakup */
3253 scb->data_len = 0;
3254
3255 sg = scsi_sglist(scb->scsi_cmd);
3256
3257 /* Spin forward to last dma chunk */
3258 sg_dma_index = scb->breakup;
3259 for (i = 0; i < scb->breakup; i++)
3260 sg = sg_next(sg);
3261
3262 /* Take care of possible partial on last chunk */
3263 ips_fill_scb_sg_single(ha,
3264 sg_dma_address(sg),
3265 scb, ips_sg_index++,
3266 sg_dma_len(sg));
3267
3268 for (; sg_dma_index < scsi_sg_count(scb->scsi_cmd);
3269 sg_dma_index++, sg = sg_next(sg)) {
3270 if (ips_fill_scb_sg_single
3271 (ha,
3272 sg_dma_address(sg),
3273 scb, ips_sg_index++,
3274 sg_dma_len(sg)) < 0)
3275 break;
3276 }
3277
3278 scb->dcdb.transfer_length = scb->data_len;
3279 scb->dcdb.cmd_attribute |=
3280 ips_command_direction[scb->scsi_cmd->cmnd[0]];
3281
3282 if (!(scb->dcdb.cmd_attribute & 0x3))
3283 scb->dcdb.transfer_length = 0;
3284
3285 if (scb->data_len >= IPS_MAX_XFER) {
3286 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
3287 scb->dcdb.transfer_length = 0;
3288 }
3289
3290 ret = ips_send_cmd(ha, scb);
3291
3292 switch (ret) {
3293 case IPS_FAILURE:
3294 if (scb->scsi_cmd) {
3295 scb->scsi_cmd->result = DID_ERROR << 16;
3296 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3297 }
3298
3299 ips_freescb(ha, scb);
3300 break;
3301 case IPS_SUCCESS_IMM:
3302 if (scb->scsi_cmd) {
3303 scb->scsi_cmd->result = DID_ERROR << 16;
3304 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3305 }
3306
3307 ips_freescb(ha, scb);
3308 break;
3309 default:
3310 break;
3311 } /* end case */
3312
3313 return;
3314 }
3315 } /* end if passthru */
3316
3317 if (scb->bus) {
3318 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id);
3319 }
3320
3321 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3322
3323 ips_freescb(ha, scb);
3324}
3325
3326/****************************************************************************/
3327/* */
3328/* Routine Name: ips_map_status */
3329/* */
3330/* Routine Description: */
3331/* */
3332/* Map Controller Error codes to Linux Error Codes */
3333/* */
3334/****************************************************************************/
3335static int
3336ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3337{
3338 int errcode;
3339 int device_error;
3340 uint32_t transfer_len;
3341 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3342 IPS_SCSI_INQ_DATA inquiryData;
3343
3344 METHOD_TRACE("ips_map_status", 1);
3345
3346 if (scb->bus) {
3347 DEBUG_VAR(2,
3348 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x",
3349 ips_name, ha->host_num,
3350 scb->scsi_cmd->device->channel,
3351 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun,
3352 scb->basic_status, scb->extended_status,
3353 scb->extended_status ==
3354 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0,
3355 scb->extended_status ==
3356 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0,
3357 scb->extended_status ==
3358 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0);
3359 }
3360
3361 /* default driver error */
3362 errcode = DID_ERROR;
3363 device_error = 0;
3364
3365 switch (scb->basic_status & IPS_GSC_STATUS_MASK) {
3366 case IPS_CMD_TIMEOUT:
3367 errcode = DID_TIME_OUT;
3368 break;
3369
3370 case IPS_INVAL_OPCO:
3371 case IPS_INVAL_CMD_BLK:
3372 case IPS_INVAL_PARM_BLK:
3373 case IPS_LD_ERROR:
3374 case IPS_CMD_CMPLT_WERROR:
3375 break;
3376
3377 case IPS_PHYS_DRV_ERROR:
3378 switch (scb->extended_status) {
3379 case IPS_ERR_SEL_TO:
3380 if (scb->bus)
3381 errcode = DID_NO_CONNECT;
3382
3383 break;
3384
3385 case IPS_ERR_OU_RUN:
3386 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) ||
3387 (scb->cmd.dcdb.op_code ==
3388 IPS_CMD_EXTENDED_DCDB_SG)) {
3389 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3390 transfer_len = tapeDCDB->transfer_length;
3391 } else {
3392 transfer_len =
3393 (uint32_t) scb->dcdb.transfer_length;
3394 }
3395
3396 if ((scb->bus) && (transfer_len < scb->data_len)) {
3397 /* Underrun - set default to no error */
3398 errcode = DID_OK;
3399
3400 /* Restrict access to physical DASD */
3401 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3402 ips_scmd_buf_read(scb->scsi_cmd,
3403 &inquiryData, sizeof (inquiryData));
3404 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) {
3405 errcode = DID_TIME_OUT;
3406 break;
3407 }
3408 }
3409 } else
3410 errcode = DID_ERROR;
3411
3412 break;
3413
3414 case IPS_ERR_RECOVERY:
3415 /* don't fail recovered errors */
3416 if (scb->bus)
3417 errcode = DID_OK;
3418
3419 break;
3420
3421 case IPS_ERR_HOST_RESET:
3422 case IPS_ERR_DEV_RESET:
3423 errcode = DID_RESET;
3424 break;
3425
3426 case IPS_ERR_CKCOND:
3427 if (scb->bus) {
3428 if ((scb->cmd.dcdb.op_code ==
3429 IPS_CMD_EXTENDED_DCDB)
3430 || (scb->cmd.dcdb.op_code ==
3431 IPS_CMD_EXTENDED_DCDB_SG)) {
3432 tapeDCDB =
3433 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3434 memcpy(scb->scsi_cmd->sense_buffer,
3435 tapeDCDB->sense_info,
3436 SCSI_SENSE_BUFFERSIZE);
3437 } else {
3438 memcpy(scb->scsi_cmd->sense_buffer,
3439 scb->dcdb.sense_info,
3440 SCSI_SENSE_BUFFERSIZE);
3441 }
3442 device_error = 2; /* check condition */
3443 }
3444
3445 errcode = DID_OK;
3446
3447 break;
3448
3449 default:
3450 errcode = DID_ERROR;
3451 break;
3452
3453 } /* end switch */
3454 } /* end switch */
3455
3456 scb->scsi_cmd->result = device_error | (errcode << 16);
3457
3458 return (1);
3459}
3460
3461/****************************************************************************/
3462/* */
3463/* Routine Name: ips_send_wait */
3464/* */
3465/* Routine Description: */
3466/* */
3467/* Send a command to the controller and wait for it to return */
3468/* */
3469/* The FFDC Time Stamp use this function for the callback, but doesn't */
3470/* actually need to wait. */
3471/****************************************************************************/
3472static int
3473ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr)
3474{
3475 int ret;
3476
3477 METHOD_TRACE("ips_send_wait", 1);
3478
3479 if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */
3480 ha->waitflag = TRUE;
3481 ha->cmd_in_progress = scb->cdb[0];
3482 }
3483 scb->callback = ipsintr_blocking;
3484 ret = ips_send_cmd(ha, scb);
3485
3486 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM))
3487 return (ret);
3488
3489 if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */
3490 ret = ips_wait(ha, timeout, intr);
3491
3492 return (ret);
3493}
3494
3495/****************************************************************************/
3496/* */
3497/* Routine Name: ips_scmd_buf_write */
3498/* */
3499/* Routine Description: */
3500/* Write data to struct scsi_cmnd request_buffer at proper offsets */
3501/****************************************************************************/
3502static void
3503ips_scmd_buf_write(struct scsi_cmnd *scmd, void *data, unsigned int count)
3504{
3505 unsigned long flags;
3506
3507 local_irq_save(flags);
3508 scsi_sg_copy_from_buffer(scmd, data, count);
3509 local_irq_restore(flags);
3510}
3511
3512/****************************************************************************/
3513/* */
3514/* Routine Name: ips_scmd_buf_read */
3515/* */
3516/* Routine Description: */
3517/* Copy data from a struct scsi_cmnd to a new, linear buffer */
3518/****************************************************************************/
3519static void
3520ips_scmd_buf_read(struct scsi_cmnd *scmd, void *data, unsigned int count)
3521{
3522 unsigned long flags;
3523
3524 local_irq_save(flags);
3525 scsi_sg_copy_to_buffer(scmd, data, count);
3526 local_irq_restore(flags);
3527}
3528
3529/****************************************************************************/
3530/* */
3531/* Routine Name: ips_send_cmd */
3532/* */
3533/* Routine Description: */
3534/* */
3535/* Map SCSI commands to ServeRAID commands for logical drives */
3536/* */
3537/****************************************************************************/
3538static int
3539ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
3540{
3541 int ret;
3542 char *sp;
3543 int device_error;
3544 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3545 int TimeOut;
3546
3547 METHOD_TRACE("ips_send_cmd", 1);
3548
3549 ret = IPS_SUCCESS;
3550
3551 if (!scb->scsi_cmd) {
3552 /* internal command */
3553
3554 if (scb->bus > 0) {
3555 /* Controller commands can't be issued */
3556 /* to real devices -- fail them */
3557 if ((ha->waitflag == TRUE) &&
3558 (ha->cmd_in_progress == scb->cdb[0])) {
3559 ha->waitflag = FALSE;
3560 }
3561
3562 return (1);
3563 }
3564 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) {
3565 /* command to logical bus -- interpret */
3566 ret = IPS_SUCCESS_IMM;
3567
3568 switch (scb->scsi_cmd->cmnd[0]) {
3569 case ALLOW_MEDIUM_REMOVAL:
3570 case REZERO_UNIT:
3571 case ERASE:
3572 case WRITE_FILEMARKS:
3573 case SPACE:
3574 scb->scsi_cmd->result = DID_ERROR << 16;
3575 break;
3576
3577 case START_STOP:
3578 scb->scsi_cmd->result = DID_OK << 16;
3579
3580 case TEST_UNIT_READY:
3581 case INQUIRY:
3582 if (scb->target_id == IPS_ADAPTER_ID) {
3583 /*
3584 * Either we have a TUR
3585 * or we have a SCSI inquiry
3586 */
3587 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY)
3588 scb->scsi_cmd->result = DID_OK << 16;
3589
3590 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3591 IPS_SCSI_INQ_DATA inquiry;
3592
3593 memset(&inquiry, 0,
3594 sizeof (IPS_SCSI_INQ_DATA));
3595
3596 inquiry.DeviceType =
3597 IPS_SCSI_INQ_TYPE_PROCESSOR;
3598 inquiry.DeviceTypeQualifier =
3599 IPS_SCSI_INQ_LU_CONNECTED;
3600 inquiry.Version = IPS_SCSI_INQ_REV2;
3601 inquiry.ResponseDataFormat =
3602 IPS_SCSI_INQ_RD_REV2;
3603 inquiry.AdditionalLength = 31;
3604 inquiry.Flags[0] =
3605 IPS_SCSI_INQ_Address16;
3606 inquiry.Flags[1] =
3607 IPS_SCSI_INQ_WBus16 |
3608 IPS_SCSI_INQ_Sync;
3609 strncpy(inquiry.VendorId, "IBM ",
3610 8);
3611 strncpy(inquiry.ProductId,
3612 "SERVERAID ", 16);
3613 strncpy(inquiry.ProductRevisionLevel,
3614 "1.00", 4);
3615
3616 ips_scmd_buf_write(scb->scsi_cmd,
3617 &inquiry,
3618 sizeof (inquiry));
3619
3620 scb->scsi_cmd->result = DID_OK << 16;
3621 }
3622 } else {
3623 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3624 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3625 scb->cmd.logical_info.reserved = 0;
3626 scb->cmd.logical_info.reserved2 = 0;
3627 scb->data_len = sizeof (IPS_LD_INFO);
3628 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3629 scb->flags = 0;
3630 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3631 ret = IPS_SUCCESS;
3632 }
3633
3634 break;
3635
3636 case REQUEST_SENSE:
3637 ips_reqsen(ha, scb);
3638 scb->scsi_cmd->result = DID_OK << 16;
3639 break;
3640
3641 case READ_6:
3642 case WRITE_6:
3643 if (!scb->sg_len) {
3644 scb->cmd.basic_io.op_code =
3645 (scb->scsi_cmd->cmnd[0] ==
3646 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE;
3647 scb->cmd.basic_io.enhanced_sg = 0;
3648 scb->cmd.basic_io.sg_addr =
3649 cpu_to_le32(scb->data_busaddr);
3650 } else {
3651 scb->cmd.basic_io.op_code =
3652 (scb->scsi_cmd->cmnd[0] ==
3653 READ_6) ? IPS_CMD_READ_SG :
3654 IPS_CMD_WRITE_SG;
3655 scb->cmd.basic_io.enhanced_sg =
3656 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3657 scb->cmd.basic_io.sg_addr =
3658 cpu_to_le32(scb->sg_busaddr);
3659 }
3660
3661 scb->cmd.basic_io.segment_4G = 0;
3662 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3663 scb->cmd.basic_io.log_drv = scb->target_id;
3664 scb->cmd.basic_io.sg_count = scb->sg_len;
3665
3666 if (scb->cmd.basic_io.lba)
3667 le32_add_cpu(&scb->cmd.basic_io.lba,
3668 le16_to_cpu(scb->cmd.basic_io.
3669 sector_count));
3670 else
3671 scb->cmd.basic_io.lba =
3672 (((scb->scsi_cmd->
3673 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd->
3674 cmnd[2] << 8) |
3675 (scb->scsi_cmd->cmnd[3]));
3676
3677 scb->cmd.basic_io.sector_count =
3678 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3679
3680 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0)
3681 scb->cmd.basic_io.sector_count =
3682 cpu_to_le16(256);
3683
3684 ret = IPS_SUCCESS;
3685 break;
3686
3687 case READ_10:
3688 case WRITE_10:
3689 if (!scb->sg_len) {
3690 scb->cmd.basic_io.op_code =
3691 (scb->scsi_cmd->cmnd[0] ==
3692 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE;
3693 scb->cmd.basic_io.enhanced_sg = 0;
3694 scb->cmd.basic_io.sg_addr =
3695 cpu_to_le32(scb->data_busaddr);
3696 } else {
3697 scb->cmd.basic_io.op_code =
3698 (scb->scsi_cmd->cmnd[0] ==
3699 READ_10) ? IPS_CMD_READ_SG :
3700 IPS_CMD_WRITE_SG;
3701 scb->cmd.basic_io.enhanced_sg =
3702 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3703 scb->cmd.basic_io.sg_addr =
3704 cpu_to_le32(scb->sg_busaddr);
3705 }
3706
3707 scb->cmd.basic_io.segment_4G = 0;
3708 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3709 scb->cmd.basic_io.log_drv = scb->target_id;
3710 scb->cmd.basic_io.sg_count = scb->sg_len;
3711
3712 if (scb->cmd.basic_io.lba)
3713 le32_add_cpu(&scb->cmd.basic_io.lba,
3714 le16_to_cpu(scb->cmd.basic_io.
3715 sector_count));
3716 else
3717 scb->cmd.basic_io.lba =
3718 ((scb->scsi_cmd->cmnd[2] << 24) | (scb->
3719 scsi_cmd->
3720 cmnd[3]
3721 << 16) |
3722 (scb->scsi_cmd->cmnd[4] << 8) | scb->
3723 scsi_cmd->cmnd[5]);
3724
3725 scb->cmd.basic_io.sector_count =
3726 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3727
3728 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) {
3729 /*
3730 * This is a null condition
3731 * we don't have to do anything
3732 * so just return
3733 */
3734 scb->scsi_cmd->result = DID_OK << 16;
3735 } else
3736 ret = IPS_SUCCESS;
3737
3738 break;
3739
3740 case RESERVE:
3741 case RELEASE:
3742 scb->scsi_cmd->result = DID_OK << 16;
3743 break;
3744
3745 case MODE_SENSE:
3746 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
3747 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3748 scb->cmd.basic_io.segment_4G = 0;
3749 scb->cmd.basic_io.enhanced_sg = 0;
3750 scb->data_len = sizeof (*ha->enq);
3751 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
3752 ret = IPS_SUCCESS;
3753 break;
3754
3755 case READ_CAPACITY:
3756 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3757 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3758 scb->cmd.logical_info.reserved = 0;
3759 scb->cmd.logical_info.reserved2 = 0;
3760 scb->cmd.logical_info.reserved3 = 0;
3761 scb->data_len = sizeof (IPS_LD_INFO);
3762 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3763 scb->flags = 0;
3764 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3765 ret = IPS_SUCCESS;
3766 break;
3767
3768 case SEND_DIAGNOSTIC:
3769 case REASSIGN_BLOCKS:
3770 case FORMAT_UNIT:
3771 case SEEK_10:
3772 case VERIFY:
3773 case READ_DEFECT_DATA:
3774 case READ_BUFFER:
3775 case WRITE_BUFFER:
3776 scb->scsi_cmd->result = DID_OK << 16;
3777 break;
3778
3779 default:
3780 /* Set the Return Info to appear like the Command was */
3781 /* attempted, a Check Condition occurred, and Sense */
3782 /* Data indicating an Invalid CDB OpCode is returned. */
3783 sp = (char *) scb->scsi_cmd->sense_buffer;
3784
3785 sp[0] = 0x70; /* Error Code */
3786 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */
3787 sp[7] = 0x0A; /* Additional Sense Length */
3788 sp[12] = 0x20; /* ASC = Invalid OpCode */
3789 sp[13] = 0x00; /* ASCQ */
3790
3791 device_error = 2; /* Indicate Check Condition */
3792 scb->scsi_cmd->result = device_error | (DID_OK << 16);
3793 break;
3794 } /* end switch */
3795 }
3796 /* end if */
3797 if (ret == IPS_SUCCESS_IMM)
3798 return (ret);
3799
3800 /* setup DCDB */
3801 if (scb->bus > 0) {
3802
3803 /* If we already know the Device is Not there, no need to attempt a Command */
3804 /* This also protects an NT FailOver Controller from getting CDB's sent to it */
3805 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) {
3806 scb->scsi_cmd->result = DID_NO_CONNECT << 16;
3807 return (IPS_SUCCESS_IMM);
3808 }
3809
3810 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id);
3811 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb);
3812 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
3813 (unsigned long) &scb->
3814 dcdb -
3815 (unsigned long) scb);
3816 scb->cmd.dcdb.reserved = 0;
3817 scb->cmd.dcdb.reserved2 = 0;
3818 scb->cmd.dcdb.reserved3 = 0;
3819 scb->cmd.dcdb.segment_4G = 0;
3820 scb->cmd.dcdb.enhanced_sg = 0;
3821
3822 TimeOut = scb->scsi_cmd->request->timeout;
3823
3824 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */
3825 if (!scb->sg_len) {
3826 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB;
3827 } else {
3828 scb->cmd.dcdb.op_code =
3829 IPS_CMD_EXTENDED_DCDB_SG;
3830 scb->cmd.dcdb.enhanced_sg =
3831 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3832 }
3833
3834 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */
3835 tapeDCDB->device_address =
3836 ((scb->bus - 1) << 4) | scb->target_id;
3837 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3838 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */
3839
3840 if (TimeOut) {
3841 if (TimeOut < (10 * HZ))
3842 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
3843 else if (TimeOut < (60 * HZ))
3844 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
3845 else if (TimeOut < (1200 * HZ))
3846 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
3847 }
3848
3849 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len;
3850 tapeDCDB->reserved_for_LUN = 0;
3851 tapeDCDB->transfer_length = scb->data_len;
3852 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG)
3853 tapeDCDB->buffer_pointer =
3854 cpu_to_le32(scb->sg_busaddr);
3855 else
3856 tapeDCDB->buffer_pointer =
3857 cpu_to_le32(scb->data_busaddr);
3858 tapeDCDB->sg_count = scb->sg_len;
3859 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info);
3860 tapeDCDB->scsi_status = 0;
3861 tapeDCDB->reserved = 0;
3862 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd,
3863 scb->scsi_cmd->cmd_len);
3864 } else {
3865 if (!scb->sg_len) {
3866 scb->cmd.dcdb.op_code = IPS_CMD_DCDB;
3867 } else {
3868 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG;
3869 scb->cmd.dcdb.enhanced_sg =
3870 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3871 }
3872
3873 scb->dcdb.device_address =
3874 ((scb->bus - 1) << 4) | scb->target_id;
3875 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3876
3877 if (TimeOut) {
3878 if (TimeOut < (10 * HZ))
3879 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
3880 else if (TimeOut < (60 * HZ))
3881 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
3882 else if (TimeOut < (1200 * HZ))
3883 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
3884 }
3885
3886 scb->dcdb.transfer_length = scb->data_len;
3887 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K)
3888 scb->dcdb.transfer_length = 0;
3889 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG)
3890 scb->dcdb.buffer_pointer =
3891 cpu_to_le32(scb->sg_busaddr);
3892 else
3893 scb->dcdb.buffer_pointer =
3894 cpu_to_le32(scb->data_busaddr);
3895 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len;
3896 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info);
3897 scb->dcdb.sg_count = scb->sg_len;
3898 scb->dcdb.reserved = 0;
3899 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd,
3900 scb->scsi_cmd->cmd_len);
3901 scb->dcdb.scsi_status = 0;
3902 scb->dcdb.reserved2[0] = 0;
3903 scb->dcdb.reserved2[1] = 0;
3904 scb->dcdb.reserved2[2] = 0;
3905 }
3906 }
3907
3908 return ((*ha->func.issue) (ha, scb));
3909}
3910
3911/****************************************************************************/
3912/* */
3913/* Routine Name: ips_chk_status */
3914/* */
3915/* Routine Description: */
3916/* */
3917/* Check the status of commands to logical drives */
3918/* Assumed to be called with the HA lock */
3919/****************************************************************************/
3920static void
3921ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
3922{
3923 ips_scb_t *scb;
3924 ips_stat_t *sp;
3925 uint8_t basic_status;
3926 uint8_t ext_status;
3927 int errcode;
3928 IPS_SCSI_INQ_DATA inquiryData;
3929
3930 METHOD_TRACE("ips_chkstatus", 1);
3931
3932 scb = &ha->scbs[pstatus->fields.command_id];
3933 scb->basic_status = basic_status =
3934 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK;
3935 scb->extended_status = ext_status = pstatus->fields.extended_status;
3936
3937 sp = &ha->sp;
3938 sp->residue_len = 0;
3939 sp->scb_addr = (void *) scb;
3940
3941 /* Remove the item from the active queue */
3942 ips_removeq_scb(&ha->scb_activelist, scb);
3943
3944 if (!scb->scsi_cmd)
3945 /* internal commands are handled in do_ipsintr */
3946 return;
3947
3948 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)",
3949 ips_name,
3950 ha->host_num,
3951 scb->cdb[0],
3952 scb->cmd.basic_io.command_id,
3953 scb->bus, scb->target_id, scb->lun);
3954
3955 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd)))
3956 /* passthru - just returns the raw result */
3957 return;
3958
3959 errcode = DID_OK;
3960
3961 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) ||
3962 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) {
3963
3964 if (scb->bus == 0) {
3965 if ((basic_status & IPS_GSC_STATUS_MASK) ==
3966 IPS_CMD_RECOVERED_ERROR) {
3967 DEBUG_VAR(1,
3968 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
3969 ips_name, ha->host_num,
3970 scb->cmd.basic_io.op_code,
3971 basic_status, ext_status);
3972 }
3973
3974 switch (scb->scsi_cmd->cmnd[0]) {
3975 case ALLOW_MEDIUM_REMOVAL:
3976 case REZERO_UNIT:
3977 case ERASE:
3978 case WRITE_FILEMARKS:
3979 case SPACE:
3980 errcode = DID_ERROR;
3981 break;
3982
3983 case START_STOP:
3984 break;
3985
3986 case TEST_UNIT_READY:
3987 if (!ips_online(ha, scb)) {
3988 errcode = DID_TIME_OUT;
3989 }
3990 break;
3991
3992 case INQUIRY:
3993 if (ips_online(ha, scb)) {
3994 ips_inquiry(ha, scb);
3995 } else {
3996 errcode = DID_TIME_OUT;
3997 }
3998 break;
3999
4000 case REQUEST_SENSE:
4001 ips_reqsen(ha, scb);
4002 break;
4003
4004 case READ_6:
4005 case WRITE_6:
4006 case READ_10:
4007 case WRITE_10:
4008 case RESERVE:
4009 case RELEASE:
4010 break;
4011
4012 case MODE_SENSE:
4013 if (!ips_online(ha, scb)
4014 || !ips_msense(ha, scb)) {
4015 errcode = DID_ERROR;
4016 }
4017 break;
4018
4019 case READ_CAPACITY:
4020 if (ips_online(ha, scb))
4021 ips_rdcap(ha, scb);
4022 else {
4023 errcode = DID_TIME_OUT;
4024 }
4025 break;
4026
4027 case SEND_DIAGNOSTIC:
4028 case REASSIGN_BLOCKS:
4029 break;
4030
4031 case FORMAT_UNIT:
4032 errcode = DID_ERROR;
4033 break;
4034
4035 case SEEK_10:
4036 case VERIFY:
4037 case READ_DEFECT_DATA:
4038 case READ_BUFFER:
4039 case WRITE_BUFFER:
4040 break;
4041
4042 default:
4043 errcode = DID_ERROR;
4044 } /* end switch */
4045
4046 scb->scsi_cmd->result = errcode << 16;
4047 } else { /* bus == 0 */
4048 /* restrict access to physical drives */
4049 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
4050 ips_scmd_buf_read(scb->scsi_cmd,
4051 &inquiryData, sizeof (inquiryData));
4052 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK)
4053 scb->scsi_cmd->result = DID_TIME_OUT << 16;
4054 }
4055 } /* else */
4056 } else { /* recovered error / success */
4057 if (scb->bus == 0) {
4058 DEBUG_VAR(1,
4059 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
4060 ips_name, ha->host_num,
4061 scb->cmd.basic_io.op_code, basic_status,
4062 ext_status);
4063 }
4064
4065 ips_map_status(ha, scb, sp);
4066 } /* else */
4067}
4068
4069/****************************************************************************/
4070/* */
4071/* Routine Name: ips_online */
4072/* */
4073/* Routine Description: */
4074/* */
4075/* Determine if a logical drive is online */
4076/* */
4077/****************************************************************************/
4078static int
4079ips_online(ips_ha_t * ha, ips_scb_t * scb)
4080{
4081 METHOD_TRACE("ips_online", 1);
4082
4083 if (scb->target_id >= IPS_MAX_LD)
4084 return (0);
4085
4086 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) {
4087 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO));
4088 return (0);
4089 }
4090
4091 if (ha->logical_drive_info->drive_info[scb->target_id].state !=
4092 IPS_LD_OFFLINE
4093 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4094 IPS_LD_FREE
4095 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4096 IPS_LD_CRS
4097 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4098 IPS_LD_SYS)
4099 return (1);
4100 else
4101 return (0);
4102}
4103
4104/****************************************************************************/
4105/* */
4106/* Routine Name: ips_inquiry */
4107/* */
4108/* Routine Description: */
4109/* */
4110/* Simulate an inquiry command to a logical drive */
4111/* */
4112/****************************************************************************/
4113static int
4114ips_inquiry(ips_ha_t * ha, ips_scb_t * scb)
4115{
4116 IPS_SCSI_INQ_DATA inquiry;
4117
4118 METHOD_TRACE("ips_inquiry", 1);
4119
4120 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA));
4121
4122 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD;
4123 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED;
4124 inquiry.Version = IPS_SCSI_INQ_REV2;
4125 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2;
4126 inquiry.AdditionalLength = 31;
4127 inquiry.Flags[0] = IPS_SCSI_INQ_Address16;
4128 inquiry.Flags[1] =
4129 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue;
4130 strncpy(inquiry.VendorId, "IBM ", 8);
4131 strncpy(inquiry.ProductId, "SERVERAID ", 16);
4132 strncpy(inquiry.ProductRevisionLevel, "1.00", 4);
4133
4134 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry));
4135
4136 return (1);
4137}
4138
4139/****************************************************************************/
4140/* */
4141/* Routine Name: ips_rdcap */
4142/* */
4143/* Routine Description: */
4144/* */
4145/* Simulate a read capacity command to a logical drive */
4146/* */
4147/****************************************************************************/
4148static int
4149ips_rdcap(ips_ha_t * ha, ips_scb_t * scb)
4150{
4151 IPS_SCSI_CAPACITY cap;
4152
4153 METHOD_TRACE("ips_rdcap", 1);
4154
4155 if (scsi_bufflen(scb->scsi_cmd) < 8)
4156 return (0);
4157
4158 cap.lba =
4159 cpu_to_be32(le32_to_cpu
4160 (ha->logical_drive_info->
4161 drive_info[scb->target_id].sector_count) - 1);
4162 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE);
4163
4164 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap));
4165
4166 return (1);
4167}
4168
4169/****************************************************************************/
4170/* */
4171/* Routine Name: ips_msense */
4172/* */
4173/* Routine Description: */
4174/* */
4175/* Simulate a mode sense command to a logical drive */
4176/* */
4177/****************************************************************************/
4178static int
4179ips_msense(ips_ha_t * ha, ips_scb_t * scb)
4180{
4181 uint16_t heads;
4182 uint16_t sectors;
4183 uint32_t cylinders;
4184 IPS_SCSI_MODE_PAGE_DATA mdata;
4185
4186 METHOD_TRACE("ips_msense", 1);
4187
4188 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 &&
4189 (ha->enq->ucMiscFlag & 0x8) == 0) {
4190 heads = IPS_NORM_HEADS;
4191 sectors = IPS_NORM_SECTORS;
4192 } else {
4193 heads = IPS_COMP_HEADS;
4194 sectors = IPS_COMP_SECTORS;
4195 }
4196
4197 cylinders =
4198 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) -
4199 1) / (heads * sectors);
4200
4201 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA));
4202
4203 mdata.hdr.BlockDescLength = 8;
4204
4205 switch (scb->scsi_cmd->cmnd[2] & 0x3f) {
4206 case 0x03: /* page 3 */
4207 mdata.pdata.pg3.PageCode = 3;
4208 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3);
4209 mdata.hdr.DataLength =
4210 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength;
4211 mdata.pdata.pg3.TracksPerZone = 0;
4212 mdata.pdata.pg3.AltSectorsPerZone = 0;
4213 mdata.pdata.pg3.AltTracksPerZone = 0;
4214 mdata.pdata.pg3.AltTracksPerVolume = 0;
4215 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors);
4216 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE);
4217 mdata.pdata.pg3.Interleave = cpu_to_be16(1);
4218 mdata.pdata.pg3.TrackSkew = 0;
4219 mdata.pdata.pg3.CylinderSkew = 0;
4220 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector;
4221 break;
4222
4223 case 0x4:
4224 mdata.pdata.pg4.PageCode = 4;
4225 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4);
4226 mdata.hdr.DataLength =
4227 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength;
4228 mdata.pdata.pg4.CylindersHigh =
4229 cpu_to_be16((cylinders >> 8) & 0xFFFF);
4230 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF);
4231 mdata.pdata.pg4.Heads = heads;
4232 mdata.pdata.pg4.WritePrecompHigh = 0;
4233 mdata.pdata.pg4.WritePrecompLow = 0;
4234 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0;
4235 mdata.pdata.pg4.ReducedWriteCurrentLow = 0;
4236 mdata.pdata.pg4.StepRate = cpu_to_be16(1);
4237 mdata.pdata.pg4.LandingZoneHigh = 0;
4238 mdata.pdata.pg4.LandingZoneLow = 0;
4239 mdata.pdata.pg4.flags = 0;
4240 mdata.pdata.pg4.RotationalOffset = 0;
4241 mdata.pdata.pg4.MediumRotationRate = 0;
4242 break;
4243 case 0x8:
4244 mdata.pdata.pg8.PageCode = 8;
4245 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8);
4246 mdata.hdr.DataLength =
4247 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength;
4248 /* everything else is left set to 0 */
4249 break;
4250
4251 default:
4252 return (0);
4253 } /* end switch */
4254
4255 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata));
4256
4257 return (1);
4258}
4259
4260/****************************************************************************/
4261/* */
4262/* Routine Name: ips_reqsen */
4263/* */
4264/* Routine Description: */
4265/* */
4266/* Simulate a request sense command to a logical drive */
4267/* */
4268/****************************************************************************/
4269static int
4270ips_reqsen(ips_ha_t * ha, ips_scb_t * scb)
4271{
4272 IPS_SCSI_REQSEN reqsen;
4273
4274 METHOD_TRACE("ips_reqsen", 1);
4275
4276 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN));
4277
4278 reqsen.ResponseCode =
4279 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR;
4280 reqsen.AdditionalLength = 10;
4281 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE;
4282 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE;
4283
4284 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen));
4285
4286 return (1);
4287}
4288
4289/****************************************************************************/
4290/* */
4291/* Routine Name: ips_free */
4292/* */
4293/* Routine Description: */
4294/* */
4295/* Free any allocated space for this controller */
4296/* */
4297/****************************************************************************/
4298static void
4299ips_free(ips_ha_t * ha)
4300{
4301
4302 METHOD_TRACE("ips_free", 1);
4303
4304 if (ha) {
4305 if (ha->enq) {
4306 pci_free_consistent(ha->pcidev, sizeof(IPS_ENQ),
4307 ha->enq, ha->enq_busaddr);
4308 ha->enq = NULL;
4309 }
4310
4311 kfree(ha->conf);
4312 ha->conf = NULL;
4313
4314 if (ha->adapt) {
4315 pci_free_consistent(ha->pcidev,
4316 sizeof (IPS_ADAPTER) +
4317 sizeof (IPS_IO_CMD), ha->adapt,
4318 ha->adapt->hw_status_start);
4319 ha->adapt = NULL;
4320 }
4321
4322 if (ha->logical_drive_info) {
4323 pci_free_consistent(ha->pcidev,
4324 sizeof (IPS_LD_INFO),
4325 ha->logical_drive_info,
4326 ha->logical_drive_info_dma_addr);
4327 ha->logical_drive_info = NULL;
4328 }
4329
4330 kfree(ha->nvram);
4331 ha->nvram = NULL;
4332
4333 kfree(ha->subsys);
4334 ha->subsys = NULL;
4335
4336 if (ha->ioctl_data) {
4337 pci_free_consistent(ha->pcidev, ha->ioctl_len,
4338 ha->ioctl_data, ha->ioctl_busaddr);
4339 ha->ioctl_data = NULL;
4340 ha->ioctl_datasize = 0;
4341 ha->ioctl_len = 0;
4342 }
4343 ips_deallocatescbs(ha, ha->max_cmds);
4344
4345 /* free memory mapped (if applicable) */
4346 if (ha->mem_ptr) {
4347 iounmap(ha->ioremap_ptr);
4348 ha->ioremap_ptr = NULL;
4349 ha->mem_ptr = NULL;
4350 }
4351
4352 ha->mem_addr = 0;
4353
4354 }
4355}
4356
4357/****************************************************************************/
4358/* */
4359/* Routine Name: ips_deallocatescbs */
4360/* */
4361/* Routine Description: */
4362/* */
4363/* Free the command blocks */
4364/* */
4365/****************************************************************************/
4366static int
4367ips_deallocatescbs(ips_ha_t * ha, int cmds)
4368{
4369 if (ha->scbs) {
4370 pci_free_consistent(ha->pcidev,
4371 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds,
4372 ha->scbs->sg_list.list,
4373 ha->scbs->sg_busaddr);
4374 pci_free_consistent(ha->pcidev, sizeof (ips_scb_t) * cmds,
4375 ha->scbs, ha->scbs->scb_busaddr);
4376 ha->scbs = NULL;
4377 } /* end if */
4378 return 1;
4379}
4380
4381/****************************************************************************/
4382/* */
4383/* Routine Name: ips_allocatescbs */
4384/* */
4385/* Routine Description: */
4386/* */
4387/* Allocate the command blocks */
4388/* */
4389/****************************************************************************/
4390static int
4391ips_allocatescbs(ips_ha_t * ha)
4392{
4393 ips_scb_t *scb_p;
4394 IPS_SG_LIST ips_sg;
4395 int i;
4396 dma_addr_t command_dma, sg_dma;
4397
4398 METHOD_TRACE("ips_allocatescbs", 1);
4399
4400 /* Allocate memory for the SCBs */
4401 ha->scbs =
4402 pci_alloc_consistent(ha->pcidev, ha->max_cmds * sizeof (ips_scb_t),
4403 &command_dma);
4404 if (ha->scbs == NULL)
4405 return 0;
4406 ips_sg.list =
4407 pci_alloc_consistent(ha->pcidev,
4408 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG *
4409 ha->max_cmds, &sg_dma);
4410 if (ips_sg.list == NULL) {
4411 pci_free_consistent(ha->pcidev,
4412 ha->max_cmds * sizeof (ips_scb_t), ha->scbs,
4413 command_dma);
4414 return 0;
4415 }
4416
4417 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t));
4418
4419 for (i = 0; i < ha->max_cmds; i++) {
4420 scb_p = &ha->scbs[i];
4421 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i;
4422 /* set up S/G list */
4423 if (IPS_USE_ENH_SGLIST(ha)) {
4424 scb_p->sg_list.enh_list =
4425 ips_sg.enh_list + i * IPS_MAX_SG;
4426 scb_p->sg_busaddr =
4427 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4428 } else {
4429 scb_p->sg_list.std_list =
4430 ips_sg.std_list + i * IPS_MAX_SG;
4431 scb_p->sg_busaddr =
4432 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4433 }
4434
4435 /* add to the free list */
4436 if (i < ha->max_cmds - 1) {
4437 scb_p->q_next = ha->scb_freelist;
4438 ha->scb_freelist = scb_p;
4439 }
4440 }
4441
4442 /* success */
4443 return (1);
4444}
4445
4446/****************************************************************************/
4447/* */
4448/* Routine Name: ips_init_scb */
4449/* */
4450/* Routine Description: */
4451/* */
4452/* Initialize a CCB to default values */
4453/* */
4454/****************************************************************************/
4455static void
4456ips_init_scb(ips_ha_t * ha, ips_scb_t * scb)
4457{
4458 IPS_SG_LIST sg_list;
4459 uint32_t cmd_busaddr, sg_busaddr;
4460 METHOD_TRACE("ips_init_scb", 1);
4461
4462 if (scb == NULL)
4463 return;
4464
4465 sg_list.list = scb->sg_list.list;
4466 cmd_busaddr = scb->scb_busaddr;
4467 sg_busaddr = scb->sg_busaddr;
4468 /* zero fill */
4469 memset(scb, 0, sizeof (ips_scb_t));
4470 memset(ha->dummy, 0, sizeof (IPS_IO_CMD));
4471
4472 /* Initialize dummy command bucket */
4473 ha->dummy->op_code = 0xFF;
4474 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start
4475 + sizeof (IPS_ADAPTER));
4476 ha->dummy->command_id = IPS_MAX_CMDS;
4477
4478 /* set bus address of scb */
4479 scb->scb_busaddr = cmd_busaddr;
4480 scb->sg_busaddr = sg_busaddr;
4481 scb->sg_list.list = sg_list.list;
4482
4483 /* Neptune Fix */
4484 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE);
4485 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start
4486 + sizeof (IPS_ADAPTER));
4487}
4488
4489/****************************************************************************/
4490/* */
4491/* Routine Name: ips_get_scb */
4492/* */
4493/* Routine Description: */
4494/* */
4495/* Initialize a CCB to default values */
4496/* */
4497/* ASSUMED to be callled from within a lock */
4498/* */
4499/****************************************************************************/
4500static ips_scb_t *
4501ips_getscb(ips_ha_t * ha)
4502{
4503 ips_scb_t *scb;
4504
4505 METHOD_TRACE("ips_getscb", 1);
4506
4507 if ((scb = ha->scb_freelist) == NULL) {
4508
4509 return (NULL);
4510 }
4511
4512 ha->scb_freelist = scb->q_next;
4513 scb->flags = 0;
4514 scb->q_next = NULL;
4515
4516 ips_init_scb(ha, scb);
4517
4518 return (scb);
4519}
4520
4521/****************************************************************************/
4522/* */
4523/* Routine Name: ips_free_scb */
4524/* */
4525/* Routine Description: */
4526/* */
4527/* Return an unused CCB back to the free list */
4528/* */
4529/* ASSUMED to be called from within a lock */
4530/* */
4531/****************************************************************************/
4532static void
4533ips_freescb(ips_ha_t * ha, ips_scb_t * scb)
4534{
4535
4536 METHOD_TRACE("ips_freescb", 1);
4537 if (scb->flags & IPS_SCB_MAP_SG)
4538 scsi_dma_unmap(scb->scsi_cmd);
4539 else if (scb->flags & IPS_SCB_MAP_SINGLE)
4540 pci_unmap_single(ha->pcidev, scb->data_busaddr, scb->data_len,
4541 IPS_DMA_DIR(scb));
4542
4543 /* check to make sure this is not our "special" scb */
4544 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) {
4545 scb->q_next = ha->scb_freelist;
4546 ha->scb_freelist = scb;
4547 }
4548}
4549
4550/****************************************************************************/
4551/* */
4552/* Routine Name: ips_isinit_copperhead */
4553/* */
4554/* Routine Description: */
4555/* */
4556/* Is controller initialized ? */
4557/* */
4558/****************************************************************************/
4559static int
4560ips_isinit_copperhead(ips_ha_t * ha)
4561{
4562 uint8_t scpr;
4563 uint8_t isr;
4564
4565 METHOD_TRACE("ips_isinit_copperhead", 1);
4566
4567 isr = inb(ha->io_addr + IPS_REG_HISR);
4568 scpr = inb(ha->io_addr + IPS_REG_SCPR);
4569
4570 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4571 return (0);
4572 else
4573 return (1);
4574}
4575
4576/****************************************************************************/
4577/* */
4578/* Routine Name: ips_isinit_copperhead_memio */
4579/* */
4580/* Routine Description: */
4581/* */
4582/* Is controller initialized ? */
4583/* */
4584/****************************************************************************/
4585static int
4586ips_isinit_copperhead_memio(ips_ha_t * ha)
4587{
4588 uint8_t isr = 0;
4589 uint8_t scpr;
4590
4591 METHOD_TRACE("ips_is_init_copperhead_memio", 1);
4592
4593 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4594 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4595
4596 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4597 return (0);
4598 else
4599 return (1);
4600}
4601
4602/****************************************************************************/
4603/* */
4604/* Routine Name: ips_isinit_morpheus */
4605/* */
4606/* Routine Description: */
4607/* */
4608/* Is controller initialized ? */
4609/* */
4610/****************************************************************************/
4611static int
4612ips_isinit_morpheus(ips_ha_t * ha)
4613{
4614 uint32_t post;
4615 uint32_t bits;
4616
4617 METHOD_TRACE("ips_is_init_morpheus", 1);
4618
4619 if (ips_isintr_morpheus(ha))
4620 ips_flush_and_reset(ha);
4621
4622 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4623 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4624
4625 if (post == 0)
4626 return (0);
4627 else if (bits & 0x3)
4628 return (0);
4629 else
4630 return (1);
4631}
4632
4633/****************************************************************************/
4634/* */
4635/* Routine Name: ips_flush_and_reset */
4636/* */
4637/* Routine Description: */
4638/* */
4639/* Perform cleanup ( FLUSH and RESET ) when the adapter is in an unknown */
4640/* state ( was trying to INIT and an interrupt was already pending ) ... */
4641/* */
4642/****************************************************************************/
4643static void
4644ips_flush_and_reset(ips_ha_t *ha)
4645{
4646 ips_scb_t *scb;
4647 int ret;
4648 int time;
4649 int done;
4650 dma_addr_t command_dma;
4651
4652 /* Create a usuable SCB */
4653 scb = pci_alloc_consistent(ha->pcidev, sizeof(ips_scb_t), &command_dma);
4654 if (scb) {
4655 memset(scb, 0, sizeof(ips_scb_t));
4656 ips_init_scb(ha, scb);
4657 scb->scb_busaddr = command_dma;
4658
4659 scb->timeout = ips_cmd_timeout;
4660 scb->cdb[0] = IPS_CMD_FLUSH;
4661
4662 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
4663 scb->cmd.flush_cache.command_id = IPS_MAX_CMDS; /* Use an ID that would otherwise not exist */
4664 scb->cmd.flush_cache.state = IPS_NORM_STATE;
4665 scb->cmd.flush_cache.reserved = 0;
4666 scb->cmd.flush_cache.reserved2 = 0;
4667 scb->cmd.flush_cache.reserved3 = 0;
4668 scb->cmd.flush_cache.reserved4 = 0;
4669
4670 ret = ips_send_cmd(ha, scb); /* Send the Flush Command */
4671
4672 if (ret == IPS_SUCCESS) {
4673 time = 60 * IPS_ONE_SEC; /* Max Wait time is 60 seconds */
4674 done = 0;
4675
4676 while ((time > 0) && (!done)) {
4677 done = ips_poll_for_flush_complete(ha);
4678 /* This may look evil, but it's only done during extremely rare start-up conditions ! */
4679 udelay(1000);
4680 time--;
4681 }
4682 }
4683 }
4684
4685 /* Now RESET and INIT the adapter */
4686 (*ha->func.reset) (ha);
4687
4688 pci_free_consistent(ha->pcidev, sizeof(ips_scb_t), scb, command_dma);
4689 return;
4690}
4691
4692/****************************************************************************/
4693/* */
4694/* Routine Name: ips_poll_for_flush_complete */
4695/* */
4696/* Routine Description: */
4697/* */
4698/* Poll for the Flush Command issued by ips_flush_and_reset() to complete */
4699/* All other responses are just taken off the queue and ignored */
4700/* */
4701/****************************************************************************/
4702static int
4703ips_poll_for_flush_complete(ips_ha_t * ha)
4704{
4705 IPS_STATUS cstatus;
4706
4707 while (TRUE) {
4708 cstatus.value = (*ha->func.statupd) (ha);
4709
4710 if (cstatus.value == 0xffffffff) /* If No Interrupt to process */
4711 break;
4712
4713 /* Success is when we see the Flush Command ID */
4714 if (cstatus.fields.command_id == IPS_MAX_CMDS)
4715 return 1;
4716 }
4717
4718 return 0;
4719}
4720
4721/****************************************************************************/
4722/* */
4723/* Routine Name: ips_enable_int_copperhead */
4724/* */
4725/* Routine Description: */
4726/* Turn on interrupts */
4727/* */
4728/****************************************************************************/
4729static void
4730ips_enable_int_copperhead(ips_ha_t * ha)
4731{
4732 METHOD_TRACE("ips_enable_int_copperhead", 1);
4733
4734 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
4735 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4736}
4737
4738/****************************************************************************/
4739/* */
4740/* Routine Name: ips_enable_int_copperhead_memio */
4741/* */
4742/* Routine Description: */
4743/* Turn on interrupts */
4744/* */
4745/****************************************************************************/
4746static void
4747ips_enable_int_copperhead_memio(ips_ha_t * ha)
4748{
4749 METHOD_TRACE("ips_enable_int_copperhead_memio", 1);
4750
4751 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4752 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4753}
4754
4755/****************************************************************************/
4756/* */
4757/* Routine Name: ips_enable_int_morpheus */
4758/* */
4759/* Routine Description: */
4760/* Turn on interrupts */
4761/* */
4762/****************************************************************************/
4763static void
4764ips_enable_int_morpheus(ips_ha_t * ha)
4765{
4766 uint32_t Oimr;
4767
4768 METHOD_TRACE("ips_enable_int_morpheus", 1);
4769
4770 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4771 Oimr &= ~0x08;
4772 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4773 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/
4774}
4775
4776/****************************************************************************/
4777/* */
4778/* Routine Name: ips_init_copperhead */
4779/* */
4780/* Routine Description: */
4781/* */
4782/* Initialize a copperhead controller */
4783/* */
4784/****************************************************************************/
4785static int
4786ips_init_copperhead(ips_ha_t * ha)
4787{
4788 uint8_t Isr;
4789 uint8_t Cbsp;
4790 uint8_t PostByte[IPS_MAX_POST_BYTES];
4791 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4792 int i, j;
4793
4794 METHOD_TRACE("ips_init_copperhead", 1);
4795
4796 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4797 for (j = 0; j < 45; j++) {
4798 Isr = inb(ha->io_addr + IPS_REG_HISR);
4799 if (Isr & IPS_BIT_GHI)
4800 break;
4801
4802 /* Delay for 1 Second */
4803 MDELAY(IPS_ONE_SEC);
4804 }
4805
4806 if (j >= 45)
4807 /* error occurred */
4808 return (0);
4809
4810 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4811 outb(Isr, ha->io_addr + IPS_REG_HISR);
4812 }
4813
4814 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4815 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4816 "reset controller fails (post status %x %x).\n",
4817 PostByte[0], PostByte[1]);
4818
4819 return (0);
4820 }
4821
4822 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4823 for (j = 0; j < 240; j++) {
4824 Isr = inb(ha->io_addr + IPS_REG_HISR);
4825 if (Isr & IPS_BIT_GHI)
4826 break;
4827
4828 /* Delay for 1 Second */
4829 MDELAY(IPS_ONE_SEC);
4830 }
4831
4832 if (j >= 240)
4833 /* error occurred */
4834 return (0);
4835
4836 ConfigByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4837 outb(Isr, ha->io_addr + IPS_REG_HISR);
4838 }
4839
4840 for (i = 0; i < 240; i++) {
4841 Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
4842
4843 if ((Cbsp & IPS_BIT_OP) == 0)
4844 break;
4845
4846 /* Delay for 1 Second */
4847 MDELAY(IPS_ONE_SEC);
4848 }
4849
4850 if (i >= 240)
4851 /* reset failed */
4852 return (0);
4853
4854 /* setup CCCR */
4855 outl(0x1010, ha->io_addr + IPS_REG_CCCR);
4856
4857 /* Enable busmastering */
4858 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
4859
4860 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4861 /* fix for anaconda64 */
4862 outl(0, ha->io_addr + IPS_REG_NDAE);
4863
4864 /* Enable interrupts */
4865 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
4866
4867 return (1);
4868}
4869
4870/****************************************************************************/
4871/* */
4872/* Routine Name: ips_init_copperhead_memio */
4873/* */
4874/* Routine Description: */
4875/* */
4876/* Initialize a copperhead controller with memory mapped I/O */
4877/* */
4878/****************************************************************************/
4879static int
4880ips_init_copperhead_memio(ips_ha_t * ha)
4881{
4882 uint8_t Isr = 0;
4883 uint8_t Cbsp;
4884 uint8_t PostByte[IPS_MAX_POST_BYTES];
4885 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4886 int i, j;
4887
4888 METHOD_TRACE("ips_init_copperhead_memio", 1);
4889
4890 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4891 for (j = 0; j < 45; j++) {
4892 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4893 if (Isr & IPS_BIT_GHI)
4894 break;
4895
4896 /* Delay for 1 Second */
4897 MDELAY(IPS_ONE_SEC);
4898 }
4899
4900 if (j >= 45)
4901 /* error occurred */
4902 return (0);
4903
4904 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4905 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4906 }
4907
4908 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4909 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4910 "reset controller fails (post status %x %x).\n",
4911 PostByte[0], PostByte[1]);
4912
4913 return (0);
4914 }
4915
4916 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4917 for (j = 0; j < 240; j++) {
4918 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4919 if (Isr & IPS_BIT_GHI)
4920 break;
4921
4922 /* Delay for 1 Second */
4923 MDELAY(IPS_ONE_SEC);
4924 }
4925
4926 if (j >= 240)
4927 /* error occurred */
4928 return (0);
4929
4930 ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4931 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4932 }
4933
4934 for (i = 0; i < 240; i++) {
4935 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
4936
4937 if ((Cbsp & IPS_BIT_OP) == 0)
4938 break;
4939
4940 /* Delay for 1 Second */
4941 MDELAY(IPS_ONE_SEC);
4942 }
4943
4944 if (i >= 240)
4945 /* error occurred */
4946 return (0);
4947
4948 /* setup CCCR */
4949 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
4950
4951 /* Enable busmastering */
4952 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
4953
4954 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4955 /* fix for anaconda64 */
4956 writel(0, ha->mem_ptr + IPS_REG_NDAE);
4957
4958 /* Enable interrupts */
4959 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4960
4961 /* if we get here then everything went OK */
4962 return (1);
4963}
4964
4965/****************************************************************************/
4966/* */
4967/* Routine Name: ips_init_morpheus */
4968/* */
4969/* Routine Description: */
4970/* */
4971/* Initialize a morpheus controller */
4972/* */
4973/****************************************************************************/
4974static int
4975ips_init_morpheus(ips_ha_t * ha)
4976{
4977 uint32_t Post;
4978 uint32_t Config;
4979 uint32_t Isr;
4980 uint32_t Oimr;
4981 int i;
4982
4983 METHOD_TRACE("ips_init_morpheus", 1);
4984
4985 /* Wait up to 45 secs for Post */
4986 for (i = 0; i < 45; i++) {
4987 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4988
4989 if (Isr & IPS_BIT_I960_MSG0I)
4990 break;
4991
4992 /* Delay for 1 Second */
4993 MDELAY(IPS_ONE_SEC);
4994 }
4995
4996 if (i >= 45) {
4997 /* error occurred */
4998 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4999 "timeout waiting for post.\n");
5000
5001 return (0);
5002 }
5003
5004 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
5005
5006 if (Post == 0x4F00) { /* If Flashing the Battery PIC */
5007 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5008 "Flashing Battery PIC, Please wait ...\n");
5009
5010 /* Clear the interrupt bit */
5011 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
5012 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5013
5014 for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */
5015 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
5016 if (Post != 0x4F00)
5017 break;
5018 /* Delay for 1 Second */
5019 MDELAY(IPS_ONE_SEC);
5020 }
5021
5022 if (i >= 120) {
5023 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5024 "timeout waiting for Battery PIC Flash\n");
5025 return (0);
5026 }
5027
5028 }
5029
5030 /* Clear the interrupt bit */
5031 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
5032 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5033
5034 if (Post < (IPS_GOOD_POST_STATUS << 8)) {
5035 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5036 "reset controller fails (post status %x).\n", Post);
5037
5038 return (0);
5039 }
5040
5041 /* Wait up to 240 secs for config bytes */
5042 for (i = 0; i < 240; i++) {
5043 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5044
5045 if (Isr & IPS_BIT_I960_MSG1I)
5046 break;
5047
5048 /* Delay for 1 Second */
5049 MDELAY(IPS_ONE_SEC);
5050 }
5051
5052 if (i >= 240) {
5053 /* error occurred */
5054 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5055 "timeout waiting for config.\n");
5056
5057 return (0);
5058 }
5059
5060 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
5061
5062 /* Clear interrupt bit */
5063 Isr = (uint32_t) IPS_BIT_I960_MSG1I;
5064 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5065
5066 /* Turn on the interrupts */
5067 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
5068 Oimr &= ~0x8;
5069 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
5070
5071 /* if we get here then everything went OK */
5072
5073 /* Since we did a RESET, an EraseStripeLock may be needed */
5074 if (Post == 0xEF10) {
5075 if ((Config == 0x000F) || (Config == 0x0009))
5076 ha->requires_esl = 1;
5077 }
5078
5079 return (1);
5080}
5081
5082/****************************************************************************/
5083/* */
5084/* Routine Name: ips_reset_copperhead */
5085/* */
5086/* Routine Description: */
5087/* */
5088/* Reset the controller */
5089/* */
5090/****************************************************************************/
5091static int
5092ips_reset_copperhead(ips_ha_t * ha)
5093{
5094 int reset_counter;
5095
5096 METHOD_TRACE("ips_reset_copperhead", 1);
5097
5098 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d",
5099 ips_name, ha->host_num, ha->io_addr, ha->pcidev->irq);
5100
5101 reset_counter = 0;
5102
5103 while (reset_counter < 2) {
5104 reset_counter++;
5105
5106 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
5107
5108 /* Delay for 1 Second */
5109 MDELAY(IPS_ONE_SEC);
5110
5111 outb(0, ha->io_addr + IPS_REG_SCPR);
5112
5113 /* Delay for 1 Second */
5114 MDELAY(IPS_ONE_SEC);
5115
5116 if ((*ha->func.init) (ha))
5117 break;
5118 else if (reset_counter >= 2) {
5119
5120 return (0);
5121 }
5122 }
5123
5124 return (1);
5125}
5126
5127/****************************************************************************/
5128/* */
5129/* Routine Name: ips_reset_copperhead_memio */
5130/* */
5131/* Routine Description: */
5132/* */
5133/* Reset the controller */
5134/* */
5135/****************************************************************************/
5136static int
5137ips_reset_copperhead_memio(ips_ha_t * ha)
5138{
5139 int reset_counter;
5140
5141 METHOD_TRACE("ips_reset_copperhead_memio", 1);
5142
5143 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d",
5144 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5145
5146 reset_counter = 0;
5147
5148 while (reset_counter < 2) {
5149 reset_counter++;
5150
5151 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5152
5153 /* Delay for 1 Second */
5154 MDELAY(IPS_ONE_SEC);
5155
5156 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5157
5158 /* Delay for 1 Second */
5159 MDELAY(IPS_ONE_SEC);
5160
5161 if ((*ha->func.init) (ha))
5162 break;
5163 else if (reset_counter >= 2) {
5164
5165 return (0);
5166 }
5167 }
5168
5169 return (1);
5170}
5171
5172/****************************************************************************/
5173/* */
5174/* Routine Name: ips_reset_morpheus */
5175/* */
5176/* Routine Description: */
5177/* */
5178/* Reset the controller */
5179/* */
5180/****************************************************************************/
5181static int
5182ips_reset_morpheus(ips_ha_t * ha)
5183{
5184 int reset_counter;
5185 uint8_t junk;
5186
5187 METHOD_TRACE("ips_reset_morpheus", 1);
5188
5189 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d",
5190 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5191
5192 reset_counter = 0;
5193
5194 while (reset_counter < 2) {
5195 reset_counter++;
5196
5197 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5198
5199 /* Delay for 5 Seconds */
5200 MDELAY(5 * IPS_ONE_SEC);
5201
5202 /* Do a PCI config read to wait for adapter */
5203 pci_read_config_byte(ha->pcidev, 4, &junk);
5204
5205 if ((*ha->func.init) (ha))
5206 break;
5207 else if (reset_counter >= 2) {
5208
5209 return (0);
5210 }
5211 }
5212
5213 return (1);
5214}
5215
5216/****************************************************************************/
5217/* */
5218/* Routine Name: ips_statinit */
5219/* */
5220/* Routine Description: */
5221/* */
5222/* Initialize the status queues on the controller */
5223/* */
5224/****************************************************************************/
5225static void
5226ips_statinit(ips_ha_t * ha)
5227{
5228 uint32_t phys_status_start;
5229
5230 METHOD_TRACE("ips_statinit", 1);
5231
5232 ha->adapt->p_status_start = ha->adapt->status;
5233 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5234 ha->adapt->p_status_tail = ha->adapt->status;
5235
5236 phys_status_start = ha->adapt->hw_status_start;
5237 outl(phys_status_start, ha->io_addr + IPS_REG_SQSR);
5238 outl(phys_status_start + IPS_STATUS_Q_SIZE,
5239 ha->io_addr + IPS_REG_SQER);
5240 outl(phys_status_start + IPS_STATUS_SIZE,
5241 ha->io_addr + IPS_REG_SQHR);
5242 outl(phys_status_start, ha->io_addr + IPS_REG_SQTR);
5243
5244 ha->adapt->hw_status_tail = phys_status_start;
5245}
5246
5247/****************************************************************************/
5248/* */
5249/* Routine Name: ips_statinit_memio */
5250/* */
5251/* Routine Description: */
5252/* */
5253/* Initialize the status queues on the controller */
5254/* */
5255/****************************************************************************/
5256static void
5257ips_statinit_memio(ips_ha_t * ha)
5258{
5259 uint32_t phys_status_start;
5260
5261 METHOD_TRACE("ips_statinit_memio", 1);
5262
5263 ha->adapt->p_status_start = ha->adapt->status;
5264 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5265 ha->adapt->p_status_tail = ha->adapt->status;
5266
5267 phys_status_start = ha->adapt->hw_status_start;
5268 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5269 writel(phys_status_start + IPS_STATUS_Q_SIZE,
5270 ha->mem_ptr + IPS_REG_SQER);
5271 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5272 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5273
5274 ha->adapt->hw_status_tail = phys_status_start;
5275}
5276
5277/****************************************************************************/
5278/* */
5279/* Routine Name: ips_statupd_copperhead */
5280/* */
5281/* Routine Description: */
5282/* */
5283/* Remove an element from the status queue */
5284/* */
5285/****************************************************************************/
5286static uint32_t
5287ips_statupd_copperhead(ips_ha_t * ha)
5288{
5289 METHOD_TRACE("ips_statupd_copperhead", 1);
5290
5291 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5292 ha->adapt->p_status_tail++;
5293 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5294 } else {
5295 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5296 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5297 }
5298
5299 outl(ha->adapt->hw_status_tail,
5300 ha->io_addr + IPS_REG_SQTR);
5301
5302 return (ha->adapt->p_status_tail->value);
5303}
5304
5305/****************************************************************************/
5306/* */
5307/* Routine Name: ips_statupd_copperhead_memio */
5308/* */
5309/* Routine Description: */
5310/* */
5311/* Remove an element from the status queue */
5312/* */
5313/****************************************************************************/
5314static uint32_t
5315ips_statupd_copperhead_memio(ips_ha_t * ha)
5316{
5317 METHOD_TRACE("ips_statupd_copperhead_memio", 1);
5318
5319 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5320 ha->adapt->p_status_tail++;
5321 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5322 } else {
5323 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5324 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5325 }
5326
5327 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5328
5329 return (ha->adapt->p_status_tail->value);
5330}
5331
5332/****************************************************************************/
5333/* */
5334/* Routine Name: ips_statupd_morpheus */
5335/* */
5336/* Routine Description: */
5337/* */
5338/* Remove an element from the status queue */
5339/* */
5340/****************************************************************************/
5341static uint32_t
5342ips_statupd_morpheus(ips_ha_t * ha)
5343{
5344 uint32_t val;
5345
5346 METHOD_TRACE("ips_statupd_morpheus", 1);
5347
5348 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5349
5350 return (val);
5351}
5352
5353/****************************************************************************/
5354/* */
5355/* Routine Name: ips_issue_copperhead */
5356/* */
5357/* Routine Description: */
5358/* */
5359/* Send a command down to the controller */
5360/* */
5361/****************************************************************************/
5362static int
5363ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb)
5364{
5365 uint32_t TimeOut;
5366 uint32_t val;
5367
5368 METHOD_TRACE("ips_issue_copperhead", 1);
5369
5370 if (scb->scsi_cmd) {
5371 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5372 ips_name,
5373 ha->host_num,
5374 scb->cdb[0],
5375 scb->cmd.basic_io.command_id,
5376 scb->bus, scb->target_id, scb->lun);
5377 } else {
5378 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d",
5379 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5380 }
5381
5382 TimeOut = 0;
5383
5384 while ((val =
5385 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) {
5386 udelay(1000);
5387
5388 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5389 if (!(val & IPS_BIT_START_STOP))
5390 break;
5391
5392 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5393 "ips_issue val [0x%x].\n", val);
5394 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5395 "ips_issue semaphore chk timeout.\n");
5396
5397 return (IPS_FAILURE);
5398 } /* end if */
5399 } /* end while */
5400
5401 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_CCSAR);
5402 outw(IPS_BIT_START_CMD, ha->io_addr + IPS_REG_CCCR);
5403
5404 return (IPS_SUCCESS);
5405}
5406
5407/****************************************************************************/
5408/* */
5409/* Routine Name: ips_issue_copperhead_memio */
5410/* */
5411/* Routine Description: */
5412/* */
5413/* Send a command down to the controller */
5414/* */
5415/****************************************************************************/
5416static int
5417ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb)
5418{
5419 uint32_t TimeOut;
5420 uint32_t val;
5421
5422 METHOD_TRACE("ips_issue_copperhead_memio", 1);
5423
5424 if (scb->scsi_cmd) {
5425 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5426 ips_name,
5427 ha->host_num,
5428 scb->cdb[0],
5429 scb->cmd.basic_io.command_id,
5430 scb->bus, scb->target_id, scb->lun);
5431 } else {
5432 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5433 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5434 }
5435
5436 TimeOut = 0;
5437
5438 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5439 udelay(1000);
5440
5441 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5442 if (!(val & IPS_BIT_START_STOP))
5443 break;
5444
5445 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5446 "ips_issue val [0x%x].\n", val);
5447 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5448 "ips_issue semaphore chk timeout.\n");
5449
5450 return (IPS_FAILURE);
5451 } /* end if */
5452 } /* end while */
5453
5454 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5455 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5456
5457 return (IPS_SUCCESS);
5458}
5459
5460/****************************************************************************/
5461/* */
5462/* Routine Name: ips_issue_i2o */
5463/* */
5464/* Routine Description: */
5465/* */
5466/* Send a command down to the controller */
5467/* */
5468/****************************************************************************/
5469static int
5470ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb)
5471{
5472
5473 METHOD_TRACE("ips_issue_i2o", 1);
5474
5475 if (scb->scsi_cmd) {
5476 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5477 ips_name,
5478 ha->host_num,
5479 scb->cdb[0],
5480 scb->cmd.basic_io.command_id,
5481 scb->bus, scb->target_id, scb->lun);
5482 } else {
5483 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5484 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5485 }
5486
5487 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_I2O_INMSGQ);
5488
5489 return (IPS_SUCCESS);
5490}
5491
5492/****************************************************************************/
5493/* */
5494/* Routine Name: ips_issue_i2o_memio */
5495/* */
5496/* Routine Description: */
5497/* */
5498/* Send a command down to the controller */
5499/* */
5500/****************************************************************************/
5501static int
5502ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb)
5503{
5504
5505 METHOD_TRACE("ips_issue_i2o_memio", 1);
5506
5507 if (scb->scsi_cmd) {
5508 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5509 ips_name,
5510 ha->host_num,
5511 scb->cdb[0],
5512 scb->cmd.basic_io.command_id,
5513 scb->bus, scb->target_id, scb->lun);
5514 } else {
5515 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5516 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5517 }
5518
5519 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5520
5521 return (IPS_SUCCESS);
5522}
5523
5524/****************************************************************************/
5525/* */
5526/* Routine Name: ips_isintr_copperhead */
5527/* */
5528/* Routine Description: */
5529/* */
5530/* Test to see if an interrupt is for us */
5531/* */
5532/****************************************************************************/
5533static int
5534ips_isintr_copperhead(ips_ha_t * ha)
5535{
5536 uint8_t Isr;
5537
5538 METHOD_TRACE("ips_isintr_copperhead", 2);
5539
5540 Isr = inb(ha->io_addr + IPS_REG_HISR);
5541
5542 if (Isr == 0xFF)
5543 /* ?!?! Nothing really there */
5544 return (0);
5545
5546 if (Isr & IPS_BIT_SCE)
5547 return (1);
5548 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5549 /* status queue overflow or GHI */
5550 /* just clear the interrupt */
5551 outb(Isr, ha->io_addr + IPS_REG_HISR);
5552 }
5553
5554 return (0);
5555}
5556
5557/****************************************************************************/
5558/* */
5559/* Routine Name: ips_isintr_copperhead_memio */
5560/* */
5561/* Routine Description: */
5562/* */
5563/* Test to see if an interrupt is for us */
5564/* */
5565/****************************************************************************/
5566static int
5567ips_isintr_copperhead_memio(ips_ha_t * ha)
5568{
5569 uint8_t Isr;
5570
5571 METHOD_TRACE("ips_isintr_memio", 2);
5572
5573 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5574
5575 if (Isr == 0xFF)
5576 /* ?!?! Nothing really there */
5577 return (0);
5578
5579 if (Isr & IPS_BIT_SCE)
5580 return (1);
5581 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5582 /* status queue overflow or GHI */
5583 /* just clear the interrupt */
5584 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5585 }
5586
5587 return (0);
5588}
5589
5590/****************************************************************************/
5591/* */
5592/* Routine Name: ips_isintr_morpheus */
5593/* */
5594/* Routine Description: */
5595/* */
5596/* Test to see if an interrupt is for us */
5597/* */
5598/****************************************************************************/
5599static int
5600ips_isintr_morpheus(ips_ha_t * ha)
5601{
5602 uint32_t Isr;
5603
5604 METHOD_TRACE("ips_isintr_morpheus", 2);
5605
5606 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5607
5608 if (Isr & IPS_BIT_I2O_OPQI)
5609 return (1);
5610 else
5611 return (0);
5612}
5613
5614/****************************************************************************/
5615/* */
5616/* Routine Name: ips_wait */
5617/* */
5618/* Routine Description: */
5619/* */
5620/* Wait for a command to complete */
5621/* */
5622/****************************************************************************/
5623static int
5624ips_wait(ips_ha_t * ha, int time, int intr)
5625{
5626 int ret;
5627 int done;
5628
5629 METHOD_TRACE("ips_wait", 1);
5630
5631 ret = IPS_FAILURE;
5632 done = FALSE;
5633
5634 time *= IPS_ONE_SEC; /* convert seconds */
5635
5636 while ((time > 0) && (!done)) {
5637 if (intr == IPS_INTR_ON) {
5638 if (ha->waitflag == FALSE) {
5639 ret = IPS_SUCCESS;
5640 done = TRUE;
5641 break;
5642 }
5643 } else if (intr == IPS_INTR_IORL) {
5644 if (ha->waitflag == FALSE) {
5645 /*
5646 * controller generated an interrupt to
5647 * acknowledge completion of the command
5648 * and ips_intr() has serviced the interrupt.
5649 */
5650 ret = IPS_SUCCESS;
5651 done = TRUE;
5652 break;
5653 }
5654
5655 /*
5656 * NOTE: we already have the io_request_lock so
5657 * even if we get an interrupt it won't get serviced
5658 * until after we finish.
5659 */
5660
5661 (*ha->func.intr) (ha);
5662 }
5663
5664 /* This looks like a very evil loop, but it only does this during start-up */
5665 udelay(1000);
5666 time--;
5667 }
5668
5669 return (ret);
5670}
5671
5672/****************************************************************************/
5673/* */
5674/* Routine Name: ips_write_driver_status */
5675/* */
5676/* Routine Description: */
5677/* */
5678/* Write OS/Driver version to Page 5 of the nvram on the controller */
5679/* */
5680/****************************************************************************/
5681static int
5682ips_write_driver_status(ips_ha_t * ha, int intr)
5683{
5684 METHOD_TRACE("ips_write_driver_status", 1);
5685
5686 if (!ips_readwrite_page5(ha, FALSE, intr)) {
5687 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5688 "unable to read NVRAM page 5.\n");
5689
5690 return (0);
5691 }
5692
5693 /* check to make sure the page has a valid */
5694 /* signature */
5695 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) {
5696 DEBUG_VAR(1,
5697 "(%s%d) NVRAM page 5 has an invalid signature: %X.",
5698 ips_name, ha->host_num, ha->nvram->signature);
5699 ha->nvram->signature = IPS_NVRAM_P5_SIG;
5700 }
5701
5702 DEBUG_VAR(2,
5703 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.",
5704 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type),
5705 ha->nvram->adapter_slot, ha->nvram->bios_high[0],
5706 ha->nvram->bios_high[1], ha->nvram->bios_high[2],
5707 ha->nvram->bios_high[3], ha->nvram->bios_low[0],
5708 ha->nvram->bios_low[1], ha->nvram->bios_low[2],
5709 ha->nvram->bios_low[3]);
5710
5711 ips_get_bios_version(ha, intr);
5712
5713 /* change values (as needed) */
5714 ha->nvram->operating_system = IPS_OS_LINUX;
5715 ha->nvram->adapter_type = ha->ad_type;
5716 strncpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4);
5717 strncpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4);
5718 strncpy((char *) ha->nvram->bios_high, ha->bios_version, 4);
5719 strncpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4);
5720
5721 ha->nvram->versioning = 0; /* Indicate the Driver Does Not Support Versioning */
5722
5723 /* now update the page */
5724 if (!ips_readwrite_page5(ha, TRUE, intr)) {
5725 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5726 "unable to write NVRAM page 5.\n");
5727
5728 return (0);
5729 }
5730
5731 /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */
5732 ha->slot_num = ha->nvram->adapter_slot;
5733
5734 return (1);
5735}
5736
5737/****************************************************************************/
5738/* */
5739/* Routine Name: ips_read_adapter_status */
5740/* */
5741/* Routine Description: */
5742/* */
5743/* Do an Inquiry command to the adapter */
5744/* */
5745/****************************************************************************/
5746static int
5747ips_read_adapter_status(ips_ha_t * ha, int intr)
5748{
5749 ips_scb_t *scb;
5750 int ret;
5751
5752 METHOD_TRACE("ips_read_adapter_status", 1);
5753
5754 scb = &ha->scbs[ha->max_cmds - 1];
5755
5756 ips_init_scb(ha, scb);
5757
5758 scb->timeout = ips_cmd_timeout;
5759 scb->cdb[0] = IPS_CMD_ENQUIRY;
5760
5761 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
5762 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5763 scb->cmd.basic_io.sg_count = 0;
5764 scb->cmd.basic_io.lba = 0;
5765 scb->cmd.basic_io.sector_count = 0;
5766 scb->cmd.basic_io.log_drv = 0;
5767 scb->data_len = sizeof (*ha->enq);
5768 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
5769
5770 /* send command */
5771 if (((ret =
5772 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5773 || (ret == IPS_SUCCESS_IMM)
5774 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5775 return (0);
5776
5777 return (1);
5778}
5779
5780/****************************************************************************/
5781/* */
5782/* Routine Name: ips_read_subsystem_parameters */
5783/* */
5784/* Routine Description: */
5785/* */
5786/* Read subsystem parameters from the adapter */
5787/* */
5788/****************************************************************************/
5789static int
5790ips_read_subsystem_parameters(ips_ha_t * ha, int intr)
5791{
5792 ips_scb_t *scb;
5793 int ret;
5794
5795 METHOD_TRACE("ips_read_subsystem_parameters", 1);
5796
5797 scb = &ha->scbs[ha->max_cmds - 1];
5798
5799 ips_init_scb(ha, scb);
5800
5801 scb->timeout = ips_cmd_timeout;
5802 scb->cdb[0] = IPS_CMD_GET_SUBSYS;
5803
5804 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS;
5805 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5806 scb->cmd.basic_io.sg_count = 0;
5807 scb->cmd.basic_io.lba = 0;
5808 scb->cmd.basic_io.sector_count = 0;
5809 scb->cmd.basic_io.log_drv = 0;
5810 scb->data_len = sizeof (*ha->subsys);
5811 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5812
5813 /* send command */
5814 if (((ret =
5815 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5816 || (ret == IPS_SUCCESS_IMM)
5817 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5818 return (0);
5819
5820 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys));
5821 return (1);
5822}
5823
5824/****************************************************************************/
5825/* */
5826/* Routine Name: ips_read_config */
5827/* */
5828/* Routine Description: */
5829/* */
5830/* Read the configuration on the adapter */
5831/* */
5832/****************************************************************************/
5833static int
5834ips_read_config(ips_ha_t * ha, int intr)
5835{
5836 ips_scb_t *scb;
5837 int i;
5838 int ret;
5839
5840 METHOD_TRACE("ips_read_config", 1);
5841
5842 /* set defaults for initiator IDs */
5843 for (i = 0; i < 4; i++)
5844 ha->conf->init_id[i] = 7;
5845
5846 scb = &ha->scbs[ha->max_cmds - 1];
5847
5848 ips_init_scb(ha, scb);
5849
5850 scb->timeout = ips_cmd_timeout;
5851 scb->cdb[0] = IPS_CMD_READ_CONF;
5852
5853 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF;
5854 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5855 scb->data_len = sizeof (*ha->conf);
5856 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5857
5858 /* send command */
5859 if (((ret =
5860 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5861 || (ret == IPS_SUCCESS_IMM)
5862 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5863
5864 memset(ha->conf, 0, sizeof (IPS_CONF));
5865
5866 /* reset initiator IDs */
5867 for (i = 0; i < 4; i++)
5868 ha->conf->init_id[i] = 7;
5869
5870 /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */
5871 if ((scb->basic_status & IPS_GSC_STATUS_MASK) ==
5872 IPS_CMD_CMPLT_WERROR)
5873 return (1);
5874
5875 return (0);
5876 }
5877
5878 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
5879 return (1);
5880}
5881
5882/****************************************************************************/
5883/* */
5884/* Routine Name: ips_readwrite_page5 */
5885/* */
5886/* Routine Description: */
5887/* */
5888/* Read nvram page 5 from the adapter */
5889/* */
5890/****************************************************************************/
5891static int
5892ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
5893{
5894 ips_scb_t *scb;
5895 int ret;
5896
5897 METHOD_TRACE("ips_readwrite_page5", 1);
5898
5899 scb = &ha->scbs[ha->max_cmds - 1];
5900
5901 ips_init_scb(ha, scb);
5902
5903 scb->timeout = ips_cmd_timeout;
5904 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE;
5905
5906 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE;
5907 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb);
5908 scb->cmd.nvram.page = 5;
5909 scb->cmd.nvram.write = write;
5910 scb->cmd.nvram.reserved = 0;
5911 scb->cmd.nvram.reserved2 = 0;
5912 scb->data_len = sizeof (*ha->nvram);
5913 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
5914 if (write)
5915 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
5916
5917 /* issue the command */
5918 if (((ret =
5919 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5920 || (ret == IPS_SUCCESS_IMM)
5921 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5922
5923 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5));
5924
5925 return (0);
5926 }
5927 if (!write)
5928 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram));
5929 return (1);
5930}
5931
5932/****************************************************************************/
5933/* */
5934/* Routine Name: ips_clear_adapter */
5935/* */
5936/* Routine Description: */
5937/* */
5938/* Clear the stripe lock tables */
5939/* */
5940/****************************************************************************/
5941static int
5942ips_clear_adapter(ips_ha_t * ha, int intr)
5943{
5944 ips_scb_t *scb;
5945 int ret;
5946
5947 METHOD_TRACE("ips_clear_adapter", 1);
5948
5949 scb = &ha->scbs[ha->max_cmds - 1];
5950
5951 ips_init_scb(ha, scb);
5952
5953 scb->timeout = ips_reset_timeout;
5954 scb->cdb[0] = IPS_CMD_CONFIG_SYNC;
5955
5956 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC;
5957 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb);
5958 scb->cmd.config_sync.channel = 0;
5959 scb->cmd.config_sync.source_target = IPS_POCL;
5960 scb->cmd.config_sync.reserved = 0;
5961 scb->cmd.config_sync.reserved2 = 0;
5962 scb->cmd.config_sync.reserved3 = 0;
5963
5964 /* issue command */
5965 if (((ret =
5966 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE)
5967 || (ret == IPS_SUCCESS_IMM)
5968 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5969 return (0);
5970
5971 /* send unlock stripe command */
5972 ips_init_scb(ha, scb);
5973
5974 scb->cdb[0] = IPS_CMD_ERROR_TABLE;
5975 scb->timeout = ips_reset_timeout;
5976
5977 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE;
5978 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb);
5979 scb->cmd.unlock_stripe.log_drv = 0;
5980 scb->cmd.unlock_stripe.control = IPS_CSL;
5981 scb->cmd.unlock_stripe.reserved = 0;
5982 scb->cmd.unlock_stripe.reserved2 = 0;
5983 scb->cmd.unlock_stripe.reserved3 = 0;
5984
5985 /* issue command */
5986 if (((ret =
5987 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5988 || (ret == IPS_SUCCESS_IMM)
5989 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5990 return (0);
5991
5992 return (1);
5993}
5994
5995/****************************************************************************/
5996/* */
5997/* Routine Name: ips_ffdc_reset */
5998/* */
5999/* Routine Description: */
6000/* */
6001/* FFDC: write reset info */
6002/* */
6003/****************************************************************************/
6004static void
6005ips_ffdc_reset(ips_ha_t * ha, int intr)
6006{
6007 ips_scb_t *scb;
6008
6009 METHOD_TRACE("ips_ffdc_reset", 1);
6010
6011 scb = &ha->scbs[ha->max_cmds - 1];
6012
6013 ips_init_scb(ha, scb);
6014
6015 scb->timeout = ips_cmd_timeout;
6016 scb->cdb[0] = IPS_CMD_FFDC;
6017 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
6018 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
6019 scb->cmd.ffdc.reset_count = ha->reset_count;
6020 scb->cmd.ffdc.reset_type = 0x80;
6021
6022 /* convert time to what the card wants */
6023 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
6024
6025 /* issue command */
6026 ips_send_wait(ha, scb, ips_cmd_timeout, intr);
6027}
6028
6029/****************************************************************************/
6030/* */
6031/* Routine Name: ips_ffdc_time */
6032/* */
6033/* Routine Description: */
6034/* */
6035/* FFDC: write time info */
6036/* */
6037/****************************************************************************/
6038static void
6039ips_ffdc_time(ips_ha_t * ha)
6040{
6041 ips_scb_t *scb;
6042
6043 METHOD_TRACE("ips_ffdc_time", 1);
6044
6045 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num);
6046
6047 scb = &ha->scbs[ha->max_cmds - 1];
6048
6049 ips_init_scb(ha, scb);
6050
6051 scb->timeout = ips_cmd_timeout;
6052 scb->cdb[0] = IPS_CMD_FFDC;
6053 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
6054 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
6055 scb->cmd.ffdc.reset_count = 0;
6056 scb->cmd.ffdc.reset_type = 0;
6057
6058 /* convert time to what the card wants */
6059 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
6060
6061 /* issue command */
6062 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC);
6063}
6064
6065/****************************************************************************/
6066/* */
6067/* Routine Name: ips_fix_ffdc_time */
6068/* */
6069/* Routine Description: */
6070/* Adjust time_t to what the card wants */
6071/* */
6072/****************************************************************************/
6073static void
6074ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time_t current_time)
6075{
6076 long days;
6077 long rem;
6078 int i;
6079 int year;
6080 int yleap;
6081 int year_lengths[2] = { IPS_DAYS_NORMAL_YEAR, IPS_DAYS_LEAP_YEAR };
6082 int month_lengths[12][2] = { {31, 31},
6083 {28, 29},
6084 {31, 31},
6085 {30, 30},
6086 {31, 31},
6087 {30, 30},
6088 {31, 31},
6089 {31, 31},
6090 {30, 30},
6091 {31, 31},
6092 {30, 30},
6093 {31, 31}
6094 };
6095
6096 METHOD_TRACE("ips_fix_ffdc_time", 1);
6097
6098 days = current_time / IPS_SECS_DAY;
6099 rem = current_time % IPS_SECS_DAY;
6100
6101 scb->cmd.ffdc.hour = (rem / IPS_SECS_HOUR);
6102 rem = rem % IPS_SECS_HOUR;
6103 scb->cmd.ffdc.minute = (rem / IPS_SECS_MIN);
6104 scb->cmd.ffdc.second = (rem % IPS_SECS_MIN);
6105
6106 year = IPS_EPOCH_YEAR;
6107 while (days < 0 || days >= year_lengths[yleap = IPS_IS_LEAP_YEAR(year)]) {
6108 int newy;
6109
6110 newy = year + (days / IPS_DAYS_NORMAL_YEAR);
6111 if (days < 0)
6112 --newy;
6113 days -= (newy - year) * IPS_DAYS_NORMAL_YEAR +
6114 IPS_NUM_LEAP_YEARS_THROUGH(newy - 1) -
6115 IPS_NUM_LEAP_YEARS_THROUGH(year - 1);
6116 year = newy;
6117 }
6118
6119 scb->cmd.ffdc.yearH = year / 100;
6120 scb->cmd.ffdc.yearL = year % 100;
6121
6122 for (i = 0; days >= month_lengths[i][yleap]; ++i)
6123 days -= month_lengths[i][yleap];
6124
6125 scb->cmd.ffdc.month = i + 1;
6126 scb->cmd.ffdc.day = days + 1;
6127}
6128
6129/****************************************************************************
6130 * BIOS Flash Routines *
6131 ****************************************************************************/
6132
6133/****************************************************************************/
6134/* */
6135/* Routine Name: ips_erase_bios */
6136/* */
6137/* Routine Description: */
6138/* Erase the BIOS on the adapter */
6139/* */
6140/****************************************************************************/
6141static int
6142ips_erase_bios(ips_ha_t * ha)
6143{
6144 int timeout;
6145 uint8_t status = 0;
6146
6147 METHOD_TRACE("ips_erase_bios", 1);
6148
6149 status = 0;
6150
6151 /* Clear the status register */
6152 outl(0, ha->io_addr + IPS_REG_FLAP);
6153 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6154 udelay(25); /* 25 us */
6155
6156 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6157 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6158 udelay(25); /* 25 us */
6159
6160 /* Erase Setup */
6161 outb(0x20, ha->io_addr + IPS_REG_FLDP);
6162 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6163 udelay(25); /* 25 us */
6164
6165 /* Erase Confirm */
6166 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
6167 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6168 udelay(25); /* 25 us */
6169
6170 /* Erase Status */
6171 outb(0x70, ha->io_addr + IPS_REG_FLDP);
6172 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6173 udelay(25); /* 25 us */
6174
6175 timeout = 80000; /* 80 seconds */
6176
6177 while (timeout > 0) {
6178 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6179 outl(0, ha->io_addr + IPS_REG_FLAP);
6180 udelay(25); /* 25 us */
6181 }
6182
6183 status = inb(ha->io_addr + IPS_REG_FLDP);
6184
6185 if (status & 0x80)
6186 break;
6187
6188 MDELAY(1);
6189 timeout--;
6190 }
6191
6192 /* check for timeout */
6193 if (timeout <= 0) {
6194 /* timeout */
6195
6196 /* try to suspend the erase */
6197 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
6198 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6199 udelay(25); /* 25 us */
6200
6201 /* wait for 10 seconds */
6202 timeout = 10000;
6203 while (timeout > 0) {
6204 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6205 outl(0, ha->io_addr + IPS_REG_FLAP);
6206 udelay(25); /* 25 us */
6207 }
6208
6209 status = inb(ha->io_addr + IPS_REG_FLDP);
6210
6211 if (status & 0xC0)
6212 break;
6213
6214 MDELAY(1);
6215 timeout--;
6216 }
6217
6218 return (1);
6219 }
6220
6221 /* check for valid VPP */
6222 if (status & 0x08)
6223 /* VPP failure */
6224 return (1);
6225
6226 /* check for successful flash */
6227 if (status & 0x30)
6228 /* sequence error */
6229 return (1);
6230
6231 /* Otherwise, we were successful */
6232 /* clear status */
6233 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6234 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6235 udelay(25); /* 25 us */
6236
6237 /* enable reads */
6238 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6239 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6240 udelay(25); /* 25 us */
6241
6242 return (0);
6243}
6244
6245/****************************************************************************/
6246/* */
6247/* Routine Name: ips_erase_bios_memio */
6248/* */
6249/* Routine Description: */
6250/* Erase the BIOS on the adapter */
6251/* */
6252/****************************************************************************/
6253static int
6254ips_erase_bios_memio(ips_ha_t * ha)
6255{
6256 int timeout;
6257 uint8_t status;
6258
6259 METHOD_TRACE("ips_erase_bios_memio", 1);
6260
6261 status = 0;
6262
6263 /* Clear the status register */
6264 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6265 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6266 udelay(25); /* 25 us */
6267
6268 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6269 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6270 udelay(25); /* 25 us */
6271
6272 /* Erase Setup */
6273 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6274 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6275 udelay(25); /* 25 us */
6276
6277 /* Erase Confirm */
6278 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6279 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6280 udelay(25); /* 25 us */
6281
6282 /* Erase Status */
6283 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6284 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6285 udelay(25); /* 25 us */
6286
6287 timeout = 80000; /* 80 seconds */
6288
6289 while (timeout > 0) {
6290 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6291 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6292 udelay(25); /* 25 us */
6293 }
6294
6295 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6296
6297 if (status & 0x80)
6298 break;
6299
6300 MDELAY(1);
6301 timeout--;
6302 }
6303
6304 /* check for timeout */
6305 if (timeout <= 0) {
6306 /* timeout */
6307
6308 /* try to suspend the erase */
6309 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6310 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6311 udelay(25); /* 25 us */
6312
6313 /* wait for 10 seconds */
6314 timeout = 10000;
6315 while (timeout > 0) {
6316 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6317 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6318 udelay(25); /* 25 us */
6319 }
6320
6321 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6322
6323 if (status & 0xC0)
6324 break;
6325
6326 MDELAY(1);
6327 timeout--;
6328 }
6329
6330 return (1);
6331 }
6332
6333 /* check for valid VPP */
6334 if (status & 0x08)
6335 /* VPP failure */
6336 return (1);
6337
6338 /* check for successful flash */
6339 if (status & 0x30)
6340 /* sequence error */
6341 return (1);
6342
6343 /* Otherwise, we were successful */
6344 /* clear status */
6345 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6346 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6347 udelay(25); /* 25 us */
6348
6349 /* enable reads */
6350 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6351 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6352 udelay(25); /* 25 us */
6353
6354 return (0);
6355}
6356
6357/****************************************************************************/
6358/* */
6359/* Routine Name: ips_program_bios */
6360/* */
6361/* Routine Description: */
6362/* Program the BIOS on the adapter */
6363/* */
6364/****************************************************************************/
6365static int
6366ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6367 uint32_t offset)
6368{
6369 int i;
6370 int timeout;
6371 uint8_t status = 0;
6372
6373 METHOD_TRACE("ips_program_bios", 1);
6374
6375 status = 0;
6376
6377 for (i = 0; i < buffersize; i++) {
6378 /* write a byte */
6379 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6380 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6381 udelay(25); /* 25 us */
6382
6383 outb(0x40, ha->io_addr + IPS_REG_FLDP);
6384 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6385 udelay(25); /* 25 us */
6386
6387 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
6388 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6389 udelay(25); /* 25 us */
6390
6391 /* wait up to one second */
6392 timeout = 1000;
6393 while (timeout > 0) {
6394 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6395 outl(0, ha->io_addr + IPS_REG_FLAP);
6396 udelay(25); /* 25 us */
6397 }
6398
6399 status = inb(ha->io_addr + IPS_REG_FLDP);
6400
6401 if (status & 0x80)
6402 break;
6403
6404 MDELAY(1);
6405 timeout--;
6406 }
6407
6408 if (timeout == 0) {
6409 /* timeout error */
6410 outl(0, ha->io_addr + IPS_REG_FLAP);
6411 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6412 udelay(25); /* 25 us */
6413
6414 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6415 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6416 udelay(25); /* 25 us */
6417
6418 return (1);
6419 }
6420
6421 /* check the status */
6422 if (status & 0x18) {
6423 /* programming error */
6424 outl(0, ha->io_addr + IPS_REG_FLAP);
6425 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6426 udelay(25); /* 25 us */
6427
6428 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6429 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6430 udelay(25); /* 25 us */
6431
6432 return (1);
6433 }
6434 } /* end for */
6435
6436 /* Enable reading */
6437 outl(0, ha->io_addr + IPS_REG_FLAP);
6438 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6439 udelay(25); /* 25 us */
6440
6441 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6442 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6443 udelay(25); /* 25 us */
6444
6445 return (0);
6446}
6447
6448/****************************************************************************/
6449/* */
6450/* Routine Name: ips_program_bios_memio */
6451/* */
6452/* Routine Description: */
6453/* Program the BIOS on the adapter */
6454/* */
6455/****************************************************************************/
6456static int
6457ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6458 uint32_t offset)
6459{
6460 int i;
6461 int timeout;
6462 uint8_t status = 0;
6463
6464 METHOD_TRACE("ips_program_bios_memio", 1);
6465
6466 status = 0;
6467
6468 for (i = 0; i < buffersize; i++) {
6469 /* write a byte */
6470 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6471 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6472 udelay(25); /* 25 us */
6473
6474 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6475 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6476 udelay(25); /* 25 us */
6477
6478 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6479 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6480 udelay(25); /* 25 us */
6481
6482 /* wait up to one second */
6483 timeout = 1000;
6484 while (timeout > 0) {
6485 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6486 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6487 udelay(25); /* 25 us */
6488 }
6489
6490 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6491
6492 if (status & 0x80)
6493 break;
6494
6495 MDELAY(1);
6496 timeout--;
6497 }
6498
6499 if (timeout == 0) {
6500 /* timeout error */
6501 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6502 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6503 udelay(25); /* 25 us */
6504
6505 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6506 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6507 udelay(25); /* 25 us */
6508
6509 return (1);
6510 }
6511
6512 /* check the status */
6513 if (status & 0x18) {
6514 /* programming error */
6515 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6516 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6517 udelay(25); /* 25 us */
6518
6519 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6520 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6521 udelay(25); /* 25 us */
6522
6523 return (1);
6524 }
6525 } /* end for */
6526
6527 /* Enable reading */
6528 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6529 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6530 udelay(25); /* 25 us */
6531
6532 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6533 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6534 udelay(25); /* 25 us */
6535
6536 return (0);
6537}
6538
6539/****************************************************************************/
6540/* */
6541/* Routine Name: ips_verify_bios */
6542/* */
6543/* Routine Description: */
6544/* Verify the BIOS on the adapter */
6545/* */
6546/****************************************************************************/
6547static int
6548ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6549 uint32_t offset)
6550{
6551 uint8_t checksum;
6552 int i;
6553
6554 METHOD_TRACE("ips_verify_bios", 1);
6555
6556 /* test 1st byte */
6557 outl(0, ha->io_addr + IPS_REG_FLAP);
6558 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6559 udelay(25); /* 25 us */
6560
6561 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6562 return (1);
6563
6564 outl(1, ha->io_addr + IPS_REG_FLAP);
6565 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6566 udelay(25); /* 25 us */
6567 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6568 return (1);
6569
6570 checksum = 0xff;
6571 for (i = 2; i < buffersize; i++) {
6572
6573 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6574 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6575 udelay(25); /* 25 us */
6576
6577 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
6578 }
6579
6580 if (checksum != 0)
6581 /* failure */
6582 return (1);
6583 else
6584 /* success */
6585 return (0);
6586}
6587
6588/****************************************************************************/
6589/* */
6590/* Routine Name: ips_verify_bios_memio */
6591/* */
6592/* Routine Description: */
6593/* Verify the BIOS on the adapter */
6594/* */
6595/****************************************************************************/
6596static int
6597ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6598 uint32_t offset)
6599{
6600 uint8_t checksum;
6601 int i;
6602
6603 METHOD_TRACE("ips_verify_bios_memio", 1);
6604
6605 /* test 1st byte */
6606 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6607 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6608 udelay(25); /* 25 us */
6609
6610 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6611 return (1);
6612
6613 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6614 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6615 udelay(25); /* 25 us */
6616 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6617 return (1);
6618
6619 checksum = 0xff;
6620 for (i = 2; i < buffersize; i++) {
6621
6622 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6623 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6624 udelay(25); /* 25 us */
6625
6626 checksum =
6627 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6628 }
6629
6630 if (checksum != 0)
6631 /* failure */
6632 return (1);
6633 else
6634 /* success */
6635 return (0);
6636}
6637
6638/****************************************************************************/
6639/* */
6640/* Routine Name: ips_abort_init */
6641/* */
6642/* Routine Description: */
6643/* cleanup routine for a failed adapter initialization */
6644/****************************************************************************/
6645static int
6646ips_abort_init(ips_ha_t * ha, int index)
6647{
6648 ha->active = 0;
6649 ips_free(ha);
6650 ips_ha[index] = NULL;
6651 ips_sh[index] = NULL;
6652 return -1;
6653}
6654
6655/****************************************************************************/
6656/* */
6657/* Routine Name: ips_shift_controllers */
6658/* */
6659/* Routine Description: */
6660/* helper function for ordering adapters */
6661/****************************************************************************/
6662static void
6663ips_shift_controllers(int lowindex, int highindex)
6664{
6665 ips_ha_t *ha_sav = ips_ha[highindex];
6666 struct Scsi_Host *sh_sav = ips_sh[highindex];
6667 int i;
6668
6669 for (i = highindex; i > lowindex; i--) {
6670 ips_ha[i] = ips_ha[i - 1];
6671 ips_sh[i] = ips_sh[i - 1];
6672 ips_ha[i]->host_num = i;
6673 }
6674 ha_sav->host_num = lowindex;
6675 ips_ha[lowindex] = ha_sav;
6676 ips_sh[lowindex] = sh_sav;
6677}
6678
6679/****************************************************************************/
6680/* */
6681/* Routine Name: ips_order_controllers */
6682/* */
6683/* Routine Description: */
6684/* place controllers is the "proper" boot order */
6685/****************************************************************************/
6686static void
6687ips_order_controllers(void)
6688{
6689 int i, j, tmp, position = 0;
6690 IPS_NVRAM_P5 *nvram;
6691 if (!ips_ha[0])
6692 return;
6693 nvram = ips_ha[0]->nvram;
6694
6695 if (nvram->adapter_order[0]) {
6696 for (i = 1; i <= nvram->adapter_order[0]; i++) {
6697 for (j = position; j < ips_num_controllers; j++) {
6698 switch (ips_ha[j]->ad_type) {
6699 case IPS_ADTYPE_SERVERAID6M:
6700 case IPS_ADTYPE_SERVERAID7M:
6701 if (nvram->adapter_order[i] == 'M') {
6702 ips_shift_controllers(position,
6703 j);
6704 position++;
6705 }
6706 break;
6707 case IPS_ADTYPE_SERVERAID4L:
6708 case IPS_ADTYPE_SERVERAID4M:
6709 case IPS_ADTYPE_SERVERAID4MX:
6710 case IPS_ADTYPE_SERVERAID4LX:
6711 if (nvram->adapter_order[i] == 'N') {
6712 ips_shift_controllers(position,
6713 j);
6714 position++;
6715 }
6716 break;
6717 case IPS_ADTYPE_SERVERAID6I:
6718 case IPS_ADTYPE_SERVERAID5I2:
6719 case IPS_ADTYPE_SERVERAID5I1:
6720 case IPS_ADTYPE_SERVERAID7k:
6721 if (nvram->adapter_order[i] == 'S') {
6722 ips_shift_controllers(position,
6723 j);
6724 position++;
6725 }
6726 break;
6727 case IPS_ADTYPE_SERVERAID:
6728 case IPS_ADTYPE_SERVERAID2:
6729 case IPS_ADTYPE_NAVAJO:
6730 case IPS_ADTYPE_KIOWA:
6731 case IPS_ADTYPE_SERVERAID3L:
6732 case IPS_ADTYPE_SERVERAID3:
6733 case IPS_ADTYPE_SERVERAID4H:
6734 if (nvram->adapter_order[i] == 'A') {
6735 ips_shift_controllers(position,
6736 j);
6737 position++;
6738 }
6739 break;
6740 default:
6741 break;
6742 }
6743 }
6744 }
6745 /* if adapter_order[0], then ordering is complete */
6746 return;
6747 }
6748 /* old bios, use older ordering */
6749 tmp = 0;
6750 for (i = position; i < ips_num_controllers; i++) {
6751 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 ||
6752 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) {
6753 ips_shift_controllers(position, i);
6754 position++;
6755 tmp = 1;
6756 }
6757 }
6758 /* if there were no 5I cards, then don't do any extra ordering */
6759 if (!tmp)
6760 return;
6761 for (i = position; i < ips_num_controllers; i++) {
6762 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L ||
6763 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M ||
6764 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX ||
6765 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) {
6766 ips_shift_controllers(position, i);
6767 position++;
6768 }
6769 }
6770
6771 return;
6772}
6773
6774/****************************************************************************/
6775/* */
6776/* Routine Name: ips_register_scsi */
6777/* */
6778/* Routine Description: */
6779/* perform any registration and setup with the scsi layer */
6780/****************************************************************************/
6781static int
6782ips_register_scsi(int index)
6783{
6784 struct Scsi_Host *sh;
6785 ips_ha_t *ha, *oldha = ips_ha[index];
6786 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t));
6787 if (!sh) {
6788 IPS_PRINTK(KERN_WARNING, oldha->pcidev,
6789 "Unable to register controller with SCSI subsystem\n");
6790 return -1;
6791 }
6792 ha = IPS_HA(sh);
6793 memcpy(ha, oldha, sizeof (ips_ha_t));
6794 free_irq(oldha->pcidev->irq, oldha);
6795 /* Install the interrupt handler with the new ha */
6796 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
6797 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6798 "Unable to install interrupt handler\n");
6799 goto err_out_sh;
6800 }
6801
6802 kfree(oldha);
6803
6804 /* Store away needed values for later use */
6805 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
6806 sh->sg_tablesize = sh->hostt->sg_tablesize;
6807 sh->can_queue = sh->hostt->can_queue;
6808 sh->cmd_per_lun = sh->hostt->cmd_per_lun;
6809 sh->use_clustering = sh->hostt->use_clustering;
6810 sh->max_sectors = 128;
6811
6812 sh->max_id = ha->ntargets;
6813 sh->max_lun = ha->nlun;
6814 sh->max_channel = ha->nbus - 1;
6815 sh->can_queue = ha->max_cmds - 1;
6816
6817 if (scsi_add_host(sh, &ha->pcidev->dev))
6818 goto err_out;
6819
6820 ips_sh[index] = sh;
6821 ips_ha[index] = ha;
6822
6823 scsi_scan_host(sh);
6824
6825 return 0;
6826
6827err_out:
6828 free_irq(ha->pcidev->irq, ha);
6829err_out_sh:
6830 scsi_host_put(sh);
6831 return -1;
6832}
6833
6834/*---------------------------------------------------------------------------*/
6835/* Routine Name: ips_remove_device */
6836/* */
6837/* Routine Description: */
6838/* Remove one Adapter ( Hot Plugging ) */
6839/*---------------------------------------------------------------------------*/
6840static void __devexit
6841ips_remove_device(struct pci_dev *pci_dev)
6842{
6843 struct Scsi_Host *sh = pci_get_drvdata(pci_dev);
6844
6845 pci_set_drvdata(pci_dev, NULL);
6846
6847 ips_release(sh);
6848
6849 pci_release_regions(pci_dev);
6850 pci_disable_device(pci_dev);
6851}
6852
6853/****************************************************************************/
6854/* */
6855/* Routine Name: ips_module_init */
6856/* */
6857/* Routine Description: */
6858/* function called on module load */
6859/****************************************************************************/
6860static int __init
6861ips_module_init(void)
6862{
6863 if (pci_register_driver(&ips_pci_driver) < 0)
6864 return -ENODEV;
6865 ips_driver_template.module = THIS_MODULE;
6866 ips_order_controllers();
6867 if (!ips_detect(&ips_driver_template)) {
6868 pci_unregister_driver(&ips_pci_driver);
6869 return -ENODEV;
6870 }
6871 register_reboot_notifier(&ips_notifier);
6872 return 0;
6873}
6874
6875/****************************************************************************/
6876/* */
6877/* Routine Name: ips_module_exit */
6878/* */
6879/* Routine Description: */
6880/* function called on module unload */
6881/****************************************************************************/
6882static void __exit
6883ips_module_exit(void)
6884{
6885 pci_unregister_driver(&ips_pci_driver);
6886 unregister_reboot_notifier(&ips_notifier);
6887}
6888
6889module_init(ips_module_init);
6890module_exit(ips_module_exit);
6891
6892/*---------------------------------------------------------------------------*/
6893/* Routine Name: ips_insert_device */
6894/* */
6895/* Routine Description: */
6896/* Add One Adapter ( Hot Plug ) */
6897/* */
6898/* Return Value: */
6899/* 0 if Successful, else non-zero */
6900/*---------------------------------------------------------------------------*/
6901static int __devinit
6902ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent)
6903{
6904 int index = -1;
6905 int rc;
6906
6907 METHOD_TRACE("ips_insert_device", 1);
6908 rc = pci_enable_device(pci_dev);
6909 if (rc)
6910 return rc;
6911
6912 rc = pci_request_regions(pci_dev, "ips");
6913 if (rc)
6914 goto err_out;
6915
6916 rc = ips_init_phase1(pci_dev, &index);
6917 if (rc == SUCCESS)
6918 rc = ips_init_phase2(index);
6919
6920 if (ips_hotplug)
6921 if (ips_register_scsi(index)) {
6922 ips_free(ips_ha[index]);
6923 rc = -1;
6924 }
6925
6926 if (rc == SUCCESS)
6927 ips_num_controllers++;
6928
6929 ips_next_controller = ips_num_controllers;
6930
6931 if (rc < 0) {
6932 rc = -ENODEV;
6933 goto err_out_regions;
6934 }
6935
6936 pci_set_drvdata(pci_dev, ips_sh[index]);
6937 return 0;
6938
6939err_out_regions:
6940 pci_release_regions(pci_dev);
6941err_out:
6942 pci_disable_device(pci_dev);
6943 return rc;
6944}
6945
6946/*---------------------------------------------------------------------------*/
6947/* Routine Name: ips_init_phase1 */
6948/* */
6949/* Routine Description: */
6950/* Adapter Initialization */
6951/* */
6952/* Return Value: */
6953/* 0 if Successful, else non-zero */
6954/*---------------------------------------------------------------------------*/
6955static int
6956ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
6957{
6958 ips_ha_t *ha;
6959 uint32_t io_addr;
6960 uint32_t mem_addr;
6961 uint32_t io_len;
6962 uint32_t mem_len;
6963 uint8_t bus;
6964 uint8_t func;
6965 int j;
6966 int index;
6967 dma_addr_t dma_address;
6968 char __iomem *ioremap_ptr;
6969 char __iomem *mem_ptr;
6970 uint32_t IsDead;
6971
6972 METHOD_TRACE("ips_init_phase1", 1);
6973 index = IPS_MAX_ADAPTERS;
6974 for (j = 0; j < IPS_MAX_ADAPTERS; j++) {
6975 if (ips_ha[j] == NULL) {
6976 index = j;
6977 break;
6978 }
6979 }
6980
6981 if (index >= IPS_MAX_ADAPTERS)
6982 return -1;
6983
6984 /* stuff that we get in dev */
6985 bus = pci_dev->bus->number;
6986 func = pci_dev->devfn;
6987
6988 /* Init MEM/IO addresses to 0 */
6989 mem_addr = 0;
6990 io_addr = 0;
6991 mem_len = 0;
6992 io_len = 0;
6993
6994 for (j = 0; j < 2; j++) {
6995 if (!pci_resource_start(pci_dev, j))
6996 break;
6997
6998 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) {
6999 io_addr = pci_resource_start(pci_dev, j);
7000 io_len = pci_resource_len(pci_dev, j);
7001 } else {
7002 mem_addr = pci_resource_start(pci_dev, j);
7003 mem_len = pci_resource_len(pci_dev, j);
7004 }
7005 }
7006
7007 /* setup memory mapped area (if applicable) */
7008 if (mem_addr) {
7009 uint32_t base;
7010 uint32_t offs;
7011
7012 base = mem_addr & PAGE_MASK;
7013 offs = mem_addr - base;
7014 ioremap_ptr = ioremap(base, PAGE_SIZE);
7015 if (!ioremap_ptr)
7016 return -1;
7017 mem_ptr = ioremap_ptr + offs;
7018 } else {
7019 ioremap_ptr = NULL;
7020 mem_ptr = NULL;
7021 }
7022
7023 /* found a controller */
7024 ha = kzalloc(sizeof (ips_ha_t), GFP_KERNEL);
7025 if (ha == NULL) {
7026 IPS_PRINTK(KERN_WARNING, pci_dev,
7027 "Unable to allocate temporary ha struct\n");
7028 return -1;
7029 }
7030
7031 ips_sh[index] = NULL;
7032 ips_ha[index] = ha;
7033 ha->active = 1;
7034
7035 /* Store info in HA structure */
7036 ha->io_addr = io_addr;
7037 ha->io_len = io_len;
7038 ha->mem_addr = mem_addr;
7039 ha->mem_len = mem_len;
7040 ha->mem_ptr = mem_ptr;
7041 ha->ioremap_ptr = ioremap_ptr;
7042 ha->host_num = (uint32_t) index;
7043 ha->slot_num = PCI_SLOT(pci_dev->devfn);
7044 ha->pcidev = pci_dev;
7045
7046 /*
7047 * Set the pci_dev's dma_mask. Not all adapters support 64bit
7048 * addressing so don't enable it if the adapter can't support
7049 * it! Also, don't use 64bit addressing if dma addresses
7050 * are guaranteed to be < 4G.
7051 */
7052 if (IPS_ENABLE_DMA64 && IPS_HAS_ENH_SGLIST(ha) &&
7053 !pci_set_dma_mask(ha->pcidev, DMA_BIT_MASK(64))) {
7054 (ha)->flags |= IPS_HA_ENH_SG;
7055 } else {
7056 if (pci_set_dma_mask(ha->pcidev, DMA_BIT_MASK(32)) != 0) {
7057 printk(KERN_WARNING "Unable to set DMA Mask\n");
7058 return ips_abort_init(ha, index);
7059 }
7060 }
7061 if(ips_cd_boot && !ips_FlashData){
7062 ips_FlashData = pci_alloc_consistent(pci_dev, PAGE_SIZE << 7,
7063 &ips_flashbusaddr);
7064 }
7065
7066 ha->enq = pci_alloc_consistent(pci_dev, sizeof (IPS_ENQ),
7067 &ha->enq_busaddr);
7068 if (!ha->enq) {
7069 IPS_PRINTK(KERN_WARNING, pci_dev,
7070 "Unable to allocate host inquiry structure\n");
7071 return ips_abort_init(ha, index);
7072 }
7073
7074 ha->adapt = pci_alloc_consistent(pci_dev, sizeof (IPS_ADAPTER) +
7075 sizeof (IPS_IO_CMD), &dma_address);
7076 if (!ha->adapt) {
7077 IPS_PRINTK(KERN_WARNING, pci_dev,
7078 "Unable to allocate host adapt & dummy structures\n");
7079 return ips_abort_init(ha, index);
7080 }
7081 ha->adapt->hw_status_start = dma_address;
7082 ha->dummy = (void *) (ha->adapt + 1);
7083
7084
7085
7086 ha->logical_drive_info = pci_alloc_consistent(pci_dev, sizeof (IPS_LD_INFO), &dma_address);
7087 if (!ha->logical_drive_info) {
7088 IPS_PRINTK(KERN_WARNING, pci_dev,
7089 "Unable to allocate logical drive info structure\n");
7090 return ips_abort_init(ha, index);
7091 }
7092 ha->logical_drive_info_dma_addr = dma_address;
7093
7094
7095 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL);
7096
7097 if (!ha->conf) {
7098 IPS_PRINTK(KERN_WARNING, pci_dev,
7099 "Unable to allocate host conf structure\n");
7100 return ips_abort_init(ha, index);
7101 }
7102
7103 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL);
7104
7105 if (!ha->nvram) {
7106 IPS_PRINTK(KERN_WARNING, pci_dev,
7107 "Unable to allocate host NVRAM structure\n");
7108 return ips_abort_init(ha, index);
7109 }
7110
7111 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL);
7112
7113 if (!ha->subsys) {
7114 IPS_PRINTK(KERN_WARNING, pci_dev,
7115 "Unable to allocate host subsystem structure\n");
7116 return ips_abort_init(ha, index);
7117 }
7118
7119 /* the ioctl buffer is now used during adapter initialization, so its
7120 * successful allocation is now required */
7121 if (ips_ioctlsize < PAGE_SIZE)
7122 ips_ioctlsize = PAGE_SIZE;
7123
7124 ha->ioctl_data = pci_alloc_consistent(pci_dev, ips_ioctlsize,
7125 &ha->ioctl_busaddr);
7126 ha->ioctl_len = ips_ioctlsize;
7127 if (!ha->ioctl_data) {
7128 IPS_PRINTK(KERN_WARNING, pci_dev,
7129 "Unable to allocate IOCTL data\n");
7130 return ips_abort_init(ha, index);
7131 }
7132
7133 /*
7134 * Setup Functions
7135 */
7136 ips_setup_funclist(ha);
7137
7138 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) {
7139 /* If Morpheus appears dead, reset it */
7140 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
7141 if (IsDead == 0xDEADBEEF) {
7142 ips_reset_morpheus(ha);
7143 }
7144 }
7145
7146 /*
7147 * Initialize the card if it isn't already
7148 */
7149
7150 if (!(*ha->func.isinit) (ha)) {
7151 if (!(*ha->func.init) (ha)) {
7152 /*
7153 * Initialization failed
7154 */
7155 IPS_PRINTK(KERN_WARNING, pci_dev,
7156 "Unable to initialize controller\n");
7157 return ips_abort_init(ha, index);
7158 }
7159 }
7160
7161 *indexPtr = index;
7162 return SUCCESS;
7163}
7164
7165/*---------------------------------------------------------------------------*/
7166/* Routine Name: ips_init_phase2 */
7167/* */
7168/* Routine Description: */
7169/* Adapter Initialization Phase 2 */
7170/* */
7171/* Return Value: */
7172/* 0 if Successful, else non-zero */
7173/*---------------------------------------------------------------------------*/
7174static int
7175ips_init_phase2(int index)
7176{
7177 ips_ha_t *ha;
7178
7179 ha = ips_ha[index];
7180
7181 METHOD_TRACE("ips_init_phase2", 1);
7182 if (!ha->active) {
7183 ips_ha[index] = NULL;
7184 return -1;
7185 }
7186
7187 /* Install the interrupt handler */
7188 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
7189 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7190 "Unable to install interrupt handler\n");
7191 return ips_abort_init(ha, index);
7192 }
7193
7194 /*
7195 * Allocate a temporary SCB for initialization
7196 */
7197 ha->max_cmds = 1;
7198 if (!ips_allocatescbs(ha)) {
7199 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7200 "Unable to allocate a CCB\n");
7201 free_irq(ha->pcidev->irq, ha);
7202 return ips_abort_init(ha, index);
7203 }
7204
7205 if (!ips_hainit(ha)) {
7206 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7207 "Unable to initialize controller\n");
7208 free_irq(ha->pcidev->irq, ha);
7209 return ips_abort_init(ha, index);
7210 }
7211 /* Free the temporary SCB */
7212 ips_deallocatescbs(ha, 1);
7213
7214 /* allocate CCBs */
7215 if (!ips_allocatescbs(ha)) {
7216 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7217 "Unable to allocate CCBs\n");
7218 free_irq(ha->pcidev->irq, ha);
7219 return ips_abort_init(ha, index);
7220 }
7221
7222 return SUCCESS;
7223}
7224
7225MODULE_LICENSE("GPL");
7226MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING);
7227MODULE_VERSION(IPS_VER_STRING);
7228
7229
7230/*
7231 * Overrides for Emacs so that we almost follow Linus's tabbing style.
7232 * Emacs will notice this stuff at the end of the file and automatically
7233 * adjust the settings for this buffer only. This must remain at the end
7234 * of the file.
7235 * ---------------------------------------------------------------------------
7236 * Local variables:
7237 * c-indent-level: 2
7238 * c-brace-imaginary-offset: 0
7239 * c-brace-offset: -2
7240 * c-argdecl-indent: 2
7241 * c-label-offset: -2
7242 * c-continued-statement-offset: 2
7243 * c-continued-brace-offset: 0
7244 * indent-tabs-mode: nil
7245 * tab-width: 8
7246 * End:
7247 */
1/*****************************************************************************/
2/* ips.c -- driver for the Adaptec / IBM ServeRAID controller */
3/* */
4/* Written By: Keith Mitchell, IBM Corporation */
5/* Jack Hammer, Adaptec, Inc. */
6/* David Jeffery, Adaptec, Inc. */
7/* */
8/* Copyright (C) 2000 IBM Corporation */
9/* Copyright (C) 2002,2003 Adaptec, Inc. */
10/* */
11/* This program is free software; you can redistribute it and/or modify */
12/* it under the terms of the GNU General Public License as published by */
13/* the Free Software Foundation; either version 2 of the License, or */
14/* (at your option) any later version. */
15/* */
16/* This program is distributed in the hope that it will be useful, */
17/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19/* GNU General Public License for more details. */
20/* */
21/* NO WARRANTY */
22/* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23/* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24/* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25/* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26/* solely responsible for determining the appropriateness of using and */
27/* distributing the Program and assumes all risks associated with its */
28/* exercise of rights under this Agreement, including but not limited to */
29/* the risks and costs of program errors, damage to or loss of data, */
30/* programs or equipment, and unavailability or interruption of operations. */
31/* */
32/* DISCLAIMER OF LIABILITY */
33/* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34/* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35/* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37/* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38/* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39/* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
40/* */
41/* You should have received a copy of the GNU General Public License */
42/* along with this program; if not, write to the Free Software */
43/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
44/* */
45/* Bugs/Comments/Suggestions about this driver should be mailed to: */
46/* ipslinux@adaptec.com */
47/* */
48/* For system support issues, contact your local IBM Customer support. */
49/* Directions to find IBM Customer Support for each country can be found at: */
50/* http://www.ibm.com/planetwide/ */
51/* */
52/*****************************************************************************/
53
54/*****************************************************************************/
55/* Change Log */
56/* */
57/* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */
58/* 0.99.03 - Make interrupt routine handle all completed request on the */
59/* adapter not just the first one */
60/* - Make sure passthru commands get woken up if we run out of */
61/* SCBs */
62/* - Send all of the commands on the queue at once rather than */
63/* one at a time since the card will support it. */
64/* 0.99.04 - Fix race condition in the passthru mechanism -- this required */
65/* the interface to the utilities to change */
66/* - Fix error recovery code */
67/* 0.99.05 - Fix an oops when we get certain passthru commands */
68/* 1.00.00 - Initial Public Release */
69/* Functionally equivalent to 0.99.05 */
70/* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */
71/* - Change version to 3.60 to coincide with release numbering. */
72/* 3.60.01 - Remove bogus error check in passthru routine */
73/* 3.60.02 - Make DCDB direction based on lookup table */
74/* - Only allow one DCDB command to a SCSI ID at a time */
75/* 4.00.00 - Add support for ServeRAID 4 */
76/* 4.00.01 - Add support for First Failure Data Capture */
77/* 4.00.02 - Fix problem with PT DCDB with no buffer */
78/* 4.00.03 - Add alternative passthru interface */
79/* - Add ability to flash BIOS */
80/* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */
81/* 4.00.05 - Remove wish_block from init routine */
82/* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */
83/* 2.3.18 and later */
84/* - Sync with other changes from the 2.3 kernels */
85/* 4.00.06 - Fix timeout with initial FFDC command */
86/* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */
87/* 4.10.00 - Add support for ServeRAID 4M/4L */
88/* 4.10.13 - Fix for dynamic unload and proc file system */
89/* 4.20.03 - Rename version to coincide with new release schedules */
90/* Performance fixes */
91/* Fix truncation of /proc files with cat */
92/* Merge in changes through kernel 2.4.0test1ac21 */
93/* 4.20.13 - Fix some failure cases / reset code */
94/* - Hook into the reboot_notifier to flush the controller cache */
95/* 4.50.01 - Fix problem when there is a hole in logical drive numbering */
96/* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */
97/* - Add IPSSEND Flash Support */
98/* - Set Sense Data for Unknown SCSI Command */
99/* - Use Slot Number from NVRAM Page 5 */
100/* - Restore caller's DCDB Structure */
101/* 4.70.12 - Corrective actions for bad controller ( during initialization )*/
102/* 4.70.13 - Don't Send CDB's if we already know the device is not present */
103/* - Don't release HA Lock in ips_next() until SC taken off queue */
104/* - Unregister SCSI device in ips_release() */
105/* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */
106/* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */
107/* Code Clean-Up for 2.4.x kernel */
108/* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */
109/* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */
110/* - Don't Issue Internal FFDC Command if there are Active Commands */
111/* - Close Window for getting too many IOCTL's active */
112/* 4.80.00 - Make ia64 Safe */
113/* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */
114/* - Adjustments to Device Queue Depth */
115/* 4.80.14 - Take all semaphores off stack */
116/* - Clean Up New_IOCTL path */
117/* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */
118/* - 5 second delay needed after resetting an i960 adapter */
119/* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */
120/* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */
121/* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */
122/* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */
123/* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */
124/* 4.90.11 - Don't actually RESET unless it's physically required */
125/* - Remove unused compile options */
126/* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */
127/* - Get rid on IOCTL_NEW_COMMAND code */
128/* - Add Extended DCDB Commands for Tape Support in 5I */
129/* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */
130/* 5.10.15 - remove unused code (sem, macros, etc.) */
131/* 5.30.00 - use __devexit_p() */
132/* 6.00.00 - Add 6x Adapters and Battery Flash */
133/* 6.10.00 - Remove 1G Addressing Limitations */
134/* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */
135/* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */
136/* 7.10.18 - Add highmem_io flag in SCSI Templete for 2.4 kernels */
137/* - Fix path/name for scsi_hosts.h include for 2.6 kernels */
138/* - Fix sort order of 7k */
139/* - Remove 3 unused "inline" functions */
140/* 7.12.xx - Use STATIC functions wherever possible */
141/* - Clean up deprecated MODULE_PARM calls */
142/* 7.12.05 - Remove Version Matching per IBM request */
143/*****************************************************************************/
144
145/*
146 * Conditional Compilation directives for this driver:
147 *
148 * IPS_DEBUG - Turn on debugging info
149 *
150 * Parameters:
151 *
152 * debug:<number> - Set debug level to <number>
153 * NOTE: only works when IPS_DEBUG compile directive is used.
154 * 1 - Normal debug messages
155 * 2 - Verbose debug messages
156 * 11 - Method trace (non interrupt)
157 * 12 - Method trace (includes interrupt)
158 *
159 * noi2o - Don't use I2O Queues (ServeRAID 4 only)
160 * nommap - Don't use memory mapped I/O
161 * ioctlsize - Initial size of the IOCTL buffer
162 */
163
164#include <asm/io.h>
165#include <asm/byteorder.h>
166#include <asm/page.h>
167#include <linux/stddef.h>
168#include <linux/string.h>
169#include <linux/errno.h>
170#include <linux/kernel.h>
171#include <linux/ioport.h>
172#include <linux/slab.h>
173#include <linux/delay.h>
174#include <linux/pci.h>
175#include <linux/proc_fs.h>
176#include <linux/reboot.h>
177#include <linux/interrupt.h>
178
179#include <linux/blkdev.h>
180#include <linux/types.h>
181#include <linux/dma-mapping.h>
182
183#include <scsi/sg.h>
184#include "scsi.h"
185#include <scsi/scsi_host.h>
186
187#include "ips.h"
188
189#include <linux/module.h>
190
191#include <linux/stat.h>
192
193#include <linux/spinlock.h>
194#include <linux/init.h>
195
196#include <linux/smp.h>
197
198#ifdef MODULE
199static char *ips = NULL;
200module_param(ips, charp, 0);
201#endif
202
203/*
204 * DRIVER_VER
205 */
206#define IPS_VERSION_HIGH IPS_VER_MAJOR_STRING "." IPS_VER_MINOR_STRING
207#define IPS_VERSION_LOW "." IPS_VER_BUILD_STRING " "
208
209#define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \
210 DMA_NONE == scb->scsi_cmd->sc_data_direction) ? \
211 PCI_DMA_BIDIRECTIONAL : \
212 scb->scsi_cmd->sc_data_direction)
213
214#ifdef IPS_DEBUG
215#define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n");
216#define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n");
217#define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v);
218#else
219#define METHOD_TRACE(s, i)
220#define DEBUG(i, s)
221#define DEBUG_VAR(i, s, v...)
222#endif
223
224/*
225 * Function prototypes
226 */
227static int ips_eh_abort(struct scsi_cmnd *);
228static int ips_eh_reset(struct scsi_cmnd *);
229static int ips_queue(struct Scsi_Host *, struct scsi_cmnd *);
230static const char *ips_info(struct Scsi_Host *);
231static irqreturn_t do_ipsintr(int, void *);
232static int ips_hainit(ips_ha_t *);
233static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *);
234static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int);
235static int ips_send_cmd(ips_ha_t *, ips_scb_t *);
236static int ips_online(ips_ha_t *, ips_scb_t *);
237static int ips_inquiry(ips_ha_t *, ips_scb_t *);
238static int ips_rdcap(ips_ha_t *, ips_scb_t *);
239static int ips_msense(ips_ha_t *, ips_scb_t *);
240static int ips_reqsen(ips_ha_t *, ips_scb_t *);
241static int ips_deallocatescbs(ips_ha_t *, int);
242static int ips_allocatescbs(ips_ha_t *);
243static int ips_reset_copperhead(ips_ha_t *);
244static int ips_reset_copperhead_memio(ips_ha_t *);
245static int ips_reset_morpheus(ips_ha_t *);
246static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *);
247static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *);
248static int ips_issue_i2o(ips_ha_t *, ips_scb_t *);
249static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *);
250static int ips_isintr_copperhead(ips_ha_t *);
251static int ips_isintr_copperhead_memio(ips_ha_t *);
252static int ips_isintr_morpheus(ips_ha_t *);
253static int ips_wait(ips_ha_t *, int, int);
254static int ips_write_driver_status(ips_ha_t *, int);
255static int ips_read_adapter_status(ips_ha_t *, int);
256static int ips_read_subsystem_parameters(ips_ha_t *, int);
257static int ips_read_config(ips_ha_t *, int);
258static int ips_clear_adapter(ips_ha_t *, int);
259static int ips_readwrite_page5(ips_ha_t *, int, int);
260static int ips_init_copperhead(ips_ha_t *);
261static int ips_init_copperhead_memio(ips_ha_t *);
262static int ips_init_morpheus(ips_ha_t *);
263static int ips_isinit_copperhead(ips_ha_t *);
264static int ips_isinit_copperhead_memio(ips_ha_t *);
265static int ips_isinit_morpheus(ips_ha_t *);
266static int ips_erase_bios(ips_ha_t *);
267static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t);
268static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t);
269static int ips_erase_bios_memio(ips_ha_t *);
270static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
271static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
272static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
273static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
274static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
275static void ips_free_flash_copperhead(ips_ha_t * ha);
276static void ips_get_bios_version(ips_ha_t *, int);
277static void ips_identify_controller(ips_ha_t *);
278static void ips_chkstatus(ips_ha_t *, IPS_STATUS *);
279static void ips_enable_int_copperhead(ips_ha_t *);
280static void ips_enable_int_copperhead_memio(ips_ha_t *);
281static void ips_enable_int_morpheus(ips_ha_t *);
282static int ips_intr_copperhead(ips_ha_t *);
283static int ips_intr_morpheus(ips_ha_t *);
284static void ips_next(ips_ha_t *, int);
285static void ipsintr_blocking(ips_ha_t *, struct ips_scb *);
286static void ipsintr_done(ips_ha_t *, struct ips_scb *);
287static void ips_done(ips_ha_t *, ips_scb_t *);
288static void ips_free(ips_ha_t *);
289static void ips_init_scb(ips_ha_t *, ips_scb_t *);
290static void ips_freescb(ips_ha_t *, ips_scb_t *);
291static void ips_setup_funclist(ips_ha_t *);
292static void ips_statinit(ips_ha_t *);
293static void ips_statinit_memio(ips_ha_t *);
294static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time_t);
295static void ips_ffdc_reset(ips_ha_t *, int);
296static void ips_ffdc_time(ips_ha_t *);
297static uint32_t ips_statupd_copperhead(ips_ha_t *);
298static uint32_t ips_statupd_copperhead_memio(ips_ha_t *);
299static uint32_t ips_statupd_morpheus(ips_ha_t *);
300static ips_scb_t *ips_getscb(ips_ha_t *);
301static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *);
302static void ips_putq_wait_tail(ips_wait_queue_entry_t *, struct scsi_cmnd *);
303static void ips_putq_copp_tail(ips_copp_queue_t *,
304 ips_copp_wait_item_t *);
305static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *);
306static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *);
307static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *);
308static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *,
309 struct scsi_cmnd *);
310static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *,
311 ips_copp_wait_item_t *);
312static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *);
313
314static int ips_is_passthru(struct scsi_cmnd *);
315static int ips_make_passthru(ips_ha_t *, struct scsi_cmnd *, ips_scb_t *, int);
316static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
317static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *);
318static void ips_scmd_buf_write(struct scsi_cmnd * scmd, void *data,
319 unsigned int count);
320static void ips_scmd_buf_read(struct scsi_cmnd * scmd, void *data,
321 unsigned int count);
322
323static int ips_write_info(struct Scsi_Host *, char *, int);
324static int ips_show_info(struct seq_file *, struct Scsi_Host *);
325static int ips_host_info(ips_ha_t *, struct seq_file *);
326static int ips_abort_init(ips_ha_t * ha, int index);
327static int ips_init_phase2(int index);
328
329static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr);
330static int ips_register_scsi(int index);
331
332static int ips_poll_for_flush_complete(ips_ha_t * ha);
333static void ips_flush_and_reset(ips_ha_t *ha);
334
335/*
336 * global variables
337 */
338static const char ips_name[] = "ips";
339static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */
340static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */
341static unsigned int ips_next_controller;
342static unsigned int ips_num_controllers;
343static unsigned int ips_released_controllers;
344static int ips_hotplug;
345static int ips_cmd_timeout = 60;
346static int ips_reset_timeout = 60 * 5;
347static int ips_force_memio = 1; /* Always use Memory Mapped I/O */
348static int ips_force_i2o = 1; /* Always use I2O command delivery */
349static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */
350static int ips_cd_boot; /* Booting from Manager CD */
351static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */
352static dma_addr_t ips_flashbusaddr;
353static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */
354static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */
355static struct scsi_host_template ips_driver_template = {
356 .info = ips_info,
357 .queuecommand = ips_queue,
358 .eh_abort_handler = ips_eh_abort,
359 .eh_host_reset_handler = ips_eh_reset,
360 .proc_name = "ips",
361 .show_info = ips_show_info,
362 .write_info = ips_write_info,
363 .slave_configure = ips_slave_configure,
364 .bios_param = ips_biosparam,
365 .this_id = -1,
366 .sg_tablesize = IPS_MAX_SG,
367 .cmd_per_lun = 3,
368 .use_clustering = ENABLE_CLUSTERING,
369 .no_write_same = 1,
370};
371
372
373/* This table describes all ServeRAID Adapters */
374static struct pci_device_id ips_pci_table[] = {
375 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
376 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
377 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
378 { 0, }
379};
380
381MODULE_DEVICE_TABLE( pci, ips_pci_table );
382
383static char ips_hot_plug_name[] = "ips";
384
385static int ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent);
386static void ips_remove_device(struct pci_dev *pci_dev);
387
388static struct pci_driver ips_pci_driver = {
389 .name = ips_hot_plug_name,
390 .id_table = ips_pci_table,
391 .probe = ips_insert_device,
392 .remove = ips_remove_device,
393};
394
395
396/*
397 * Necessary forward function protoypes
398 */
399static int ips_halt(struct notifier_block *nb, ulong event, void *buf);
400
401#define MAX_ADAPTER_NAME 15
402
403static char ips_adapter_name[][30] = {
404 "ServeRAID",
405 "ServeRAID II",
406 "ServeRAID on motherboard",
407 "ServeRAID on motherboard",
408 "ServeRAID 3H",
409 "ServeRAID 3L",
410 "ServeRAID 4H",
411 "ServeRAID 4M",
412 "ServeRAID 4L",
413 "ServeRAID 4Mx",
414 "ServeRAID 4Lx",
415 "ServeRAID 5i",
416 "ServeRAID 5i",
417 "ServeRAID 6M",
418 "ServeRAID 6i",
419 "ServeRAID 7t",
420 "ServeRAID 7k",
421 "ServeRAID 7M"
422};
423
424static struct notifier_block ips_notifier = {
425 ips_halt, NULL, 0
426};
427
428/*
429 * Direction table
430 */
431static char ips_command_direction[] = {
432 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT,
433 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK,
434 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
435 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
436 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT,
437 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
438 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN,
439 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
440 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK,
441 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
442 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE,
443 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
444 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT,
445 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE,
446 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK,
447 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
448 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
449 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
450 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
451 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
452 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
453 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
454 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
455 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
456 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
457 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
458 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
459 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
460 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
461 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
462 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
463 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
464 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
465 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE,
466 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT,
467 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE,
468 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN,
469 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
470 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
471 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
472 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
473 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
474 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
475 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
476 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
477 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
478 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT,
479 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
480 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
481 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
482 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK
483};
484
485
486/****************************************************************************/
487/* */
488/* Routine Name: ips_setup */
489/* */
490/* Routine Description: */
491/* */
492/* setup parameters to the driver */
493/* */
494/****************************************************************************/
495static int
496ips_setup(char *ips_str)
497{
498
499 int i;
500 char *key;
501 char *value;
502 IPS_OPTION options[] = {
503 {"noi2o", &ips_force_i2o, 0},
504 {"nommap", &ips_force_memio, 0},
505 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE},
506 {"cdboot", &ips_cd_boot, 0},
507 {"maxcmds", &MaxLiteCmds, 32},
508 };
509
510 /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */
511 /* Search for value */
512 while ((key = strsep(&ips_str, ",."))) {
513 if (!*key)
514 continue;
515 value = strchr(key, ':');
516 if (value)
517 *value++ = '\0';
518 /*
519 * We now have key/value pairs.
520 * Update the variables
521 */
522 for (i = 0; i < ARRAY_SIZE(options); i++) {
523 if (strncasecmp
524 (key, options[i].option_name,
525 strlen(options[i].option_name)) == 0) {
526 if (value)
527 *options[i].option_flag =
528 simple_strtoul(value, NULL, 0);
529 else
530 *options[i].option_flag =
531 options[i].option_value;
532 break;
533 }
534 }
535 }
536
537 return (1);
538}
539
540__setup("ips=", ips_setup);
541
542/****************************************************************************/
543/* */
544/* Routine Name: ips_detect */
545/* */
546/* Routine Description: */
547/* */
548/* Detect and initialize the driver */
549/* */
550/* NOTE: this routine is called under the io_request_lock spinlock */
551/* */
552/****************************************************************************/
553static int
554ips_detect(struct scsi_host_template * SHT)
555{
556 int i;
557
558 METHOD_TRACE("ips_detect", 1);
559
560#ifdef MODULE
561 if (ips)
562 ips_setup(ips);
563#endif
564
565 for (i = 0; i < ips_num_controllers; i++) {
566 if (ips_register_scsi(i))
567 ips_free(ips_ha[i]);
568 ips_released_controllers++;
569 }
570 ips_hotplug = 1;
571 return (ips_num_controllers);
572}
573
574/****************************************************************************/
575/* configure the function pointers to use the functions that will work */
576/* with the found version of the adapter */
577/****************************************************************************/
578static void
579ips_setup_funclist(ips_ha_t * ha)
580{
581
582 /*
583 * Setup Functions
584 */
585 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
586 /* morpheus / marco / sebring */
587 ha->func.isintr = ips_isintr_morpheus;
588 ha->func.isinit = ips_isinit_morpheus;
589 ha->func.issue = ips_issue_i2o_memio;
590 ha->func.init = ips_init_morpheus;
591 ha->func.statupd = ips_statupd_morpheus;
592 ha->func.reset = ips_reset_morpheus;
593 ha->func.intr = ips_intr_morpheus;
594 ha->func.enableint = ips_enable_int_morpheus;
595 } else if (IPS_USE_MEMIO(ha)) {
596 /* copperhead w/MEMIO */
597 ha->func.isintr = ips_isintr_copperhead_memio;
598 ha->func.isinit = ips_isinit_copperhead_memio;
599 ha->func.init = ips_init_copperhead_memio;
600 ha->func.statupd = ips_statupd_copperhead_memio;
601 ha->func.statinit = ips_statinit_memio;
602 ha->func.reset = ips_reset_copperhead_memio;
603 ha->func.intr = ips_intr_copperhead;
604 ha->func.erasebios = ips_erase_bios_memio;
605 ha->func.programbios = ips_program_bios_memio;
606 ha->func.verifybios = ips_verify_bios_memio;
607 ha->func.enableint = ips_enable_int_copperhead_memio;
608 if (IPS_USE_I2O_DELIVER(ha))
609 ha->func.issue = ips_issue_i2o_memio;
610 else
611 ha->func.issue = ips_issue_copperhead_memio;
612 } else {
613 /* copperhead */
614 ha->func.isintr = ips_isintr_copperhead;
615 ha->func.isinit = ips_isinit_copperhead;
616 ha->func.init = ips_init_copperhead;
617 ha->func.statupd = ips_statupd_copperhead;
618 ha->func.statinit = ips_statinit;
619 ha->func.reset = ips_reset_copperhead;
620 ha->func.intr = ips_intr_copperhead;
621 ha->func.erasebios = ips_erase_bios;
622 ha->func.programbios = ips_program_bios;
623 ha->func.verifybios = ips_verify_bios;
624 ha->func.enableint = ips_enable_int_copperhead;
625
626 if (IPS_USE_I2O_DELIVER(ha))
627 ha->func.issue = ips_issue_i2o;
628 else
629 ha->func.issue = ips_issue_copperhead;
630 }
631}
632
633/****************************************************************************/
634/* */
635/* Routine Name: ips_release */
636/* */
637/* Routine Description: */
638/* */
639/* Remove a driver */
640/* */
641/****************************************************************************/
642static int
643ips_release(struct Scsi_Host *sh)
644{
645 ips_scb_t *scb;
646 ips_ha_t *ha;
647 int i;
648
649 METHOD_TRACE("ips_release", 1);
650
651 scsi_remove_host(sh);
652
653 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ;
654
655 if (i == IPS_MAX_ADAPTERS) {
656 printk(KERN_WARNING
657 "(%s) release, invalid Scsi_Host pointer.\n", ips_name);
658 BUG();
659 return (FALSE);
660 }
661
662 ha = IPS_HA(sh);
663
664 if (!ha)
665 return (FALSE);
666
667 /* flush the cache on the controller */
668 scb = &ha->scbs[ha->max_cmds - 1];
669
670 ips_init_scb(ha, scb);
671
672 scb->timeout = ips_cmd_timeout;
673 scb->cdb[0] = IPS_CMD_FLUSH;
674
675 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
676 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
677 scb->cmd.flush_cache.state = IPS_NORM_STATE;
678 scb->cmd.flush_cache.reserved = 0;
679 scb->cmd.flush_cache.reserved2 = 0;
680 scb->cmd.flush_cache.reserved3 = 0;
681 scb->cmd.flush_cache.reserved4 = 0;
682
683 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
684
685 /* send command */
686 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE)
687 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n");
688
689 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n");
690
691 ips_sh[i] = NULL;
692 ips_ha[i] = NULL;
693
694 /* free extra memory */
695 ips_free(ha);
696
697 /* free IRQ */
698 free_irq(ha->pcidev->irq, ha);
699
700 scsi_host_put(sh);
701
702 ips_released_controllers++;
703
704 return (FALSE);
705}
706
707/****************************************************************************/
708/* */
709/* Routine Name: ips_halt */
710/* */
711/* Routine Description: */
712/* */
713/* Perform cleanup when the system reboots */
714/* */
715/****************************************************************************/
716static int
717ips_halt(struct notifier_block *nb, ulong event, void *buf)
718{
719 ips_scb_t *scb;
720 ips_ha_t *ha;
721 int i;
722
723 if ((event != SYS_RESTART) && (event != SYS_HALT) &&
724 (event != SYS_POWER_OFF))
725 return (NOTIFY_DONE);
726
727 for (i = 0; i < ips_next_controller; i++) {
728 ha = (ips_ha_t *) ips_ha[i];
729
730 if (!ha)
731 continue;
732
733 if (!ha->active)
734 continue;
735
736 /* flush the cache on the controller */
737 scb = &ha->scbs[ha->max_cmds - 1];
738
739 ips_init_scb(ha, scb);
740
741 scb->timeout = ips_cmd_timeout;
742 scb->cdb[0] = IPS_CMD_FLUSH;
743
744 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
745 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
746 scb->cmd.flush_cache.state = IPS_NORM_STATE;
747 scb->cmd.flush_cache.reserved = 0;
748 scb->cmd.flush_cache.reserved2 = 0;
749 scb->cmd.flush_cache.reserved3 = 0;
750 scb->cmd.flush_cache.reserved4 = 0;
751
752 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
753
754 /* send command */
755 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) ==
756 IPS_FAILURE)
757 IPS_PRINTK(KERN_WARNING, ha->pcidev,
758 "Incomplete Flush.\n");
759 else
760 IPS_PRINTK(KERN_WARNING, ha->pcidev,
761 "Flushing Complete.\n");
762 }
763
764 return (NOTIFY_OK);
765}
766
767/****************************************************************************/
768/* */
769/* Routine Name: ips_eh_abort */
770/* */
771/* Routine Description: */
772/* */
773/* Abort a command (using the new error code stuff) */
774/* Note: this routine is called under the io_request_lock */
775/****************************************************************************/
776int ips_eh_abort(struct scsi_cmnd *SC)
777{
778 ips_ha_t *ha;
779 ips_copp_wait_item_t *item;
780 int ret;
781 struct Scsi_Host *host;
782
783 METHOD_TRACE("ips_eh_abort", 1);
784
785 if (!SC)
786 return (FAILED);
787
788 host = SC->device->host;
789 ha = (ips_ha_t *) SC->device->host->hostdata;
790
791 if (!ha)
792 return (FAILED);
793
794 if (!ha->active)
795 return (FAILED);
796
797 spin_lock(host->host_lock);
798
799 /* See if the command is on the copp queue */
800 item = ha->copp_waitlist.head;
801 while ((item) && (item->scsi_cmd != SC))
802 item = item->next;
803
804 if (item) {
805 /* Found it */
806 ips_removeq_copp(&ha->copp_waitlist, item);
807 ret = (SUCCESS);
808
809 /* See if the command is on the wait queue */
810 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
811 /* command not sent yet */
812 ret = (SUCCESS);
813 } else {
814 /* command must have already been sent */
815 ret = (FAILED);
816 }
817
818 spin_unlock(host->host_lock);
819 return ret;
820}
821
822/****************************************************************************/
823/* */
824/* Routine Name: ips_eh_reset */
825/* */
826/* Routine Description: */
827/* */
828/* Reset the controller (with new eh error code) */
829/* */
830/* NOTE: this routine is called under the io_request_lock spinlock */
831/* */
832/****************************************************************************/
833static int __ips_eh_reset(struct scsi_cmnd *SC)
834{
835 int ret;
836 int i;
837 ips_ha_t *ha;
838 ips_scb_t *scb;
839 ips_copp_wait_item_t *item;
840
841 METHOD_TRACE("ips_eh_reset", 1);
842
843#ifdef NO_IPS_RESET
844 return (FAILED);
845#else
846
847 if (!SC) {
848 DEBUG(1, "Reset called with NULL scsi command");
849
850 return (FAILED);
851 }
852
853 ha = (ips_ha_t *) SC->device->host->hostdata;
854
855 if (!ha) {
856 DEBUG(1, "Reset called with NULL ha struct");
857
858 return (FAILED);
859 }
860
861 if (!ha->active)
862 return (FAILED);
863
864 /* See if the command is on the copp queue */
865 item = ha->copp_waitlist.head;
866 while ((item) && (item->scsi_cmd != SC))
867 item = item->next;
868
869 if (item) {
870 /* Found it */
871 ips_removeq_copp(&ha->copp_waitlist, item);
872 return (SUCCESS);
873 }
874
875 /* See if the command is on the wait queue */
876 if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
877 /* command not sent yet */
878 return (SUCCESS);
879 }
880
881 /* An explanation for the casual observer: */
882 /* Part of the function of a RAID controller is automatic error */
883 /* detection and recovery. As such, the only problem that physically */
884 /* resetting an adapter will ever fix is when, for some reason, */
885 /* the driver is not successfully communicating with the adapter. */
886 /* Therefore, we will attempt to flush this adapter. If that succeeds, */
887 /* then there's no real purpose in a physical reset. This will complete */
888 /* much faster and avoids any problems that might be caused by a */
889 /* physical reset ( such as having to fail all the outstanding I/O's ). */
890
891 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */
892 scb = &ha->scbs[ha->max_cmds - 1];
893
894 ips_init_scb(ha, scb);
895
896 scb->timeout = ips_cmd_timeout;
897 scb->cdb[0] = IPS_CMD_FLUSH;
898
899 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
900 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
901 scb->cmd.flush_cache.state = IPS_NORM_STATE;
902 scb->cmd.flush_cache.reserved = 0;
903 scb->cmd.flush_cache.reserved2 = 0;
904 scb->cmd.flush_cache.reserved3 = 0;
905 scb->cmd.flush_cache.reserved4 = 0;
906
907 /* Attempt the flush command */
908 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL);
909 if (ret == IPS_SUCCESS) {
910 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
911 "Reset Request - Flushed Cache\n");
912 return (SUCCESS);
913 }
914 }
915
916 /* Either we can't communicate with the adapter or it's an IOCTL request */
917 /* from a utility. A physical reset is needed at this point. */
918
919 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */
920
921 /*
922 * command must have already been sent
923 * reset the controller
924 */
925 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n");
926 ret = (*ha->func.reset) (ha);
927
928 if (!ret) {
929 struct scsi_cmnd *scsi_cmd;
930
931 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
932 "Controller reset failed - controller now offline.\n");
933
934 /* Now fail all of the active commands */
935 DEBUG_VAR(1, "(%s%d) Failing active commands",
936 ips_name, ha->host_num);
937
938 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
939 scb->scsi_cmd->result = DID_ERROR << 16;
940 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
941 ips_freescb(ha, scb);
942 }
943
944 /* Now fail all of the pending commands */
945 DEBUG_VAR(1, "(%s%d) Failing pending commands",
946 ips_name, ha->host_num);
947
948 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
949 scsi_cmd->result = DID_ERROR;
950 scsi_cmd->scsi_done(scsi_cmd);
951 }
952
953 ha->active = FALSE;
954 return (FAILED);
955 }
956
957 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) {
958 struct scsi_cmnd *scsi_cmd;
959
960 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
961 "Controller reset failed - controller now offline.\n");
962
963 /* Now fail all of the active commands */
964 DEBUG_VAR(1, "(%s%d) Failing active commands",
965 ips_name, ha->host_num);
966
967 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
968 scb->scsi_cmd->result = DID_ERROR << 16;
969 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
970 ips_freescb(ha, scb);
971 }
972
973 /* Now fail all of the pending commands */
974 DEBUG_VAR(1, "(%s%d) Failing pending commands",
975 ips_name, ha->host_num);
976
977 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
978 scsi_cmd->result = DID_ERROR << 16;
979 scsi_cmd->scsi_done(scsi_cmd);
980 }
981
982 ha->active = FALSE;
983 return (FAILED);
984 }
985
986 /* FFDC */
987 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) {
988 struct timeval tv;
989
990 do_gettimeofday(&tv);
991 ha->last_ffdc = tv.tv_sec;
992 ha->reset_count++;
993 ips_ffdc_reset(ha, IPS_INTR_IORL);
994 }
995
996 /* Now fail all of the active commands */
997 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num);
998
999 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
1000 scb->scsi_cmd->result = DID_RESET << 16;
1001 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
1002 ips_freescb(ha, scb);
1003 }
1004
1005 /* Reset DCDB active command bits */
1006 for (i = 1; i < ha->nbus; i++)
1007 ha->dcdb_active[i - 1] = 0;
1008
1009 /* Reset the number of active IOCTLs */
1010 ha->num_ioctl = 0;
1011
1012 ips_next(ha, IPS_INTR_IORL);
1013
1014 return (SUCCESS);
1015#endif /* NO_IPS_RESET */
1016
1017}
1018
1019static int ips_eh_reset(struct scsi_cmnd *SC)
1020{
1021 int rc;
1022
1023 spin_lock_irq(SC->device->host->host_lock);
1024 rc = __ips_eh_reset(SC);
1025 spin_unlock_irq(SC->device->host->host_lock);
1026
1027 return rc;
1028}
1029
1030/****************************************************************************/
1031/* */
1032/* Routine Name: ips_queue */
1033/* */
1034/* Routine Description: */
1035/* */
1036/* Send a command to the controller */
1037/* */
1038/* NOTE: */
1039/* Linux obtains io_request_lock before calling this function */
1040/* */
1041/****************************************************************************/
1042static int ips_queue_lck(struct scsi_cmnd *SC, void (*done) (struct scsi_cmnd *))
1043{
1044 ips_ha_t *ha;
1045 ips_passthru_t *pt;
1046
1047 METHOD_TRACE("ips_queue", 1);
1048
1049 ha = (ips_ha_t *) SC->device->host->hostdata;
1050
1051 if (!ha)
1052 return (1);
1053
1054 if (!ha->active)
1055 return (DID_ERROR);
1056
1057 if (ips_is_passthru(SC)) {
1058 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) {
1059 SC->result = DID_BUS_BUSY << 16;
1060 done(SC);
1061
1062 return (0);
1063 }
1064 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) {
1065 SC->result = DID_BUS_BUSY << 16;
1066 done(SC);
1067
1068 return (0);
1069 }
1070
1071 SC->scsi_done = done;
1072
1073 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)",
1074 ips_name,
1075 ha->host_num,
1076 SC->cmnd[0],
1077 SC->device->channel, SC->device->id, SC->device->lun);
1078
1079 /* Check for command to initiator IDs */
1080 if ((scmd_channel(SC) > 0)
1081 && (scmd_id(SC) == ha->ha_id[scmd_channel(SC)])) {
1082 SC->result = DID_NO_CONNECT << 16;
1083 done(SC);
1084
1085 return (0);
1086 }
1087
1088 if (ips_is_passthru(SC)) {
1089
1090 ips_copp_wait_item_t *scratch;
1091
1092 /* A Reset IOCTL is only sent by the boot CD in extreme cases. */
1093 /* There can never be any system activity ( network or disk ), but check */
1094 /* anyway just as a good practice. */
1095 pt = (ips_passthru_t *) scsi_sglist(SC);
1096 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) &&
1097 (pt->CoppCP.cmd.reset.adapter_flag == 1)) {
1098 if (ha->scb_activelist.count != 0) {
1099 SC->result = DID_BUS_BUSY << 16;
1100 done(SC);
1101 return (0);
1102 }
1103 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */
1104 __ips_eh_reset(SC);
1105 SC->result = DID_OK << 16;
1106 SC->scsi_done(SC);
1107 return (0);
1108 }
1109
1110 /* allocate space for the scribble */
1111 scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC);
1112
1113 if (!scratch) {
1114 SC->result = DID_ERROR << 16;
1115 done(SC);
1116
1117 return (0);
1118 }
1119
1120 scratch->scsi_cmd = SC;
1121 scratch->next = NULL;
1122
1123 ips_putq_copp_tail(&ha->copp_waitlist, scratch);
1124 } else {
1125 ips_putq_wait_tail(&ha->scb_waitlist, SC);
1126 }
1127
1128 ips_next(ha, IPS_INTR_IORL);
1129
1130 return (0);
1131}
1132
1133static DEF_SCSI_QCMD(ips_queue)
1134
1135/****************************************************************************/
1136/* */
1137/* Routine Name: ips_biosparam */
1138/* */
1139/* Routine Description: */
1140/* */
1141/* Set bios geometry for the controller */
1142/* */
1143/****************************************************************************/
1144static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
1145 sector_t capacity, int geom[])
1146{
1147 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata;
1148 int heads;
1149 int sectors;
1150 int cylinders;
1151
1152 METHOD_TRACE("ips_biosparam", 1);
1153
1154 if (!ha)
1155 /* ?!?! host adater info invalid */
1156 return (0);
1157
1158 if (!ha->active)
1159 return (0);
1160
1161 if (!ips_read_adapter_status(ha, IPS_INTR_ON))
1162 /* ?!?! Enquiry command failed */
1163 return (0);
1164
1165 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) {
1166 heads = IPS_NORM_HEADS;
1167 sectors = IPS_NORM_SECTORS;
1168 } else {
1169 heads = IPS_COMP_HEADS;
1170 sectors = IPS_COMP_SECTORS;
1171 }
1172
1173 cylinders = (unsigned long) capacity / (heads * sectors);
1174
1175 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d",
1176 heads, sectors, cylinders);
1177
1178 geom[0] = heads;
1179 geom[1] = sectors;
1180 geom[2] = cylinders;
1181
1182 return (0);
1183}
1184
1185/****************************************************************************/
1186/* */
1187/* Routine Name: ips_slave_configure */
1188/* */
1189/* Routine Description: */
1190/* */
1191/* Set queue depths on devices once scan is complete */
1192/* */
1193/****************************************************************************/
1194static int
1195ips_slave_configure(struct scsi_device * SDptr)
1196{
1197 ips_ha_t *ha;
1198 int min;
1199
1200 ha = IPS_HA(SDptr->host);
1201 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) {
1202 min = ha->max_cmds / 2;
1203 if (ha->enq->ucLogDriveCount <= 2)
1204 min = ha->max_cmds - 1;
1205 scsi_change_queue_depth(SDptr, min);
1206 }
1207
1208 SDptr->skip_ms_page_8 = 1;
1209 SDptr->skip_ms_page_3f = 1;
1210 return 0;
1211}
1212
1213/****************************************************************************/
1214/* */
1215/* Routine Name: do_ipsintr */
1216/* */
1217/* Routine Description: */
1218/* */
1219/* Wrapper for the interrupt handler */
1220/* */
1221/****************************************************************************/
1222static irqreturn_t
1223do_ipsintr(int irq, void *dev_id)
1224{
1225 ips_ha_t *ha;
1226 struct Scsi_Host *host;
1227 int irqstatus;
1228
1229 METHOD_TRACE("do_ipsintr", 2);
1230
1231 ha = (ips_ha_t *) dev_id;
1232 if (!ha)
1233 return IRQ_NONE;
1234 host = ips_sh[ha->host_num];
1235 /* interrupt during initialization */
1236 if (!host) {
1237 (*ha->func.intr) (ha);
1238 return IRQ_HANDLED;
1239 }
1240
1241 spin_lock(host->host_lock);
1242
1243 if (!ha->active) {
1244 spin_unlock(host->host_lock);
1245 return IRQ_HANDLED;
1246 }
1247
1248 irqstatus = (*ha->func.intr) (ha);
1249
1250 spin_unlock(host->host_lock);
1251
1252 /* start the next command */
1253 ips_next(ha, IPS_INTR_ON);
1254 return IRQ_RETVAL(irqstatus);
1255}
1256
1257/****************************************************************************/
1258/* */
1259/* Routine Name: ips_intr_copperhead */
1260/* */
1261/* Routine Description: */
1262/* */
1263/* Polling interrupt handler */
1264/* */
1265/* ASSUMES interrupts are disabled */
1266/* */
1267/****************************************************************************/
1268int
1269ips_intr_copperhead(ips_ha_t * ha)
1270{
1271 ips_stat_t *sp;
1272 ips_scb_t *scb;
1273 IPS_STATUS cstatus;
1274 int intrstatus;
1275
1276 METHOD_TRACE("ips_intr", 2);
1277
1278 if (!ha)
1279 return 0;
1280
1281 if (!ha->active)
1282 return 0;
1283
1284 intrstatus = (*ha->func.isintr) (ha);
1285
1286 if (!intrstatus) {
1287 /*
1288 * Unexpected/Shared interrupt
1289 */
1290
1291 return 0;
1292 }
1293
1294 while (TRUE) {
1295 sp = &ha->sp;
1296
1297 intrstatus = (*ha->func.isintr) (ha);
1298
1299 if (!intrstatus)
1300 break;
1301 else
1302 cstatus.value = (*ha->func.statupd) (ha);
1303
1304 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1305 /* Spurious Interrupt ? */
1306 continue;
1307 }
1308
1309 ips_chkstatus(ha, &cstatus);
1310 scb = (ips_scb_t *) sp->scb_addr;
1311
1312 /*
1313 * use the callback function to finish things up
1314 * NOTE: interrupts are OFF for this
1315 */
1316 (*scb->callback) (ha, scb);
1317 } /* end while */
1318 return 1;
1319}
1320
1321/****************************************************************************/
1322/* */
1323/* Routine Name: ips_intr_morpheus */
1324/* */
1325/* Routine Description: */
1326/* */
1327/* Polling interrupt handler */
1328/* */
1329/* ASSUMES interrupts are disabled */
1330/* */
1331/****************************************************************************/
1332int
1333ips_intr_morpheus(ips_ha_t * ha)
1334{
1335 ips_stat_t *sp;
1336 ips_scb_t *scb;
1337 IPS_STATUS cstatus;
1338 int intrstatus;
1339
1340 METHOD_TRACE("ips_intr_morpheus", 2);
1341
1342 if (!ha)
1343 return 0;
1344
1345 if (!ha->active)
1346 return 0;
1347
1348 intrstatus = (*ha->func.isintr) (ha);
1349
1350 if (!intrstatus) {
1351 /*
1352 * Unexpected/Shared interrupt
1353 */
1354
1355 return 0;
1356 }
1357
1358 while (TRUE) {
1359 sp = &ha->sp;
1360
1361 intrstatus = (*ha->func.isintr) (ha);
1362
1363 if (!intrstatus)
1364 break;
1365 else
1366 cstatus.value = (*ha->func.statupd) (ha);
1367
1368 if (cstatus.value == 0xffffffff)
1369 /* No more to process */
1370 break;
1371
1372 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1373 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1374 "Spurious interrupt; no ccb.\n");
1375
1376 continue;
1377 }
1378
1379 ips_chkstatus(ha, &cstatus);
1380 scb = (ips_scb_t *) sp->scb_addr;
1381
1382 /*
1383 * use the callback function to finish things up
1384 * NOTE: interrupts are OFF for this
1385 */
1386 (*scb->callback) (ha, scb);
1387 } /* end while */
1388 return 1;
1389}
1390
1391/****************************************************************************/
1392/* */
1393/* Routine Name: ips_info */
1394/* */
1395/* Routine Description: */
1396/* */
1397/* Return info about the driver */
1398/* */
1399/****************************************************************************/
1400static const char *
1401ips_info(struct Scsi_Host *SH)
1402{
1403 static char buffer[256];
1404 char *bp;
1405 ips_ha_t *ha;
1406
1407 METHOD_TRACE("ips_info", 1);
1408
1409 ha = IPS_HA(SH);
1410
1411 if (!ha)
1412 return (NULL);
1413
1414 bp = &buffer[0];
1415 memset(bp, 0, sizeof (buffer));
1416
1417 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ",
1418 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT);
1419
1420 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) {
1421 strcat(bp, " <");
1422 strcat(bp, ips_adapter_name[ha->ad_type - 1]);
1423 strcat(bp, ">");
1424 }
1425
1426 return (bp);
1427}
1428
1429static int
1430ips_write_info(struct Scsi_Host *host, char *buffer, int length)
1431{
1432 int i;
1433 ips_ha_t *ha = NULL;
1434
1435 /* Find our host structure */
1436 for (i = 0; i < ips_next_controller; i++) {
1437 if (ips_sh[i]) {
1438 if (ips_sh[i] == host) {
1439 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1440 break;
1441 }
1442 }
1443 }
1444
1445 if (!ha)
1446 return (-EINVAL);
1447
1448 return 0;
1449}
1450
1451static int
1452ips_show_info(struct seq_file *m, struct Scsi_Host *host)
1453{
1454 int i;
1455 ips_ha_t *ha = NULL;
1456
1457 /* Find our host structure */
1458 for (i = 0; i < ips_next_controller; i++) {
1459 if (ips_sh[i]) {
1460 if (ips_sh[i] == host) {
1461 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1462 break;
1463 }
1464 }
1465 }
1466
1467 if (!ha)
1468 return (-EINVAL);
1469
1470 return ips_host_info(ha, m);
1471}
1472
1473/*--------------------------------------------------------------------------*/
1474/* Helper Functions */
1475/*--------------------------------------------------------------------------*/
1476
1477/****************************************************************************/
1478/* */
1479/* Routine Name: ips_is_passthru */
1480/* */
1481/* Routine Description: */
1482/* */
1483/* Determine if the specified SCSI command is really a passthru command */
1484/* */
1485/****************************************************************************/
1486static int ips_is_passthru(struct scsi_cmnd *SC)
1487{
1488 unsigned long flags;
1489
1490 METHOD_TRACE("ips_is_passthru", 1);
1491
1492 if (!SC)
1493 return (0);
1494
1495 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) &&
1496 (SC->device->channel == 0) &&
1497 (SC->device->id == IPS_ADAPTER_ID) &&
1498 (SC->device->lun == 0) && scsi_sglist(SC)) {
1499 struct scatterlist *sg = scsi_sglist(SC);
1500 char *buffer;
1501
1502 /* kmap_atomic() ensures addressability of the user buffer.*/
1503 /* local_irq_save() protects the KM_IRQ0 address slot. */
1504 local_irq_save(flags);
1505 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
1506 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' &&
1507 buffer[2] == 'P' && buffer[3] == 'P') {
1508 kunmap_atomic(buffer - sg->offset);
1509 local_irq_restore(flags);
1510 return 1;
1511 }
1512 kunmap_atomic(buffer - sg->offset);
1513 local_irq_restore(flags);
1514 }
1515 return 0;
1516}
1517
1518/****************************************************************************/
1519/* */
1520/* Routine Name: ips_alloc_passthru_buffer */
1521/* */
1522/* Routine Description: */
1523/* allocate a buffer large enough for the ioctl data if the ioctl buffer */
1524/* is too small or doesn't exist */
1525/****************************************************************************/
1526static int
1527ips_alloc_passthru_buffer(ips_ha_t * ha, int length)
1528{
1529 void *bigger_buf;
1530 dma_addr_t dma_busaddr;
1531
1532 if (ha->ioctl_data && length <= ha->ioctl_len)
1533 return 0;
1534 /* there is no buffer or it's not big enough, allocate a new one */
1535 bigger_buf = pci_alloc_consistent(ha->pcidev, length, &dma_busaddr);
1536 if (bigger_buf) {
1537 /* free the old memory */
1538 pci_free_consistent(ha->pcidev, ha->ioctl_len, ha->ioctl_data,
1539 ha->ioctl_busaddr);
1540 /* use the new memory */
1541 ha->ioctl_data = (char *) bigger_buf;
1542 ha->ioctl_len = length;
1543 ha->ioctl_busaddr = dma_busaddr;
1544 } else {
1545 return -1;
1546 }
1547 return 0;
1548}
1549
1550/****************************************************************************/
1551/* */
1552/* Routine Name: ips_make_passthru */
1553/* */
1554/* Routine Description: */
1555/* */
1556/* Make a passthru command out of the info in the Scsi block */
1557/* */
1558/****************************************************************************/
1559static int
1560ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr)
1561{
1562 ips_passthru_t *pt;
1563 int length = 0;
1564 int i, ret;
1565 struct scatterlist *sg = scsi_sglist(SC);
1566
1567 METHOD_TRACE("ips_make_passthru", 1);
1568
1569 scsi_for_each_sg(SC, sg, scsi_sg_count(SC), i)
1570 length += sg->length;
1571
1572 if (length < sizeof (ips_passthru_t)) {
1573 /* wrong size */
1574 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size",
1575 ips_name, ha->host_num);
1576 return (IPS_FAILURE);
1577 }
1578 if (ips_alloc_passthru_buffer(ha, length)) {
1579 /* allocation failure! If ha->ioctl_data exists, use it to return
1580 some error codes. Return a failed command to the scsi layer. */
1581 if (ha->ioctl_data) {
1582 pt = (ips_passthru_t *) ha->ioctl_data;
1583 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t));
1584 pt->BasicStatus = 0x0B;
1585 pt->ExtendedStatus = 0x00;
1586 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t));
1587 }
1588 return IPS_FAILURE;
1589 }
1590 ha->ioctl_datasize = length;
1591
1592 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize);
1593 pt = (ips_passthru_t *) ha->ioctl_data;
1594
1595 /*
1596 * Some notes about the passthru interface used
1597 *
1598 * IF the scsi op_code == 0x0d then we assume
1599 * that the data came along with/goes with the
1600 * packet we received from the sg driver. In this
1601 * case the CmdBSize field of the pt structure is
1602 * used for the size of the buffer.
1603 */
1604
1605 switch (pt->CoppCmd) {
1606 case IPS_NUMCTRLS:
1607 memcpy(ha->ioctl_data + sizeof (ips_passthru_t),
1608 &ips_num_controllers, sizeof (int));
1609 ips_scmd_buf_write(SC, ha->ioctl_data,
1610 sizeof (ips_passthru_t) + sizeof (int));
1611 SC->result = DID_OK << 16;
1612
1613 return (IPS_SUCCESS_IMM);
1614
1615 case IPS_COPPUSRCMD:
1616 case IPS_COPPIOCCMD:
1617 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) {
1618 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) {
1619 /* wrong size */
1620 DEBUG_VAR(1,
1621 "(%s%d) Passthru structure wrong size",
1622 ips_name, ha->host_num);
1623
1624 return (IPS_FAILURE);
1625 }
1626
1627 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
1628 pt->CoppCP.cmd.flashfw.op_code ==
1629 IPS_CMD_RW_BIOSFW) {
1630 ret = ips_flash_copperhead(ha, pt, scb);
1631 ips_scmd_buf_write(SC, ha->ioctl_data,
1632 sizeof (ips_passthru_t));
1633 return ret;
1634 }
1635 if (ips_usrcmd(ha, pt, scb))
1636 return (IPS_SUCCESS);
1637 else
1638 return (IPS_FAILURE);
1639 }
1640
1641 break;
1642
1643 } /* end switch */
1644
1645 return (IPS_FAILURE);
1646}
1647
1648/****************************************************************************/
1649/* Routine Name: ips_flash_copperhead */
1650/* Routine Description: */
1651/* Flash the BIOS/FW on a Copperhead style controller */
1652/****************************************************************************/
1653static int
1654ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1655{
1656 int datasize;
1657
1658 /* Trombone is the only copperhead that can do packet flash, but only
1659 * for firmware. No one said it had to make sense. */
1660 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) {
1661 if (ips_usrcmd(ha, pt, scb))
1662 return IPS_SUCCESS;
1663 else
1664 return IPS_FAILURE;
1665 }
1666 pt->BasicStatus = 0x0B;
1667 pt->ExtendedStatus = 0;
1668 scb->scsi_cmd->result = DID_OK << 16;
1669 /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */
1670 /* avoid allocating a huge buffer per adapter ( which can fail ). */
1671 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1672 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1673 pt->BasicStatus = 0;
1674 return ips_flash_bios(ha, pt, scb);
1675 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) {
1676 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){
1677 ha->flash_data = ips_FlashData;
1678 ha->flash_busaddr = ips_flashbusaddr;
1679 ha->flash_len = PAGE_SIZE << 7;
1680 ha->flash_datasize = 0;
1681 } else if (!ha->flash_data) {
1682 datasize = pt->CoppCP.cmd.flashfw.total_packets *
1683 pt->CoppCP.cmd.flashfw.count;
1684 ha->flash_data = pci_alloc_consistent(ha->pcidev,
1685 datasize,
1686 &ha->flash_busaddr);
1687 if (!ha->flash_data){
1688 printk(KERN_WARNING "Unable to allocate a flash buffer\n");
1689 return IPS_FAILURE;
1690 }
1691 ha->flash_datasize = 0;
1692 ha->flash_len = datasize;
1693 } else
1694 return IPS_FAILURE;
1695 } else {
1696 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize >
1697 ha->flash_len) {
1698 ips_free_flash_copperhead(ha);
1699 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1700 "failed size sanity check\n");
1701 return IPS_FAILURE;
1702 }
1703 }
1704 if (!ha->flash_data)
1705 return IPS_FAILURE;
1706 pt->BasicStatus = 0;
1707 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1,
1708 pt->CoppCP.cmd.flashfw.count);
1709 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count;
1710 if (pt->CoppCP.cmd.flashfw.packet_num ==
1711 pt->CoppCP.cmd.flashfw.total_packets - 1) {
1712 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE)
1713 return ips_flash_bios(ha, pt, scb);
1714 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE)
1715 return ips_flash_firmware(ha, pt, scb);
1716 }
1717 return IPS_SUCCESS_IMM;
1718}
1719
1720/****************************************************************************/
1721/* Routine Name: ips_flash_bios */
1722/* Routine Description: */
1723/* flashes the bios of a copperhead adapter */
1724/****************************************************************************/
1725static int
1726ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1727{
1728
1729 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1730 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) {
1731 if ((!ha->func.programbios) || (!ha->func.erasebios) ||
1732 (!ha->func.verifybios))
1733 goto error;
1734 if ((*ha->func.erasebios) (ha)) {
1735 DEBUG_VAR(1,
1736 "(%s%d) flash bios failed - unable to erase flash",
1737 ips_name, ha->host_num);
1738 goto error;
1739 } else
1740 if ((*ha->func.programbios) (ha,
1741 ha->flash_data +
1742 IPS_BIOS_HEADER,
1743 ha->flash_datasize -
1744 IPS_BIOS_HEADER, 0)) {
1745 DEBUG_VAR(1,
1746 "(%s%d) flash bios failed - unable to flash",
1747 ips_name, ha->host_num);
1748 goto error;
1749 } else
1750 if ((*ha->func.verifybios) (ha,
1751 ha->flash_data +
1752 IPS_BIOS_HEADER,
1753 ha->flash_datasize -
1754 IPS_BIOS_HEADER, 0)) {
1755 DEBUG_VAR(1,
1756 "(%s%d) flash bios failed - unable to verify flash",
1757 ips_name, ha->host_num);
1758 goto error;
1759 }
1760 ips_free_flash_copperhead(ha);
1761 return IPS_SUCCESS_IMM;
1762 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1763 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1764 if (!ha->func.erasebios)
1765 goto error;
1766 if ((*ha->func.erasebios) (ha)) {
1767 DEBUG_VAR(1,
1768 "(%s%d) flash bios failed - unable to erase flash",
1769 ips_name, ha->host_num);
1770 goto error;
1771 }
1772 return IPS_SUCCESS_IMM;
1773 }
1774 error:
1775 pt->BasicStatus = 0x0B;
1776 pt->ExtendedStatus = 0x00;
1777 ips_free_flash_copperhead(ha);
1778 return IPS_FAILURE;
1779}
1780
1781/****************************************************************************/
1782/* */
1783/* Routine Name: ips_fill_scb_sg_single */
1784/* */
1785/* Routine Description: */
1786/* Fill in a single scb sg_list element from an address */
1787/* return a -1 if a breakup occurred */
1788/****************************************************************************/
1789static int
1790ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr,
1791 ips_scb_t * scb, int indx, unsigned int e_len)
1792{
1793
1794 int ret_val = 0;
1795
1796 if ((scb->data_len + e_len) > ha->max_xfer) {
1797 e_len = ha->max_xfer - scb->data_len;
1798 scb->breakup = indx;
1799 ++scb->sg_break;
1800 ret_val = -1;
1801 } else {
1802 scb->breakup = 0;
1803 scb->sg_break = 0;
1804 }
1805 if (IPS_USE_ENH_SGLIST(ha)) {
1806 scb->sg_list.enh_list[indx].address_lo =
1807 cpu_to_le32(pci_dma_lo32(busaddr));
1808 scb->sg_list.enh_list[indx].address_hi =
1809 cpu_to_le32(pci_dma_hi32(busaddr));
1810 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len);
1811 } else {
1812 scb->sg_list.std_list[indx].address =
1813 cpu_to_le32(pci_dma_lo32(busaddr));
1814 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len);
1815 }
1816
1817 ++scb->sg_len;
1818 scb->data_len += e_len;
1819 return ret_val;
1820}
1821
1822/****************************************************************************/
1823/* Routine Name: ips_flash_firmware */
1824/* Routine Description: */
1825/* flashes the firmware of a copperhead adapter */
1826/****************************************************************************/
1827static int
1828ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1829{
1830 IPS_SG_LIST sg_list;
1831 uint32_t cmd_busaddr;
1832
1833 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE &&
1834 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) {
1835 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND));
1836 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD;
1837 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize);
1838 } else {
1839 pt->BasicStatus = 0x0B;
1840 pt->ExtendedStatus = 0x00;
1841 ips_free_flash_copperhead(ha);
1842 return IPS_FAILURE;
1843 }
1844 /* Save the S/G list pointer so it doesn't get clobbered */
1845 sg_list.list = scb->sg_list.list;
1846 cmd_busaddr = scb->scb_busaddr;
1847 /* copy in the CP */
1848 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1849 /* FIX stuff that might be wrong */
1850 scb->sg_list.list = sg_list.list;
1851 scb->scb_busaddr = cmd_busaddr;
1852 scb->bus = scb->scsi_cmd->device->channel;
1853 scb->target_id = scb->scsi_cmd->device->id;
1854 scb->lun = scb->scsi_cmd->device->lun;
1855 scb->sg_len = 0;
1856 scb->data_len = 0;
1857 scb->flags = 0;
1858 scb->op_code = 0;
1859 scb->callback = ipsintr_done;
1860 scb->timeout = ips_cmd_timeout;
1861
1862 scb->data_len = ha->flash_datasize;
1863 scb->data_busaddr =
1864 pci_map_single(ha->pcidev, ha->flash_data, scb->data_len,
1865 IPS_DMA_DIR(scb));
1866 scb->flags |= IPS_SCB_MAP_SINGLE;
1867 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
1868 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr);
1869 if (pt->TimeOut)
1870 scb->timeout = pt->TimeOut;
1871 scb->scsi_cmd->result = DID_OK << 16;
1872 return IPS_SUCCESS;
1873}
1874
1875/****************************************************************************/
1876/* Routine Name: ips_free_flash_copperhead */
1877/* Routine Description: */
1878/* release the memory resources used to hold the flash image */
1879/****************************************************************************/
1880static void
1881ips_free_flash_copperhead(ips_ha_t * ha)
1882{
1883 if (ha->flash_data == ips_FlashData)
1884 test_and_clear_bit(0, &ips_FlashDataInUse);
1885 else if (ha->flash_data)
1886 pci_free_consistent(ha->pcidev, ha->flash_len, ha->flash_data,
1887 ha->flash_busaddr);
1888 ha->flash_data = NULL;
1889}
1890
1891/****************************************************************************/
1892/* */
1893/* Routine Name: ips_usrcmd */
1894/* */
1895/* Routine Description: */
1896/* */
1897/* Process a user command and make it ready to send */
1898/* */
1899/****************************************************************************/
1900static int
1901ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1902{
1903 IPS_SG_LIST sg_list;
1904 uint32_t cmd_busaddr;
1905
1906 METHOD_TRACE("ips_usrcmd", 1);
1907
1908 if ((!scb) || (!pt) || (!ha))
1909 return (0);
1910
1911 /* Save the S/G list pointer so it doesn't get clobbered */
1912 sg_list.list = scb->sg_list.list;
1913 cmd_busaddr = scb->scb_busaddr;
1914 /* copy in the CP */
1915 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1916 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE));
1917
1918 /* FIX stuff that might be wrong */
1919 scb->sg_list.list = sg_list.list;
1920 scb->scb_busaddr = cmd_busaddr;
1921 scb->bus = scb->scsi_cmd->device->channel;
1922 scb->target_id = scb->scsi_cmd->device->id;
1923 scb->lun = scb->scsi_cmd->device->lun;
1924 scb->sg_len = 0;
1925 scb->data_len = 0;
1926 scb->flags = 0;
1927 scb->op_code = 0;
1928 scb->callback = ipsintr_done;
1929 scb->timeout = ips_cmd_timeout;
1930 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
1931
1932 /* we don't support DCDB/READ/WRITE Scatter Gather */
1933 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) ||
1934 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) ||
1935 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG))
1936 return (0);
1937
1938 if (pt->CmdBSize) {
1939 scb->data_len = pt->CmdBSize;
1940 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t);
1941 } else {
1942 scb->data_busaddr = 0L;
1943 }
1944
1945 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1946 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
1947 (unsigned long) &scb->
1948 dcdb -
1949 (unsigned long) scb);
1950
1951 if (pt->CmdBSize) {
1952 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1953 scb->dcdb.buffer_pointer =
1954 cpu_to_le32(scb->data_busaddr);
1955 else
1956 scb->cmd.basic_io.sg_addr =
1957 cpu_to_le32(scb->data_busaddr);
1958 }
1959
1960 /* set timeouts */
1961 if (pt->TimeOut) {
1962 scb->timeout = pt->TimeOut;
1963
1964 if (pt->TimeOut <= 10)
1965 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10;
1966 else if (pt->TimeOut <= 60)
1967 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60;
1968 else
1969 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M;
1970 }
1971
1972 /* assume success */
1973 scb->scsi_cmd->result = DID_OK << 16;
1974
1975 /* success */
1976 return (1);
1977}
1978
1979/****************************************************************************/
1980/* */
1981/* Routine Name: ips_cleanup_passthru */
1982/* */
1983/* Routine Description: */
1984/* */
1985/* Cleanup after a passthru command */
1986/* */
1987/****************************************************************************/
1988static void
1989ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
1990{
1991 ips_passthru_t *pt;
1992
1993 METHOD_TRACE("ips_cleanup_passthru", 1);
1994
1995 if ((!scb) || (!scb->scsi_cmd) || (!scsi_sglist(scb->scsi_cmd))) {
1996 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru",
1997 ips_name, ha->host_num);
1998
1999 return;
2000 }
2001 pt = (ips_passthru_t *) ha->ioctl_data;
2002
2003 /* Copy data back to the user */
2004 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */
2005 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE));
2006
2007 pt->BasicStatus = scb->basic_status;
2008 pt->ExtendedStatus = scb->extended_status;
2009 pt->AdapterType = ha->ad_type;
2010
2011 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
2012 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD ||
2013 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW))
2014 ips_free_flash_copperhead(ha);
2015
2016 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize);
2017}
2018
2019/****************************************************************************/
2020/* */
2021/* Routine Name: ips_host_info */
2022/* */
2023/* Routine Description: */
2024/* */
2025/* The passthru interface for the driver */
2026/* */
2027/****************************************************************************/
2028static int
2029ips_host_info(ips_ha_t *ha, struct seq_file *m)
2030{
2031 METHOD_TRACE("ips_host_info", 1);
2032
2033 seq_puts(m, "\nIBM ServeRAID General Information:\n\n");
2034
2035 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) &&
2036 (le16_to_cpu(ha->nvram->adapter_type) != 0))
2037 seq_printf(m, "\tController Type : %s\n",
2038 ips_adapter_name[ha->ad_type - 1]);
2039 else
2040 seq_puts(m, "\tController Type : Unknown\n");
2041
2042 if (ha->io_addr)
2043 seq_printf(m,
2044 "\tIO region : 0x%x (%d bytes)\n",
2045 ha->io_addr, ha->io_len);
2046
2047 if (ha->mem_addr) {
2048 seq_printf(m,
2049 "\tMemory region : 0x%x (%d bytes)\n",
2050 ha->mem_addr, ha->mem_len);
2051 seq_printf(m,
2052 "\tShared memory address : 0x%lx\n",
2053 (unsigned long)ha->mem_ptr);
2054 }
2055
2056 seq_printf(m, "\tIRQ number : %d\n", ha->pcidev->irq);
2057
2058 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */
2059 /* That keeps everything happy for "text" operations on the proc file. */
2060
2061 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) {
2062 if (ha->nvram->bios_low[3] == 0) {
2063 seq_printf(m,
2064 "\tBIOS Version : %c%c%c%c%c%c%c\n",
2065 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2066 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2067 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2068 ha->nvram->bios_low[2]);
2069
2070 } else {
2071 seq_printf(m,
2072 "\tBIOS Version : %c%c%c%c%c%c%c%c\n",
2073 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2074 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2075 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2076 ha->nvram->bios_low[2], ha->nvram->bios_low[3]);
2077 }
2078
2079 }
2080
2081 if (ha->enq->CodeBlkVersion[7] == 0) {
2082 seq_printf(m,
2083 "\tFirmware Version : %c%c%c%c%c%c%c\n",
2084 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2085 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2086 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2087 ha->enq->CodeBlkVersion[6]);
2088 } else {
2089 seq_printf(m,
2090 "\tFirmware Version : %c%c%c%c%c%c%c%c\n",
2091 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2092 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2093 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2094 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]);
2095 }
2096
2097 if (ha->enq->BootBlkVersion[7] == 0) {
2098 seq_printf(m,
2099 "\tBoot Block Version : %c%c%c%c%c%c%c\n",
2100 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2101 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2102 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2103 ha->enq->BootBlkVersion[6]);
2104 } else {
2105 seq_printf(m,
2106 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n",
2107 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2108 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2109 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2110 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]);
2111 }
2112
2113 seq_printf(m, "\tDriver Version : %s%s\n",
2114 IPS_VERSION_HIGH, IPS_VERSION_LOW);
2115
2116 seq_printf(m, "\tDriver Build : %d\n",
2117 IPS_BUILD_IDENT);
2118
2119 seq_printf(m, "\tMax Physical Devices : %d\n",
2120 ha->enq->ucMaxPhysicalDevices);
2121 seq_printf(m, "\tMax Active Commands : %d\n",
2122 ha->max_cmds);
2123 seq_printf(m, "\tCurrent Queued Commands : %d\n",
2124 ha->scb_waitlist.count);
2125 seq_printf(m, "\tCurrent Active Commands : %d\n",
2126 ha->scb_activelist.count - ha->num_ioctl);
2127 seq_printf(m, "\tCurrent Queued PT Commands : %d\n",
2128 ha->copp_waitlist.count);
2129 seq_printf(m, "\tCurrent Active PT Commands : %d\n",
2130 ha->num_ioctl);
2131
2132 seq_putc(m, '\n');
2133
2134 return 0;
2135}
2136
2137/****************************************************************************/
2138/* */
2139/* Routine Name: ips_identify_controller */
2140/* */
2141/* Routine Description: */
2142/* */
2143/* Identify this controller */
2144/* */
2145/****************************************************************************/
2146static void
2147ips_identify_controller(ips_ha_t * ha)
2148{
2149 METHOD_TRACE("ips_identify_controller", 1);
2150
2151 switch (ha->pcidev->device) {
2152 case IPS_DEVICEID_COPPERHEAD:
2153 if (ha->pcidev->revision <= IPS_REVID_SERVERAID) {
2154 ha->ad_type = IPS_ADTYPE_SERVERAID;
2155 } else if (ha->pcidev->revision == IPS_REVID_SERVERAID2) {
2156 ha->ad_type = IPS_ADTYPE_SERVERAID2;
2157 } else if (ha->pcidev->revision == IPS_REVID_NAVAJO) {
2158 ha->ad_type = IPS_ADTYPE_NAVAJO;
2159 } else if ((ha->pcidev->revision == IPS_REVID_SERVERAID2)
2160 && (ha->slot_num == 0)) {
2161 ha->ad_type = IPS_ADTYPE_KIOWA;
2162 } else if ((ha->pcidev->revision >= IPS_REVID_CLARINETP1) &&
2163 (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) {
2164 if (ha->enq->ucMaxPhysicalDevices == 15)
2165 ha->ad_type = IPS_ADTYPE_SERVERAID3L;
2166 else
2167 ha->ad_type = IPS_ADTYPE_SERVERAID3;
2168 } else if ((ha->pcidev->revision >= IPS_REVID_TROMBONE32) &&
2169 (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) {
2170 ha->ad_type = IPS_ADTYPE_SERVERAID4H;
2171 }
2172 break;
2173
2174 case IPS_DEVICEID_MORPHEUS:
2175 switch (ha->pcidev->subsystem_device) {
2176 case IPS_SUBDEVICEID_4L:
2177 ha->ad_type = IPS_ADTYPE_SERVERAID4L;
2178 break;
2179
2180 case IPS_SUBDEVICEID_4M:
2181 ha->ad_type = IPS_ADTYPE_SERVERAID4M;
2182 break;
2183
2184 case IPS_SUBDEVICEID_4MX:
2185 ha->ad_type = IPS_ADTYPE_SERVERAID4MX;
2186 break;
2187
2188 case IPS_SUBDEVICEID_4LX:
2189 ha->ad_type = IPS_ADTYPE_SERVERAID4LX;
2190 break;
2191
2192 case IPS_SUBDEVICEID_5I2:
2193 ha->ad_type = IPS_ADTYPE_SERVERAID5I2;
2194 break;
2195
2196 case IPS_SUBDEVICEID_5I1:
2197 ha->ad_type = IPS_ADTYPE_SERVERAID5I1;
2198 break;
2199 }
2200
2201 break;
2202
2203 case IPS_DEVICEID_MARCO:
2204 switch (ha->pcidev->subsystem_device) {
2205 case IPS_SUBDEVICEID_6M:
2206 ha->ad_type = IPS_ADTYPE_SERVERAID6M;
2207 break;
2208 case IPS_SUBDEVICEID_6I:
2209 ha->ad_type = IPS_ADTYPE_SERVERAID6I;
2210 break;
2211 case IPS_SUBDEVICEID_7k:
2212 ha->ad_type = IPS_ADTYPE_SERVERAID7k;
2213 break;
2214 case IPS_SUBDEVICEID_7M:
2215 ha->ad_type = IPS_ADTYPE_SERVERAID7M;
2216 break;
2217 }
2218 break;
2219 }
2220}
2221
2222/****************************************************************************/
2223/* */
2224/* Routine Name: ips_get_bios_version */
2225/* */
2226/* Routine Description: */
2227/* */
2228/* Get the BIOS revision number */
2229/* */
2230/****************************************************************************/
2231static void
2232ips_get_bios_version(ips_ha_t * ha, int intr)
2233{
2234 ips_scb_t *scb;
2235 int ret;
2236 uint8_t major;
2237 uint8_t minor;
2238 uint8_t subminor;
2239 uint8_t *buffer;
2240
2241 METHOD_TRACE("ips_get_bios_version", 1);
2242
2243 major = 0;
2244 minor = 0;
2245
2246 strncpy(ha->bios_version, " ?", 8);
2247
2248 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) {
2249 if (IPS_USE_MEMIO(ha)) {
2250 /* Memory Mapped I/O */
2251
2252 /* test 1st byte */
2253 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2254 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2255 udelay(25); /* 25 us */
2256
2257 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2258 return;
2259
2260 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2261 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2262 udelay(25); /* 25 us */
2263
2264 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2265 return;
2266
2267 /* Get Major version */
2268 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2269 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2270 udelay(25); /* 25 us */
2271
2272 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2273
2274 /* Get Minor version */
2275 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2276 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2277 udelay(25); /* 25 us */
2278 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2279
2280 /* Get SubMinor version */
2281 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2282 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2283 udelay(25); /* 25 us */
2284 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
2285
2286 } else {
2287 /* Programmed I/O */
2288
2289 /* test 1st byte */
2290 outl(0, ha->io_addr + IPS_REG_FLAP);
2291 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2292 udelay(25); /* 25 us */
2293
2294 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2295 return;
2296
2297 outl(1, ha->io_addr + IPS_REG_FLAP);
2298 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2299 udelay(25); /* 25 us */
2300
2301 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
2302 return;
2303
2304 /* Get Major version */
2305 outl(0x1FF, ha->io_addr + IPS_REG_FLAP);
2306 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2307 udelay(25); /* 25 us */
2308
2309 major = inb(ha->io_addr + IPS_REG_FLDP);
2310
2311 /* Get Minor version */
2312 outl(0x1FE, ha->io_addr + IPS_REG_FLAP);
2313 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2314 udelay(25); /* 25 us */
2315
2316 minor = inb(ha->io_addr + IPS_REG_FLDP);
2317
2318 /* Get SubMinor version */
2319 outl(0x1FD, ha->io_addr + IPS_REG_FLAP);
2320 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2321 udelay(25); /* 25 us */
2322
2323 subminor = inb(ha->io_addr + IPS_REG_FLDP);
2324
2325 }
2326 } else {
2327 /* Morpheus Family - Send Command to the card */
2328
2329 buffer = ha->ioctl_data;
2330
2331 memset(buffer, 0, 0x1000);
2332
2333 scb = &ha->scbs[ha->max_cmds - 1];
2334
2335 ips_init_scb(ha, scb);
2336
2337 scb->timeout = ips_cmd_timeout;
2338 scb->cdb[0] = IPS_CMD_RW_BIOSFW;
2339
2340 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW;
2341 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
2342 scb->cmd.flashfw.type = 1;
2343 scb->cmd.flashfw.direction = 0;
2344 scb->cmd.flashfw.count = cpu_to_le32(0x800);
2345 scb->cmd.flashfw.total_packets = 1;
2346 scb->cmd.flashfw.packet_num = 0;
2347 scb->data_len = 0x1000;
2348 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr;
2349
2350 /* issue the command */
2351 if (((ret =
2352 ips_send_wait(ha, scb, ips_cmd_timeout,
2353 intr)) == IPS_FAILURE)
2354 || (ret == IPS_SUCCESS_IMM)
2355 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
2356 /* Error occurred */
2357
2358 return;
2359 }
2360
2361 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) {
2362 major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */
2363 minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */
2364 subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */
2365 } else {
2366 return;
2367 }
2368 }
2369
2370 ha->bios_version[0] = hex_asc_upper_hi(major);
2371 ha->bios_version[1] = '.';
2372 ha->bios_version[2] = hex_asc_upper_lo(major);
2373 ha->bios_version[3] = hex_asc_upper_lo(subminor);
2374 ha->bios_version[4] = '.';
2375 ha->bios_version[5] = hex_asc_upper_hi(minor);
2376 ha->bios_version[6] = hex_asc_upper_lo(minor);
2377 ha->bios_version[7] = 0;
2378}
2379
2380/****************************************************************************/
2381/* */
2382/* Routine Name: ips_hainit */
2383/* */
2384/* Routine Description: */
2385/* */
2386/* Initialize the controller */
2387/* */
2388/* NOTE: Assumes to be called from with a lock */
2389/* */
2390/****************************************************************************/
2391static int
2392ips_hainit(ips_ha_t * ha)
2393{
2394 int i;
2395 struct timeval tv;
2396
2397 METHOD_TRACE("ips_hainit", 1);
2398
2399 if (!ha)
2400 return (0);
2401
2402 if (ha->func.statinit)
2403 (*ha->func.statinit) (ha);
2404
2405 if (ha->func.enableint)
2406 (*ha->func.enableint) (ha);
2407
2408 /* Send FFDC */
2409 ha->reset_count = 1;
2410 do_gettimeofday(&tv);
2411 ha->last_ffdc = tv.tv_sec;
2412 ips_ffdc_reset(ha, IPS_INTR_IORL);
2413
2414 if (!ips_read_config(ha, IPS_INTR_IORL)) {
2415 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2416 "unable to read config from controller.\n");
2417
2418 return (0);
2419 }
2420 /* end if */
2421 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) {
2422 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2423 "unable to read controller status.\n");
2424
2425 return (0);
2426 }
2427
2428 /* Identify this controller */
2429 ips_identify_controller(ha);
2430
2431 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) {
2432 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2433 "unable to read subsystem parameters.\n");
2434
2435 return (0);
2436 }
2437
2438 /* write nvram user page 5 */
2439 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) {
2440 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2441 "unable to write driver info to controller.\n");
2442
2443 return (0);
2444 }
2445
2446 /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */
2447 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1))
2448 ips_clear_adapter(ha, IPS_INTR_IORL);
2449
2450 /* set limits on SID, LUN, BUS */
2451 ha->ntargets = IPS_MAX_TARGETS + 1;
2452 ha->nlun = 1;
2453 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1;
2454
2455 switch (ha->conf->logical_drive[0].ucStripeSize) {
2456 case 4:
2457 ha->max_xfer = 0x10000;
2458 break;
2459
2460 case 5:
2461 ha->max_xfer = 0x20000;
2462 break;
2463
2464 case 6:
2465 ha->max_xfer = 0x40000;
2466 break;
2467
2468 case 7:
2469 default:
2470 ha->max_xfer = 0x80000;
2471 break;
2472 }
2473
2474 /* setup max concurrent commands */
2475 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) {
2476 /* Use the new method */
2477 ha->max_cmds = ha->enq->ucConcurrentCmdCount;
2478 } else {
2479 /* use the old method */
2480 switch (ha->conf->logical_drive[0].ucStripeSize) {
2481 case 4:
2482 ha->max_cmds = 32;
2483 break;
2484
2485 case 5:
2486 ha->max_cmds = 16;
2487 break;
2488
2489 case 6:
2490 ha->max_cmds = 8;
2491 break;
2492
2493 case 7:
2494 default:
2495 ha->max_cmds = 4;
2496 break;
2497 }
2498 }
2499
2500 /* Limit the Active Commands on a Lite Adapter */
2501 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) ||
2502 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) ||
2503 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) {
2504 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds))
2505 ha->max_cmds = MaxLiteCmds;
2506 }
2507
2508 /* set controller IDs */
2509 ha->ha_id[0] = IPS_ADAPTER_ID;
2510 for (i = 1; i < ha->nbus; i++) {
2511 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f;
2512 ha->dcdb_active[i - 1] = 0;
2513 }
2514
2515 return (1);
2516}
2517
2518/****************************************************************************/
2519/* */
2520/* Routine Name: ips_next */
2521/* */
2522/* Routine Description: */
2523/* */
2524/* Take the next command off the queue and send it to the controller */
2525/* */
2526/****************************************************************************/
2527static void
2528ips_next(ips_ha_t * ha, int intr)
2529{
2530 ips_scb_t *scb;
2531 struct scsi_cmnd *SC;
2532 struct scsi_cmnd *p;
2533 struct scsi_cmnd *q;
2534 ips_copp_wait_item_t *item;
2535 int ret;
2536 struct Scsi_Host *host;
2537 METHOD_TRACE("ips_next", 1);
2538
2539 if (!ha)
2540 return;
2541 host = ips_sh[ha->host_num];
2542 /*
2543 * Block access to the queue function so
2544 * this command won't time out
2545 */
2546 if (intr == IPS_INTR_ON)
2547 spin_lock(host->host_lock);
2548
2549 if ((ha->subsys->param[3] & 0x300000)
2550 && (ha->scb_activelist.count == 0)) {
2551 struct timeval tv;
2552
2553 do_gettimeofday(&tv);
2554
2555 if (tv.tv_sec - ha->last_ffdc > IPS_SECS_8HOURS) {
2556 ha->last_ffdc = tv.tv_sec;
2557 ips_ffdc_time(ha);
2558 }
2559 }
2560
2561 /*
2562 * Send passthru commands
2563 * These have priority over normal I/O
2564 * but shouldn't affect performance too much
2565 * since we limit the number that can be active
2566 * on the card at any one time
2567 */
2568 while ((ha->num_ioctl < IPS_MAX_IOCTL) &&
2569 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) {
2570
2571 item = ips_removeq_copp_head(&ha->copp_waitlist);
2572 ha->num_ioctl++;
2573 if (intr == IPS_INTR_ON)
2574 spin_unlock(host->host_lock);
2575 scb->scsi_cmd = item->scsi_cmd;
2576 kfree(item);
2577
2578 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr);
2579
2580 if (intr == IPS_INTR_ON)
2581 spin_lock(host->host_lock);
2582 switch (ret) {
2583 case IPS_FAILURE:
2584 if (scb->scsi_cmd) {
2585 scb->scsi_cmd->result = DID_ERROR << 16;
2586 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2587 }
2588
2589 ips_freescb(ha, scb);
2590 break;
2591 case IPS_SUCCESS_IMM:
2592 if (scb->scsi_cmd) {
2593 scb->scsi_cmd->result = DID_OK << 16;
2594 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2595 }
2596
2597 ips_freescb(ha, scb);
2598 break;
2599 default:
2600 break;
2601 } /* end case */
2602
2603 if (ret != IPS_SUCCESS) {
2604 ha->num_ioctl--;
2605 continue;
2606 }
2607
2608 ret = ips_send_cmd(ha, scb);
2609
2610 if (ret == IPS_SUCCESS)
2611 ips_putq_scb_head(&ha->scb_activelist, scb);
2612 else
2613 ha->num_ioctl--;
2614
2615 switch (ret) {
2616 case IPS_FAILURE:
2617 if (scb->scsi_cmd) {
2618 scb->scsi_cmd->result = DID_ERROR << 16;
2619 }
2620
2621 ips_freescb(ha, scb);
2622 break;
2623 case IPS_SUCCESS_IMM:
2624 ips_freescb(ha, scb);
2625 break;
2626 default:
2627 break;
2628 } /* end case */
2629
2630 }
2631
2632 /*
2633 * Send "Normal" I/O commands
2634 */
2635
2636 p = ha->scb_waitlist.head;
2637 while ((p) && (scb = ips_getscb(ha))) {
2638 if ((scmd_channel(p) > 0)
2639 && (ha->
2640 dcdb_active[scmd_channel(p) -
2641 1] & (1 << scmd_id(p)))) {
2642 ips_freescb(ha, scb);
2643 p = (struct scsi_cmnd *) p->host_scribble;
2644 continue;
2645 }
2646
2647 q = p;
2648 SC = ips_removeq_wait(&ha->scb_waitlist, q);
2649
2650 if (intr == IPS_INTR_ON)
2651 spin_unlock(host->host_lock); /* Unlock HA after command is taken off queue */
2652
2653 SC->result = DID_OK;
2654 SC->host_scribble = NULL;
2655
2656 scb->target_id = SC->device->id;
2657 scb->lun = SC->device->lun;
2658 scb->bus = SC->device->channel;
2659 scb->scsi_cmd = SC;
2660 scb->breakup = 0;
2661 scb->data_len = 0;
2662 scb->callback = ipsintr_done;
2663 scb->timeout = ips_cmd_timeout;
2664 memset(&scb->cmd, 0, 16);
2665
2666 /* copy in the CDB */
2667 memcpy(scb->cdb, SC->cmnd, SC->cmd_len);
2668
2669 scb->sg_count = scsi_dma_map(SC);
2670 BUG_ON(scb->sg_count < 0);
2671 if (scb->sg_count) {
2672 struct scatterlist *sg;
2673 int i;
2674
2675 scb->flags |= IPS_SCB_MAP_SG;
2676
2677 scsi_for_each_sg(SC, sg, scb->sg_count, i) {
2678 if (ips_fill_scb_sg_single
2679 (ha, sg_dma_address(sg), scb, i,
2680 sg_dma_len(sg)) < 0)
2681 break;
2682 }
2683 scb->dcdb.transfer_length = scb->data_len;
2684 } else {
2685 scb->data_busaddr = 0L;
2686 scb->sg_len = 0;
2687 scb->data_len = 0;
2688 scb->dcdb.transfer_length = 0;
2689 }
2690
2691 scb->dcdb.cmd_attribute =
2692 ips_command_direction[scb->scsi_cmd->cmnd[0]];
2693
2694 /* Allow a WRITE BUFFER Command to Have no Data */
2695 /* This is Used by Tape Flash Utilites */
2696 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) &&
2697 (scb->data_len == 0))
2698 scb->dcdb.cmd_attribute = 0;
2699
2700 if (!(scb->dcdb.cmd_attribute & 0x3))
2701 scb->dcdb.transfer_length = 0;
2702
2703 if (scb->data_len >= IPS_MAX_XFER) {
2704 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
2705 scb->dcdb.transfer_length = 0;
2706 }
2707 if (intr == IPS_INTR_ON)
2708 spin_lock(host->host_lock);
2709
2710 ret = ips_send_cmd(ha, scb);
2711
2712 switch (ret) {
2713 case IPS_SUCCESS:
2714 ips_putq_scb_head(&ha->scb_activelist, scb);
2715 break;
2716 case IPS_FAILURE:
2717 if (scb->scsi_cmd) {
2718 scb->scsi_cmd->result = DID_ERROR << 16;
2719 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2720 }
2721
2722 if (scb->bus)
2723 ha->dcdb_active[scb->bus - 1] &=
2724 ~(1 << scb->target_id);
2725
2726 ips_freescb(ha, scb);
2727 break;
2728 case IPS_SUCCESS_IMM:
2729 if (scb->scsi_cmd)
2730 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2731
2732 if (scb->bus)
2733 ha->dcdb_active[scb->bus - 1] &=
2734 ~(1 << scb->target_id);
2735
2736 ips_freescb(ha, scb);
2737 break;
2738 default:
2739 break;
2740 } /* end case */
2741
2742 p = (struct scsi_cmnd *) p->host_scribble;
2743
2744 } /* end while */
2745
2746 if (intr == IPS_INTR_ON)
2747 spin_unlock(host->host_lock);
2748}
2749
2750/****************************************************************************/
2751/* */
2752/* Routine Name: ips_putq_scb_head */
2753/* */
2754/* Routine Description: */
2755/* */
2756/* Add an item to the head of the queue */
2757/* */
2758/* ASSUMED to be called from within the HA lock */
2759/* */
2760/****************************************************************************/
2761static void
2762ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item)
2763{
2764 METHOD_TRACE("ips_putq_scb_head", 1);
2765
2766 if (!item)
2767 return;
2768
2769 item->q_next = queue->head;
2770 queue->head = item;
2771
2772 if (!queue->tail)
2773 queue->tail = item;
2774
2775 queue->count++;
2776}
2777
2778/****************************************************************************/
2779/* */
2780/* Routine Name: ips_removeq_scb_head */
2781/* */
2782/* Routine Description: */
2783/* */
2784/* Remove the head of the queue */
2785/* */
2786/* ASSUMED to be called from within the HA lock */
2787/* */
2788/****************************************************************************/
2789static ips_scb_t *
2790ips_removeq_scb_head(ips_scb_queue_t * queue)
2791{
2792 ips_scb_t *item;
2793
2794 METHOD_TRACE("ips_removeq_scb_head", 1);
2795
2796 item = queue->head;
2797
2798 if (!item) {
2799 return (NULL);
2800 }
2801
2802 queue->head = item->q_next;
2803 item->q_next = NULL;
2804
2805 if (queue->tail == item)
2806 queue->tail = NULL;
2807
2808 queue->count--;
2809
2810 return (item);
2811}
2812
2813/****************************************************************************/
2814/* */
2815/* Routine Name: ips_removeq_scb */
2816/* */
2817/* Routine Description: */
2818/* */
2819/* Remove an item from a queue */
2820/* */
2821/* ASSUMED to be called from within the HA lock */
2822/* */
2823/****************************************************************************/
2824static ips_scb_t *
2825ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item)
2826{
2827 ips_scb_t *p;
2828
2829 METHOD_TRACE("ips_removeq_scb", 1);
2830
2831 if (!item)
2832 return (NULL);
2833
2834 if (item == queue->head) {
2835 return (ips_removeq_scb_head(queue));
2836 }
2837
2838 p = queue->head;
2839
2840 while ((p) && (item != p->q_next))
2841 p = p->q_next;
2842
2843 if (p) {
2844 /* found a match */
2845 p->q_next = item->q_next;
2846
2847 if (!item->q_next)
2848 queue->tail = p;
2849
2850 item->q_next = NULL;
2851 queue->count--;
2852
2853 return (item);
2854 }
2855
2856 return (NULL);
2857}
2858
2859/****************************************************************************/
2860/* */
2861/* Routine Name: ips_putq_wait_tail */
2862/* */
2863/* Routine Description: */
2864/* */
2865/* Add an item to the tail of the queue */
2866/* */
2867/* ASSUMED to be called from within the HA lock */
2868/* */
2869/****************************************************************************/
2870static void ips_putq_wait_tail(ips_wait_queue_entry_t *queue, struct scsi_cmnd *item)
2871{
2872 METHOD_TRACE("ips_putq_wait_tail", 1);
2873
2874 if (!item)
2875 return;
2876
2877 item->host_scribble = NULL;
2878
2879 if (queue->tail)
2880 queue->tail->host_scribble = (char *) item;
2881
2882 queue->tail = item;
2883
2884 if (!queue->head)
2885 queue->head = item;
2886
2887 queue->count++;
2888}
2889
2890/****************************************************************************/
2891/* */
2892/* Routine Name: ips_removeq_wait_head */
2893/* */
2894/* Routine Description: */
2895/* */
2896/* Remove the head of the queue */
2897/* */
2898/* ASSUMED to be called from within the HA lock */
2899/* */
2900/****************************************************************************/
2901static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *queue)
2902{
2903 struct scsi_cmnd *item;
2904
2905 METHOD_TRACE("ips_removeq_wait_head", 1);
2906
2907 item = queue->head;
2908
2909 if (!item) {
2910 return (NULL);
2911 }
2912
2913 queue->head = (struct scsi_cmnd *) item->host_scribble;
2914 item->host_scribble = NULL;
2915
2916 if (queue->tail == item)
2917 queue->tail = NULL;
2918
2919 queue->count--;
2920
2921 return (item);
2922}
2923
2924/****************************************************************************/
2925/* */
2926/* Routine Name: ips_removeq_wait */
2927/* */
2928/* Routine Description: */
2929/* */
2930/* Remove an item from a queue */
2931/* */
2932/* ASSUMED to be called from within the HA lock */
2933/* */
2934/****************************************************************************/
2935static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *queue,
2936 struct scsi_cmnd *item)
2937{
2938 struct scsi_cmnd *p;
2939
2940 METHOD_TRACE("ips_removeq_wait", 1);
2941
2942 if (!item)
2943 return (NULL);
2944
2945 if (item == queue->head) {
2946 return (ips_removeq_wait_head(queue));
2947 }
2948
2949 p = queue->head;
2950
2951 while ((p) && (item != (struct scsi_cmnd *) p->host_scribble))
2952 p = (struct scsi_cmnd *) p->host_scribble;
2953
2954 if (p) {
2955 /* found a match */
2956 p->host_scribble = item->host_scribble;
2957
2958 if (!item->host_scribble)
2959 queue->tail = p;
2960
2961 item->host_scribble = NULL;
2962 queue->count--;
2963
2964 return (item);
2965 }
2966
2967 return (NULL);
2968}
2969
2970/****************************************************************************/
2971/* */
2972/* Routine Name: ips_putq_copp_tail */
2973/* */
2974/* Routine Description: */
2975/* */
2976/* Add an item to the tail of the queue */
2977/* */
2978/* ASSUMED to be called from within the HA lock */
2979/* */
2980/****************************************************************************/
2981static void
2982ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
2983{
2984 METHOD_TRACE("ips_putq_copp_tail", 1);
2985
2986 if (!item)
2987 return;
2988
2989 item->next = NULL;
2990
2991 if (queue->tail)
2992 queue->tail->next = item;
2993
2994 queue->tail = item;
2995
2996 if (!queue->head)
2997 queue->head = item;
2998
2999 queue->count++;
3000}
3001
3002/****************************************************************************/
3003/* */
3004/* Routine Name: ips_removeq_copp_head */
3005/* */
3006/* Routine Description: */
3007/* */
3008/* Remove the head of the queue */
3009/* */
3010/* ASSUMED to be called from within the HA lock */
3011/* */
3012/****************************************************************************/
3013static ips_copp_wait_item_t *
3014ips_removeq_copp_head(ips_copp_queue_t * queue)
3015{
3016 ips_copp_wait_item_t *item;
3017
3018 METHOD_TRACE("ips_removeq_copp_head", 1);
3019
3020 item = queue->head;
3021
3022 if (!item) {
3023 return (NULL);
3024 }
3025
3026 queue->head = item->next;
3027 item->next = NULL;
3028
3029 if (queue->tail == item)
3030 queue->tail = NULL;
3031
3032 queue->count--;
3033
3034 return (item);
3035}
3036
3037/****************************************************************************/
3038/* */
3039/* Routine Name: ips_removeq_copp */
3040/* */
3041/* Routine Description: */
3042/* */
3043/* Remove an item from a queue */
3044/* */
3045/* ASSUMED to be called from within the HA lock */
3046/* */
3047/****************************************************************************/
3048static ips_copp_wait_item_t *
3049ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3050{
3051 ips_copp_wait_item_t *p;
3052
3053 METHOD_TRACE("ips_removeq_copp", 1);
3054
3055 if (!item)
3056 return (NULL);
3057
3058 if (item == queue->head) {
3059 return (ips_removeq_copp_head(queue));
3060 }
3061
3062 p = queue->head;
3063
3064 while ((p) && (item != p->next))
3065 p = p->next;
3066
3067 if (p) {
3068 /* found a match */
3069 p->next = item->next;
3070
3071 if (!item->next)
3072 queue->tail = p;
3073
3074 item->next = NULL;
3075 queue->count--;
3076
3077 return (item);
3078 }
3079
3080 return (NULL);
3081}
3082
3083/****************************************************************************/
3084/* */
3085/* Routine Name: ipsintr_blocking */
3086/* */
3087/* Routine Description: */
3088/* */
3089/* Finalize an interrupt for internal commands */
3090/* */
3091/****************************************************************************/
3092static void
3093ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb)
3094{
3095 METHOD_TRACE("ipsintr_blocking", 2);
3096
3097 ips_freescb(ha, scb);
3098 if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) {
3099 ha->waitflag = FALSE;
3100
3101 return;
3102 }
3103}
3104
3105/****************************************************************************/
3106/* */
3107/* Routine Name: ipsintr_done */
3108/* */
3109/* Routine Description: */
3110/* */
3111/* Finalize an interrupt for non-internal commands */
3112/* */
3113/****************************************************************************/
3114static void
3115ipsintr_done(ips_ha_t * ha, ips_scb_t * scb)
3116{
3117 METHOD_TRACE("ipsintr_done", 2);
3118
3119 if (!scb) {
3120 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3121 "Spurious interrupt; scb NULL.\n");
3122
3123 return;
3124 }
3125
3126 if (scb->scsi_cmd == NULL) {
3127 /* unexpected interrupt */
3128 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3129 "Spurious interrupt; scsi_cmd not set.\n");
3130
3131 return;
3132 }
3133
3134 ips_done(ha, scb);
3135}
3136
3137/****************************************************************************/
3138/* */
3139/* Routine Name: ips_done */
3140/* */
3141/* Routine Description: */
3142/* */
3143/* Do housekeeping on completed commands */
3144/* ASSUMED to be called form within the request lock */
3145/****************************************************************************/
3146static void
3147ips_done(ips_ha_t * ha, ips_scb_t * scb)
3148{
3149 int ret;
3150
3151 METHOD_TRACE("ips_done", 1);
3152
3153 if (!scb)
3154 return;
3155
3156 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) {
3157 ips_cleanup_passthru(ha, scb);
3158 ha->num_ioctl--;
3159 } else {
3160 /*
3161 * Check to see if this command had too much
3162 * data and had to be broke up. If so, queue
3163 * the rest of the data and continue.
3164 */
3165 if ((scb->breakup) || (scb->sg_break)) {
3166 struct scatterlist *sg;
3167 int i, sg_dma_index, ips_sg_index = 0;
3168
3169 /* we had a data breakup */
3170 scb->data_len = 0;
3171
3172 sg = scsi_sglist(scb->scsi_cmd);
3173
3174 /* Spin forward to last dma chunk */
3175 sg_dma_index = scb->breakup;
3176 for (i = 0; i < scb->breakup; i++)
3177 sg = sg_next(sg);
3178
3179 /* Take care of possible partial on last chunk */
3180 ips_fill_scb_sg_single(ha,
3181 sg_dma_address(sg),
3182 scb, ips_sg_index++,
3183 sg_dma_len(sg));
3184
3185 for (; sg_dma_index < scsi_sg_count(scb->scsi_cmd);
3186 sg_dma_index++, sg = sg_next(sg)) {
3187 if (ips_fill_scb_sg_single
3188 (ha,
3189 sg_dma_address(sg),
3190 scb, ips_sg_index++,
3191 sg_dma_len(sg)) < 0)
3192 break;
3193 }
3194
3195 scb->dcdb.transfer_length = scb->data_len;
3196 scb->dcdb.cmd_attribute |=
3197 ips_command_direction[scb->scsi_cmd->cmnd[0]];
3198
3199 if (!(scb->dcdb.cmd_attribute & 0x3))
3200 scb->dcdb.transfer_length = 0;
3201
3202 if (scb->data_len >= IPS_MAX_XFER) {
3203 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
3204 scb->dcdb.transfer_length = 0;
3205 }
3206
3207 ret = ips_send_cmd(ha, scb);
3208
3209 switch (ret) {
3210 case IPS_FAILURE:
3211 if (scb->scsi_cmd) {
3212 scb->scsi_cmd->result = DID_ERROR << 16;
3213 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3214 }
3215
3216 ips_freescb(ha, scb);
3217 break;
3218 case IPS_SUCCESS_IMM:
3219 if (scb->scsi_cmd) {
3220 scb->scsi_cmd->result = DID_ERROR << 16;
3221 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3222 }
3223
3224 ips_freescb(ha, scb);
3225 break;
3226 default:
3227 break;
3228 } /* end case */
3229
3230 return;
3231 }
3232 } /* end if passthru */
3233
3234 if (scb->bus) {
3235 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id);
3236 }
3237
3238 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3239
3240 ips_freescb(ha, scb);
3241}
3242
3243/****************************************************************************/
3244/* */
3245/* Routine Name: ips_map_status */
3246/* */
3247/* Routine Description: */
3248/* */
3249/* Map Controller Error codes to Linux Error Codes */
3250/* */
3251/****************************************************************************/
3252static int
3253ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3254{
3255 int errcode;
3256 int device_error;
3257 uint32_t transfer_len;
3258 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3259 IPS_SCSI_INQ_DATA inquiryData;
3260
3261 METHOD_TRACE("ips_map_status", 1);
3262
3263 if (scb->bus) {
3264 DEBUG_VAR(2,
3265 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x",
3266 ips_name, ha->host_num,
3267 scb->scsi_cmd->device->channel,
3268 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun,
3269 scb->basic_status, scb->extended_status,
3270 scb->extended_status ==
3271 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0,
3272 scb->extended_status ==
3273 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0,
3274 scb->extended_status ==
3275 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0);
3276 }
3277
3278 /* default driver error */
3279 errcode = DID_ERROR;
3280 device_error = 0;
3281
3282 switch (scb->basic_status & IPS_GSC_STATUS_MASK) {
3283 case IPS_CMD_TIMEOUT:
3284 errcode = DID_TIME_OUT;
3285 break;
3286
3287 case IPS_INVAL_OPCO:
3288 case IPS_INVAL_CMD_BLK:
3289 case IPS_INVAL_PARM_BLK:
3290 case IPS_LD_ERROR:
3291 case IPS_CMD_CMPLT_WERROR:
3292 break;
3293
3294 case IPS_PHYS_DRV_ERROR:
3295 switch (scb->extended_status) {
3296 case IPS_ERR_SEL_TO:
3297 if (scb->bus)
3298 errcode = DID_NO_CONNECT;
3299
3300 break;
3301
3302 case IPS_ERR_OU_RUN:
3303 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) ||
3304 (scb->cmd.dcdb.op_code ==
3305 IPS_CMD_EXTENDED_DCDB_SG)) {
3306 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3307 transfer_len = tapeDCDB->transfer_length;
3308 } else {
3309 transfer_len =
3310 (uint32_t) scb->dcdb.transfer_length;
3311 }
3312
3313 if ((scb->bus) && (transfer_len < scb->data_len)) {
3314 /* Underrun - set default to no error */
3315 errcode = DID_OK;
3316
3317 /* Restrict access to physical DASD */
3318 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3319 ips_scmd_buf_read(scb->scsi_cmd,
3320 &inquiryData, sizeof (inquiryData));
3321 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) {
3322 errcode = DID_TIME_OUT;
3323 break;
3324 }
3325 }
3326 } else
3327 errcode = DID_ERROR;
3328
3329 break;
3330
3331 case IPS_ERR_RECOVERY:
3332 /* don't fail recovered errors */
3333 if (scb->bus)
3334 errcode = DID_OK;
3335
3336 break;
3337
3338 case IPS_ERR_HOST_RESET:
3339 case IPS_ERR_DEV_RESET:
3340 errcode = DID_RESET;
3341 break;
3342
3343 case IPS_ERR_CKCOND:
3344 if (scb->bus) {
3345 if ((scb->cmd.dcdb.op_code ==
3346 IPS_CMD_EXTENDED_DCDB)
3347 || (scb->cmd.dcdb.op_code ==
3348 IPS_CMD_EXTENDED_DCDB_SG)) {
3349 tapeDCDB =
3350 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3351 memcpy(scb->scsi_cmd->sense_buffer,
3352 tapeDCDB->sense_info,
3353 SCSI_SENSE_BUFFERSIZE);
3354 } else {
3355 memcpy(scb->scsi_cmd->sense_buffer,
3356 scb->dcdb.sense_info,
3357 SCSI_SENSE_BUFFERSIZE);
3358 }
3359 device_error = 2; /* check condition */
3360 }
3361
3362 errcode = DID_OK;
3363
3364 break;
3365
3366 default:
3367 errcode = DID_ERROR;
3368 break;
3369
3370 } /* end switch */
3371 } /* end switch */
3372
3373 scb->scsi_cmd->result = device_error | (errcode << 16);
3374
3375 return (1);
3376}
3377
3378/****************************************************************************/
3379/* */
3380/* Routine Name: ips_send_wait */
3381/* */
3382/* Routine Description: */
3383/* */
3384/* Send a command to the controller and wait for it to return */
3385/* */
3386/* The FFDC Time Stamp use this function for the callback, but doesn't */
3387/* actually need to wait. */
3388/****************************************************************************/
3389static int
3390ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr)
3391{
3392 int ret;
3393
3394 METHOD_TRACE("ips_send_wait", 1);
3395
3396 if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */
3397 ha->waitflag = TRUE;
3398 ha->cmd_in_progress = scb->cdb[0];
3399 }
3400 scb->callback = ipsintr_blocking;
3401 ret = ips_send_cmd(ha, scb);
3402
3403 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM))
3404 return (ret);
3405
3406 if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */
3407 ret = ips_wait(ha, timeout, intr);
3408
3409 return (ret);
3410}
3411
3412/****************************************************************************/
3413/* */
3414/* Routine Name: ips_scmd_buf_write */
3415/* */
3416/* Routine Description: */
3417/* Write data to struct scsi_cmnd request_buffer at proper offsets */
3418/****************************************************************************/
3419static void
3420ips_scmd_buf_write(struct scsi_cmnd *scmd, void *data, unsigned int count)
3421{
3422 unsigned long flags;
3423
3424 local_irq_save(flags);
3425 scsi_sg_copy_from_buffer(scmd, data, count);
3426 local_irq_restore(flags);
3427}
3428
3429/****************************************************************************/
3430/* */
3431/* Routine Name: ips_scmd_buf_read */
3432/* */
3433/* Routine Description: */
3434/* Copy data from a struct scsi_cmnd to a new, linear buffer */
3435/****************************************************************************/
3436static void
3437ips_scmd_buf_read(struct scsi_cmnd *scmd, void *data, unsigned int count)
3438{
3439 unsigned long flags;
3440
3441 local_irq_save(flags);
3442 scsi_sg_copy_to_buffer(scmd, data, count);
3443 local_irq_restore(flags);
3444}
3445
3446/****************************************************************************/
3447/* */
3448/* Routine Name: ips_send_cmd */
3449/* */
3450/* Routine Description: */
3451/* */
3452/* Map SCSI commands to ServeRAID commands for logical drives */
3453/* */
3454/****************************************************************************/
3455static int
3456ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
3457{
3458 int ret;
3459 char *sp;
3460 int device_error;
3461 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3462 int TimeOut;
3463
3464 METHOD_TRACE("ips_send_cmd", 1);
3465
3466 ret = IPS_SUCCESS;
3467
3468 if (!scb->scsi_cmd) {
3469 /* internal command */
3470
3471 if (scb->bus > 0) {
3472 /* Controller commands can't be issued */
3473 /* to real devices -- fail them */
3474 if ((ha->waitflag == TRUE) &&
3475 (ha->cmd_in_progress == scb->cdb[0])) {
3476 ha->waitflag = FALSE;
3477 }
3478
3479 return (1);
3480 }
3481 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) {
3482 /* command to logical bus -- interpret */
3483 ret = IPS_SUCCESS_IMM;
3484
3485 switch (scb->scsi_cmd->cmnd[0]) {
3486 case ALLOW_MEDIUM_REMOVAL:
3487 case REZERO_UNIT:
3488 case ERASE:
3489 case WRITE_FILEMARKS:
3490 case SPACE:
3491 scb->scsi_cmd->result = DID_ERROR << 16;
3492 break;
3493
3494 case START_STOP:
3495 scb->scsi_cmd->result = DID_OK << 16;
3496
3497 case TEST_UNIT_READY:
3498 case INQUIRY:
3499 if (scb->target_id == IPS_ADAPTER_ID) {
3500 /*
3501 * Either we have a TUR
3502 * or we have a SCSI inquiry
3503 */
3504 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY)
3505 scb->scsi_cmd->result = DID_OK << 16;
3506
3507 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3508 IPS_SCSI_INQ_DATA inquiry;
3509
3510 memset(&inquiry, 0,
3511 sizeof (IPS_SCSI_INQ_DATA));
3512
3513 inquiry.DeviceType =
3514 IPS_SCSI_INQ_TYPE_PROCESSOR;
3515 inquiry.DeviceTypeQualifier =
3516 IPS_SCSI_INQ_LU_CONNECTED;
3517 inquiry.Version = IPS_SCSI_INQ_REV2;
3518 inquiry.ResponseDataFormat =
3519 IPS_SCSI_INQ_RD_REV2;
3520 inquiry.AdditionalLength = 31;
3521 inquiry.Flags[0] =
3522 IPS_SCSI_INQ_Address16;
3523 inquiry.Flags[1] =
3524 IPS_SCSI_INQ_WBus16 |
3525 IPS_SCSI_INQ_Sync;
3526 strncpy(inquiry.VendorId, "IBM ",
3527 8);
3528 strncpy(inquiry.ProductId,
3529 "SERVERAID ", 16);
3530 strncpy(inquiry.ProductRevisionLevel,
3531 "1.00", 4);
3532
3533 ips_scmd_buf_write(scb->scsi_cmd,
3534 &inquiry,
3535 sizeof (inquiry));
3536
3537 scb->scsi_cmd->result = DID_OK << 16;
3538 }
3539 } else {
3540 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3541 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3542 scb->cmd.logical_info.reserved = 0;
3543 scb->cmd.logical_info.reserved2 = 0;
3544 scb->data_len = sizeof (IPS_LD_INFO);
3545 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3546 scb->flags = 0;
3547 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3548 ret = IPS_SUCCESS;
3549 }
3550
3551 break;
3552
3553 case REQUEST_SENSE:
3554 ips_reqsen(ha, scb);
3555 scb->scsi_cmd->result = DID_OK << 16;
3556 break;
3557
3558 case READ_6:
3559 case WRITE_6:
3560 if (!scb->sg_len) {
3561 scb->cmd.basic_io.op_code =
3562 (scb->scsi_cmd->cmnd[0] ==
3563 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE;
3564 scb->cmd.basic_io.enhanced_sg = 0;
3565 scb->cmd.basic_io.sg_addr =
3566 cpu_to_le32(scb->data_busaddr);
3567 } else {
3568 scb->cmd.basic_io.op_code =
3569 (scb->scsi_cmd->cmnd[0] ==
3570 READ_6) ? IPS_CMD_READ_SG :
3571 IPS_CMD_WRITE_SG;
3572 scb->cmd.basic_io.enhanced_sg =
3573 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3574 scb->cmd.basic_io.sg_addr =
3575 cpu_to_le32(scb->sg_busaddr);
3576 }
3577
3578 scb->cmd.basic_io.segment_4G = 0;
3579 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3580 scb->cmd.basic_io.log_drv = scb->target_id;
3581 scb->cmd.basic_io.sg_count = scb->sg_len;
3582
3583 if (scb->cmd.basic_io.lba)
3584 le32_add_cpu(&scb->cmd.basic_io.lba,
3585 le16_to_cpu(scb->cmd.basic_io.
3586 sector_count));
3587 else
3588 scb->cmd.basic_io.lba =
3589 (((scb->scsi_cmd->
3590 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd->
3591 cmnd[2] << 8) |
3592 (scb->scsi_cmd->cmnd[3]));
3593
3594 scb->cmd.basic_io.sector_count =
3595 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3596
3597 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0)
3598 scb->cmd.basic_io.sector_count =
3599 cpu_to_le16(256);
3600
3601 ret = IPS_SUCCESS;
3602 break;
3603
3604 case READ_10:
3605 case WRITE_10:
3606 if (!scb->sg_len) {
3607 scb->cmd.basic_io.op_code =
3608 (scb->scsi_cmd->cmnd[0] ==
3609 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE;
3610 scb->cmd.basic_io.enhanced_sg = 0;
3611 scb->cmd.basic_io.sg_addr =
3612 cpu_to_le32(scb->data_busaddr);
3613 } else {
3614 scb->cmd.basic_io.op_code =
3615 (scb->scsi_cmd->cmnd[0] ==
3616 READ_10) ? IPS_CMD_READ_SG :
3617 IPS_CMD_WRITE_SG;
3618 scb->cmd.basic_io.enhanced_sg =
3619 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3620 scb->cmd.basic_io.sg_addr =
3621 cpu_to_le32(scb->sg_busaddr);
3622 }
3623
3624 scb->cmd.basic_io.segment_4G = 0;
3625 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3626 scb->cmd.basic_io.log_drv = scb->target_id;
3627 scb->cmd.basic_io.sg_count = scb->sg_len;
3628
3629 if (scb->cmd.basic_io.lba)
3630 le32_add_cpu(&scb->cmd.basic_io.lba,
3631 le16_to_cpu(scb->cmd.basic_io.
3632 sector_count));
3633 else
3634 scb->cmd.basic_io.lba =
3635 ((scb->scsi_cmd->cmnd[2] << 24) | (scb->
3636 scsi_cmd->
3637 cmnd[3]
3638 << 16) |
3639 (scb->scsi_cmd->cmnd[4] << 8) | scb->
3640 scsi_cmd->cmnd[5]);
3641
3642 scb->cmd.basic_io.sector_count =
3643 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3644
3645 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) {
3646 /*
3647 * This is a null condition
3648 * we don't have to do anything
3649 * so just return
3650 */
3651 scb->scsi_cmd->result = DID_OK << 16;
3652 } else
3653 ret = IPS_SUCCESS;
3654
3655 break;
3656
3657 case RESERVE:
3658 case RELEASE:
3659 scb->scsi_cmd->result = DID_OK << 16;
3660 break;
3661
3662 case MODE_SENSE:
3663 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
3664 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3665 scb->cmd.basic_io.segment_4G = 0;
3666 scb->cmd.basic_io.enhanced_sg = 0;
3667 scb->data_len = sizeof (*ha->enq);
3668 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
3669 ret = IPS_SUCCESS;
3670 break;
3671
3672 case READ_CAPACITY:
3673 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3674 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3675 scb->cmd.logical_info.reserved = 0;
3676 scb->cmd.logical_info.reserved2 = 0;
3677 scb->cmd.logical_info.reserved3 = 0;
3678 scb->data_len = sizeof (IPS_LD_INFO);
3679 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3680 scb->flags = 0;
3681 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3682 ret = IPS_SUCCESS;
3683 break;
3684
3685 case SEND_DIAGNOSTIC:
3686 case REASSIGN_BLOCKS:
3687 case FORMAT_UNIT:
3688 case SEEK_10:
3689 case VERIFY:
3690 case READ_DEFECT_DATA:
3691 case READ_BUFFER:
3692 case WRITE_BUFFER:
3693 scb->scsi_cmd->result = DID_OK << 16;
3694 break;
3695
3696 default:
3697 /* Set the Return Info to appear like the Command was */
3698 /* attempted, a Check Condition occurred, and Sense */
3699 /* Data indicating an Invalid CDB OpCode is returned. */
3700 sp = (char *) scb->scsi_cmd->sense_buffer;
3701
3702 sp[0] = 0x70; /* Error Code */
3703 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */
3704 sp[7] = 0x0A; /* Additional Sense Length */
3705 sp[12] = 0x20; /* ASC = Invalid OpCode */
3706 sp[13] = 0x00; /* ASCQ */
3707
3708 device_error = 2; /* Indicate Check Condition */
3709 scb->scsi_cmd->result = device_error | (DID_OK << 16);
3710 break;
3711 } /* end switch */
3712 }
3713 /* end if */
3714 if (ret == IPS_SUCCESS_IMM)
3715 return (ret);
3716
3717 /* setup DCDB */
3718 if (scb->bus > 0) {
3719
3720 /* If we already know the Device is Not there, no need to attempt a Command */
3721 /* This also protects an NT FailOver Controller from getting CDB's sent to it */
3722 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) {
3723 scb->scsi_cmd->result = DID_NO_CONNECT << 16;
3724 return (IPS_SUCCESS_IMM);
3725 }
3726
3727 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id);
3728 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb);
3729 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
3730 (unsigned long) &scb->
3731 dcdb -
3732 (unsigned long) scb);
3733 scb->cmd.dcdb.reserved = 0;
3734 scb->cmd.dcdb.reserved2 = 0;
3735 scb->cmd.dcdb.reserved3 = 0;
3736 scb->cmd.dcdb.segment_4G = 0;
3737 scb->cmd.dcdb.enhanced_sg = 0;
3738
3739 TimeOut = scb->scsi_cmd->request->timeout;
3740
3741 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */
3742 if (!scb->sg_len) {
3743 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB;
3744 } else {
3745 scb->cmd.dcdb.op_code =
3746 IPS_CMD_EXTENDED_DCDB_SG;
3747 scb->cmd.dcdb.enhanced_sg =
3748 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3749 }
3750
3751 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */
3752 tapeDCDB->device_address =
3753 ((scb->bus - 1) << 4) | scb->target_id;
3754 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3755 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */
3756
3757 if (TimeOut) {
3758 if (TimeOut < (10 * HZ))
3759 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
3760 else if (TimeOut < (60 * HZ))
3761 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
3762 else if (TimeOut < (1200 * HZ))
3763 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
3764 }
3765
3766 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len;
3767 tapeDCDB->reserved_for_LUN = 0;
3768 tapeDCDB->transfer_length = scb->data_len;
3769 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG)
3770 tapeDCDB->buffer_pointer =
3771 cpu_to_le32(scb->sg_busaddr);
3772 else
3773 tapeDCDB->buffer_pointer =
3774 cpu_to_le32(scb->data_busaddr);
3775 tapeDCDB->sg_count = scb->sg_len;
3776 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info);
3777 tapeDCDB->scsi_status = 0;
3778 tapeDCDB->reserved = 0;
3779 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd,
3780 scb->scsi_cmd->cmd_len);
3781 } else {
3782 if (!scb->sg_len) {
3783 scb->cmd.dcdb.op_code = IPS_CMD_DCDB;
3784 } else {
3785 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG;
3786 scb->cmd.dcdb.enhanced_sg =
3787 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3788 }
3789
3790 scb->dcdb.device_address =
3791 ((scb->bus - 1) << 4) | scb->target_id;
3792 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3793
3794 if (TimeOut) {
3795 if (TimeOut < (10 * HZ))
3796 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
3797 else if (TimeOut < (60 * HZ))
3798 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
3799 else if (TimeOut < (1200 * HZ))
3800 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
3801 }
3802
3803 scb->dcdb.transfer_length = scb->data_len;
3804 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K)
3805 scb->dcdb.transfer_length = 0;
3806 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG)
3807 scb->dcdb.buffer_pointer =
3808 cpu_to_le32(scb->sg_busaddr);
3809 else
3810 scb->dcdb.buffer_pointer =
3811 cpu_to_le32(scb->data_busaddr);
3812 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len;
3813 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info);
3814 scb->dcdb.sg_count = scb->sg_len;
3815 scb->dcdb.reserved = 0;
3816 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd,
3817 scb->scsi_cmd->cmd_len);
3818 scb->dcdb.scsi_status = 0;
3819 scb->dcdb.reserved2[0] = 0;
3820 scb->dcdb.reserved2[1] = 0;
3821 scb->dcdb.reserved2[2] = 0;
3822 }
3823 }
3824
3825 return ((*ha->func.issue) (ha, scb));
3826}
3827
3828/****************************************************************************/
3829/* */
3830/* Routine Name: ips_chk_status */
3831/* */
3832/* Routine Description: */
3833/* */
3834/* Check the status of commands to logical drives */
3835/* Assumed to be called with the HA lock */
3836/****************************************************************************/
3837static void
3838ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
3839{
3840 ips_scb_t *scb;
3841 ips_stat_t *sp;
3842 uint8_t basic_status;
3843 uint8_t ext_status;
3844 int errcode;
3845 IPS_SCSI_INQ_DATA inquiryData;
3846
3847 METHOD_TRACE("ips_chkstatus", 1);
3848
3849 scb = &ha->scbs[pstatus->fields.command_id];
3850 scb->basic_status = basic_status =
3851 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK;
3852 scb->extended_status = ext_status = pstatus->fields.extended_status;
3853
3854 sp = &ha->sp;
3855 sp->residue_len = 0;
3856 sp->scb_addr = (void *) scb;
3857
3858 /* Remove the item from the active queue */
3859 ips_removeq_scb(&ha->scb_activelist, scb);
3860
3861 if (!scb->scsi_cmd)
3862 /* internal commands are handled in do_ipsintr */
3863 return;
3864
3865 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)",
3866 ips_name,
3867 ha->host_num,
3868 scb->cdb[0],
3869 scb->cmd.basic_io.command_id,
3870 scb->bus, scb->target_id, scb->lun);
3871
3872 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd)))
3873 /* passthru - just returns the raw result */
3874 return;
3875
3876 errcode = DID_OK;
3877
3878 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) ||
3879 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) {
3880
3881 if (scb->bus == 0) {
3882 if ((basic_status & IPS_GSC_STATUS_MASK) ==
3883 IPS_CMD_RECOVERED_ERROR) {
3884 DEBUG_VAR(1,
3885 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
3886 ips_name, ha->host_num,
3887 scb->cmd.basic_io.op_code,
3888 basic_status, ext_status);
3889 }
3890
3891 switch (scb->scsi_cmd->cmnd[0]) {
3892 case ALLOW_MEDIUM_REMOVAL:
3893 case REZERO_UNIT:
3894 case ERASE:
3895 case WRITE_FILEMARKS:
3896 case SPACE:
3897 errcode = DID_ERROR;
3898 break;
3899
3900 case START_STOP:
3901 break;
3902
3903 case TEST_UNIT_READY:
3904 if (!ips_online(ha, scb)) {
3905 errcode = DID_TIME_OUT;
3906 }
3907 break;
3908
3909 case INQUIRY:
3910 if (ips_online(ha, scb)) {
3911 ips_inquiry(ha, scb);
3912 } else {
3913 errcode = DID_TIME_OUT;
3914 }
3915 break;
3916
3917 case REQUEST_SENSE:
3918 ips_reqsen(ha, scb);
3919 break;
3920
3921 case READ_6:
3922 case WRITE_6:
3923 case READ_10:
3924 case WRITE_10:
3925 case RESERVE:
3926 case RELEASE:
3927 break;
3928
3929 case MODE_SENSE:
3930 if (!ips_online(ha, scb)
3931 || !ips_msense(ha, scb)) {
3932 errcode = DID_ERROR;
3933 }
3934 break;
3935
3936 case READ_CAPACITY:
3937 if (ips_online(ha, scb))
3938 ips_rdcap(ha, scb);
3939 else {
3940 errcode = DID_TIME_OUT;
3941 }
3942 break;
3943
3944 case SEND_DIAGNOSTIC:
3945 case REASSIGN_BLOCKS:
3946 break;
3947
3948 case FORMAT_UNIT:
3949 errcode = DID_ERROR;
3950 break;
3951
3952 case SEEK_10:
3953 case VERIFY:
3954 case READ_DEFECT_DATA:
3955 case READ_BUFFER:
3956 case WRITE_BUFFER:
3957 break;
3958
3959 default:
3960 errcode = DID_ERROR;
3961 } /* end switch */
3962
3963 scb->scsi_cmd->result = errcode << 16;
3964 } else { /* bus == 0 */
3965 /* restrict access to physical drives */
3966 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3967 ips_scmd_buf_read(scb->scsi_cmd,
3968 &inquiryData, sizeof (inquiryData));
3969 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK)
3970 scb->scsi_cmd->result = DID_TIME_OUT << 16;
3971 }
3972 } /* else */
3973 } else { /* recovered error / success */
3974 if (scb->bus == 0) {
3975 DEBUG_VAR(1,
3976 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
3977 ips_name, ha->host_num,
3978 scb->cmd.basic_io.op_code, basic_status,
3979 ext_status);
3980 }
3981
3982 ips_map_status(ha, scb, sp);
3983 } /* else */
3984}
3985
3986/****************************************************************************/
3987/* */
3988/* Routine Name: ips_online */
3989/* */
3990/* Routine Description: */
3991/* */
3992/* Determine if a logical drive is online */
3993/* */
3994/****************************************************************************/
3995static int
3996ips_online(ips_ha_t * ha, ips_scb_t * scb)
3997{
3998 METHOD_TRACE("ips_online", 1);
3999
4000 if (scb->target_id >= IPS_MAX_LD)
4001 return (0);
4002
4003 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) {
4004 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO));
4005 return (0);
4006 }
4007
4008 if (ha->logical_drive_info->drive_info[scb->target_id].state !=
4009 IPS_LD_OFFLINE
4010 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4011 IPS_LD_FREE
4012 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4013 IPS_LD_CRS
4014 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4015 IPS_LD_SYS)
4016 return (1);
4017 else
4018 return (0);
4019}
4020
4021/****************************************************************************/
4022/* */
4023/* Routine Name: ips_inquiry */
4024/* */
4025/* Routine Description: */
4026/* */
4027/* Simulate an inquiry command to a logical drive */
4028/* */
4029/****************************************************************************/
4030static int
4031ips_inquiry(ips_ha_t * ha, ips_scb_t * scb)
4032{
4033 IPS_SCSI_INQ_DATA inquiry;
4034
4035 METHOD_TRACE("ips_inquiry", 1);
4036
4037 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA));
4038
4039 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD;
4040 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED;
4041 inquiry.Version = IPS_SCSI_INQ_REV2;
4042 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2;
4043 inquiry.AdditionalLength = 31;
4044 inquiry.Flags[0] = IPS_SCSI_INQ_Address16;
4045 inquiry.Flags[1] =
4046 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue;
4047 strncpy(inquiry.VendorId, "IBM ", 8);
4048 strncpy(inquiry.ProductId, "SERVERAID ", 16);
4049 strncpy(inquiry.ProductRevisionLevel, "1.00", 4);
4050
4051 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry));
4052
4053 return (1);
4054}
4055
4056/****************************************************************************/
4057/* */
4058/* Routine Name: ips_rdcap */
4059/* */
4060/* Routine Description: */
4061/* */
4062/* Simulate a read capacity command to a logical drive */
4063/* */
4064/****************************************************************************/
4065static int
4066ips_rdcap(ips_ha_t * ha, ips_scb_t * scb)
4067{
4068 IPS_SCSI_CAPACITY cap;
4069
4070 METHOD_TRACE("ips_rdcap", 1);
4071
4072 if (scsi_bufflen(scb->scsi_cmd) < 8)
4073 return (0);
4074
4075 cap.lba =
4076 cpu_to_be32(le32_to_cpu
4077 (ha->logical_drive_info->
4078 drive_info[scb->target_id].sector_count) - 1);
4079 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE);
4080
4081 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap));
4082
4083 return (1);
4084}
4085
4086/****************************************************************************/
4087/* */
4088/* Routine Name: ips_msense */
4089/* */
4090/* Routine Description: */
4091/* */
4092/* Simulate a mode sense command to a logical drive */
4093/* */
4094/****************************************************************************/
4095static int
4096ips_msense(ips_ha_t * ha, ips_scb_t * scb)
4097{
4098 uint16_t heads;
4099 uint16_t sectors;
4100 uint32_t cylinders;
4101 IPS_SCSI_MODE_PAGE_DATA mdata;
4102
4103 METHOD_TRACE("ips_msense", 1);
4104
4105 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 &&
4106 (ha->enq->ucMiscFlag & 0x8) == 0) {
4107 heads = IPS_NORM_HEADS;
4108 sectors = IPS_NORM_SECTORS;
4109 } else {
4110 heads = IPS_COMP_HEADS;
4111 sectors = IPS_COMP_SECTORS;
4112 }
4113
4114 cylinders =
4115 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) -
4116 1) / (heads * sectors);
4117
4118 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA));
4119
4120 mdata.hdr.BlockDescLength = 8;
4121
4122 switch (scb->scsi_cmd->cmnd[2] & 0x3f) {
4123 case 0x03: /* page 3 */
4124 mdata.pdata.pg3.PageCode = 3;
4125 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3);
4126 mdata.hdr.DataLength =
4127 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength;
4128 mdata.pdata.pg3.TracksPerZone = 0;
4129 mdata.pdata.pg3.AltSectorsPerZone = 0;
4130 mdata.pdata.pg3.AltTracksPerZone = 0;
4131 mdata.pdata.pg3.AltTracksPerVolume = 0;
4132 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors);
4133 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE);
4134 mdata.pdata.pg3.Interleave = cpu_to_be16(1);
4135 mdata.pdata.pg3.TrackSkew = 0;
4136 mdata.pdata.pg3.CylinderSkew = 0;
4137 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector;
4138 break;
4139
4140 case 0x4:
4141 mdata.pdata.pg4.PageCode = 4;
4142 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4);
4143 mdata.hdr.DataLength =
4144 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength;
4145 mdata.pdata.pg4.CylindersHigh =
4146 cpu_to_be16((cylinders >> 8) & 0xFFFF);
4147 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF);
4148 mdata.pdata.pg4.Heads = heads;
4149 mdata.pdata.pg4.WritePrecompHigh = 0;
4150 mdata.pdata.pg4.WritePrecompLow = 0;
4151 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0;
4152 mdata.pdata.pg4.ReducedWriteCurrentLow = 0;
4153 mdata.pdata.pg4.StepRate = cpu_to_be16(1);
4154 mdata.pdata.pg4.LandingZoneHigh = 0;
4155 mdata.pdata.pg4.LandingZoneLow = 0;
4156 mdata.pdata.pg4.flags = 0;
4157 mdata.pdata.pg4.RotationalOffset = 0;
4158 mdata.pdata.pg4.MediumRotationRate = 0;
4159 break;
4160 case 0x8:
4161 mdata.pdata.pg8.PageCode = 8;
4162 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8);
4163 mdata.hdr.DataLength =
4164 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength;
4165 /* everything else is left set to 0 */
4166 break;
4167
4168 default:
4169 return (0);
4170 } /* end switch */
4171
4172 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata));
4173
4174 return (1);
4175}
4176
4177/****************************************************************************/
4178/* */
4179/* Routine Name: ips_reqsen */
4180/* */
4181/* Routine Description: */
4182/* */
4183/* Simulate a request sense command to a logical drive */
4184/* */
4185/****************************************************************************/
4186static int
4187ips_reqsen(ips_ha_t * ha, ips_scb_t * scb)
4188{
4189 IPS_SCSI_REQSEN reqsen;
4190
4191 METHOD_TRACE("ips_reqsen", 1);
4192
4193 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN));
4194
4195 reqsen.ResponseCode =
4196 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR;
4197 reqsen.AdditionalLength = 10;
4198 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE;
4199 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE;
4200
4201 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen));
4202
4203 return (1);
4204}
4205
4206/****************************************************************************/
4207/* */
4208/* Routine Name: ips_free */
4209/* */
4210/* Routine Description: */
4211/* */
4212/* Free any allocated space for this controller */
4213/* */
4214/****************************************************************************/
4215static void
4216ips_free(ips_ha_t * ha)
4217{
4218
4219 METHOD_TRACE("ips_free", 1);
4220
4221 if (ha) {
4222 if (ha->enq) {
4223 pci_free_consistent(ha->pcidev, sizeof(IPS_ENQ),
4224 ha->enq, ha->enq_busaddr);
4225 ha->enq = NULL;
4226 }
4227
4228 kfree(ha->conf);
4229 ha->conf = NULL;
4230
4231 if (ha->adapt) {
4232 pci_free_consistent(ha->pcidev,
4233 sizeof (IPS_ADAPTER) +
4234 sizeof (IPS_IO_CMD), ha->adapt,
4235 ha->adapt->hw_status_start);
4236 ha->adapt = NULL;
4237 }
4238
4239 if (ha->logical_drive_info) {
4240 pci_free_consistent(ha->pcidev,
4241 sizeof (IPS_LD_INFO),
4242 ha->logical_drive_info,
4243 ha->logical_drive_info_dma_addr);
4244 ha->logical_drive_info = NULL;
4245 }
4246
4247 kfree(ha->nvram);
4248 ha->nvram = NULL;
4249
4250 kfree(ha->subsys);
4251 ha->subsys = NULL;
4252
4253 if (ha->ioctl_data) {
4254 pci_free_consistent(ha->pcidev, ha->ioctl_len,
4255 ha->ioctl_data, ha->ioctl_busaddr);
4256 ha->ioctl_data = NULL;
4257 ha->ioctl_datasize = 0;
4258 ha->ioctl_len = 0;
4259 }
4260 ips_deallocatescbs(ha, ha->max_cmds);
4261
4262 /* free memory mapped (if applicable) */
4263 if (ha->mem_ptr) {
4264 iounmap(ha->ioremap_ptr);
4265 ha->ioremap_ptr = NULL;
4266 ha->mem_ptr = NULL;
4267 }
4268
4269 ha->mem_addr = 0;
4270
4271 }
4272}
4273
4274/****************************************************************************/
4275/* */
4276/* Routine Name: ips_deallocatescbs */
4277/* */
4278/* Routine Description: */
4279/* */
4280/* Free the command blocks */
4281/* */
4282/****************************************************************************/
4283static int
4284ips_deallocatescbs(ips_ha_t * ha, int cmds)
4285{
4286 if (ha->scbs) {
4287 pci_free_consistent(ha->pcidev,
4288 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds,
4289 ha->scbs->sg_list.list,
4290 ha->scbs->sg_busaddr);
4291 pci_free_consistent(ha->pcidev, sizeof (ips_scb_t) * cmds,
4292 ha->scbs, ha->scbs->scb_busaddr);
4293 ha->scbs = NULL;
4294 } /* end if */
4295 return 1;
4296}
4297
4298/****************************************************************************/
4299/* */
4300/* Routine Name: ips_allocatescbs */
4301/* */
4302/* Routine Description: */
4303/* */
4304/* Allocate the command blocks */
4305/* */
4306/****************************************************************************/
4307static int
4308ips_allocatescbs(ips_ha_t * ha)
4309{
4310 ips_scb_t *scb_p;
4311 IPS_SG_LIST ips_sg;
4312 int i;
4313 dma_addr_t command_dma, sg_dma;
4314
4315 METHOD_TRACE("ips_allocatescbs", 1);
4316
4317 /* Allocate memory for the SCBs */
4318 ha->scbs =
4319 pci_alloc_consistent(ha->pcidev, ha->max_cmds * sizeof (ips_scb_t),
4320 &command_dma);
4321 if (ha->scbs == NULL)
4322 return 0;
4323 ips_sg.list =
4324 pci_alloc_consistent(ha->pcidev,
4325 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG *
4326 ha->max_cmds, &sg_dma);
4327 if (ips_sg.list == NULL) {
4328 pci_free_consistent(ha->pcidev,
4329 ha->max_cmds * sizeof (ips_scb_t), ha->scbs,
4330 command_dma);
4331 return 0;
4332 }
4333
4334 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t));
4335
4336 for (i = 0; i < ha->max_cmds; i++) {
4337 scb_p = &ha->scbs[i];
4338 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i;
4339 /* set up S/G list */
4340 if (IPS_USE_ENH_SGLIST(ha)) {
4341 scb_p->sg_list.enh_list =
4342 ips_sg.enh_list + i * IPS_MAX_SG;
4343 scb_p->sg_busaddr =
4344 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4345 } else {
4346 scb_p->sg_list.std_list =
4347 ips_sg.std_list + i * IPS_MAX_SG;
4348 scb_p->sg_busaddr =
4349 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4350 }
4351
4352 /* add to the free list */
4353 if (i < ha->max_cmds - 1) {
4354 scb_p->q_next = ha->scb_freelist;
4355 ha->scb_freelist = scb_p;
4356 }
4357 }
4358
4359 /* success */
4360 return (1);
4361}
4362
4363/****************************************************************************/
4364/* */
4365/* Routine Name: ips_init_scb */
4366/* */
4367/* Routine Description: */
4368/* */
4369/* Initialize a CCB to default values */
4370/* */
4371/****************************************************************************/
4372static void
4373ips_init_scb(ips_ha_t * ha, ips_scb_t * scb)
4374{
4375 IPS_SG_LIST sg_list;
4376 uint32_t cmd_busaddr, sg_busaddr;
4377 METHOD_TRACE("ips_init_scb", 1);
4378
4379 if (scb == NULL)
4380 return;
4381
4382 sg_list.list = scb->sg_list.list;
4383 cmd_busaddr = scb->scb_busaddr;
4384 sg_busaddr = scb->sg_busaddr;
4385 /* zero fill */
4386 memset(scb, 0, sizeof (ips_scb_t));
4387 memset(ha->dummy, 0, sizeof (IPS_IO_CMD));
4388
4389 /* Initialize dummy command bucket */
4390 ha->dummy->op_code = 0xFF;
4391 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start
4392 + sizeof (IPS_ADAPTER));
4393 ha->dummy->command_id = IPS_MAX_CMDS;
4394
4395 /* set bus address of scb */
4396 scb->scb_busaddr = cmd_busaddr;
4397 scb->sg_busaddr = sg_busaddr;
4398 scb->sg_list.list = sg_list.list;
4399
4400 /* Neptune Fix */
4401 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE);
4402 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start
4403 + sizeof (IPS_ADAPTER));
4404}
4405
4406/****************************************************************************/
4407/* */
4408/* Routine Name: ips_get_scb */
4409/* */
4410/* Routine Description: */
4411/* */
4412/* Initialize a CCB to default values */
4413/* */
4414/* ASSUMED to be called from within a lock */
4415/* */
4416/****************************************************************************/
4417static ips_scb_t *
4418ips_getscb(ips_ha_t * ha)
4419{
4420 ips_scb_t *scb;
4421
4422 METHOD_TRACE("ips_getscb", 1);
4423
4424 if ((scb = ha->scb_freelist) == NULL) {
4425
4426 return (NULL);
4427 }
4428
4429 ha->scb_freelist = scb->q_next;
4430 scb->flags = 0;
4431 scb->q_next = NULL;
4432
4433 ips_init_scb(ha, scb);
4434
4435 return (scb);
4436}
4437
4438/****************************************************************************/
4439/* */
4440/* Routine Name: ips_free_scb */
4441/* */
4442/* Routine Description: */
4443/* */
4444/* Return an unused CCB back to the free list */
4445/* */
4446/* ASSUMED to be called from within a lock */
4447/* */
4448/****************************************************************************/
4449static void
4450ips_freescb(ips_ha_t * ha, ips_scb_t * scb)
4451{
4452
4453 METHOD_TRACE("ips_freescb", 1);
4454 if (scb->flags & IPS_SCB_MAP_SG)
4455 scsi_dma_unmap(scb->scsi_cmd);
4456 else if (scb->flags & IPS_SCB_MAP_SINGLE)
4457 pci_unmap_single(ha->pcidev, scb->data_busaddr, scb->data_len,
4458 IPS_DMA_DIR(scb));
4459
4460 /* check to make sure this is not our "special" scb */
4461 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) {
4462 scb->q_next = ha->scb_freelist;
4463 ha->scb_freelist = scb;
4464 }
4465}
4466
4467/****************************************************************************/
4468/* */
4469/* Routine Name: ips_isinit_copperhead */
4470/* */
4471/* Routine Description: */
4472/* */
4473/* Is controller initialized ? */
4474/* */
4475/****************************************************************************/
4476static int
4477ips_isinit_copperhead(ips_ha_t * ha)
4478{
4479 uint8_t scpr;
4480 uint8_t isr;
4481
4482 METHOD_TRACE("ips_isinit_copperhead", 1);
4483
4484 isr = inb(ha->io_addr + IPS_REG_HISR);
4485 scpr = inb(ha->io_addr + IPS_REG_SCPR);
4486
4487 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4488 return (0);
4489 else
4490 return (1);
4491}
4492
4493/****************************************************************************/
4494/* */
4495/* Routine Name: ips_isinit_copperhead_memio */
4496/* */
4497/* Routine Description: */
4498/* */
4499/* Is controller initialized ? */
4500/* */
4501/****************************************************************************/
4502static int
4503ips_isinit_copperhead_memio(ips_ha_t * ha)
4504{
4505 uint8_t isr = 0;
4506 uint8_t scpr;
4507
4508 METHOD_TRACE("ips_is_init_copperhead_memio", 1);
4509
4510 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4511 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4512
4513 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4514 return (0);
4515 else
4516 return (1);
4517}
4518
4519/****************************************************************************/
4520/* */
4521/* Routine Name: ips_isinit_morpheus */
4522/* */
4523/* Routine Description: */
4524/* */
4525/* Is controller initialized ? */
4526/* */
4527/****************************************************************************/
4528static int
4529ips_isinit_morpheus(ips_ha_t * ha)
4530{
4531 uint32_t post;
4532 uint32_t bits;
4533
4534 METHOD_TRACE("ips_is_init_morpheus", 1);
4535
4536 if (ips_isintr_morpheus(ha))
4537 ips_flush_and_reset(ha);
4538
4539 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4540 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4541
4542 if (post == 0)
4543 return (0);
4544 else if (bits & 0x3)
4545 return (0);
4546 else
4547 return (1);
4548}
4549
4550/****************************************************************************/
4551/* */
4552/* Routine Name: ips_flush_and_reset */
4553/* */
4554/* Routine Description: */
4555/* */
4556/* Perform cleanup ( FLUSH and RESET ) when the adapter is in an unknown */
4557/* state ( was trying to INIT and an interrupt was already pending ) ... */
4558/* */
4559/****************************************************************************/
4560static void
4561ips_flush_and_reset(ips_ha_t *ha)
4562{
4563 ips_scb_t *scb;
4564 int ret;
4565 int time;
4566 int done;
4567 dma_addr_t command_dma;
4568
4569 /* Create a usuable SCB */
4570 scb = pci_alloc_consistent(ha->pcidev, sizeof(ips_scb_t), &command_dma);
4571 if (scb) {
4572 memset(scb, 0, sizeof(ips_scb_t));
4573 ips_init_scb(ha, scb);
4574 scb->scb_busaddr = command_dma;
4575
4576 scb->timeout = ips_cmd_timeout;
4577 scb->cdb[0] = IPS_CMD_FLUSH;
4578
4579 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
4580 scb->cmd.flush_cache.command_id = IPS_MAX_CMDS; /* Use an ID that would otherwise not exist */
4581 scb->cmd.flush_cache.state = IPS_NORM_STATE;
4582 scb->cmd.flush_cache.reserved = 0;
4583 scb->cmd.flush_cache.reserved2 = 0;
4584 scb->cmd.flush_cache.reserved3 = 0;
4585 scb->cmd.flush_cache.reserved4 = 0;
4586
4587 ret = ips_send_cmd(ha, scb); /* Send the Flush Command */
4588
4589 if (ret == IPS_SUCCESS) {
4590 time = 60 * IPS_ONE_SEC; /* Max Wait time is 60 seconds */
4591 done = 0;
4592
4593 while ((time > 0) && (!done)) {
4594 done = ips_poll_for_flush_complete(ha);
4595 /* This may look evil, but it's only done during extremely rare start-up conditions ! */
4596 udelay(1000);
4597 time--;
4598 }
4599 }
4600 }
4601
4602 /* Now RESET and INIT the adapter */
4603 (*ha->func.reset) (ha);
4604
4605 pci_free_consistent(ha->pcidev, sizeof(ips_scb_t), scb, command_dma);
4606 return;
4607}
4608
4609/****************************************************************************/
4610/* */
4611/* Routine Name: ips_poll_for_flush_complete */
4612/* */
4613/* Routine Description: */
4614/* */
4615/* Poll for the Flush Command issued by ips_flush_and_reset() to complete */
4616/* All other responses are just taken off the queue and ignored */
4617/* */
4618/****************************************************************************/
4619static int
4620ips_poll_for_flush_complete(ips_ha_t * ha)
4621{
4622 IPS_STATUS cstatus;
4623
4624 while (TRUE) {
4625 cstatus.value = (*ha->func.statupd) (ha);
4626
4627 if (cstatus.value == 0xffffffff) /* If No Interrupt to process */
4628 break;
4629
4630 /* Success is when we see the Flush Command ID */
4631 if (cstatus.fields.command_id == IPS_MAX_CMDS)
4632 return 1;
4633 }
4634
4635 return 0;
4636}
4637
4638/****************************************************************************/
4639/* */
4640/* Routine Name: ips_enable_int_copperhead */
4641/* */
4642/* Routine Description: */
4643/* Turn on interrupts */
4644/* */
4645/****************************************************************************/
4646static void
4647ips_enable_int_copperhead(ips_ha_t * ha)
4648{
4649 METHOD_TRACE("ips_enable_int_copperhead", 1);
4650
4651 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
4652 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4653}
4654
4655/****************************************************************************/
4656/* */
4657/* Routine Name: ips_enable_int_copperhead_memio */
4658/* */
4659/* Routine Description: */
4660/* Turn on interrupts */
4661/* */
4662/****************************************************************************/
4663static void
4664ips_enable_int_copperhead_memio(ips_ha_t * ha)
4665{
4666 METHOD_TRACE("ips_enable_int_copperhead_memio", 1);
4667
4668 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4669 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4670}
4671
4672/****************************************************************************/
4673/* */
4674/* Routine Name: ips_enable_int_morpheus */
4675/* */
4676/* Routine Description: */
4677/* Turn on interrupts */
4678/* */
4679/****************************************************************************/
4680static void
4681ips_enable_int_morpheus(ips_ha_t * ha)
4682{
4683 uint32_t Oimr;
4684
4685 METHOD_TRACE("ips_enable_int_morpheus", 1);
4686
4687 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4688 Oimr &= ~0x08;
4689 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4690 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/
4691}
4692
4693/****************************************************************************/
4694/* */
4695/* Routine Name: ips_init_copperhead */
4696/* */
4697/* Routine Description: */
4698/* */
4699/* Initialize a copperhead controller */
4700/* */
4701/****************************************************************************/
4702static int
4703ips_init_copperhead(ips_ha_t * ha)
4704{
4705 uint8_t Isr;
4706 uint8_t Cbsp;
4707 uint8_t PostByte[IPS_MAX_POST_BYTES];
4708 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4709 int i, j;
4710
4711 METHOD_TRACE("ips_init_copperhead", 1);
4712
4713 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4714 for (j = 0; j < 45; j++) {
4715 Isr = inb(ha->io_addr + IPS_REG_HISR);
4716 if (Isr & IPS_BIT_GHI)
4717 break;
4718
4719 /* Delay for 1 Second */
4720 MDELAY(IPS_ONE_SEC);
4721 }
4722
4723 if (j >= 45)
4724 /* error occurred */
4725 return (0);
4726
4727 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4728 outb(Isr, ha->io_addr + IPS_REG_HISR);
4729 }
4730
4731 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4732 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4733 "reset controller fails (post status %x %x).\n",
4734 PostByte[0], PostByte[1]);
4735
4736 return (0);
4737 }
4738
4739 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4740 for (j = 0; j < 240; j++) {
4741 Isr = inb(ha->io_addr + IPS_REG_HISR);
4742 if (Isr & IPS_BIT_GHI)
4743 break;
4744
4745 /* Delay for 1 Second */
4746 MDELAY(IPS_ONE_SEC);
4747 }
4748
4749 if (j >= 240)
4750 /* error occurred */
4751 return (0);
4752
4753 ConfigByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4754 outb(Isr, ha->io_addr + IPS_REG_HISR);
4755 }
4756
4757 for (i = 0; i < 240; i++) {
4758 Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
4759
4760 if ((Cbsp & IPS_BIT_OP) == 0)
4761 break;
4762
4763 /* Delay for 1 Second */
4764 MDELAY(IPS_ONE_SEC);
4765 }
4766
4767 if (i >= 240)
4768 /* reset failed */
4769 return (0);
4770
4771 /* setup CCCR */
4772 outl(0x1010, ha->io_addr + IPS_REG_CCCR);
4773
4774 /* Enable busmastering */
4775 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
4776
4777 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4778 /* fix for anaconda64 */
4779 outl(0, ha->io_addr + IPS_REG_NDAE);
4780
4781 /* Enable interrupts */
4782 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
4783
4784 return (1);
4785}
4786
4787/****************************************************************************/
4788/* */
4789/* Routine Name: ips_init_copperhead_memio */
4790/* */
4791/* Routine Description: */
4792/* */
4793/* Initialize a copperhead controller with memory mapped I/O */
4794/* */
4795/****************************************************************************/
4796static int
4797ips_init_copperhead_memio(ips_ha_t * ha)
4798{
4799 uint8_t Isr = 0;
4800 uint8_t Cbsp;
4801 uint8_t PostByte[IPS_MAX_POST_BYTES];
4802 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4803 int i, j;
4804
4805 METHOD_TRACE("ips_init_copperhead_memio", 1);
4806
4807 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4808 for (j = 0; j < 45; j++) {
4809 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4810 if (Isr & IPS_BIT_GHI)
4811 break;
4812
4813 /* Delay for 1 Second */
4814 MDELAY(IPS_ONE_SEC);
4815 }
4816
4817 if (j >= 45)
4818 /* error occurred */
4819 return (0);
4820
4821 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4822 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4823 }
4824
4825 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4826 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4827 "reset controller fails (post status %x %x).\n",
4828 PostByte[0], PostByte[1]);
4829
4830 return (0);
4831 }
4832
4833 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4834 for (j = 0; j < 240; j++) {
4835 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4836 if (Isr & IPS_BIT_GHI)
4837 break;
4838
4839 /* Delay for 1 Second */
4840 MDELAY(IPS_ONE_SEC);
4841 }
4842
4843 if (j >= 240)
4844 /* error occurred */
4845 return (0);
4846
4847 ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4848 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4849 }
4850
4851 for (i = 0; i < 240; i++) {
4852 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
4853
4854 if ((Cbsp & IPS_BIT_OP) == 0)
4855 break;
4856
4857 /* Delay for 1 Second */
4858 MDELAY(IPS_ONE_SEC);
4859 }
4860
4861 if (i >= 240)
4862 /* error occurred */
4863 return (0);
4864
4865 /* setup CCCR */
4866 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
4867
4868 /* Enable busmastering */
4869 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
4870
4871 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4872 /* fix for anaconda64 */
4873 writel(0, ha->mem_ptr + IPS_REG_NDAE);
4874
4875 /* Enable interrupts */
4876 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4877
4878 /* if we get here then everything went OK */
4879 return (1);
4880}
4881
4882/****************************************************************************/
4883/* */
4884/* Routine Name: ips_init_morpheus */
4885/* */
4886/* Routine Description: */
4887/* */
4888/* Initialize a morpheus controller */
4889/* */
4890/****************************************************************************/
4891static int
4892ips_init_morpheus(ips_ha_t * ha)
4893{
4894 uint32_t Post;
4895 uint32_t Config;
4896 uint32_t Isr;
4897 uint32_t Oimr;
4898 int i;
4899
4900 METHOD_TRACE("ips_init_morpheus", 1);
4901
4902 /* Wait up to 45 secs for Post */
4903 for (i = 0; i < 45; i++) {
4904 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4905
4906 if (Isr & IPS_BIT_I960_MSG0I)
4907 break;
4908
4909 /* Delay for 1 Second */
4910 MDELAY(IPS_ONE_SEC);
4911 }
4912
4913 if (i >= 45) {
4914 /* error occurred */
4915 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4916 "timeout waiting for post.\n");
4917
4918 return (0);
4919 }
4920
4921 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4922
4923 if (Post == 0x4F00) { /* If Flashing the Battery PIC */
4924 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4925 "Flashing Battery PIC, Please wait ...\n");
4926
4927 /* Clear the interrupt bit */
4928 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
4929 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4930
4931 for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */
4932 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4933 if (Post != 0x4F00)
4934 break;
4935 /* Delay for 1 Second */
4936 MDELAY(IPS_ONE_SEC);
4937 }
4938
4939 if (i >= 120) {
4940 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4941 "timeout waiting for Battery PIC Flash\n");
4942 return (0);
4943 }
4944
4945 }
4946
4947 /* Clear the interrupt bit */
4948 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
4949 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4950
4951 if (Post < (IPS_GOOD_POST_STATUS << 8)) {
4952 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4953 "reset controller fails (post status %x).\n", Post);
4954
4955 return (0);
4956 }
4957
4958 /* Wait up to 240 secs for config bytes */
4959 for (i = 0; i < 240; i++) {
4960 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4961
4962 if (Isr & IPS_BIT_I960_MSG1I)
4963 break;
4964
4965 /* Delay for 1 Second */
4966 MDELAY(IPS_ONE_SEC);
4967 }
4968
4969 if (i >= 240) {
4970 /* error occurred */
4971 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4972 "timeout waiting for config.\n");
4973
4974 return (0);
4975 }
4976
4977 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
4978
4979 /* Clear interrupt bit */
4980 Isr = (uint32_t) IPS_BIT_I960_MSG1I;
4981 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4982
4983 /* Turn on the interrupts */
4984 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4985 Oimr &= ~0x8;
4986 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4987
4988 /* if we get here then everything went OK */
4989
4990 /* Since we did a RESET, an EraseStripeLock may be needed */
4991 if (Post == 0xEF10) {
4992 if ((Config == 0x000F) || (Config == 0x0009))
4993 ha->requires_esl = 1;
4994 }
4995
4996 return (1);
4997}
4998
4999/****************************************************************************/
5000/* */
5001/* Routine Name: ips_reset_copperhead */
5002/* */
5003/* Routine Description: */
5004/* */
5005/* Reset the controller */
5006/* */
5007/****************************************************************************/
5008static int
5009ips_reset_copperhead(ips_ha_t * ha)
5010{
5011 int reset_counter;
5012
5013 METHOD_TRACE("ips_reset_copperhead", 1);
5014
5015 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d",
5016 ips_name, ha->host_num, ha->io_addr, ha->pcidev->irq);
5017
5018 reset_counter = 0;
5019
5020 while (reset_counter < 2) {
5021 reset_counter++;
5022
5023 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
5024
5025 /* Delay for 1 Second */
5026 MDELAY(IPS_ONE_SEC);
5027
5028 outb(0, ha->io_addr + IPS_REG_SCPR);
5029
5030 /* Delay for 1 Second */
5031 MDELAY(IPS_ONE_SEC);
5032
5033 if ((*ha->func.init) (ha))
5034 break;
5035 else if (reset_counter >= 2) {
5036
5037 return (0);
5038 }
5039 }
5040
5041 return (1);
5042}
5043
5044/****************************************************************************/
5045/* */
5046/* Routine Name: ips_reset_copperhead_memio */
5047/* */
5048/* Routine Description: */
5049/* */
5050/* Reset the controller */
5051/* */
5052/****************************************************************************/
5053static int
5054ips_reset_copperhead_memio(ips_ha_t * ha)
5055{
5056 int reset_counter;
5057
5058 METHOD_TRACE("ips_reset_copperhead_memio", 1);
5059
5060 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d",
5061 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5062
5063 reset_counter = 0;
5064
5065 while (reset_counter < 2) {
5066 reset_counter++;
5067
5068 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5069
5070 /* Delay for 1 Second */
5071 MDELAY(IPS_ONE_SEC);
5072
5073 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5074
5075 /* Delay for 1 Second */
5076 MDELAY(IPS_ONE_SEC);
5077
5078 if ((*ha->func.init) (ha))
5079 break;
5080 else if (reset_counter >= 2) {
5081
5082 return (0);
5083 }
5084 }
5085
5086 return (1);
5087}
5088
5089/****************************************************************************/
5090/* */
5091/* Routine Name: ips_reset_morpheus */
5092/* */
5093/* Routine Description: */
5094/* */
5095/* Reset the controller */
5096/* */
5097/****************************************************************************/
5098static int
5099ips_reset_morpheus(ips_ha_t * ha)
5100{
5101 int reset_counter;
5102 uint8_t junk;
5103
5104 METHOD_TRACE("ips_reset_morpheus", 1);
5105
5106 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d",
5107 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5108
5109 reset_counter = 0;
5110
5111 while (reset_counter < 2) {
5112 reset_counter++;
5113
5114 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5115
5116 /* Delay for 5 Seconds */
5117 MDELAY(5 * IPS_ONE_SEC);
5118
5119 /* Do a PCI config read to wait for adapter */
5120 pci_read_config_byte(ha->pcidev, 4, &junk);
5121
5122 if ((*ha->func.init) (ha))
5123 break;
5124 else if (reset_counter >= 2) {
5125
5126 return (0);
5127 }
5128 }
5129
5130 return (1);
5131}
5132
5133/****************************************************************************/
5134/* */
5135/* Routine Name: ips_statinit */
5136/* */
5137/* Routine Description: */
5138/* */
5139/* Initialize the status queues on the controller */
5140/* */
5141/****************************************************************************/
5142static void
5143ips_statinit(ips_ha_t * ha)
5144{
5145 uint32_t phys_status_start;
5146
5147 METHOD_TRACE("ips_statinit", 1);
5148
5149 ha->adapt->p_status_start = ha->adapt->status;
5150 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5151 ha->adapt->p_status_tail = ha->adapt->status;
5152
5153 phys_status_start = ha->adapt->hw_status_start;
5154 outl(phys_status_start, ha->io_addr + IPS_REG_SQSR);
5155 outl(phys_status_start + IPS_STATUS_Q_SIZE,
5156 ha->io_addr + IPS_REG_SQER);
5157 outl(phys_status_start + IPS_STATUS_SIZE,
5158 ha->io_addr + IPS_REG_SQHR);
5159 outl(phys_status_start, ha->io_addr + IPS_REG_SQTR);
5160
5161 ha->adapt->hw_status_tail = phys_status_start;
5162}
5163
5164/****************************************************************************/
5165/* */
5166/* Routine Name: ips_statinit_memio */
5167/* */
5168/* Routine Description: */
5169/* */
5170/* Initialize the status queues on the controller */
5171/* */
5172/****************************************************************************/
5173static void
5174ips_statinit_memio(ips_ha_t * ha)
5175{
5176 uint32_t phys_status_start;
5177
5178 METHOD_TRACE("ips_statinit_memio", 1);
5179
5180 ha->adapt->p_status_start = ha->adapt->status;
5181 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5182 ha->adapt->p_status_tail = ha->adapt->status;
5183
5184 phys_status_start = ha->adapt->hw_status_start;
5185 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5186 writel(phys_status_start + IPS_STATUS_Q_SIZE,
5187 ha->mem_ptr + IPS_REG_SQER);
5188 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5189 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5190
5191 ha->adapt->hw_status_tail = phys_status_start;
5192}
5193
5194/****************************************************************************/
5195/* */
5196/* Routine Name: ips_statupd_copperhead */
5197/* */
5198/* Routine Description: */
5199/* */
5200/* Remove an element from the status queue */
5201/* */
5202/****************************************************************************/
5203static uint32_t
5204ips_statupd_copperhead(ips_ha_t * ha)
5205{
5206 METHOD_TRACE("ips_statupd_copperhead", 1);
5207
5208 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5209 ha->adapt->p_status_tail++;
5210 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5211 } else {
5212 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5213 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5214 }
5215
5216 outl(ha->adapt->hw_status_tail,
5217 ha->io_addr + IPS_REG_SQTR);
5218
5219 return (ha->adapt->p_status_tail->value);
5220}
5221
5222/****************************************************************************/
5223/* */
5224/* Routine Name: ips_statupd_copperhead_memio */
5225/* */
5226/* Routine Description: */
5227/* */
5228/* Remove an element from the status queue */
5229/* */
5230/****************************************************************************/
5231static uint32_t
5232ips_statupd_copperhead_memio(ips_ha_t * ha)
5233{
5234 METHOD_TRACE("ips_statupd_copperhead_memio", 1);
5235
5236 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5237 ha->adapt->p_status_tail++;
5238 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5239 } else {
5240 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5241 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5242 }
5243
5244 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5245
5246 return (ha->adapt->p_status_tail->value);
5247}
5248
5249/****************************************************************************/
5250/* */
5251/* Routine Name: ips_statupd_morpheus */
5252/* */
5253/* Routine Description: */
5254/* */
5255/* Remove an element from the status queue */
5256/* */
5257/****************************************************************************/
5258static uint32_t
5259ips_statupd_morpheus(ips_ha_t * ha)
5260{
5261 uint32_t val;
5262
5263 METHOD_TRACE("ips_statupd_morpheus", 1);
5264
5265 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5266
5267 return (val);
5268}
5269
5270/****************************************************************************/
5271/* */
5272/* Routine Name: ips_issue_copperhead */
5273/* */
5274/* Routine Description: */
5275/* */
5276/* Send a command down to the controller */
5277/* */
5278/****************************************************************************/
5279static int
5280ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb)
5281{
5282 uint32_t TimeOut;
5283 uint32_t val;
5284
5285 METHOD_TRACE("ips_issue_copperhead", 1);
5286
5287 if (scb->scsi_cmd) {
5288 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5289 ips_name,
5290 ha->host_num,
5291 scb->cdb[0],
5292 scb->cmd.basic_io.command_id,
5293 scb->bus, scb->target_id, scb->lun);
5294 } else {
5295 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d",
5296 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5297 }
5298
5299 TimeOut = 0;
5300
5301 while ((val =
5302 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) {
5303 udelay(1000);
5304
5305 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5306 if (!(val & IPS_BIT_START_STOP))
5307 break;
5308
5309 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5310 "ips_issue val [0x%x].\n", val);
5311 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5312 "ips_issue semaphore chk timeout.\n");
5313
5314 return (IPS_FAILURE);
5315 } /* end if */
5316 } /* end while */
5317
5318 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_CCSAR);
5319 outw(IPS_BIT_START_CMD, ha->io_addr + IPS_REG_CCCR);
5320
5321 return (IPS_SUCCESS);
5322}
5323
5324/****************************************************************************/
5325/* */
5326/* Routine Name: ips_issue_copperhead_memio */
5327/* */
5328/* Routine Description: */
5329/* */
5330/* Send a command down to the controller */
5331/* */
5332/****************************************************************************/
5333static int
5334ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb)
5335{
5336 uint32_t TimeOut;
5337 uint32_t val;
5338
5339 METHOD_TRACE("ips_issue_copperhead_memio", 1);
5340
5341 if (scb->scsi_cmd) {
5342 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5343 ips_name,
5344 ha->host_num,
5345 scb->cdb[0],
5346 scb->cmd.basic_io.command_id,
5347 scb->bus, scb->target_id, scb->lun);
5348 } else {
5349 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5350 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5351 }
5352
5353 TimeOut = 0;
5354
5355 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5356 udelay(1000);
5357
5358 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5359 if (!(val & IPS_BIT_START_STOP))
5360 break;
5361
5362 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5363 "ips_issue val [0x%x].\n", val);
5364 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5365 "ips_issue semaphore chk timeout.\n");
5366
5367 return (IPS_FAILURE);
5368 } /* end if */
5369 } /* end while */
5370
5371 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5372 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5373
5374 return (IPS_SUCCESS);
5375}
5376
5377/****************************************************************************/
5378/* */
5379/* Routine Name: ips_issue_i2o */
5380/* */
5381/* Routine Description: */
5382/* */
5383/* Send a command down to the controller */
5384/* */
5385/****************************************************************************/
5386static int
5387ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb)
5388{
5389
5390 METHOD_TRACE("ips_issue_i2o", 1);
5391
5392 if (scb->scsi_cmd) {
5393 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5394 ips_name,
5395 ha->host_num,
5396 scb->cdb[0],
5397 scb->cmd.basic_io.command_id,
5398 scb->bus, scb->target_id, scb->lun);
5399 } else {
5400 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5401 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5402 }
5403
5404 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_I2O_INMSGQ);
5405
5406 return (IPS_SUCCESS);
5407}
5408
5409/****************************************************************************/
5410/* */
5411/* Routine Name: ips_issue_i2o_memio */
5412/* */
5413/* Routine Description: */
5414/* */
5415/* Send a command down to the controller */
5416/* */
5417/****************************************************************************/
5418static int
5419ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb)
5420{
5421
5422 METHOD_TRACE("ips_issue_i2o_memio", 1);
5423
5424 if (scb->scsi_cmd) {
5425 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5426 ips_name,
5427 ha->host_num,
5428 scb->cdb[0],
5429 scb->cmd.basic_io.command_id,
5430 scb->bus, scb->target_id, scb->lun);
5431 } else {
5432 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5433 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5434 }
5435
5436 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5437
5438 return (IPS_SUCCESS);
5439}
5440
5441/****************************************************************************/
5442/* */
5443/* Routine Name: ips_isintr_copperhead */
5444/* */
5445/* Routine Description: */
5446/* */
5447/* Test to see if an interrupt is for us */
5448/* */
5449/****************************************************************************/
5450static int
5451ips_isintr_copperhead(ips_ha_t * ha)
5452{
5453 uint8_t Isr;
5454
5455 METHOD_TRACE("ips_isintr_copperhead", 2);
5456
5457 Isr = inb(ha->io_addr + IPS_REG_HISR);
5458
5459 if (Isr == 0xFF)
5460 /* ?!?! Nothing really there */
5461 return (0);
5462
5463 if (Isr & IPS_BIT_SCE)
5464 return (1);
5465 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5466 /* status queue overflow or GHI */
5467 /* just clear the interrupt */
5468 outb(Isr, ha->io_addr + IPS_REG_HISR);
5469 }
5470
5471 return (0);
5472}
5473
5474/****************************************************************************/
5475/* */
5476/* Routine Name: ips_isintr_copperhead_memio */
5477/* */
5478/* Routine Description: */
5479/* */
5480/* Test to see if an interrupt is for us */
5481/* */
5482/****************************************************************************/
5483static int
5484ips_isintr_copperhead_memio(ips_ha_t * ha)
5485{
5486 uint8_t Isr;
5487
5488 METHOD_TRACE("ips_isintr_memio", 2);
5489
5490 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5491
5492 if (Isr == 0xFF)
5493 /* ?!?! Nothing really there */
5494 return (0);
5495
5496 if (Isr & IPS_BIT_SCE)
5497 return (1);
5498 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5499 /* status queue overflow or GHI */
5500 /* just clear the interrupt */
5501 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5502 }
5503
5504 return (0);
5505}
5506
5507/****************************************************************************/
5508/* */
5509/* Routine Name: ips_isintr_morpheus */
5510/* */
5511/* Routine Description: */
5512/* */
5513/* Test to see if an interrupt is for us */
5514/* */
5515/****************************************************************************/
5516static int
5517ips_isintr_morpheus(ips_ha_t * ha)
5518{
5519 uint32_t Isr;
5520
5521 METHOD_TRACE("ips_isintr_morpheus", 2);
5522
5523 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5524
5525 if (Isr & IPS_BIT_I2O_OPQI)
5526 return (1);
5527 else
5528 return (0);
5529}
5530
5531/****************************************************************************/
5532/* */
5533/* Routine Name: ips_wait */
5534/* */
5535/* Routine Description: */
5536/* */
5537/* Wait for a command to complete */
5538/* */
5539/****************************************************************************/
5540static int
5541ips_wait(ips_ha_t * ha, int time, int intr)
5542{
5543 int ret;
5544 int done;
5545
5546 METHOD_TRACE("ips_wait", 1);
5547
5548 ret = IPS_FAILURE;
5549 done = FALSE;
5550
5551 time *= IPS_ONE_SEC; /* convert seconds */
5552
5553 while ((time > 0) && (!done)) {
5554 if (intr == IPS_INTR_ON) {
5555 if (ha->waitflag == FALSE) {
5556 ret = IPS_SUCCESS;
5557 done = TRUE;
5558 break;
5559 }
5560 } else if (intr == IPS_INTR_IORL) {
5561 if (ha->waitflag == FALSE) {
5562 /*
5563 * controller generated an interrupt to
5564 * acknowledge completion of the command
5565 * and ips_intr() has serviced the interrupt.
5566 */
5567 ret = IPS_SUCCESS;
5568 done = TRUE;
5569 break;
5570 }
5571
5572 /*
5573 * NOTE: we already have the io_request_lock so
5574 * even if we get an interrupt it won't get serviced
5575 * until after we finish.
5576 */
5577
5578 (*ha->func.intr) (ha);
5579 }
5580
5581 /* This looks like a very evil loop, but it only does this during start-up */
5582 udelay(1000);
5583 time--;
5584 }
5585
5586 return (ret);
5587}
5588
5589/****************************************************************************/
5590/* */
5591/* Routine Name: ips_write_driver_status */
5592/* */
5593/* Routine Description: */
5594/* */
5595/* Write OS/Driver version to Page 5 of the nvram on the controller */
5596/* */
5597/****************************************************************************/
5598static int
5599ips_write_driver_status(ips_ha_t * ha, int intr)
5600{
5601 METHOD_TRACE("ips_write_driver_status", 1);
5602
5603 if (!ips_readwrite_page5(ha, FALSE, intr)) {
5604 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5605 "unable to read NVRAM page 5.\n");
5606
5607 return (0);
5608 }
5609
5610 /* check to make sure the page has a valid */
5611 /* signature */
5612 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) {
5613 DEBUG_VAR(1,
5614 "(%s%d) NVRAM page 5 has an invalid signature: %X.",
5615 ips_name, ha->host_num, ha->nvram->signature);
5616 ha->nvram->signature = IPS_NVRAM_P5_SIG;
5617 }
5618
5619 DEBUG_VAR(2,
5620 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.",
5621 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type),
5622 ha->nvram->adapter_slot, ha->nvram->bios_high[0],
5623 ha->nvram->bios_high[1], ha->nvram->bios_high[2],
5624 ha->nvram->bios_high[3], ha->nvram->bios_low[0],
5625 ha->nvram->bios_low[1], ha->nvram->bios_low[2],
5626 ha->nvram->bios_low[3]);
5627
5628 ips_get_bios_version(ha, intr);
5629
5630 /* change values (as needed) */
5631 ha->nvram->operating_system = IPS_OS_LINUX;
5632 ha->nvram->adapter_type = ha->ad_type;
5633 strncpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4);
5634 strncpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4);
5635 strncpy((char *) ha->nvram->bios_high, ha->bios_version, 4);
5636 strncpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4);
5637
5638 ha->nvram->versioning = 0; /* Indicate the Driver Does Not Support Versioning */
5639
5640 /* now update the page */
5641 if (!ips_readwrite_page5(ha, TRUE, intr)) {
5642 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5643 "unable to write NVRAM page 5.\n");
5644
5645 return (0);
5646 }
5647
5648 /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */
5649 ha->slot_num = ha->nvram->adapter_slot;
5650
5651 return (1);
5652}
5653
5654/****************************************************************************/
5655/* */
5656/* Routine Name: ips_read_adapter_status */
5657/* */
5658/* Routine Description: */
5659/* */
5660/* Do an Inquiry command to the adapter */
5661/* */
5662/****************************************************************************/
5663static int
5664ips_read_adapter_status(ips_ha_t * ha, int intr)
5665{
5666 ips_scb_t *scb;
5667 int ret;
5668
5669 METHOD_TRACE("ips_read_adapter_status", 1);
5670
5671 scb = &ha->scbs[ha->max_cmds - 1];
5672
5673 ips_init_scb(ha, scb);
5674
5675 scb->timeout = ips_cmd_timeout;
5676 scb->cdb[0] = IPS_CMD_ENQUIRY;
5677
5678 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
5679 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5680 scb->cmd.basic_io.sg_count = 0;
5681 scb->cmd.basic_io.lba = 0;
5682 scb->cmd.basic_io.sector_count = 0;
5683 scb->cmd.basic_io.log_drv = 0;
5684 scb->data_len = sizeof (*ha->enq);
5685 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
5686
5687 /* send command */
5688 if (((ret =
5689 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5690 || (ret == IPS_SUCCESS_IMM)
5691 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5692 return (0);
5693
5694 return (1);
5695}
5696
5697/****************************************************************************/
5698/* */
5699/* Routine Name: ips_read_subsystem_parameters */
5700/* */
5701/* Routine Description: */
5702/* */
5703/* Read subsystem parameters from the adapter */
5704/* */
5705/****************************************************************************/
5706static int
5707ips_read_subsystem_parameters(ips_ha_t * ha, int intr)
5708{
5709 ips_scb_t *scb;
5710 int ret;
5711
5712 METHOD_TRACE("ips_read_subsystem_parameters", 1);
5713
5714 scb = &ha->scbs[ha->max_cmds - 1];
5715
5716 ips_init_scb(ha, scb);
5717
5718 scb->timeout = ips_cmd_timeout;
5719 scb->cdb[0] = IPS_CMD_GET_SUBSYS;
5720
5721 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS;
5722 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5723 scb->cmd.basic_io.sg_count = 0;
5724 scb->cmd.basic_io.lba = 0;
5725 scb->cmd.basic_io.sector_count = 0;
5726 scb->cmd.basic_io.log_drv = 0;
5727 scb->data_len = sizeof (*ha->subsys);
5728 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5729
5730 /* send command */
5731 if (((ret =
5732 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5733 || (ret == IPS_SUCCESS_IMM)
5734 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5735 return (0);
5736
5737 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys));
5738 return (1);
5739}
5740
5741/****************************************************************************/
5742/* */
5743/* Routine Name: ips_read_config */
5744/* */
5745/* Routine Description: */
5746/* */
5747/* Read the configuration on the adapter */
5748/* */
5749/****************************************************************************/
5750static int
5751ips_read_config(ips_ha_t * ha, int intr)
5752{
5753 ips_scb_t *scb;
5754 int i;
5755 int ret;
5756
5757 METHOD_TRACE("ips_read_config", 1);
5758
5759 /* set defaults for initiator IDs */
5760 for (i = 0; i < 4; i++)
5761 ha->conf->init_id[i] = 7;
5762
5763 scb = &ha->scbs[ha->max_cmds - 1];
5764
5765 ips_init_scb(ha, scb);
5766
5767 scb->timeout = ips_cmd_timeout;
5768 scb->cdb[0] = IPS_CMD_READ_CONF;
5769
5770 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF;
5771 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5772 scb->data_len = sizeof (*ha->conf);
5773 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5774
5775 /* send command */
5776 if (((ret =
5777 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5778 || (ret == IPS_SUCCESS_IMM)
5779 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5780
5781 memset(ha->conf, 0, sizeof (IPS_CONF));
5782
5783 /* reset initiator IDs */
5784 for (i = 0; i < 4; i++)
5785 ha->conf->init_id[i] = 7;
5786
5787 /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */
5788 if ((scb->basic_status & IPS_GSC_STATUS_MASK) ==
5789 IPS_CMD_CMPLT_WERROR)
5790 return (1);
5791
5792 return (0);
5793 }
5794
5795 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
5796 return (1);
5797}
5798
5799/****************************************************************************/
5800/* */
5801/* Routine Name: ips_readwrite_page5 */
5802/* */
5803/* Routine Description: */
5804/* */
5805/* Read nvram page 5 from the adapter */
5806/* */
5807/****************************************************************************/
5808static int
5809ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
5810{
5811 ips_scb_t *scb;
5812 int ret;
5813
5814 METHOD_TRACE("ips_readwrite_page5", 1);
5815
5816 scb = &ha->scbs[ha->max_cmds - 1];
5817
5818 ips_init_scb(ha, scb);
5819
5820 scb->timeout = ips_cmd_timeout;
5821 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE;
5822
5823 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE;
5824 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb);
5825 scb->cmd.nvram.page = 5;
5826 scb->cmd.nvram.write = write;
5827 scb->cmd.nvram.reserved = 0;
5828 scb->cmd.nvram.reserved2 = 0;
5829 scb->data_len = sizeof (*ha->nvram);
5830 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
5831 if (write)
5832 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
5833
5834 /* issue the command */
5835 if (((ret =
5836 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5837 || (ret == IPS_SUCCESS_IMM)
5838 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5839
5840 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5));
5841
5842 return (0);
5843 }
5844 if (!write)
5845 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram));
5846 return (1);
5847}
5848
5849/****************************************************************************/
5850/* */
5851/* Routine Name: ips_clear_adapter */
5852/* */
5853/* Routine Description: */
5854/* */
5855/* Clear the stripe lock tables */
5856/* */
5857/****************************************************************************/
5858static int
5859ips_clear_adapter(ips_ha_t * ha, int intr)
5860{
5861 ips_scb_t *scb;
5862 int ret;
5863
5864 METHOD_TRACE("ips_clear_adapter", 1);
5865
5866 scb = &ha->scbs[ha->max_cmds - 1];
5867
5868 ips_init_scb(ha, scb);
5869
5870 scb->timeout = ips_reset_timeout;
5871 scb->cdb[0] = IPS_CMD_CONFIG_SYNC;
5872
5873 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC;
5874 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb);
5875 scb->cmd.config_sync.channel = 0;
5876 scb->cmd.config_sync.source_target = IPS_POCL;
5877 scb->cmd.config_sync.reserved = 0;
5878 scb->cmd.config_sync.reserved2 = 0;
5879 scb->cmd.config_sync.reserved3 = 0;
5880
5881 /* issue command */
5882 if (((ret =
5883 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE)
5884 || (ret == IPS_SUCCESS_IMM)
5885 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5886 return (0);
5887
5888 /* send unlock stripe command */
5889 ips_init_scb(ha, scb);
5890
5891 scb->cdb[0] = IPS_CMD_ERROR_TABLE;
5892 scb->timeout = ips_reset_timeout;
5893
5894 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE;
5895 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb);
5896 scb->cmd.unlock_stripe.log_drv = 0;
5897 scb->cmd.unlock_stripe.control = IPS_CSL;
5898 scb->cmd.unlock_stripe.reserved = 0;
5899 scb->cmd.unlock_stripe.reserved2 = 0;
5900 scb->cmd.unlock_stripe.reserved3 = 0;
5901
5902 /* issue command */
5903 if (((ret =
5904 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5905 || (ret == IPS_SUCCESS_IMM)
5906 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5907 return (0);
5908
5909 return (1);
5910}
5911
5912/****************************************************************************/
5913/* */
5914/* Routine Name: ips_ffdc_reset */
5915/* */
5916/* Routine Description: */
5917/* */
5918/* FFDC: write reset info */
5919/* */
5920/****************************************************************************/
5921static void
5922ips_ffdc_reset(ips_ha_t * ha, int intr)
5923{
5924 ips_scb_t *scb;
5925
5926 METHOD_TRACE("ips_ffdc_reset", 1);
5927
5928 scb = &ha->scbs[ha->max_cmds - 1];
5929
5930 ips_init_scb(ha, scb);
5931
5932 scb->timeout = ips_cmd_timeout;
5933 scb->cdb[0] = IPS_CMD_FFDC;
5934 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
5935 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
5936 scb->cmd.ffdc.reset_count = ha->reset_count;
5937 scb->cmd.ffdc.reset_type = 0x80;
5938
5939 /* convert time to what the card wants */
5940 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
5941
5942 /* issue command */
5943 ips_send_wait(ha, scb, ips_cmd_timeout, intr);
5944}
5945
5946/****************************************************************************/
5947/* */
5948/* Routine Name: ips_ffdc_time */
5949/* */
5950/* Routine Description: */
5951/* */
5952/* FFDC: write time info */
5953/* */
5954/****************************************************************************/
5955static void
5956ips_ffdc_time(ips_ha_t * ha)
5957{
5958 ips_scb_t *scb;
5959
5960 METHOD_TRACE("ips_ffdc_time", 1);
5961
5962 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num);
5963
5964 scb = &ha->scbs[ha->max_cmds - 1];
5965
5966 ips_init_scb(ha, scb);
5967
5968 scb->timeout = ips_cmd_timeout;
5969 scb->cdb[0] = IPS_CMD_FFDC;
5970 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
5971 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
5972 scb->cmd.ffdc.reset_count = 0;
5973 scb->cmd.ffdc.reset_type = 0;
5974
5975 /* convert time to what the card wants */
5976 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
5977
5978 /* issue command */
5979 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC);
5980}
5981
5982/****************************************************************************/
5983/* */
5984/* Routine Name: ips_fix_ffdc_time */
5985/* */
5986/* Routine Description: */
5987/* Adjust time_t to what the card wants */
5988/* */
5989/****************************************************************************/
5990static void
5991ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time_t current_time)
5992{
5993 long days;
5994 long rem;
5995 int i;
5996 int year;
5997 int yleap;
5998 int year_lengths[2] = { IPS_DAYS_NORMAL_YEAR, IPS_DAYS_LEAP_YEAR };
5999 int month_lengths[12][2] = { {31, 31},
6000 {28, 29},
6001 {31, 31},
6002 {30, 30},
6003 {31, 31},
6004 {30, 30},
6005 {31, 31},
6006 {31, 31},
6007 {30, 30},
6008 {31, 31},
6009 {30, 30},
6010 {31, 31}
6011 };
6012
6013 METHOD_TRACE("ips_fix_ffdc_time", 1);
6014
6015 days = current_time / IPS_SECS_DAY;
6016 rem = current_time % IPS_SECS_DAY;
6017
6018 scb->cmd.ffdc.hour = (rem / IPS_SECS_HOUR);
6019 rem = rem % IPS_SECS_HOUR;
6020 scb->cmd.ffdc.minute = (rem / IPS_SECS_MIN);
6021 scb->cmd.ffdc.second = (rem % IPS_SECS_MIN);
6022
6023 year = IPS_EPOCH_YEAR;
6024 while (days < 0 || days >= year_lengths[yleap = IPS_IS_LEAP_YEAR(year)]) {
6025 int newy;
6026
6027 newy = year + (days / IPS_DAYS_NORMAL_YEAR);
6028 if (days < 0)
6029 --newy;
6030 days -= (newy - year) * IPS_DAYS_NORMAL_YEAR +
6031 IPS_NUM_LEAP_YEARS_THROUGH(newy - 1) -
6032 IPS_NUM_LEAP_YEARS_THROUGH(year - 1);
6033 year = newy;
6034 }
6035
6036 scb->cmd.ffdc.yearH = year / 100;
6037 scb->cmd.ffdc.yearL = year % 100;
6038
6039 for (i = 0; days >= month_lengths[i][yleap]; ++i)
6040 days -= month_lengths[i][yleap];
6041
6042 scb->cmd.ffdc.month = i + 1;
6043 scb->cmd.ffdc.day = days + 1;
6044}
6045
6046/****************************************************************************
6047 * BIOS Flash Routines *
6048 ****************************************************************************/
6049
6050/****************************************************************************/
6051/* */
6052/* Routine Name: ips_erase_bios */
6053/* */
6054/* Routine Description: */
6055/* Erase the BIOS on the adapter */
6056/* */
6057/****************************************************************************/
6058static int
6059ips_erase_bios(ips_ha_t * ha)
6060{
6061 int timeout;
6062 uint8_t status = 0;
6063
6064 METHOD_TRACE("ips_erase_bios", 1);
6065
6066 status = 0;
6067
6068 /* Clear the status register */
6069 outl(0, ha->io_addr + IPS_REG_FLAP);
6070 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6071 udelay(25); /* 25 us */
6072
6073 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6074 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6075 udelay(25); /* 25 us */
6076
6077 /* Erase Setup */
6078 outb(0x20, ha->io_addr + IPS_REG_FLDP);
6079 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6080 udelay(25); /* 25 us */
6081
6082 /* Erase Confirm */
6083 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
6084 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6085 udelay(25); /* 25 us */
6086
6087 /* Erase Status */
6088 outb(0x70, ha->io_addr + IPS_REG_FLDP);
6089 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6090 udelay(25); /* 25 us */
6091
6092 timeout = 80000; /* 80 seconds */
6093
6094 while (timeout > 0) {
6095 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6096 outl(0, ha->io_addr + IPS_REG_FLAP);
6097 udelay(25); /* 25 us */
6098 }
6099
6100 status = inb(ha->io_addr + IPS_REG_FLDP);
6101
6102 if (status & 0x80)
6103 break;
6104
6105 MDELAY(1);
6106 timeout--;
6107 }
6108
6109 /* check for timeout */
6110 if (timeout <= 0) {
6111 /* timeout */
6112
6113 /* try to suspend the erase */
6114 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
6115 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6116 udelay(25); /* 25 us */
6117
6118 /* wait for 10 seconds */
6119 timeout = 10000;
6120 while (timeout > 0) {
6121 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6122 outl(0, ha->io_addr + IPS_REG_FLAP);
6123 udelay(25); /* 25 us */
6124 }
6125
6126 status = inb(ha->io_addr + IPS_REG_FLDP);
6127
6128 if (status & 0xC0)
6129 break;
6130
6131 MDELAY(1);
6132 timeout--;
6133 }
6134
6135 return (1);
6136 }
6137
6138 /* check for valid VPP */
6139 if (status & 0x08)
6140 /* VPP failure */
6141 return (1);
6142
6143 /* check for successful flash */
6144 if (status & 0x30)
6145 /* sequence error */
6146 return (1);
6147
6148 /* Otherwise, we were successful */
6149 /* clear status */
6150 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6151 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6152 udelay(25); /* 25 us */
6153
6154 /* enable reads */
6155 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6156 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6157 udelay(25); /* 25 us */
6158
6159 return (0);
6160}
6161
6162/****************************************************************************/
6163/* */
6164/* Routine Name: ips_erase_bios_memio */
6165/* */
6166/* Routine Description: */
6167/* Erase the BIOS on the adapter */
6168/* */
6169/****************************************************************************/
6170static int
6171ips_erase_bios_memio(ips_ha_t * ha)
6172{
6173 int timeout;
6174 uint8_t status;
6175
6176 METHOD_TRACE("ips_erase_bios_memio", 1);
6177
6178 status = 0;
6179
6180 /* Clear the status register */
6181 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6182 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6183 udelay(25); /* 25 us */
6184
6185 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6186 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6187 udelay(25); /* 25 us */
6188
6189 /* Erase Setup */
6190 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6191 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6192 udelay(25); /* 25 us */
6193
6194 /* Erase Confirm */
6195 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6196 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6197 udelay(25); /* 25 us */
6198
6199 /* Erase Status */
6200 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6201 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6202 udelay(25); /* 25 us */
6203
6204 timeout = 80000; /* 80 seconds */
6205
6206 while (timeout > 0) {
6207 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6208 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6209 udelay(25); /* 25 us */
6210 }
6211
6212 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6213
6214 if (status & 0x80)
6215 break;
6216
6217 MDELAY(1);
6218 timeout--;
6219 }
6220
6221 /* check for timeout */
6222 if (timeout <= 0) {
6223 /* timeout */
6224
6225 /* try to suspend the erase */
6226 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6227 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6228 udelay(25); /* 25 us */
6229
6230 /* wait for 10 seconds */
6231 timeout = 10000;
6232 while (timeout > 0) {
6233 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6234 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6235 udelay(25); /* 25 us */
6236 }
6237
6238 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6239
6240 if (status & 0xC0)
6241 break;
6242
6243 MDELAY(1);
6244 timeout--;
6245 }
6246
6247 return (1);
6248 }
6249
6250 /* check for valid VPP */
6251 if (status & 0x08)
6252 /* VPP failure */
6253 return (1);
6254
6255 /* check for successful flash */
6256 if (status & 0x30)
6257 /* sequence error */
6258 return (1);
6259
6260 /* Otherwise, we were successful */
6261 /* clear status */
6262 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6263 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6264 udelay(25); /* 25 us */
6265
6266 /* enable reads */
6267 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6268 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6269 udelay(25); /* 25 us */
6270
6271 return (0);
6272}
6273
6274/****************************************************************************/
6275/* */
6276/* Routine Name: ips_program_bios */
6277/* */
6278/* Routine Description: */
6279/* Program the BIOS on the adapter */
6280/* */
6281/****************************************************************************/
6282static int
6283ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6284 uint32_t offset)
6285{
6286 int i;
6287 int timeout;
6288 uint8_t status = 0;
6289
6290 METHOD_TRACE("ips_program_bios", 1);
6291
6292 status = 0;
6293
6294 for (i = 0; i < buffersize; i++) {
6295 /* write a byte */
6296 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6297 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6298 udelay(25); /* 25 us */
6299
6300 outb(0x40, ha->io_addr + IPS_REG_FLDP);
6301 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6302 udelay(25); /* 25 us */
6303
6304 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
6305 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6306 udelay(25); /* 25 us */
6307
6308 /* wait up to one second */
6309 timeout = 1000;
6310 while (timeout > 0) {
6311 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6312 outl(0, ha->io_addr + IPS_REG_FLAP);
6313 udelay(25); /* 25 us */
6314 }
6315
6316 status = inb(ha->io_addr + IPS_REG_FLDP);
6317
6318 if (status & 0x80)
6319 break;
6320
6321 MDELAY(1);
6322 timeout--;
6323 }
6324
6325 if (timeout == 0) {
6326 /* timeout error */
6327 outl(0, ha->io_addr + IPS_REG_FLAP);
6328 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6329 udelay(25); /* 25 us */
6330
6331 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6332 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6333 udelay(25); /* 25 us */
6334
6335 return (1);
6336 }
6337
6338 /* check the status */
6339 if (status & 0x18) {
6340 /* programming error */
6341 outl(0, ha->io_addr + IPS_REG_FLAP);
6342 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6343 udelay(25); /* 25 us */
6344
6345 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6346 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6347 udelay(25); /* 25 us */
6348
6349 return (1);
6350 }
6351 } /* end for */
6352
6353 /* Enable reading */
6354 outl(0, ha->io_addr + IPS_REG_FLAP);
6355 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6356 udelay(25); /* 25 us */
6357
6358 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6359 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6360 udelay(25); /* 25 us */
6361
6362 return (0);
6363}
6364
6365/****************************************************************************/
6366/* */
6367/* Routine Name: ips_program_bios_memio */
6368/* */
6369/* Routine Description: */
6370/* Program the BIOS on the adapter */
6371/* */
6372/****************************************************************************/
6373static int
6374ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6375 uint32_t offset)
6376{
6377 int i;
6378 int timeout;
6379 uint8_t status = 0;
6380
6381 METHOD_TRACE("ips_program_bios_memio", 1);
6382
6383 status = 0;
6384
6385 for (i = 0; i < buffersize; i++) {
6386 /* write a byte */
6387 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6388 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6389 udelay(25); /* 25 us */
6390
6391 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6392 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6393 udelay(25); /* 25 us */
6394
6395 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6396 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6397 udelay(25); /* 25 us */
6398
6399 /* wait up to one second */
6400 timeout = 1000;
6401 while (timeout > 0) {
6402 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6403 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6404 udelay(25); /* 25 us */
6405 }
6406
6407 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6408
6409 if (status & 0x80)
6410 break;
6411
6412 MDELAY(1);
6413 timeout--;
6414 }
6415
6416 if (timeout == 0) {
6417 /* timeout error */
6418 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6419 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6420 udelay(25); /* 25 us */
6421
6422 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6423 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6424 udelay(25); /* 25 us */
6425
6426 return (1);
6427 }
6428
6429 /* check the status */
6430 if (status & 0x18) {
6431 /* programming error */
6432 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6433 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6434 udelay(25); /* 25 us */
6435
6436 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6437 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6438 udelay(25); /* 25 us */
6439
6440 return (1);
6441 }
6442 } /* end for */
6443
6444 /* Enable reading */
6445 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6446 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6447 udelay(25); /* 25 us */
6448
6449 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6450 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6451 udelay(25); /* 25 us */
6452
6453 return (0);
6454}
6455
6456/****************************************************************************/
6457/* */
6458/* Routine Name: ips_verify_bios */
6459/* */
6460/* Routine Description: */
6461/* Verify the BIOS on the adapter */
6462/* */
6463/****************************************************************************/
6464static int
6465ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6466 uint32_t offset)
6467{
6468 uint8_t checksum;
6469 int i;
6470
6471 METHOD_TRACE("ips_verify_bios", 1);
6472
6473 /* test 1st byte */
6474 outl(0, ha->io_addr + IPS_REG_FLAP);
6475 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6476 udelay(25); /* 25 us */
6477
6478 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6479 return (1);
6480
6481 outl(1, ha->io_addr + IPS_REG_FLAP);
6482 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6483 udelay(25); /* 25 us */
6484 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6485 return (1);
6486
6487 checksum = 0xff;
6488 for (i = 2; i < buffersize; i++) {
6489
6490 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6491 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6492 udelay(25); /* 25 us */
6493
6494 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
6495 }
6496
6497 if (checksum != 0)
6498 /* failure */
6499 return (1);
6500 else
6501 /* success */
6502 return (0);
6503}
6504
6505/****************************************************************************/
6506/* */
6507/* Routine Name: ips_verify_bios_memio */
6508/* */
6509/* Routine Description: */
6510/* Verify the BIOS on the adapter */
6511/* */
6512/****************************************************************************/
6513static int
6514ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6515 uint32_t offset)
6516{
6517 uint8_t checksum;
6518 int i;
6519
6520 METHOD_TRACE("ips_verify_bios_memio", 1);
6521
6522 /* test 1st byte */
6523 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6524 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6525 udelay(25); /* 25 us */
6526
6527 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6528 return (1);
6529
6530 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6531 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6532 udelay(25); /* 25 us */
6533 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6534 return (1);
6535
6536 checksum = 0xff;
6537 for (i = 2; i < buffersize; i++) {
6538
6539 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6540 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6541 udelay(25); /* 25 us */
6542
6543 checksum =
6544 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6545 }
6546
6547 if (checksum != 0)
6548 /* failure */
6549 return (1);
6550 else
6551 /* success */
6552 return (0);
6553}
6554
6555/****************************************************************************/
6556/* */
6557/* Routine Name: ips_abort_init */
6558/* */
6559/* Routine Description: */
6560/* cleanup routine for a failed adapter initialization */
6561/****************************************************************************/
6562static int
6563ips_abort_init(ips_ha_t * ha, int index)
6564{
6565 ha->active = 0;
6566 ips_free(ha);
6567 ips_ha[index] = NULL;
6568 ips_sh[index] = NULL;
6569 return -1;
6570}
6571
6572/****************************************************************************/
6573/* */
6574/* Routine Name: ips_shift_controllers */
6575/* */
6576/* Routine Description: */
6577/* helper function for ordering adapters */
6578/****************************************************************************/
6579static void
6580ips_shift_controllers(int lowindex, int highindex)
6581{
6582 ips_ha_t *ha_sav = ips_ha[highindex];
6583 struct Scsi_Host *sh_sav = ips_sh[highindex];
6584 int i;
6585
6586 for (i = highindex; i > lowindex; i--) {
6587 ips_ha[i] = ips_ha[i - 1];
6588 ips_sh[i] = ips_sh[i - 1];
6589 ips_ha[i]->host_num = i;
6590 }
6591 ha_sav->host_num = lowindex;
6592 ips_ha[lowindex] = ha_sav;
6593 ips_sh[lowindex] = sh_sav;
6594}
6595
6596/****************************************************************************/
6597/* */
6598/* Routine Name: ips_order_controllers */
6599/* */
6600/* Routine Description: */
6601/* place controllers is the "proper" boot order */
6602/****************************************************************************/
6603static void
6604ips_order_controllers(void)
6605{
6606 int i, j, tmp, position = 0;
6607 IPS_NVRAM_P5 *nvram;
6608 if (!ips_ha[0])
6609 return;
6610 nvram = ips_ha[0]->nvram;
6611
6612 if (nvram->adapter_order[0]) {
6613 for (i = 1; i <= nvram->adapter_order[0]; i++) {
6614 for (j = position; j < ips_num_controllers; j++) {
6615 switch (ips_ha[j]->ad_type) {
6616 case IPS_ADTYPE_SERVERAID6M:
6617 case IPS_ADTYPE_SERVERAID7M:
6618 if (nvram->adapter_order[i] == 'M') {
6619 ips_shift_controllers(position,
6620 j);
6621 position++;
6622 }
6623 break;
6624 case IPS_ADTYPE_SERVERAID4L:
6625 case IPS_ADTYPE_SERVERAID4M:
6626 case IPS_ADTYPE_SERVERAID4MX:
6627 case IPS_ADTYPE_SERVERAID4LX:
6628 if (nvram->adapter_order[i] == 'N') {
6629 ips_shift_controllers(position,
6630 j);
6631 position++;
6632 }
6633 break;
6634 case IPS_ADTYPE_SERVERAID6I:
6635 case IPS_ADTYPE_SERVERAID5I2:
6636 case IPS_ADTYPE_SERVERAID5I1:
6637 case IPS_ADTYPE_SERVERAID7k:
6638 if (nvram->adapter_order[i] == 'S') {
6639 ips_shift_controllers(position,
6640 j);
6641 position++;
6642 }
6643 break;
6644 case IPS_ADTYPE_SERVERAID:
6645 case IPS_ADTYPE_SERVERAID2:
6646 case IPS_ADTYPE_NAVAJO:
6647 case IPS_ADTYPE_KIOWA:
6648 case IPS_ADTYPE_SERVERAID3L:
6649 case IPS_ADTYPE_SERVERAID3:
6650 case IPS_ADTYPE_SERVERAID4H:
6651 if (nvram->adapter_order[i] == 'A') {
6652 ips_shift_controllers(position,
6653 j);
6654 position++;
6655 }
6656 break;
6657 default:
6658 break;
6659 }
6660 }
6661 }
6662 /* if adapter_order[0], then ordering is complete */
6663 return;
6664 }
6665 /* old bios, use older ordering */
6666 tmp = 0;
6667 for (i = position; i < ips_num_controllers; i++) {
6668 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 ||
6669 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) {
6670 ips_shift_controllers(position, i);
6671 position++;
6672 tmp = 1;
6673 }
6674 }
6675 /* if there were no 5I cards, then don't do any extra ordering */
6676 if (!tmp)
6677 return;
6678 for (i = position; i < ips_num_controllers; i++) {
6679 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L ||
6680 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M ||
6681 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX ||
6682 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) {
6683 ips_shift_controllers(position, i);
6684 position++;
6685 }
6686 }
6687
6688 return;
6689}
6690
6691/****************************************************************************/
6692/* */
6693/* Routine Name: ips_register_scsi */
6694/* */
6695/* Routine Description: */
6696/* perform any registration and setup with the scsi layer */
6697/****************************************************************************/
6698static int
6699ips_register_scsi(int index)
6700{
6701 struct Scsi_Host *sh;
6702 ips_ha_t *ha, *oldha = ips_ha[index];
6703 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t));
6704 if (!sh) {
6705 IPS_PRINTK(KERN_WARNING, oldha->pcidev,
6706 "Unable to register controller with SCSI subsystem\n");
6707 return -1;
6708 }
6709 ha = IPS_HA(sh);
6710 memcpy(ha, oldha, sizeof (ips_ha_t));
6711 free_irq(oldha->pcidev->irq, oldha);
6712 /* Install the interrupt handler with the new ha */
6713 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
6714 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6715 "Unable to install interrupt handler\n");
6716 goto err_out_sh;
6717 }
6718
6719 kfree(oldha);
6720
6721 /* Store away needed values for later use */
6722 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
6723 sh->sg_tablesize = sh->hostt->sg_tablesize;
6724 sh->can_queue = sh->hostt->can_queue;
6725 sh->cmd_per_lun = sh->hostt->cmd_per_lun;
6726 sh->use_clustering = sh->hostt->use_clustering;
6727 sh->max_sectors = 128;
6728
6729 sh->max_id = ha->ntargets;
6730 sh->max_lun = ha->nlun;
6731 sh->max_channel = ha->nbus - 1;
6732 sh->can_queue = ha->max_cmds - 1;
6733
6734 if (scsi_add_host(sh, &ha->pcidev->dev))
6735 goto err_out;
6736
6737 ips_sh[index] = sh;
6738 ips_ha[index] = ha;
6739
6740 scsi_scan_host(sh);
6741
6742 return 0;
6743
6744err_out:
6745 free_irq(ha->pcidev->irq, ha);
6746err_out_sh:
6747 scsi_host_put(sh);
6748 return -1;
6749}
6750
6751/*---------------------------------------------------------------------------*/
6752/* Routine Name: ips_remove_device */
6753/* */
6754/* Routine Description: */
6755/* Remove one Adapter ( Hot Plugging ) */
6756/*---------------------------------------------------------------------------*/
6757static void
6758ips_remove_device(struct pci_dev *pci_dev)
6759{
6760 struct Scsi_Host *sh = pci_get_drvdata(pci_dev);
6761
6762 pci_set_drvdata(pci_dev, NULL);
6763
6764 ips_release(sh);
6765
6766 pci_release_regions(pci_dev);
6767 pci_disable_device(pci_dev);
6768}
6769
6770/****************************************************************************/
6771/* */
6772/* Routine Name: ips_module_init */
6773/* */
6774/* Routine Description: */
6775/* function called on module load */
6776/****************************************************************************/
6777static int __init
6778ips_module_init(void)
6779{
6780#if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__)
6781 printk(KERN_ERR "ips: This driver has only been tested on the x86/ia64/x86_64 platforms\n");
6782 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
6783#endif
6784
6785 if (pci_register_driver(&ips_pci_driver) < 0)
6786 return -ENODEV;
6787 ips_driver_template.module = THIS_MODULE;
6788 ips_order_controllers();
6789 if (!ips_detect(&ips_driver_template)) {
6790 pci_unregister_driver(&ips_pci_driver);
6791 return -ENODEV;
6792 }
6793 register_reboot_notifier(&ips_notifier);
6794 return 0;
6795}
6796
6797/****************************************************************************/
6798/* */
6799/* Routine Name: ips_module_exit */
6800/* */
6801/* Routine Description: */
6802/* function called on module unload */
6803/****************************************************************************/
6804static void __exit
6805ips_module_exit(void)
6806{
6807 pci_unregister_driver(&ips_pci_driver);
6808 unregister_reboot_notifier(&ips_notifier);
6809}
6810
6811module_init(ips_module_init);
6812module_exit(ips_module_exit);
6813
6814/*---------------------------------------------------------------------------*/
6815/* Routine Name: ips_insert_device */
6816/* */
6817/* Routine Description: */
6818/* Add One Adapter ( Hot Plug ) */
6819/* */
6820/* Return Value: */
6821/* 0 if Successful, else non-zero */
6822/*---------------------------------------------------------------------------*/
6823static int
6824ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent)
6825{
6826 int index = -1;
6827 int rc;
6828
6829 METHOD_TRACE("ips_insert_device", 1);
6830 rc = pci_enable_device(pci_dev);
6831 if (rc)
6832 return rc;
6833
6834 rc = pci_request_regions(pci_dev, "ips");
6835 if (rc)
6836 goto err_out;
6837
6838 rc = ips_init_phase1(pci_dev, &index);
6839 if (rc == SUCCESS)
6840 rc = ips_init_phase2(index);
6841
6842 if (ips_hotplug)
6843 if (ips_register_scsi(index)) {
6844 ips_free(ips_ha[index]);
6845 rc = -1;
6846 }
6847
6848 if (rc == SUCCESS)
6849 ips_num_controllers++;
6850
6851 ips_next_controller = ips_num_controllers;
6852
6853 if (rc < 0) {
6854 rc = -ENODEV;
6855 goto err_out_regions;
6856 }
6857
6858 pci_set_drvdata(pci_dev, ips_sh[index]);
6859 return 0;
6860
6861err_out_regions:
6862 pci_release_regions(pci_dev);
6863err_out:
6864 pci_disable_device(pci_dev);
6865 return rc;
6866}
6867
6868/*---------------------------------------------------------------------------*/
6869/* Routine Name: ips_init_phase1 */
6870/* */
6871/* Routine Description: */
6872/* Adapter Initialization */
6873/* */
6874/* Return Value: */
6875/* 0 if Successful, else non-zero */
6876/*---------------------------------------------------------------------------*/
6877static int
6878ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
6879{
6880 ips_ha_t *ha;
6881 uint32_t io_addr;
6882 uint32_t mem_addr;
6883 uint32_t io_len;
6884 uint32_t mem_len;
6885 uint8_t bus;
6886 uint8_t func;
6887 int j;
6888 int index;
6889 dma_addr_t dma_address;
6890 char __iomem *ioremap_ptr;
6891 char __iomem *mem_ptr;
6892 uint32_t IsDead;
6893
6894 METHOD_TRACE("ips_init_phase1", 1);
6895 index = IPS_MAX_ADAPTERS;
6896 for (j = 0; j < IPS_MAX_ADAPTERS; j++) {
6897 if (ips_ha[j] == NULL) {
6898 index = j;
6899 break;
6900 }
6901 }
6902
6903 if (index >= IPS_MAX_ADAPTERS)
6904 return -1;
6905
6906 /* stuff that we get in dev */
6907 bus = pci_dev->bus->number;
6908 func = pci_dev->devfn;
6909
6910 /* Init MEM/IO addresses to 0 */
6911 mem_addr = 0;
6912 io_addr = 0;
6913 mem_len = 0;
6914 io_len = 0;
6915
6916 for (j = 0; j < 2; j++) {
6917 if (!pci_resource_start(pci_dev, j))
6918 break;
6919
6920 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) {
6921 io_addr = pci_resource_start(pci_dev, j);
6922 io_len = pci_resource_len(pci_dev, j);
6923 } else {
6924 mem_addr = pci_resource_start(pci_dev, j);
6925 mem_len = pci_resource_len(pci_dev, j);
6926 }
6927 }
6928
6929 /* setup memory mapped area (if applicable) */
6930 if (mem_addr) {
6931 uint32_t base;
6932 uint32_t offs;
6933
6934 base = mem_addr & PAGE_MASK;
6935 offs = mem_addr - base;
6936 ioremap_ptr = ioremap(base, PAGE_SIZE);
6937 if (!ioremap_ptr)
6938 return -1;
6939 mem_ptr = ioremap_ptr + offs;
6940 } else {
6941 ioremap_ptr = NULL;
6942 mem_ptr = NULL;
6943 }
6944
6945 /* found a controller */
6946 ha = kzalloc(sizeof (ips_ha_t), GFP_KERNEL);
6947 if (ha == NULL) {
6948 IPS_PRINTK(KERN_WARNING, pci_dev,
6949 "Unable to allocate temporary ha struct\n");
6950 return -1;
6951 }
6952
6953 ips_sh[index] = NULL;
6954 ips_ha[index] = ha;
6955 ha->active = 1;
6956
6957 /* Store info in HA structure */
6958 ha->io_addr = io_addr;
6959 ha->io_len = io_len;
6960 ha->mem_addr = mem_addr;
6961 ha->mem_len = mem_len;
6962 ha->mem_ptr = mem_ptr;
6963 ha->ioremap_ptr = ioremap_ptr;
6964 ha->host_num = (uint32_t) index;
6965 ha->slot_num = PCI_SLOT(pci_dev->devfn);
6966 ha->pcidev = pci_dev;
6967
6968 /*
6969 * Set the pci_dev's dma_mask. Not all adapters support 64bit
6970 * addressing so don't enable it if the adapter can't support
6971 * it! Also, don't use 64bit addressing if dma addresses
6972 * are guaranteed to be < 4G.
6973 */
6974 if (IPS_ENABLE_DMA64 && IPS_HAS_ENH_SGLIST(ha) &&
6975 !pci_set_dma_mask(ha->pcidev, DMA_BIT_MASK(64))) {
6976 (ha)->flags |= IPS_HA_ENH_SG;
6977 } else {
6978 if (pci_set_dma_mask(ha->pcidev, DMA_BIT_MASK(32)) != 0) {
6979 printk(KERN_WARNING "Unable to set DMA Mask\n");
6980 return ips_abort_init(ha, index);
6981 }
6982 }
6983 if(ips_cd_boot && !ips_FlashData){
6984 ips_FlashData = pci_alloc_consistent(pci_dev, PAGE_SIZE << 7,
6985 &ips_flashbusaddr);
6986 }
6987
6988 ha->enq = pci_alloc_consistent(pci_dev, sizeof (IPS_ENQ),
6989 &ha->enq_busaddr);
6990 if (!ha->enq) {
6991 IPS_PRINTK(KERN_WARNING, pci_dev,
6992 "Unable to allocate host inquiry structure\n");
6993 return ips_abort_init(ha, index);
6994 }
6995
6996 ha->adapt = pci_alloc_consistent(pci_dev, sizeof (IPS_ADAPTER) +
6997 sizeof (IPS_IO_CMD), &dma_address);
6998 if (!ha->adapt) {
6999 IPS_PRINTK(KERN_WARNING, pci_dev,
7000 "Unable to allocate host adapt & dummy structures\n");
7001 return ips_abort_init(ha, index);
7002 }
7003 ha->adapt->hw_status_start = dma_address;
7004 ha->dummy = (void *) (ha->adapt + 1);
7005
7006
7007
7008 ha->logical_drive_info = pci_alloc_consistent(pci_dev, sizeof (IPS_LD_INFO), &dma_address);
7009 if (!ha->logical_drive_info) {
7010 IPS_PRINTK(KERN_WARNING, pci_dev,
7011 "Unable to allocate logical drive info structure\n");
7012 return ips_abort_init(ha, index);
7013 }
7014 ha->logical_drive_info_dma_addr = dma_address;
7015
7016
7017 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL);
7018
7019 if (!ha->conf) {
7020 IPS_PRINTK(KERN_WARNING, pci_dev,
7021 "Unable to allocate host conf structure\n");
7022 return ips_abort_init(ha, index);
7023 }
7024
7025 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL);
7026
7027 if (!ha->nvram) {
7028 IPS_PRINTK(KERN_WARNING, pci_dev,
7029 "Unable to allocate host NVRAM structure\n");
7030 return ips_abort_init(ha, index);
7031 }
7032
7033 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL);
7034
7035 if (!ha->subsys) {
7036 IPS_PRINTK(KERN_WARNING, pci_dev,
7037 "Unable to allocate host subsystem structure\n");
7038 return ips_abort_init(ha, index);
7039 }
7040
7041 /* the ioctl buffer is now used during adapter initialization, so its
7042 * successful allocation is now required */
7043 if (ips_ioctlsize < PAGE_SIZE)
7044 ips_ioctlsize = PAGE_SIZE;
7045
7046 ha->ioctl_data = pci_alloc_consistent(pci_dev, ips_ioctlsize,
7047 &ha->ioctl_busaddr);
7048 ha->ioctl_len = ips_ioctlsize;
7049 if (!ha->ioctl_data) {
7050 IPS_PRINTK(KERN_WARNING, pci_dev,
7051 "Unable to allocate IOCTL data\n");
7052 return ips_abort_init(ha, index);
7053 }
7054
7055 /*
7056 * Setup Functions
7057 */
7058 ips_setup_funclist(ha);
7059
7060 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) {
7061 /* If Morpheus appears dead, reset it */
7062 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
7063 if (IsDead == 0xDEADBEEF) {
7064 ips_reset_morpheus(ha);
7065 }
7066 }
7067
7068 /*
7069 * Initialize the card if it isn't already
7070 */
7071
7072 if (!(*ha->func.isinit) (ha)) {
7073 if (!(*ha->func.init) (ha)) {
7074 /*
7075 * Initialization failed
7076 */
7077 IPS_PRINTK(KERN_WARNING, pci_dev,
7078 "Unable to initialize controller\n");
7079 return ips_abort_init(ha, index);
7080 }
7081 }
7082
7083 *indexPtr = index;
7084 return SUCCESS;
7085}
7086
7087/*---------------------------------------------------------------------------*/
7088/* Routine Name: ips_init_phase2 */
7089/* */
7090/* Routine Description: */
7091/* Adapter Initialization Phase 2 */
7092/* */
7093/* Return Value: */
7094/* 0 if Successful, else non-zero */
7095/*---------------------------------------------------------------------------*/
7096static int
7097ips_init_phase2(int index)
7098{
7099 ips_ha_t *ha;
7100
7101 ha = ips_ha[index];
7102
7103 METHOD_TRACE("ips_init_phase2", 1);
7104 if (!ha->active) {
7105 ips_ha[index] = NULL;
7106 return -1;
7107 }
7108
7109 /* Install the interrupt handler */
7110 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
7111 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7112 "Unable to install interrupt handler\n");
7113 return ips_abort_init(ha, index);
7114 }
7115
7116 /*
7117 * Allocate a temporary SCB for initialization
7118 */
7119 ha->max_cmds = 1;
7120 if (!ips_allocatescbs(ha)) {
7121 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7122 "Unable to allocate a CCB\n");
7123 free_irq(ha->pcidev->irq, ha);
7124 return ips_abort_init(ha, index);
7125 }
7126
7127 if (!ips_hainit(ha)) {
7128 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7129 "Unable to initialize controller\n");
7130 free_irq(ha->pcidev->irq, ha);
7131 return ips_abort_init(ha, index);
7132 }
7133 /* Free the temporary SCB */
7134 ips_deallocatescbs(ha, 1);
7135
7136 /* allocate CCBs */
7137 if (!ips_allocatescbs(ha)) {
7138 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7139 "Unable to allocate CCBs\n");
7140 free_irq(ha->pcidev->irq, ha);
7141 return ips_abort_init(ha, index);
7142 }
7143
7144 return SUCCESS;
7145}
7146
7147MODULE_LICENSE("GPL");
7148MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING);
7149MODULE_VERSION(IPS_VER_STRING);
7150
7151
7152/*
7153 * Overrides for Emacs so that we almost follow Linus's tabbing style.
7154 * Emacs will notice this stuff at the end of the file and automatically
7155 * adjust the settings for this buffer only. This must remain at the end
7156 * of the file.
7157 * ---------------------------------------------------------------------------
7158 * Local variables:
7159 * c-indent-level: 2
7160 * c-brace-imaginary-offset: 0
7161 * c-brace-offset: -2
7162 * c-argdecl-indent: 2
7163 * c-label-offset: -2
7164 * c-continued-statement-offset: 2
7165 * c-continued-brace-offset: 0
7166 * indent-tabs-mode: nil
7167 * tab-width: 8
7168 * End:
7169 */