1menu "IRQ chip support"
  2
  3config IRQCHIP
  4	def_bool y
  5	depends on OF_IRQ
  6
  7config ARM_GIC
  8	bool
  9	select IRQ_DOMAIN
 10	select IRQ_DOMAIN_HIERARCHY
 11	select MULTI_IRQ_HANDLER
 12	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
 13
 14config ARM_GIC_PM
 15	bool
 16	depends on PM
 17	select ARM_GIC
 18	select PM_CLK
 19
 20config ARM_GIC_MAX_NR
 21	int
 22	default 2 if ARCH_REALVIEW
 23	default 1
 24
 25config ARM_GIC_V2M
 26	bool
 27	depends on PCI
 28	select ARM_GIC
 29	select PCI_MSI
 30
 31config GIC_NON_BANKED
 32	bool
 33
 34config ARM_GIC_V3
 35	bool
 36	select IRQ_DOMAIN
 37	select MULTI_IRQ_HANDLER
 38	select IRQ_DOMAIN_HIERARCHY
 39	select PARTITION_PERCPU
 40	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
 41
 42config ARM_GIC_V3_ITS
 43	bool
 44	select GENERIC_MSI_IRQ_DOMAIN
 45	default ARM_GIC_V3
 46
 47config ARM_GIC_V3_ITS_PCI
 48	bool
 49	depends on ARM_GIC_V3_ITS
 50	depends on PCI
 51	depends on PCI_MSI
 52	default ARM_GIC_V3_ITS
 53
 54config ARM_GIC_V3_ITS_FSL_MC
 55	bool
 56	depends on ARM_GIC_V3_ITS
 57	depends on FSL_MC_BUS
 58	default ARM_GIC_V3_ITS
 59
 60config ARM_NVIC
 61	bool
 62	select IRQ_DOMAIN
 63	select IRQ_DOMAIN_HIERARCHY
 64	select GENERIC_IRQ_CHIP
 65
 66config ARM_VIC
 67	bool
 68	select IRQ_DOMAIN
 69	select MULTI_IRQ_HANDLER
 70
 71config ARM_VIC_NR
 72	int
 73	default 4 if ARCH_S5PV210
 74	default 2
 75	depends on ARM_VIC
 76	help
 77	  The maximum number of VICs available in the system, for
 78	  power management.
 79
 80config ARMADA_370_XP_IRQ
 81	bool
 82	select GENERIC_IRQ_CHIP
 83	select PCI_MSI if PCI
 84	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
 85
 86config ALPINE_MSI
 87	bool
 88	depends on PCI
 89	select PCI_MSI
 90	select GENERIC_IRQ_CHIP
 91
 92config ATMEL_AIC_IRQ
 93	bool
 94	select GENERIC_IRQ_CHIP
 95	select IRQ_DOMAIN
 96	select MULTI_IRQ_HANDLER
 97	select SPARSE_IRQ
 98
 99config ATMEL_AIC5_IRQ
100	bool
101	select GENERIC_IRQ_CHIP
102	select IRQ_DOMAIN
103	select MULTI_IRQ_HANDLER
104	select SPARSE_IRQ
105
106config I8259
107	bool
108	select IRQ_DOMAIN
109
110config BCM6345_L1_IRQ
111	bool
112	select GENERIC_IRQ_CHIP
113	select IRQ_DOMAIN
114	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
115
116config BCM7038_L1_IRQ
117	bool
118	select GENERIC_IRQ_CHIP
119	select IRQ_DOMAIN
120	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
121
122config BCM7120_L2_IRQ
123	bool
124	select GENERIC_IRQ_CHIP
125	select IRQ_DOMAIN
126
127config BRCMSTB_L2_IRQ
128	bool
129	select GENERIC_IRQ_CHIP
130	select IRQ_DOMAIN
131
132config DW_APB_ICTL
133	bool
134	select GENERIC_IRQ_CHIP
135	select IRQ_DOMAIN
136
137config FARADAY_FTINTC010
138	bool
139	select IRQ_DOMAIN
140	select MULTI_IRQ_HANDLER
141	select SPARSE_IRQ
142
143config HISILICON_IRQ_MBIGEN
144	bool
145	select ARM_GIC_V3
146	select ARM_GIC_V3_ITS
147
148config IMGPDC_IRQ
149	bool
150	select GENERIC_IRQ_CHIP
151	select IRQ_DOMAIN
152
153config IRQ_MIPS_CPU
154	bool
155	select GENERIC_IRQ_CHIP
156	select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
157	select IRQ_DOMAIN
158	select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
159	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
160
161config CLPS711X_IRQCHIP
162	bool
163	depends on ARCH_CLPS711X
164	select IRQ_DOMAIN
165	select MULTI_IRQ_HANDLER
166	select SPARSE_IRQ
167	default y
168
169config OMPIC
170	bool
171
172config OR1K_PIC
173	bool
174	select IRQ_DOMAIN
175
176config OMAP_IRQCHIP
177	bool
178	select GENERIC_IRQ_CHIP
179	select IRQ_DOMAIN
180
181config ORION_IRQCHIP
182	bool
183	select IRQ_DOMAIN
184	select MULTI_IRQ_HANDLER
185
186config PIC32_EVIC
187	bool
188	select GENERIC_IRQ_CHIP
189	select IRQ_DOMAIN
190
191config JCORE_AIC
192	bool "J-Core integrated AIC" if COMPILE_TEST
193	depends on OF
194	select IRQ_DOMAIN
195	help
196	  Support for the J-Core integrated AIC.
197
198config RENESAS_INTC_IRQPIN
199	bool
200	select IRQ_DOMAIN
201
202config RENESAS_IRQC
203	bool
204	select GENERIC_IRQ_CHIP
205	select IRQ_DOMAIN
206
207config ST_IRQCHIP
208	bool
209	select REGMAP
210	select MFD_SYSCON
211	help
212	  Enables SysCfg Controlled IRQs on STi based platforms.
213
214config TANGO_IRQ
215	bool
216	select IRQ_DOMAIN
217	select GENERIC_IRQ_CHIP
218
219config TB10X_IRQC
220	bool
221	select IRQ_DOMAIN
222	select GENERIC_IRQ_CHIP
223
224config TS4800_IRQ
225	tristate "TS-4800 IRQ controller"
226	select IRQ_DOMAIN
227	depends on HAS_IOMEM
228	depends on SOC_IMX51 || COMPILE_TEST
229	help
230	  Support for the TS-4800 FPGA IRQ controller
231
232config VERSATILE_FPGA_IRQ
233	bool
234	select IRQ_DOMAIN
235
236config VERSATILE_FPGA_IRQ_NR
237       int
238       default 4
239       depends on VERSATILE_FPGA_IRQ
240
241config XTENSA_MX
242	bool
243	select IRQ_DOMAIN
244	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
245
246config XILINX_INTC
247	bool
248	select IRQ_DOMAIN
249
250config IRQ_CROSSBAR
251	bool
252	help
253	  Support for a CROSSBAR ip that precedes the main interrupt controller.
254	  The primary irqchip invokes the crossbar's callback which inturn allocates
255	  a free irq and configures the IP. Thus the peripheral interrupts are
256	  routed to one of the free irqchip interrupt lines.
257
258config KEYSTONE_IRQ
259	tristate "Keystone 2 IRQ controller IP"
260	depends on ARCH_KEYSTONE
261	help
262		Support for Texas Instruments Keystone 2 IRQ controller IP which
263		is part of the Keystone 2 IPC mechanism
264
265config MIPS_GIC
266	bool
267	select GENERIC_IRQ_IPI
268	select IRQ_DOMAIN_HIERARCHY
269	select MIPS_CM
270
271config INGENIC_IRQ
272	bool
273	depends on MACH_INGENIC
274	default y
275
276config RENESAS_H8300H_INTC
277        bool
278	select IRQ_DOMAIN
279
280config RENESAS_H8S_INTC
281        bool
282	select IRQ_DOMAIN
283
284config IMX_GPCV2
285	bool
286	select IRQ_DOMAIN
287	help
288	  Enables the wakeup IRQs for IMX platforms with GPCv2 block
289
290config IRQ_MXS
291	def_bool y if MACH_ASM9260 || ARCH_MXS
292	select IRQ_DOMAIN
293	select STMP_DEVICE
294
295config MSCC_OCELOT_IRQ
296	bool
297	select IRQ_DOMAIN
298	select GENERIC_IRQ_CHIP
299
300config MVEBU_GICP
301	bool
302
303config MVEBU_ICU
304	bool
305
306config MVEBU_ODMI
307	bool
308	select GENERIC_MSI_IRQ_DOMAIN
309
310config MVEBU_PIC
311	bool
312
313config LS_SCFG_MSI
314	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
315	depends on PCI && PCI_MSI
316
317config PARTITION_PERCPU
318	bool
319
320config EZNPS_GIC
321	bool "NPS400 Global Interrupt Manager (GIM)"
322	depends on ARC || (COMPILE_TEST && !64BIT)
323	select IRQ_DOMAIN
324	help
325	  Support the EZchip NPS400 global interrupt controller
326
327config STM32_EXTI
328	bool
329	select IRQ_DOMAIN
330	select GENERIC_IRQ_CHIP
331
332config QCOM_IRQ_COMBINER
333	bool "QCOM IRQ combiner support"
334	depends on ARCH_QCOM && ACPI
335	select IRQ_DOMAIN
336	select IRQ_DOMAIN_HIERARCHY
337	help
338	  Say yes here to add support for the IRQ combiner devices embedded
339	  in Qualcomm Technologies chips.
340
341config IRQ_UNIPHIER_AIDET
342	bool "UniPhier AIDET support" if COMPILE_TEST
343	depends on ARCH_UNIPHIER || COMPILE_TEST
344	default ARCH_UNIPHIER
345	select IRQ_DOMAIN_HIERARCHY
346	help
347	  Support for the UniPhier AIDET (ARM Interrupt Detector).
348
349config MESON_IRQ_GPIO
350       bool "Meson GPIO Interrupt Multiplexer"
351       depends on ARCH_MESON
352       select IRQ_DOMAIN
353       select IRQ_DOMAIN_HIERARCHY
354       help
355         Support Meson SoC Family GPIO Interrupt Multiplexer
356
357config GOLDFISH_PIC
358       bool "Goldfish programmable interrupt controller"
359       depends on MIPS && (GOLDFISH || COMPILE_TEST)
360       select IRQ_DOMAIN
361       help
362         Say yes here to enable Goldfish interrupt controller driver used
363         for Goldfish based virtual platforms.
364
365config QCOM_PDC
366	bool "QCOM PDC"
367	depends on ARCH_QCOM
368	select IRQ_DOMAIN
369	select IRQ_DOMAIN_HIERARCHY
370	help
371	  Power Domain Controller driver to manage and configure wakeup
372	  IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
373
374endmenu