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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/firmware.h>
29#include <linux/platform_device.h>
30#include <linux/slab.h>
31#include "drmP.h"
32#include "radeon.h"
33#include "radeon_asic.h"
34#include "radeon_drm.h"
35#include "rv770d.h"
36#include "atom.h"
37#include "avivod.h"
38
39#define R700_PFP_UCODE_SIZE 848
40#define R700_PM4_UCODE_SIZE 1360
41
42static void rv770_gpu_init(struct radeon_device *rdev);
43void rv770_fini(struct radeon_device *rdev);
44static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
45
46u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
47{
48 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
49 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
50
51 /* Lock the graphics update lock */
52 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
53 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
54
55 /* update the scanout addresses */
56 if (radeon_crtc->crtc_id) {
57 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
58 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
59 } else {
60 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
61 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
62 }
63 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
64 (u32)crtc_base);
65 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
66 (u32)crtc_base);
67
68 /* Wait for update_pending to go high. */
69 while (!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING));
70 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
71
72 /* Unlock the lock, so double-buffering can take place inside vblank */
73 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
74 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
75
76 /* Return current update_pending status: */
77 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
78}
79
80/* get temperature in millidegrees */
81int rv770_get_temp(struct radeon_device *rdev)
82{
83 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
84 ASIC_T_SHIFT;
85 int actual_temp;
86
87 if (temp & 0x400)
88 actual_temp = -256;
89 else if (temp & 0x200)
90 actual_temp = 255;
91 else if (temp & 0x100) {
92 actual_temp = temp & 0x1ff;
93 actual_temp |= ~0x1ff;
94 } else
95 actual_temp = temp & 0xff;
96
97 return (actual_temp * 1000) / 2;
98}
99
100void rv770_pm_misc(struct radeon_device *rdev)
101{
102 int req_ps_idx = rdev->pm.requested_power_state_index;
103 int req_cm_idx = rdev->pm.requested_clock_mode_index;
104 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
105 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
106
107 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
108 /* 0xff01 is a flag rather then an actual voltage */
109 if (voltage->voltage == 0xff01)
110 return;
111 if (voltage->voltage != rdev->pm.current_vddc) {
112 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
113 rdev->pm.current_vddc = voltage->voltage;
114 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
115 }
116 }
117}
118
119/*
120 * GART
121 */
122int rv770_pcie_gart_enable(struct radeon_device *rdev)
123{
124 u32 tmp;
125 int r, i;
126
127 if (rdev->gart.table.vram.robj == NULL) {
128 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
129 return -EINVAL;
130 }
131 r = radeon_gart_table_vram_pin(rdev);
132 if (r)
133 return r;
134 radeon_gart_restore(rdev);
135 /* Setup L2 cache */
136 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
137 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
138 EFFECTIVE_L2_QUEUE_SIZE(7));
139 WREG32(VM_L2_CNTL2, 0);
140 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
141 /* Setup TLB control */
142 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
143 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
144 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
145 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
146 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
147 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
148 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
149 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
150 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
151 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
152 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
153 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
154 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
155 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
156 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
157 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
158 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
159 (u32)(rdev->dummy_page.addr >> 12));
160 for (i = 1; i < 7; i++)
161 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
162
163 r600_pcie_gart_tlb_flush(rdev);
164 rdev->gart.ready = true;
165 return 0;
166}
167
168void rv770_pcie_gart_disable(struct radeon_device *rdev)
169{
170 u32 tmp;
171 int i, r;
172
173 /* Disable all tables */
174 for (i = 0; i < 7; i++)
175 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
176
177 /* Setup L2 cache */
178 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
179 EFFECTIVE_L2_QUEUE_SIZE(7));
180 WREG32(VM_L2_CNTL2, 0);
181 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
182 /* Setup TLB control */
183 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
184 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
185 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
186 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
187 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
188 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
189 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
190 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
191 if (rdev->gart.table.vram.robj) {
192 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
193 if (likely(r == 0)) {
194 radeon_bo_kunmap(rdev->gart.table.vram.robj);
195 radeon_bo_unpin(rdev->gart.table.vram.robj);
196 radeon_bo_unreserve(rdev->gart.table.vram.robj);
197 }
198 }
199}
200
201void rv770_pcie_gart_fini(struct radeon_device *rdev)
202{
203 radeon_gart_fini(rdev);
204 rv770_pcie_gart_disable(rdev);
205 radeon_gart_table_vram_free(rdev);
206}
207
208
209void rv770_agp_enable(struct radeon_device *rdev)
210{
211 u32 tmp;
212 int i;
213
214 /* Setup L2 cache */
215 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
216 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
217 EFFECTIVE_L2_QUEUE_SIZE(7));
218 WREG32(VM_L2_CNTL2, 0);
219 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
220 /* Setup TLB control */
221 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
222 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
223 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
224 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
225 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
226 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
227 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
228 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
229 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
230 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
231 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
232 for (i = 0; i < 7; i++)
233 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
234}
235
236static void rv770_mc_program(struct radeon_device *rdev)
237{
238 struct rv515_mc_save save;
239 u32 tmp;
240 int i, j;
241
242 /* Initialize HDP */
243 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
244 WREG32((0x2c14 + j), 0x00000000);
245 WREG32((0x2c18 + j), 0x00000000);
246 WREG32((0x2c1c + j), 0x00000000);
247 WREG32((0x2c20 + j), 0x00000000);
248 WREG32((0x2c24 + j), 0x00000000);
249 }
250 /* r7xx hw bug. Read from HDP_DEBUG1 rather
251 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
252 */
253 tmp = RREG32(HDP_DEBUG1);
254
255 rv515_mc_stop(rdev, &save);
256 if (r600_mc_wait_for_idle(rdev)) {
257 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
258 }
259 /* Lockout access through VGA aperture*/
260 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
261 /* Update configuration */
262 if (rdev->flags & RADEON_IS_AGP) {
263 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
264 /* VRAM before AGP */
265 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
266 rdev->mc.vram_start >> 12);
267 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
268 rdev->mc.gtt_end >> 12);
269 } else {
270 /* VRAM after AGP */
271 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
272 rdev->mc.gtt_start >> 12);
273 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
274 rdev->mc.vram_end >> 12);
275 }
276 } else {
277 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
278 rdev->mc.vram_start >> 12);
279 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
280 rdev->mc.vram_end >> 12);
281 }
282 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
283 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
284 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
285 WREG32(MC_VM_FB_LOCATION, tmp);
286 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
287 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
288 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
289 if (rdev->flags & RADEON_IS_AGP) {
290 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
291 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
292 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
293 } else {
294 WREG32(MC_VM_AGP_BASE, 0);
295 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
296 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
297 }
298 if (r600_mc_wait_for_idle(rdev)) {
299 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
300 }
301 rv515_mc_resume(rdev, &save);
302 /* we need to own VRAM, so turn off the VGA renderer here
303 * to stop it overwriting our objects */
304 rv515_vga_render_disable(rdev);
305}
306
307
308/*
309 * CP.
310 */
311void r700_cp_stop(struct radeon_device *rdev)
312{
313 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
314 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
315 WREG32(SCRATCH_UMSK, 0);
316}
317
318static int rv770_cp_load_microcode(struct radeon_device *rdev)
319{
320 const __be32 *fw_data;
321 int i;
322
323 if (!rdev->me_fw || !rdev->pfp_fw)
324 return -EINVAL;
325
326 r700_cp_stop(rdev);
327 WREG32(CP_RB_CNTL,
328#ifdef __BIG_ENDIAN
329 BUF_SWAP_32BIT |
330#endif
331 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
332
333 /* Reset cp */
334 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
335 RREG32(GRBM_SOFT_RESET);
336 mdelay(15);
337 WREG32(GRBM_SOFT_RESET, 0);
338
339 fw_data = (const __be32 *)rdev->pfp_fw->data;
340 WREG32(CP_PFP_UCODE_ADDR, 0);
341 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
342 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
343 WREG32(CP_PFP_UCODE_ADDR, 0);
344
345 fw_data = (const __be32 *)rdev->me_fw->data;
346 WREG32(CP_ME_RAM_WADDR, 0);
347 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
348 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
349
350 WREG32(CP_PFP_UCODE_ADDR, 0);
351 WREG32(CP_ME_RAM_WADDR, 0);
352 WREG32(CP_ME_RAM_RADDR, 0);
353 return 0;
354}
355
356void r700_cp_fini(struct radeon_device *rdev)
357{
358 r700_cp_stop(rdev);
359 radeon_ring_fini(rdev);
360}
361
362/*
363 * Core functions
364 */
365static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
366 u32 num_tile_pipes,
367 u32 num_backends,
368 u32 backend_disable_mask)
369{
370 u32 backend_map = 0;
371 u32 enabled_backends_mask;
372 u32 enabled_backends_count;
373 u32 cur_pipe;
374 u32 swizzle_pipe[R7XX_MAX_PIPES];
375 u32 cur_backend;
376 u32 i;
377 bool force_no_swizzle;
378
379 if (num_tile_pipes > R7XX_MAX_PIPES)
380 num_tile_pipes = R7XX_MAX_PIPES;
381 if (num_tile_pipes < 1)
382 num_tile_pipes = 1;
383 if (num_backends > R7XX_MAX_BACKENDS)
384 num_backends = R7XX_MAX_BACKENDS;
385 if (num_backends < 1)
386 num_backends = 1;
387
388 enabled_backends_mask = 0;
389 enabled_backends_count = 0;
390 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
391 if (((backend_disable_mask >> i) & 1) == 0) {
392 enabled_backends_mask |= (1 << i);
393 ++enabled_backends_count;
394 }
395 if (enabled_backends_count == num_backends)
396 break;
397 }
398
399 if (enabled_backends_count == 0) {
400 enabled_backends_mask = 1;
401 enabled_backends_count = 1;
402 }
403
404 if (enabled_backends_count != num_backends)
405 num_backends = enabled_backends_count;
406
407 switch (rdev->family) {
408 case CHIP_RV770:
409 case CHIP_RV730:
410 force_no_swizzle = false;
411 break;
412 case CHIP_RV710:
413 case CHIP_RV740:
414 default:
415 force_no_swizzle = true;
416 break;
417 }
418
419 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
420 switch (num_tile_pipes) {
421 case 1:
422 swizzle_pipe[0] = 0;
423 break;
424 case 2:
425 swizzle_pipe[0] = 0;
426 swizzle_pipe[1] = 1;
427 break;
428 case 3:
429 if (force_no_swizzle) {
430 swizzle_pipe[0] = 0;
431 swizzle_pipe[1] = 1;
432 swizzle_pipe[2] = 2;
433 } else {
434 swizzle_pipe[0] = 0;
435 swizzle_pipe[1] = 2;
436 swizzle_pipe[2] = 1;
437 }
438 break;
439 case 4:
440 if (force_no_swizzle) {
441 swizzle_pipe[0] = 0;
442 swizzle_pipe[1] = 1;
443 swizzle_pipe[2] = 2;
444 swizzle_pipe[3] = 3;
445 } else {
446 swizzle_pipe[0] = 0;
447 swizzle_pipe[1] = 2;
448 swizzle_pipe[2] = 3;
449 swizzle_pipe[3] = 1;
450 }
451 break;
452 case 5:
453 if (force_no_swizzle) {
454 swizzle_pipe[0] = 0;
455 swizzle_pipe[1] = 1;
456 swizzle_pipe[2] = 2;
457 swizzle_pipe[3] = 3;
458 swizzle_pipe[4] = 4;
459 } else {
460 swizzle_pipe[0] = 0;
461 swizzle_pipe[1] = 2;
462 swizzle_pipe[2] = 4;
463 swizzle_pipe[3] = 1;
464 swizzle_pipe[4] = 3;
465 }
466 break;
467 case 6:
468 if (force_no_swizzle) {
469 swizzle_pipe[0] = 0;
470 swizzle_pipe[1] = 1;
471 swizzle_pipe[2] = 2;
472 swizzle_pipe[3] = 3;
473 swizzle_pipe[4] = 4;
474 swizzle_pipe[5] = 5;
475 } else {
476 swizzle_pipe[0] = 0;
477 swizzle_pipe[1] = 2;
478 swizzle_pipe[2] = 4;
479 swizzle_pipe[3] = 5;
480 swizzle_pipe[4] = 3;
481 swizzle_pipe[5] = 1;
482 }
483 break;
484 case 7:
485 if (force_no_swizzle) {
486 swizzle_pipe[0] = 0;
487 swizzle_pipe[1] = 1;
488 swizzle_pipe[2] = 2;
489 swizzle_pipe[3] = 3;
490 swizzle_pipe[4] = 4;
491 swizzle_pipe[5] = 5;
492 swizzle_pipe[6] = 6;
493 } else {
494 swizzle_pipe[0] = 0;
495 swizzle_pipe[1] = 2;
496 swizzle_pipe[2] = 4;
497 swizzle_pipe[3] = 6;
498 swizzle_pipe[4] = 3;
499 swizzle_pipe[5] = 1;
500 swizzle_pipe[6] = 5;
501 }
502 break;
503 case 8:
504 if (force_no_swizzle) {
505 swizzle_pipe[0] = 0;
506 swizzle_pipe[1] = 1;
507 swizzle_pipe[2] = 2;
508 swizzle_pipe[3] = 3;
509 swizzle_pipe[4] = 4;
510 swizzle_pipe[5] = 5;
511 swizzle_pipe[6] = 6;
512 swizzle_pipe[7] = 7;
513 } else {
514 swizzle_pipe[0] = 0;
515 swizzle_pipe[1] = 2;
516 swizzle_pipe[2] = 4;
517 swizzle_pipe[3] = 6;
518 swizzle_pipe[4] = 3;
519 swizzle_pipe[5] = 1;
520 swizzle_pipe[6] = 7;
521 swizzle_pipe[7] = 5;
522 }
523 break;
524 }
525
526 cur_backend = 0;
527 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
528 while (((1 << cur_backend) & enabled_backends_mask) == 0)
529 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
530
531 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
532
533 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
534 }
535
536 return backend_map;
537}
538
539static void rv770_gpu_init(struct radeon_device *rdev)
540{
541 int i, j, num_qd_pipes;
542 u32 ta_aux_cntl;
543 u32 sx_debug_1;
544 u32 smx_dc_ctl0;
545 u32 db_debug3;
546 u32 num_gs_verts_per_thread;
547 u32 vgt_gs_per_es;
548 u32 gs_prim_buffer_depth = 0;
549 u32 sq_ms_fifo_sizes;
550 u32 sq_config;
551 u32 sq_thread_resource_mgmt;
552 u32 hdp_host_path_cntl;
553 u32 sq_dyn_gpr_size_simd_ab_0;
554 u32 backend_map;
555 u32 gb_tiling_config = 0;
556 u32 cc_rb_backend_disable = 0;
557 u32 cc_gc_shader_pipe_config = 0;
558 u32 mc_arb_ramcfg;
559 u32 db_debug4;
560
561 /* setup chip specs */
562 switch (rdev->family) {
563 case CHIP_RV770:
564 rdev->config.rv770.max_pipes = 4;
565 rdev->config.rv770.max_tile_pipes = 8;
566 rdev->config.rv770.max_simds = 10;
567 rdev->config.rv770.max_backends = 4;
568 rdev->config.rv770.max_gprs = 256;
569 rdev->config.rv770.max_threads = 248;
570 rdev->config.rv770.max_stack_entries = 512;
571 rdev->config.rv770.max_hw_contexts = 8;
572 rdev->config.rv770.max_gs_threads = 16 * 2;
573 rdev->config.rv770.sx_max_export_size = 128;
574 rdev->config.rv770.sx_max_export_pos_size = 16;
575 rdev->config.rv770.sx_max_export_smx_size = 112;
576 rdev->config.rv770.sq_num_cf_insts = 2;
577
578 rdev->config.rv770.sx_num_of_sets = 7;
579 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
580 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
581 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
582 break;
583 case CHIP_RV730:
584 rdev->config.rv770.max_pipes = 2;
585 rdev->config.rv770.max_tile_pipes = 4;
586 rdev->config.rv770.max_simds = 8;
587 rdev->config.rv770.max_backends = 2;
588 rdev->config.rv770.max_gprs = 128;
589 rdev->config.rv770.max_threads = 248;
590 rdev->config.rv770.max_stack_entries = 256;
591 rdev->config.rv770.max_hw_contexts = 8;
592 rdev->config.rv770.max_gs_threads = 16 * 2;
593 rdev->config.rv770.sx_max_export_size = 256;
594 rdev->config.rv770.sx_max_export_pos_size = 32;
595 rdev->config.rv770.sx_max_export_smx_size = 224;
596 rdev->config.rv770.sq_num_cf_insts = 2;
597
598 rdev->config.rv770.sx_num_of_sets = 7;
599 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
600 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
601 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
602 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
603 rdev->config.rv770.sx_max_export_pos_size -= 16;
604 rdev->config.rv770.sx_max_export_smx_size += 16;
605 }
606 break;
607 case CHIP_RV710:
608 rdev->config.rv770.max_pipes = 2;
609 rdev->config.rv770.max_tile_pipes = 2;
610 rdev->config.rv770.max_simds = 2;
611 rdev->config.rv770.max_backends = 1;
612 rdev->config.rv770.max_gprs = 256;
613 rdev->config.rv770.max_threads = 192;
614 rdev->config.rv770.max_stack_entries = 256;
615 rdev->config.rv770.max_hw_contexts = 4;
616 rdev->config.rv770.max_gs_threads = 8 * 2;
617 rdev->config.rv770.sx_max_export_size = 128;
618 rdev->config.rv770.sx_max_export_pos_size = 16;
619 rdev->config.rv770.sx_max_export_smx_size = 112;
620 rdev->config.rv770.sq_num_cf_insts = 1;
621
622 rdev->config.rv770.sx_num_of_sets = 7;
623 rdev->config.rv770.sc_prim_fifo_size = 0x40;
624 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
625 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
626 break;
627 case CHIP_RV740:
628 rdev->config.rv770.max_pipes = 4;
629 rdev->config.rv770.max_tile_pipes = 4;
630 rdev->config.rv770.max_simds = 8;
631 rdev->config.rv770.max_backends = 4;
632 rdev->config.rv770.max_gprs = 256;
633 rdev->config.rv770.max_threads = 248;
634 rdev->config.rv770.max_stack_entries = 512;
635 rdev->config.rv770.max_hw_contexts = 8;
636 rdev->config.rv770.max_gs_threads = 16 * 2;
637 rdev->config.rv770.sx_max_export_size = 256;
638 rdev->config.rv770.sx_max_export_pos_size = 32;
639 rdev->config.rv770.sx_max_export_smx_size = 224;
640 rdev->config.rv770.sq_num_cf_insts = 2;
641
642 rdev->config.rv770.sx_num_of_sets = 7;
643 rdev->config.rv770.sc_prim_fifo_size = 0x100;
644 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
645 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
646
647 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
648 rdev->config.rv770.sx_max_export_pos_size -= 16;
649 rdev->config.rv770.sx_max_export_smx_size += 16;
650 }
651 break;
652 default:
653 break;
654 }
655
656 /* Initialize HDP */
657 j = 0;
658 for (i = 0; i < 32; i++) {
659 WREG32((0x2c14 + j), 0x00000000);
660 WREG32((0x2c18 + j), 0x00000000);
661 WREG32((0x2c1c + j), 0x00000000);
662 WREG32((0x2c20 + j), 0x00000000);
663 WREG32((0x2c24 + j), 0x00000000);
664 j += 0x18;
665 }
666
667 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
668
669 /* setup tiling, simd, pipe config */
670 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
671
672 switch (rdev->config.rv770.max_tile_pipes) {
673 case 1:
674 default:
675 gb_tiling_config |= PIPE_TILING(0);
676 break;
677 case 2:
678 gb_tiling_config |= PIPE_TILING(1);
679 break;
680 case 4:
681 gb_tiling_config |= PIPE_TILING(2);
682 break;
683 case 8:
684 gb_tiling_config |= PIPE_TILING(3);
685 break;
686 }
687 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
688
689 if (rdev->family == CHIP_RV770)
690 gb_tiling_config |= BANK_TILING(1);
691 else
692 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
693 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
694 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
695 if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
696 rdev->config.rv770.tiling_group_size = 512;
697 else
698 rdev->config.rv770.tiling_group_size = 256;
699 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
700 gb_tiling_config |= ROW_TILING(3);
701 gb_tiling_config |= SAMPLE_SPLIT(3);
702 } else {
703 gb_tiling_config |=
704 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
705 gb_tiling_config |=
706 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
707 }
708
709 gb_tiling_config |= BANK_SWAPS(1);
710
711 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
712 cc_rb_backend_disable |=
713 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
714
715 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
716 cc_gc_shader_pipe_config |=
717 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
718 cc_gc_shader_pipe_config |=
719 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
720
721 if (rdev->family == CHIP_RV740)
722 backend_map = 0x28;
723 else
724 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
725 rdev->config.rv770.max_tile_pipes,
726 (R7XX_MAX_BACKENDS -
727 r600_count_pipe_bits((cc_rb_backend_disable &
728 R7XX_MAX_BACKENDS_MASK) >> 16)),
729 (cc_rb_backend_disable >> 16));
730
731 rdev->config.rv770.tile_config = gb_tiling_config;
732 rdev->config.rv770.backend_map = backend_map;
733 gb_tiling_config |= BACKEND_MAP(backend_map);
734
735 WREG32(GB_TILING_CONFIG, gb_tiling_config);
736 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
737 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
738
739 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
740 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
741 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
742 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
743
744 WREG32(CGTS_SYS_TCC_DISABLE, 0);
745 WREG32(CGTS_TCC_DISABLE, 0);
746 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
747 WREG32(CGTS_USER_TCC_DISABLE, 0);
748
749 num_qd_pipes =
750 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
751 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
752 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
753
754 /* set HW defaults for 3D engine */
755 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
756 ROQ_IB2_START(0x2b)));
757
758 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
759
760 ta_aux_cntl = RREG32(TA_CNTL_AUX);
761 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
762
763 sx_debug_1 = RREG32(SX_DEBUG_1);
764 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
765 WREG32(SX_DEBUG_1, sx_debug_1);
766
767 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
768 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
769 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
770 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
771
772 if (rdev->family != CHIP_RV740)
773 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
774 GS_FLUSH_CTL(4) |
775 ACK_FLUSH_CTL(3) |
776 SYNC_FLUSH_CTL));
777
778 db_debug3 = RREG32(DB_DEBUG3);
779 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
780 switch (rdev->family) {
781 case CHIP_RV770:
782 case CHIP_RV740:
783 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
784 break;
785 case CHIP_RV710:
786 case CHIP_RV730:
787 default:
788 db_debug3 |= DB_CLK_OFF_DELAY(2);
789 break;
790 }
791 WREG32(DB_DEBUG3, db_debug3);
792
793 if (rdev->family != CHIP_RV770) {
794 db_debug4 = RREG32(DB_DEBUG4);
795 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
796 WREG32(DB_DEBUG4, db_debug4);
797 }
798
799 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
800 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
801 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
802
803 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
804 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
805 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
806
807 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
808
809 WREG32(VGT_NUM_INSTANCES, 1);
810
811 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
812
813 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
814
815 WREG32(CP_PERFMON_CNTL, 0);
816
817 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
818 DONE_FIFO_HIWATER(0xe0) |
819 ALU_UPDATE_FIFO_HIWATER(0x8));
820 switch (rdev->family) {
821 case CHIP_RV770:
822 case CHIP_RV730:
823 case CHIP_RV710:
824 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
825 break;
826 case CHIP_RV740:
827 default:
828 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
829 break;
830 }
831 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
832
833 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
834 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
835 */
836 sq_config = RREG32(SQ_CONFIG);
837 sq_config &= ~(PS_PRIO(3) |
838 VS_PRIO(3) |
839 GS_PRIO(3) |
840 ES_PRIO(3));
841 sq_config |= (DX9_CONSTS |
842 VC_ENABLE |
843 EXPORT_SRC_C |
844 PS_PRIO(0) |
845 VS_PRIO(1) |
846 GS_PRIO(2) |
847 ES_PRIO(3));
848 if (rdev->family == CHIP_RV710)
849 /* no vertex cache */
850 sq_config &= ~VC_ENABLE;
851
852 WREG32(SQ_CONFIG, sq_config);
853
854 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
855 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
856 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
857
858 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
859 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
860
861 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
862 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
863 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
864 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
865 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
866 else
867 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
868 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
869
870 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
871 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
872
873 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
874 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
875
876 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
877 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
878 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
879 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
880
881 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
882 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
883 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
884 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
885 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
886 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
887 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
888 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
889
890 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
891 FORCE_EOV_MAX_REZ_CNT(255)));
892
893 if (rdev->family == CHIP_RV710)
894 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
895 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
896 else
897 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
898 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
899
900 switch (rdev->family) {
901 case CHIP_RV770:
902 case CHIP_RV730:
903 case CHIP_RV740:
904 gs_prim_buffer_depth = 384;
905 break;
906 case CHIP_RV710:
907 gs_prim_buffer_depth = 128;
908 break;
909 default:
910 break;
911 }
912
913 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
914 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
915 /* Max value for this is 256 */
916 if (vgt_gs_per_es > 256)
917 vgt_gs_per_es = 256;
918
919 WREG32(VGT_ES_PER_GS, 128);
920 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
921 WREG32(VGT_GS_PER_VS, 2);
922
923 /* more default values. 2D/3D driver should adjust as needed */
924 WREG32(VGT_GS_VERTEX_REUSE, 16);
925 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
926 WREG32(VGT_STRMOUT_EN, 0);
927 WREG32(SX_MISC, 0);
928 WREG32(PA_SC_MODE_CNTL, 0);
929 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
930 WREG32(PA_SC_AA_CONFIG, 0);
931 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
932 WREG32(PA_SC_LINE_STIPPLE, 0);
933 WREG32(SPI_INPUT_Z, 0);
934 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
935 WREG32(CB_COLOR7_FRAG, 0);
936
937 /* clear render buffer base addresses */
938 WREG32(CB_COLOR0_BASE, 0);
939 WREG32(CB_COLOR1_BASE, 0);
940 WREG32(CB_COLOR2_BASE, 0);
941 WREG32(CB_COLOR3_BASE, 0);
942 WREG32(CB_COLOR4_BASE, 0);
943 WREG32(CB_COLOR5_BASE, 0);
944 WREG32(CB_COLOR6_BASE, 0);
945 WREG32(CB_COLOR7_BASE, 0);
946
947 WREG32(TCP_CNTL, 0);
948
949 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
950 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
951
952 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
953
954 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
955 NUM_CLIP_SEQ(3)));
956
957}
958
959static int rv770_vram_scratch_init(struct radeon_device *rdev)
960{
961 int r;
962 u64 gpu_addr;
963
964 if (rdev->vram_scratch.robj == NULL) {
965 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
966 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
967 &rdev->vram_scratch.robj);
968 if (r) {
969 return r;
970 }
971 }
972
973 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
974 if (unlikely(r != 0))
975 return r;
976 r = radeon_bo_pin(rdev->vram_scratch.robj,
977 RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
978 if (r) {
979 radeon_bo_unreserve(rdev->vram_scratch.robj);
980 return r;
981 }
982 r = radeon_bo_kmap(rdev->vram_scratch.robj,
983 (void **)&rdev->vram_scratch.ptr);
984 if (r)
985 radeon_bo_unpin(rdev->vram_scratch.robj);
986 radeon_bo_unreserve(rdev->vram_scratch.robj);
987
988 return r;
989}
990
991static void rv770_vram_scratch_fini(struct radeon_device *rdev)
992{
993 int r;
994
995 if (rdev->vram_scratch.robj == NULL) {
996 return;
997 }
998 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
999 if (likely(r == 0)) {
1000 radeon_bo_kunmap(rdev->vram_scratch.robj);
1001 radeon_bo_unpin(rdev->vram_scratch.robj);
1002 radeon_bo_unreserve(rdev->vram_scratch.robj);
1003 }
1004 radeon_bo_unref(&rdev->vram_scratch.robj);
1005}
1006
1007void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1008{
1009 u64 size_bf, size_af;
1010
1011 if (mc->mc_vram_size > 0xE0000000) {
1012 /* leave room for at least 512M GTT */
1013 dev_warn(rdev->dev, "limiting VRAM\n");
1014 mc->real_vram_size = 0xE0000000;
1015 mc->mc_vram_size = 0xE0000000;
1016 }
1017 if (rdev->flags & RADEON_IS_AGP) {
1018 size_bf = mc->gtt_start;
1019 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1020 if (size_bf > size_af) {
1021 if (mc->mc_vram_size > size_bf) {
1022 dev_warn(rdev->dev, "limiting VRAM\n");
1023 mc->real_vram_size = size_bf;
1024 mc->mc_vram_size = size_bf;
1025 }
1026 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1027 } else {
1028 if (mc->mc_vram_size > size_af) {
1029 dev_warn(rdev->dev, "limiting VRAM\n");
1030 mc->real_vram_size = size_af;
1031 mc->mc_vram_size = size_af;
1032 }
1033 mc->vram_start = mc->gtt_end;
1034 }
1035 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1036 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1037 mc->mc_vram_size >> 20, mc->vram_start,
1038 mc->vram_end, mc->real_vram_size >> 20);
1039 } else {
1040 radeon_vram_location(rdev, &rdev->mc, 0);
1041 rdev->mc.gtt_base_align = 0;
1042 radeon_gtt_location(rdev, mc);
1043 }
1044}
1045
1046int rv770_mc_init(struct radeon_device *rdev)
1047{
1048 u32 tmp;
1049 int chansize, numchan;
1050
1051 /* Get VRAM informations */
1052 rdev->mc.vram_is_ddr = true;
1053 tmp = RREG32(MC_ARB_RAMCFG);
1054 if (tmp & CHANSIZE_OVERRIDE) {
1055 chansize = 16;
1056 } else if (tmp & CHANSIZE_MASK) {
1057 chansize = 64;
1058 } else {
1059 chansize = 32;
1060 }
1061 tmp = RREG32(MC_SHARED_CHMAP);
1062 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1063 case 0:
1064 default:
1065 numchan = 1;
1066 break;
1067 case 1:
1068 numchan = 2;
1069 break;
1070 case 2:
1071 numchan = 4;
1072 break;
1073 case 3:
1074 numchan = 8;
1075 break;
1076 }
1077 rdev->mc.vram_width = numchan * chansize;
1078 /* Could aper size report 0 ? */
1079 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1080 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1081 /* Setup GPU memory space */
1082 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1083 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1084 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1085 r700_vram_gtt_location(rdev, &rdev->mc);
1086 radeon_update_bandwidth_info(rdev);
1087
1088 return 0;
1089}
1090
1091static int rv770_startup(struct radeon_device *rdev)
1092{
1093 int r;
1094
1095 /* enable pcie gen2 link */
1096 rv770_pcie_gen2_enable(rdev);
1097
1098 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1099 r = r600_init_microcode(rdev);
1100 if (r) {
1101 DRM_ERROR("Failed to load firmware!\n");
1102 return r;
1103 }
1104 }
1105
1106 rv770_mc_program(rdev);
1107 if (rdev->flags & RADEON_IS_AGP) {
1108 rv770_agp_enable(rdev);
1109 } else {
1110 r = rv770_pcie_gart_enable(rdev);
1111 if (r)
1112 return r;
1113 }
1114 r = rv770_vram_scratch_init(rdev);
1115 if (r)
1116 return r;
1117 rv770_gpu_init(rdev);
1118 r = r600_blit_init(rdev);
1119 if (r) {
1120 r600_blit_fini(rdev);
1121 rdev->asic->copy = NULL;
1122 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1123 }
1124
1125 /* allocate wb buffer */
1126 r = radeon_wb_init(rdev);
1127 if (r)
1128 return r;
1129
1130 /* Enable IRQ */
1131 r = r600_irq_init(rdev);
1132 if (r) {
1133 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1134 radeon_irq_kms_fini(rdev);
1135 return r;
1136 }
1137 r600_irq_set(rdev);
1138
1139 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1140 if (r)
1141 return r;
1142 r = rv770_cp_load_microcode(rdev);
1143 if (r)
1144 return r;
1145 r = r600_cp_resume(rdev);
1146 if (r)
1147 return r;
1148
1149 return 0;
1150}
1151
1152int rv770_resume(struct radeon_device *rdev)
1153{
1154 int r;
1155
1156 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1157 * posting will perform necessary task to bring back GPU into good
1158 * shape.
1159 */
1160 /* post card */
1161 atom_asic_init(rdev->mode_info.atom_context);
1162
1163 r = rv770_startup(rdev);
1164 if (r) {
1165 DRM_ERROR("r600 startup failed on resume\n");
1166 return r;
1167 }
1168
1169 r = r600_ib_test(rdev);
1170 if (r) {
1171 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1172 return r;
1173 }
1174
1175 r = r600_audio_init(rdev);
1176 if (r) {
1177 dev_err(rdev->dev, "radeon: audio init failed\n");
1178 return r;
1179 }
1180
1181 return r;
1182
1183}
1184
1185int rv770_suspend(struct radeon_device *rdev)
1186{
1187 int r;
1188
1189 r600_audio_fini(rdev);
1190 /* FIXME: we should wait for ring to be empty */
1191 r700_cp_stop(rdev);
1192 rdev->cp.ready = false;
1193 r600_irq_suspend(rdev);
1194 radeon_wb_disable(rdev);
1195 rv770_pcie_gart_disable(rdev);
1196 /* unpin shaders bo */
1197 if (rdev->r600_blit.shader_obj) {
1198 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1199 if (likely(r == 0)) {
1200 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1201 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1202 }
1203 }
1204 return 0;
1205}
1206
1207/* Plan is to move initialization in that function and use
1208 * helper function so that radeon_device_init pretty much
1209 * do nothing more than calling asic specific function. This
1210 * should also allow to remove a bunch of callback function
1211 * like vram_info.
1212 */
1213int rv770_init(struct radeon_device *rdev)
1214{
1215 int r;
1216
1217 /* This don't do much */
1218 r = radeon_gem_init(rdev);
1219 if (r)
1220 return r;
1221 /* Read BIOS */
1222 if (!radeon_get_bios(rdev)) {
1223 if (ASIC_IS_AVIVO(rdev))
1224 return -EINVAL;
1225 }
1226 /* Must be an ATOMBIOS */
1227 if (!rdev->is_atom_bios) {
1228 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1229 return -EINVAL;
1230 }
1231 r = radeon_atombios_init(rdev);
1232 if (r)
1233 return r;
1234 /* Post card if necessary */
1235 if (!radeon_card_posted(rdev)) {
1236 if (!rdev->bios) {
1237 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1238 return -EINVAL;
1239 }
1240 DRM_INFO("GPU not posted. posting now...\n");
1241 atom_asic_init(rdev->mode_info.atom_context);
1242 }
1243 /* Initialize scratch registers */
1244 r600_scratch_init(rdev);
1245 /* Initialize surface registers */
1246 radeon_surface_init(rdev);
1247 /* Initialize clocks */
1248 radeon_get_clock_info(rdev->ddev);
1249 /* Fence driver */
1250 r = radeon_fence_driver_init(rdev);
1251 if (r)
1252 return r;
1253 /* initialize AGP */
1254 if (rdev->flags & RADEON_IS_AGP) {
1255 r = radeon_agp_init(rdev);
1256 if (r)
1257 radeon_agp_disable(rdev);
1258 }
1259 r = rv770_mc_init(rdev);
1260 if (r)
1261 return r;
1262 /* Memory manager */
1263 r = radeon_bo_init(rdev);
1264 if (r)
1265 return r;
1266
1267 r = radeon_irq_kms_init(rdev);
1268 if (r)
1269 return r;
1270
1271 rdev->cp.ring_obj = NULL;
1272 r600_ring_init(rdev, 1024 * 1024);
1273
1274 rdev->ih.ring_obj = NULL;
1275 r600_ih_ring_init(rdev, 64 * 1024);
1276
1277 r = r600_pcie_gart_init(rdev);
1278 if (r)
1279 return r;
1280
1281 rdev->accel_working = true;
1282 r = rv770_startup(rdev);
1283 if (r) {
1284 dev_err(rdev->dev, "disabling GPU acceleration\n");
1285 r700_cp_fini(rdev);
1286 r600_irq_fini(rdev);
1287 radeon_wb_fini(rdev);
1288 radeon_irq_kms_fini(rdev);
1289 rv770_pcie_gart_fini(rdev);
1290 rdev->accel_working = false;
1291 }
1292 if (rdev->accel_working) {
1293 r = radeon_ib_pool_init(rdev);
1294 if (r) {
1295 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1296 rdev->accel_working = false;
1297 } else {
1298 r = r600_ib_test(rdev);
1299 if (r) {
1300 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1301 rdev->accel_working = false;
1302 }
1303 }
1304 }
1305
1306 r = r600_audio_init(rdev);
1307 if (r) {
1308 dev_err(rdev->dev, "radeon: audio init failed\n");
1309 return r;
1310 }
1311
1312 return 0;
1313}
1314
1315void rv770_fini(struct radeon_device *rdev)
1316{
1317 r600_blit_fini(rdev);
1318 r700_cp_fini(rdev);
1319 r600_irq_fini(rdev);
1320 radeon_wb_fini(rdev);
1321 radeon_ib_pool_fini(rdev);
1322 radeon_irq_kms_fini(rdev);
1323 rv770_pcie_gart_fini(rdev);
1324 rv770_vram_scratch_fini(rdev);
1325 radeon_gem_fini(rdev);
1326 radeon_fence_driver_fini(rdev);
1327 radeon_agp_fini(rdev);
1328 radeon_bo_fini(rdev);
1329 radeon_atombios_fini(rdev);
1330 kfree(rdev->bios);
1331 rdev->bios = NULL;
1332}
1333
1334static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1335{
1336 u32 link_width_cntl, lanes, speed_cntl, tmp;
1337 u16 link_cntl2;
1338
1339 if (radeon_pcie_gen2 == 0)
1340 return;
1341
1342 if (rdev->flags & RADEON_IS_IGP)
1343 return;
1344
1345 if (!(rdev->flags & RADEON_IS_PCIE))
1346 return;
1347
1348 /* x2 cards have a special sequence */
1349 if (ASIC_IS_X2(rdev))
1350 return;
1351
1352 /* advertise upconfig capability */
1353 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1354 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1355 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1356 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1357 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
1358 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1359 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
1360 LC_RECONFIG_ARC_MISSING_ESCAPE);
1361 link_width_cntl |= lanes | LC_RECONFIG_NOW |
1362 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
1363 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1364 } else {
1365 link_width_cntl |= LC_UPCONFIGURE_DIS;
1366 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1367 }
1368
1369 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1370 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1371 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1372
1373 tmp = RREG32(0x541c);
1374 WREG32(0x541c, tmp | 0x8);
1375 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
1376 link_cntl2 = RREG16(0x4088);
1377 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
1378 link_cntl2 |= 0x2;
1379 WREG16(0x4088, link_cntl2);
1380 WREG32(MM_CFGREGS_CNTL, 0);
1381
1382 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1383 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
1384 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1385
1386 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1387 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1388 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1389
1390 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1391 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1392 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1393
1394 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1395 speed_cntl |= LC_GEN2_EN_STRAP;
1396 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1397
1398 } else {
1399 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1400 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
1401 if (1)
1402 link_width_cntl |= LC_UPCONFIGURE_DIS;
1403 else
1404 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1405 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1406 }
1407}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/firmware.h>
29#include <linux/slab.h>
30#include <drm/drmP.h>
31#include "radeon.h"
32#include "radeon_asic.h"
33#include "radeon_audio.h"
34#include <drm/radeon_drm.h>
35#include "rv770d.h"
36#include "atom.h"
37#include "avivod.h"
38
39#define R700_PFP_UCODE_SIZE 848
40#define R700_PM4_UCODE_SIZE 1360
41
42static void rv770_gpu_init(struct radeon_device *rdev);
43void rv770_fini(struct radeon_device *rdev);
44static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
45int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
46
47int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
48{
49 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
50 int r;
51
52 /* RV740 uses evergreen uvd clk programming */
53 if (rdev->family == CHIP_RV740)
54 return evergreen_set_uvd_clocks(rdev, vclk, dclk);
55
56 /* bypass vclk and dclk with bclk */
57 WREG32_P(CG_UPLL_FUNC_CNTL_2,
58 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
59 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
60
61 if (!vclk || !dclk) {
62 /* keep the Bypass mode, put PLL to sleep */
63 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
64 return 0;
65 }
66
67 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
68 43663, 0x03FFFFFE, 1, 30, ~0,
69 &fb_div, &vclk_div, &dclk_div);
70 if (r)
71 return r;
72
73 fb_div |= 1;
74 vclk_div -= 1;
75 dclk_div -= 1;
76
77 /* set UPLL_FB_DIV to 0x50000 */
78 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);
79
80 /* deassert UPLL_RESET and UPLL_SLEEP */
81 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK));
82
83 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */
84 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
85 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1));
86
87 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
88 if (r)
89 return r;
90
91 /* assert PLL_RESET */
92 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
93
94 /* set the required FB_DIV, REF_DIV, Post divder values */
95 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);
96 WREG32_P(CG_UPLL_FUNC_CNTL_2,
97 UPLL_SW_HILEN(vclk_div >> 1) |
98 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
99 UPLL_SW_HILEN2(dclk_div >> 1) |
100 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)),
101 ~UPLL_SW_MASK);
102
103 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div),
104 ~UPLL_FB_DIV_MASK);
105
106 /* give the PLL some time to settle */
107 mdelay(15);
108
109 /* deassert PLL_RESET */
110 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
111
112 mdelay(15);
113
114 /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */
115 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
116 WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1));
117
118 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
119 if (r)
120 return r;
121
122 /* switch VCLK and DCLK selection */
123 WREG32_P(CG_UPLL_FUNC_CNTL_2,
124 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
125 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
126
127 mdelay(100);
128
129 return 0;
130}
131
132static const u32 r7xx_golden_registers[] =
133{
134 0x8d00, 0xffffffff, 0x0e0e0074,
135 0x8d04, 0xffffffff, 0x013a2b34,
136 0x9508, 0xffffffff, 0x00000002,
137 0x8b20, 0xffffffff, 0,
138 0x88c4, 0xffffffff, 0x000000c2,
139 0x28350, 0xffffffff, 0,
140 0x9058, 0xffffffff, 0x0fffc40f,
141 0x240c, 0xffffffff, 0x00000380,
142 0x733c, 0xffffffff, 0x00000002,
143 0x2650, 0x00040000, 0,
144 0x20bc, 0x00040000, 0,
145 0x7300, 0xffffffff, 0x001000f0
146};
147
148static const u32 r7xx_golden_dyn_gpr_registers[] =
149{
150 0x8db0, 0xffffffff, 0x98989898,
151 0x8db4, 0xffffffff, 0x98989898,
152 0x8db8, 0xffffffff, 0x98989898,
153 0x8dbc, 0xffffffff, 0x98989898,
154 0x8dc0, 0xffffffff, 0x98989898,
155 0x8dc4, 0xffffffff, 0x98989898,
156 0x8dc8, 0xffffffff, 0x98989898,
157 0x8dcc, 0xffffffff, 0x98989898,
158 0x88c4, 0xffffffff, 0x00000082
159};
160
161static const u32 rv770_golden_registers[] =
162{
163 0x562c, 0xffffffff, 0,
164 0x3f90, 0xffffffff, 0,
165 0x9148, 0xffffffff, 0,
166 0x3f94, 0xffffffff, 0,
167 0x914c, 0xffffffff, 0,
168 0x9698, 0x18000000, 0x18000000
169};
170
171static const u32 rv770ce_golden_registers[] =
172{
173 0x562c, 0xffffffff, 0,
174 0x3f90, 0xffffffff, 0x00cc0000,
175 0x9148, 0xffffffff, 0x00cc0000,
176 0x3f94, 0xffffffff, 0x00cc0000,
177 0x914c, 0xffffffff, 0x00cc0000,
178 0x9b7c, 0xffffffff, 0x00fa0000,
179 0x3f8c, 0xffffffff, 0x00fa0000,
180 0x9698, 0x18000000, 0x18000000
181};
182
183static const u32 rv770_mgcg_init[] =
184{
185 0x8bcc, 0xffffffff, 0x130300f9,
186 0x5448, 0xffffffff, 0x100,
187 0x55e4, 0xffffffff, 0x100,
188 0x160c, 0xffffffff, 0x100,
189 0x5644, 0xffffffff, 0x100,
190 0xc164, 0xffffffff, 0x100,
191 0x8a18, 0xffffffff, 0x100,
192 0x897c, 0xffffffff, 0x8000100,
193 0x8b28, 0xffffffff, 0x3c000100,
194 0x9144, 0xffffffff, 0x100,
195 0x9a1c, 0xffffffff, 0x10000,
196 0x9a50, 0xffffffff, 0x100,
197 0x9a1c, 0xffffffff, 0x10001,
198 0x9a50, 0xffffffff, 0x100,
199 0x9a1c, 0xffffffff, 0x10002,
200 0x9a50, 0xffffffff, 0x100,
201 0x9a1c, 0xffffffff, 0x10003,
202 0x9a50, 0xffffffff, 0x100,
203 0x9a1c, 0xffffffff, 0x0,
204 0x9870, 0xffffffff, 0x100,
205 0x8d58, 0xffffffff, 0x100,
206 0x9500, 0xffffffff, 0x0,
207 0x9510, 0xffffffff, 0x100,
208 0x9500, 0xffffffff, 0x1,
209 0x9510, 0xffffffff, 0x100,
210 0x9500, 0xffffffff, 0x2,
211 0x9510, 0xffffffff, 0x100,
212 0x9500, 0xffffffff, 0x3,
213 0x9510, 0xffffffff, 0x100,
214 0x9500, 0xffffffff, 0x4,
215 0x9510, 0xffffffff, 0x100,
216 0x9500, 0xffffffff, 0x5,
217 0x9510, 0xffffffff, 0x100,
218 0x9500, 0xffffffff, 0x6,
219 0x9510, 0xffffffff, 0x100,
220 0x9500, 0xffffffff, 0x7,
221 0x9510, 0xffffffff, 0x100,
222 0x9500, 0xffffffff, 0x8,
223 0x9510, 0xffffffff, 0x100,
224 0x9500, 0xffffffff, 0x9,
225 0x9510, 0xffffffff, 0x100,
226 0x9500, 0xffffffff, 0x8000,
227 0x9490, 0xffffffff, 0x0,
228 0x949c, 0xffffffff, 0x100,
229 0x9490, 0xffffffff, 0x1,
230 0x949c, 0xffffffff, 0x100,
231 0x9490, 0xffffffff, 0x2,
232 0x949c, 0xffffffff, 0x100,
233 0x9490, 0xffffffff, 0x3,
234 0x949c, 0xffffffff, 0x100,
235 0x9490, 0xffffffff, 0x4,
236 0x949c, 0xffffffff, 0x100,
237 0x9490, 0xffffffff, 0x5,
238 0x949c, 0xffffffff, 0x100,
239 0x9490, 0xffffffff, 0x6,
240 0x949c, 0xffffffff, 0x100,
241 0x9490, 0xffffffff, 0x7,
242 0x949c, 0xffffffff, 0x100,
243 0x9490, 0xffffffff, 0x8,
244 0x949c, 0xffffffff, 0x100,
245 0x9490, 0xffffffff, 0x9,
246 0x949c, 0xffffffff, 0x100,
247 0x9490, 0xffffffff, 0x8000,
248 0x9604, 0xffffffff, 0x0,
249 0x9654, 0xffffffff, 0x100,
250 0x9604, 0xffffffff, 0x1,
251 0x9654, 0xffffffff, 0x100,
252 0x9604, 0xffffffff, 0x2,
253 0x9654, 0xffffffff, 0x100,
254 0x9604, 0xffffffff, 0x3,
255 0x9654, 0xffffffff, 0x100,
256 0x9604, 0xffffffff, 0x4,
257 0x9654, 0xffffffff, 0x100,
258 0x9604, 0xffffffff, 0x5,
259 0x9654, 0xffffffff, 0x100,
260 0x9604, 0xffffffff, 0x6,
261 0x9654, 0xffffffff, 0x100,
262 0x9604, 0xffffffff, 0x7,
263 0x9654, 0xffffffff, 0x100,
264 0x9604, 0xffffffff, 0x8,
265 0x9654, 0xffffffff, 0x100,
266 0x9604, 0xffffffff, 0x9,
267 0x9654, 0xffffffff, 0x100,
268 0x9604, 0xffffffff, 0x80000000,
269 0x9030, 0xffffffff, 0x100,
270 0x9034, 0xffffffff, 0x100,
271 0x9038, 0xffffffff, 0x100,
272 0x903c, 0xffffffff, 0x100,
273 0x9040, 0xffffffff, 0x100,
274 0xa200, 0xffffffff, 0x100,
275 0xa204, 0xffffffff, 0x100,
276 0xa208, 0xffffffff, 0x100,
277 0xa20c, 0xffffffff, 0x100,
278 0x971c, 0xffffffff, 0x100,
279 0x915c, 0xffffffff, 0x00020001,
280 0x9160, 0xffffffff, 0x00040003,
281 0x916c, 0xffffffff, 0x00060005,
282 0x9170, 0xffffffff, 0x00080007,
283 0x9174, 0xffffffff, 0x000a0009,
284 0x9178, 0xffffffff, 0x000c000b,
285 0x917c, 0xffffffff, 0x000e000d,
286 0x9180, 0xffffffff, 0x0010000f,
287 0x918c, 0xffffffff, 0x00120011,
288 0x9190, 0xffffffff, 0x00140013,
289 0x9194, 0xffffffff, 0x00020001,
290 0x9198, 0xffffffff, 0x00040003,
291 0x919c, 0xffffffff, 0x00060005,
292 0x91a8, 0xffffffff, 0x00080007,
293 0x91ac, 0xffffffff, 0x000a0009,
294 0x91b0, 0xffffffff, 0x000c000b,
295 0x91b4, 0xffffffff, 0x000e000d,
296 0x91b8, 0xffffffff, 0x0010000f,
297 0x91c4, 0xffffffff, 0x00120011,
298 0x91c8, 0xffffffff, 0x00140013,
299 0x91cc, 0xffffffff, 0x00020001,
300 0x91d0, 0xffffffff, 0x00040003,
301 0x91d4, 0xffffffff, 0x00060005,
302 0x91e0, 0xffffffff, 0x00080007,
303 0x91e4, 0xffffffff, 0x000a0009,
304 0x91e8, 0xffffffff, 0x000c000b,
305 0x91ec, 0xffffffff, 0x00020001,
306 0x91f0, 0xffffffff, 0x00040003,
307 0x91f4, 0xffffffff, 0x00060005,
308 0x9200, 0xffffffff, 0x00080007,
309 0x9204, 0xffffffff, 0x000a0009,
310 0x9208, 0xffffffff, 0x000c000b,
311 0x920c, 0xffffffff, 0x000e000d,
312 0x9210, 0xffffffff, 0x0010000f,
313 0x921c, 0xffffffff, 0x00120011,
314 0x9220, 0xffffffff, 0x00140013,
315 0x9224, 0xffffffff, 0x00020001,
316 0x9228, 0xffffffff, 0x00040003,
317 0x922c, 0xffffffff, 0x00060005,
318 0x9238, 0xffffffff, 0x00080007,
319 0x923c, 0xffffffff, 0x000a0009,
320 0x9240, 0xffffffff, 0x000c000b,
321 0x9244, 0xffffffff, 0x000e000d,
322 0x9248, 0xffffffff, 0x0010000f,
323 0x9254, 0xffffffff, 0x00120011,
324 0x9258, 0xffffffff, 0x00140013,
325 0x925c, 0xffffffff, 0x00020001,
326 0x9260, 0xffffffff, 0x00040003,
327 0x9264, 0xffffffff, 0x00060005,
328 0x9270, 0xffffffff, 0x00080007,
329 0x9274, 0xffffffff, 0x000a0009,
330 0x9278, 0xffffffff, 0x000c000b,
331 0x927c, 0xffffffff, 0x000e000d,
332 0x9280, 0xffffffff, 0x0010000f,
333 0x928c, 0xffffffff, 0x00120011,
334 0x9290, 0xffffffff, 0x00140013,
335 0x9294, 0xffffffff, 0x00020001,
336 0x929c, 0xffffffff, 0x00040003,
337 0x92a0, 0xffffffff, 0x00060005,
338 0x92a4, 0xffffffff, 0x00080007
339};
340
341static const u32 rv710_golden_registers[] =
342{
343 0x3f90, 0x00ff0000, 0x00fc0000,
344 0x9148, 0x00ff0000, 0x00fc0000,
345 0x3f94, 0x00ff0000, 0x00fc0000,
346 0x914c, 0x00ff0000, 0x00fc0000,
347 0xb4c, 0x00000020, 0x00000020,
348 0xa180, 0xffffffff, 0x00003f3f
349};
350
351static const u32 rv710_mgcg_init[] =
352{
353 0x8bcc, 0xffffffff, 0x13030040,
354 0x5448, 0xffffffff, 0x100,
355 0x55e4, 0xffffffff, 0x100,
356 0x160c, 0xffffffff, 0x100,
357 0x5644, 0xffffffff, 0x100,
358 0xc164, 0xffffffff, 0x100,
359 0x8a18, 0xffffffff, 0x100,
360 0x897c, 0xffffffff, 0x8000100,
361 0x8b28, 0xffffffff, 0x3c000100,
362 0x9144, 0xffffffff, 0x100,
363 0x9a1c, 0xffffffff, 0x10000,
364 0x9a50, 0xffffffff, 0x100,
365 0x9a1c, 0xffffffff, 0x0,
366 0x9870, 0xffffffff, 0x100,
367 0x8d58, 0xffffffff, 0x100,
368 0x9500, 0xffffffff, 0x0,
369 0x9510, 0xffffffff, 0x100,
370 0x9500, 0xffffffff, 0x1,
371 0x9510, 0xffffffff, 0x100,
372 0x9500, 0xffffffff, 0x8000,
373 0x9490, 0xffffffff, 0x0,
374 0x949c, 0xffffffff, 0x100,
375 0x9490, 0xffffffff, 0x1,
376 0x949c, 0xffffffff, 0x100,
377 0x9490, 0xffffffff, 0x8000,
378 0x9604, 0xffffffff, 0x0,
379 0x9654, 0xffffffff, 0x100,
380 0x9604, 0xffffffff, 0x1,
381 0x9654, 0xffffffff, 0x100,
382 0x9604, 0xffffffff, 0x80000000,
383 0x9030, 0xffffffff, 0x100,
384 0x9034, 0xffffffff, 0x100,
385 0x9038, 0xffffffff, 0x100,
386 0x903c, 0xffffffff, 0x100,
387 0x9040, 0xffffffff, 0x100,
388 0xa200, 0xffffffff, 0x100,
389 0xa204, 0xffffffff, 0x100,
390 0xa208, 0xffffffff, 0x100,
391 0xa20c, 0xffffffff, 0x100,
392 0x971c, 0xffffffff, 0x100,
393 0x915c, 0xffffffff, 0x00020001,
394 0x9174, 0xffffffff, 0x00000003,
395 0x9178, 0xffffffff, 0x00050001,
396 0x917c, 0xffffffff, 0x00030002,
397 0x918c, 0xffffffff, 0x00000004,
398 0x9190, 0xffffffff, 0x00070006,
399 0x9194, 0xffffffff, 0x00050001,
400 0x9198, 0xffffffff, 0x00030002,
401 0x91a8, 0xffffffff, 0x00000004,
402 0x91ac, 0xffffffff, 0x00070006,
403 0x91e8, 0xffffffff, 0x00000001,
404 0x9294, 0xffffffff, 0x00000001,
405 0x929c, 0xffffffff, 0x00000002,
406 0x92a0, 0xffffffff, 0x00040003,
407 0x9150, 0xffffffff, 0x4d940000
408};
409
410static const u32 rv730_golden_registers[] =
411{
412 0x3f90, 0x00ff0000, 0x00f00000,
413 0x9148, 0x00ff0000, 0x00f00000,
414 0x3f94, 0x00ff0000, 0x00f00000,
415 0x914c, 0x00ff0000, 0x00f00000,
416 0x900c, 0xffffffff, 0x003b033f,
417 0xb4c, 0x00000020, 0x00000020,
418 0xa180, 0xffffffff, 0x00003f3f
419};
420
421static const u32 rv730_mgcg_init[] =
422{
423 0x8bcc, 0xffffffff, 0x130300f9,
424 0x5448, 0xffffffff, 0x100,
425 0x55e4, 0xffffffff, 0x100,
426 0x160c, 0xffffffff, 0x100,
427 0x5644, 0xffffffff, 0x100,
428 0xc164, 0xffffffff, 0x100,
429 0x8a18, 0xffffffff, 0x100,
430 0x897c, 0xffffffff, 0x8000100,
431 0x8b28, 0xffffffff, 0x3c000100,
432 0x9144, 0xffffffff, 0x100,
433 0x9a1c, 0xffffffff, 0x10000,
434 0x9a50, 0xffffffff, 0x100,
435 0x9a1c, 0xffffffff, 0x10001,
436 0x9a50, 0xffffffff, 0x100,
437 0x9a1c, 0xffffffff, 0x0,
438 0x9870, 0xffffffff, 0x100,
439 0x8d58, 0xffffffff, 0x100,
440 0x9500, 0xffffffff, 0x0,
441 0x9510, 0xffffffff, 0x100,
442 0x9500, 0xffffffff, 0x1,
443 0x9510, 0xffffffff, 0x100,
444 0x9500, 0xffffffff, 0x2,
445 0x9510, 0xffffffff, 0x100,
446 0x9500, 0xffffffff, 0x3,
447 0x9510, 0xffffffff, 0x100,
448 0x9500, 0xffffffff, 0x4,
449 0x9510, 0xffffffff, 0x100,
450 0x9500, 0xffffffff, 0x5,
451 0x9510, 0xffffffff, 0x100,
452 0x9500, 0xffffffff, 0x6,
453 0x9510, 0xffffffff, 0x100,
454 0x9500, 0xffffffff, 0x7,
455 0x9510, 0xffffffff, 0x100,
456 0x9500, 0xffffffff, 0x8000,
457 0x9490, 0xffffffff, 0x0,
458 0x949c, 0xffffffff, 0x100,
459 0x9490, 0xffffffff, 0x1,
460 0x949c, 0xffffffff, 0x100,
461 0x9490, 0xffffffff, 0x2,
462 0x949c, 0xffffffff, 0x100,
463 0x9490, 0xffffffff, 0x3,
464 0x949c, 0xffffffff, 0x100,
465 0x9490, 0xffffffff, 0x4,
466 0x949c, 0xffffffff, 0x100,
467 0x9490, 0xffffffff, 0x5,
468 0x949c, 0xffffffff, 0x100,
469 0x9490, 0xffffffff, 0x6,
470 0x949c, 0xffffffff, 0x100,
471 0x9490, 0xffffffff, 0x7,
472 0x949c, 0xffffffff, 0x100,
473 0x9490, 0xffffffff, 0x8000,
474 0x9604, 0xffffffff, 0x0,
475 0x9654, 0xffffffff, 0x100,
476 0x9604, 0xffffffff, 0x1,
477 0x9654, 0xffffffff, 0x100,
478 0x9604, 0xffffffff, 0x2,
479 0x9654, 0xffffffff, 0x100,
480 0x9604, 0xffffffff, 0x3,
481 0x9654, 0xffffffff, 0x100,
482 0x9604, 0xffffffff, 0x4,
483 0x9654, 0xffffffff, 0x100,
484 0x9604, 0xffffffff, 0x5,
485 0x9654, 0xffffffff, 0x100,
486 0x9604, 0xffffffff, 0x6,
487 0x9654, 0xffffffff, 0x100,
488 0x9604, 0xffffffff, 0x7,
489 0x9654, 0xffffffff, 0x100,
490 0x9604, 0xffffffff, 0x80000000,
491 0x9030, 0xffffffff, 0x100,
492 0x9034, 0xffffffff, 0x100,
493 0x9038, 0xffffffff, 0x100,
494 0x903c, 0xffffffff, 0x100,
495 0x9040, 0xffffffff, 0x100,
496 0xa200, 0xffffffff, 0x100,
497 0xa204, 0xffffffff, 0x100,
498 0xa208, 0xffffffff, 0x100,
499 0xa20c, 0xffffffff, 0x100,
500 0x971c, 0xffffffff, 0x100,
501 0x915c, 0xffffffff, 0x00020001,
502 0x916c, 0xffffffff, 0x00040003,
503 0x9170, 0xffffffff, 0x00000005,
504 0x9178, 0xffffffff, 0x00050001,
505 0x917c, 0xffffffff, 0x00030002,
506 0x918c, 0xffffffff, 0x00000004,
507 0x9190, 0xffffffff, 0x00070006,
508 0x9194, 0xffffffff, 0x00050001,
509 0x9198, 0xffffffff, 0x00030002,
510 0x91a8, 0xffffffff, 0x00000004,
511 0x91ac, 0xffffffff, 0x00070006,
512 0x91b0, 0xffffffff, 0x00050001,
513 0x91b4, 0xffffffff, 0x00030002,
514 0x91c4, 0xffffffff, 0x00000004,
515 0x91c8, 0xffffffff, 0x00070006,
516 0x91cc, 0xffffffff, 0x00050001,
517 0x91d0, 0xffffffff, 0x00030002,
518 0x91e0, 0xffffffff, 0x00000004,
519 0x91e4, 0xffffffff, 0x00070006,
520 0x91e8, 0xffffffff, 0x00000001,
521 0x91ec, 0xffffffff, 0x00050001,
522 0x91f0, 0xffffffff, 0x00030002,
523 0x9200, 0xffffffff, 0x00000004,
524 0x9204, 0xffffffff, 0x00070006,
525 0x9208, 0xffffffff, 0x00050001,
526 0x920c, 0xffffffff, 0x00030002,
527 0x921c, 0xffffffff, 0x00000004,
528 0x9220, 0xffffffff, 0x00070006,
529 0x9224, 0xffffffff, 0x00050001,
530 0x9228, 0xffffffff, 0x00030002,
531 0x9238, 0xffffffff, 0x00000004,
532 0x923c, 0xffffffff, 0x00070006,
533 0x9240, 0xffffffff, 0x00050001,
534 0x9244, 0xffffffff, 0x00030002,
535 0x9254, 0xffffffff, 0x00000004,
536 0x9258, 0xffffffff, 0x00070006,
537 0x9294, 0xffffffff, 0x00000001,
538 0x929c, 0xffffffff, 0x00000002,
539 0x92a0, 0xffffffff, 0x00040003,
540 0x92a4, 0xffffffff, 0x00000005
541};
542
543static const u32 rv740_golden_registers[] =
544{
545 0x88c4, 0xffffffff, 0x00000082,
546 0x28a50, 0xfffffffc, 0x00000004,
547 0x2650, 0x00040000, 0,
548 0x20bc, 0x00040000, 0,
549 0x733c, 0xffffffff, 0x00000002,
550 0x7300, 0xffffffff, 0x001000f0,
551 0x3f90, 0x00ff0000, 0,
552 0x9148, 0x00ff0000, 0,
553 0x3f94, 0x00ff0000, 0,
554 0x914c, 0x00ff0000, 0,
555 0x240c, 0xffffffff, 0x00000380,
556 0x8a14, 0x00000007, 0x00000007,
557 0x8b24, 0xffffffff, 0x00ff0fff,
558 0x28a4c, 0xffffffff, 0x00004000,
559 0xa180, 0xffffffff, 0x00003f3f,
560 0x8d00, 0xffffffff, 0x0e0e003a,
561 0x8d04, 0xffffffff, 0x013a0e2a,
562 0x8c00, 0xffffffff, 0xe400000f,
563 0x8db0, 0xffffffff, 0x98989898,
564 0x8db4, 0xffffffff, 0x98989898,
565 0x8db8, 0xffffffff, 0x98989898,
566 0x8dbc, 0xffffffff, 0x98989898,
567 0x8dc0, 0xffffffff, 0x98989898,
568 0x8dc4, 0xffffffff, 0x98989898,
569 0x8dc8, 0xffffffff, 0x98989898,
570 0x8dcc, 0xffffffff, 0x98989898,
571 0x9058, 0xffffffff, 0x0fffc40f,
572 0x900c, 0xffffffff, 0x003b033f,
573 0x28350, 0xffffffff, 0,
574 0x8cf0, 0x1fffffff, 0x08e00420,
575 0x9508, 0xffffffff, 0x00000002,
576 0x88c4, 0xffffffff, 0x000000c2,
577 0x9698, 0x18000000, 0x18000000
578};
579
580static const u32 rv740_mgcg_init[] =
581{
582 0x8bcc, 0xffffffff, 0x13030100,
583 0x5448, 0xffffffff, 0x100,
584 0x55e4, 0xffffffff, 0x100,
585 0x160c, 0xffffffff, 0x100,
586 0x5644, 0xffffffff, 0x100,
587 0xc164, 0xffffffff, 0x100,
588 0x8a18, 0xffffffff, 0x100,
589 0x897c, 0xffffffff, 0x100,
590 0x8b28, 0xffffffff, 0x100,
591 0x9144, 0xffffffff, 0x100,
592 0x9a1c, 0xffffffff, 0x10000,
593 0x9a50, 0xffffffff, 0x100,
594 0x9a1c, 0xffffffff, 0x10001,
595 0x9a50, 0xffffffff, 0x100,
596 0x9a1c, 0xffffffff, 0x10002,
597 0x9a50, 0xffffffff, 0x100,
598 0x9a1c, 0xffffffff, 0x10003,
599 0x9a50, 0xffffffff, 0x100,
600 0x9a1c, 0xffffffff, 0x0,
601 0x9870, 0xffffffff, 0x100,
602 0x8d58, 0xffffffff, 0x100,
603 0x9500, 0xffffffff, 0x0,
604 0x9510, 0xffffffff, 0x100,
605 0x9500, 0xffffffff, 0x1,
606 0x9510, 0xffffffff, 0x100,
607 0x9500, 0xffffffff, 0x2,
608 0x9510, 0xffffffff, 0x100,
609 0x9500, 0xffffffff, 0x3,
610 0x9510, 0xffffffff, 0x100,
611 0x9500, 0xffffffff, 0x4,
612 0x9510, 0xffffffff, 0x100,
613 0x9500, 0xffffffff, 0x5,
614 0x9510, 0xffffffff, 0x100,
615 0x9500, 0xffffffff, 0x6,
616 0x9510, 0xffffffff, 0x100,
617 0x9500, 0xffffffff, 0x7,
618 0x9510, 0xffffffff, 0x100,
619 0x9500, 0xffffffff, 0x8000,
620 0x9490, 0xffffffff, 0x0,
621 0x949c, 0xffffffff, 0x100,
622 0x9490, 0xffffffff, 0x1,
623 0x949c, 0xffffffff, 0x100,
624 0x9490, 0xffffffff, 0x2,
625 0x949c, 0xffffffff, 0x100,
626 0x9490, 0xffffffff, 0x3,
627 0x949c, 0xffffffff, 0x100,
628 0x9490, 0xffffffff, 0x4,
629 0x949c, 0xffffffff, 0x100,
630 0x9490, 0xffffffff, 0x5,
631 0x949c, 0xffffffff, 0x100,
632 0x9490, 0xffffffff, 0x6,
633 0x949c, 0xffffffff, 0x100,
634 0x9490, 0xffffffff, 0x7,
635 0x949c, 0xffffffff, 0x100,
636 0x9490, 0xffffffff, 0x8000,
637 0x9604, 0xffffffff, 0x0,
638 0x9654, 0xffffffff, 0x100,
639 0x9604, 0xffffffff, 0x1,
640 0x9654, 0xffffffff, 0x100,
641 0x9604, 0xffffffff, 0x2,
642 0x9654, 0xffffffff, 0x100,
643 0x9604, 0xffffffff, 0x3,
644 0x9654, 0xffffffff, 0x100,
645 0x9604, 0xffffffff, 0x4,
646 0x9654, 0xffffffff, 0x100,
647 0x9604, 0xffffffff, 0x5,
648 0x9654, 0xffffffff, 0x100,
649 0x9604, 0xffffffff, 0x6,
650 0x9654, 0xffffffff, 0x100,
651 0x9604, 0xffffffff, 0x7,
652 0x9654, 0xffffffff, 0x100,
653 0x9604, 0xffffffff, 0x80000000,
654 0x9030, 0xffffffff, 0x100,
655 0x9034, 0xffffffff, 0x100,
656 0x9038, 0xffffffff, 0x100,
657 0x903c, 0xffffffff, 0x100,
658 0x9040, 0xffffffff, 0x100,
659 0xa200, 0xffffffff, 0x100,
660 0xa204, 0xffffffff, 0x100,
661 0xa208, 0xffffffff, 0x100,
662 0xa20c, 0xffffffff, 0x100,
663 0x971c, 0xffffffff, 0x100,
664 0x915c, 0xffffffff, 0x00020001,
665 0x9160, 0xffffffff, 0x00040003,
666 0x916c, 0xffffffff, 0x00060005,
667 0x9170, 0xffffffff, 0x00080007,
668 0x9174, 0xffffffff, 0x000a0009,
669 0x9178, 0xffffffff, 0x000c000b,
670 0x917c, 0xffffffff, 0x000e000d,
671 0x9180, 0xffffffff, 0x0010000f,
672 0x918c, 0xffffffff, 0x00120011,
673 0x9190, 0xffffffff, 0x00140013,
674 0x9194, 0xffffffff, 0x00020001,
675 0x9198, 0xffffffff, 0x00040003,
676 0x919c, 0xffffffff, 0x00060005,
677 0x91a8, 0xffffffff, 0x00080007,
678 0x91ac, 0xffffffff, 0x000a0009,
679 0x91b0, 0xffffffff, 0x000c000b,
680 0x91b4, 0xffffffff, 0x000e000d,
681 0x91b8, 0xffffffff, 0x0010000f,
682 0x91c4, 0xffffffff, 0x00120011,
683 0x91c8, 0xffffffff, 0x00140013,
684 0x91cc, 0xffffffff, 0x00020001,
685 0x91d0, 0xffffffff, 0x00040003,
686 0x91d4, 0xffffffff, 0x00060005,
687 0x91e0, 0xffffffff, 0x00080007,
688 0x91e4, 0xffffffff, 0x000a0009,
689 0x91e8, 0xffffffff, 0x000c000b,
690 0x91ec, 0xffffffff, 0x00020001,
691 0x91f0, 0xffffffff, 0x00040003,
692 0x91f4, 0xffffffff, 0x00060005,
693 0x9200, 0xffffffff, 0x00080007,
694 0x9204, 0xffffffff, 0x000a0009,
695 0x9208, 0xffffffff, 0x000c000b,
696 0x920c, 0xffffffff, 0x000e000d,
697 0x9210, 0xffffffff, 0x0010000f,
698 0x921c, 0xffffffff, 0x00120011,
699 0x9220, 0xffffffff, 0x00140013,
700 0x9224, 0xffffffff, 0x00020001,
701 0x9228, 0xffffffff, 0x00040003,
702 0x922c, 0xffffffff, 0x00060005,
703 0x9238, 0xffffffff, 0x00080007,
704 0x923c, 0xffffffff, 0x000a0009,
705 0x9240, 0xffffffff, 0x000c000b,
706 0x9244, 0xffffffff, 0x000e000d,
707 0x9248, 0xffffffff, 0x0010000f,
708 0x9254, 0xffffffff, 0x00120011,
709 0x9258, 0xffffffff, 0x00140013,
710 0x9294, 0xffffffff, 0x00020001,
711 0x929c, 0xffffffff, 0x00040003,
712 0x92a0, 0xffffffff, 0x00060005,
713 0x92a4, 0xffffffff, 0x00080007
714};
715
716static void rv770_init_golden_registers(struct radeon_device *rdev)
717{
718 switch (rdev->family) {
719 case CHIP_RV770:
720 radeon_program_register_sequence(rdev,
721 r7xx_golden_registers,
722 (const u32)ARRAY_SIZE(r7xx_golden_registers));
723 radeon_program_register_sequence(rdev,
724 r7xx_golden_dyn_gpr_registers,
725 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
726 if (rdev->pdev->device == 0x994e)
727 radeon_program_register_sequence(rdev,
728 rv770ce_golden_registers,
729 (const u32)ARRAY_SIZE(rv770ce_golden_registers));
730 else
731 radeon_program_register_sequence(rdev,
732 rv770_golden_registers,
733 (const u32)ARRAY_SIZE(rv770_golden_registers));
734 radeon_program_register_sequence(rdev,
735 rv770_mgcg_init,
736 (const u32)ARRAY_SIZE(rv770_mgcg_init));
737 break;
738 case CHIP_RV730:
739 radeon_program_register_sequence(rdev,
740 r7xx_golden_registers,
741 (const u32)ARRAY_SIZE(r7xx_golden_registers));
742 radeon_program_register_sequence(rdev,
743 r7xx_golden_dyn_gpr_registers,
744 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
745 radeon_program_register_sequence(rdev,
746 rv730_golden_registers,
747 (const u32)ARRAY_SIZE(rv730_golden_registers));
748 radeon_program_register_sequence(rdev,
749 rv730_mgcg_init,
750 (const u32)ARRAY_SIZE(rv730_mgcg_init));
751 break;
752 case CHIP_RV710:
753 radeon_program_register_sequence(rdev,
754 r7xx_golden_registers,
755 (const u32)ARRAY_SIZE(r7xx_golden_registers));
756 radeon_program_register_sequence(rdev,
757 r7xx_golden_dyn_gpr_registers,
758 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
759 radeon_program_register_sequence(rdev,
760 rv710_golden_registers,
761 (const u32)ARRAY_SIZE(rv710_golden_registers));
762 radeon_program_register_sequence(rdev,
763 rv710_mgcg_init,
764 (const u32)ARRAY_SIZE(rv710_mgcg_init));
765 break;
766 case CHIP_RV740:
767 radeon_program_register_sequence(rdev,
768 rv740_golden_registers,
769 (const u32)ARRAY_SIZE(rv740_golden_registers));
770 radeon_program_register_sequence(rdev,
771 rv740_mgcg_init,
772 (const u32)ARRAY_SIZE(rv740_mgcg_init));
773 break;
774 default:
775 break;
776 }
777}
778
779#define PCIE_BUS_CLK 10000
780#define TCLK (PCIE_BUS_CLK / 10)
781
782/**
783 * rv770_get_xclk - get the xclk
784 *
785 * @rdev: radeon_device pointer
786 *
787 * Returns the reference clock used by the gfx engine
788 * (r7xx-cayman).
789 */
790u32 rv770_get_xclk(struct radeon_device *rdev)
791{
792 u32 reference_clock = rdev->clock.spll.reference_freq;
793 u32 tmp = RREG32(CG_CLKPIN_CNTL);
794
795 if (tmp & MUX_TCLK_TO_XCLK)
796 return TCLK;
797
798 if (tmp & XTALIN_DIVIDE)
799 return reference_clock / 4;
800
801 return reference_clock;
802}
803
804void rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
805{
806 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
807 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
808 int i;
809
810 /* Lock the graphics update lock */
811 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
812 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
813
814 /* update the scanout addresses */
815 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,
816 async ? AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0);
817 if (radeon_crtc->crtc_id) {
818 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
819 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
820 } else {
821 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
822 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
823 }
824 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
825 (u32)crtc_base);
826 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
827 (u32)crtc_base);
828
829 /* Wait for update_pending to go high. */
830 for (i = 0; i < rdev->usec_timeout; i++) {
831 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
832 break;
833 udelay(1);
834 }
835 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
836
837 /* Unlock the lock, so double-buffering can take place inside vblank */
838 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
839 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
840}
841
842bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc_id)
843{
844 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
845
846 /* Return current update_pending status: */
847 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
848 AVIVO_D1GRPH_SURFACE_UPDATE_PENDING);
849}
850
851/* get temperature in millidegrees */
852int rv770_get_temp(struct radeon_device *rdev)
853{
854 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
855 ASIC_T_SHIFT;
856 int actual_temp;
857
858 if (temp & 0x400)
859 actual_temp = -256;
860 else if (temp & 0x200)
861 actual_temp = 255;
862 else if (temp & 0x100) {
863 actual_temp = temp & 0x1ff;
864 actual_temp |= ~0x1ff;
865 } else
866 actual_temp = temp & 0xff;
867
868 return (actual_temp * 1000) / 2;
869}
870
871void rv770_pm_misc(struct radeon_device *rdev)
872{
873 int req_ps_idx = rdev->pm.requested_power_state_index;
874 int req_cm_idx = rdev->pm.requested_clock_mode_index;
875 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
876 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
877
878 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
879 /* 0xff01 is a flag rather then an actual voltage */
880 if (voltage->voltage == 0xff01)
881 return;
882 if (voltage->voltage != rdev->pm.current_vddc) {
883 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
884 rdev->pm.current_vddc = voltage->voltage;
885 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
886 }
887 }
888}
889
890/*
891 * GART
892 */
893static int rv770_pcie_gart_enable(struct radeon_device *rdev)
894{
895 u32 tmp;
896 int r, i;
897
898 if (rdev->gart.robj == NULL) {
899 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
900 return -EINVAL;
901 }
902 r = radeon_gart_table_vram_pin(rdev);
903 if (r)
904 return r;
905 /* Setup L2 cache */
906 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
907 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
908 EFFECTIVE_L2_QUEUE_SIZE(7));
909 WREG32(VM_L2_CNTL2, 0);
910 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
911 /* Setup TLB control */
912 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
913 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
914 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
915 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
916 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
917 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
918 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
919 if (rdev->family == CHIP_RV740)
920 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
921 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
922 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
923 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
924 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
925 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
926 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
927 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
928 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
929 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
930 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
931 (u32)(rdev->dummy_page.addr >> 12));
932 for (i = 1; i < 7; i++)
933 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
934
935 r600_pcie_gart_tlb_flush(rdev);
936 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
937 (unsigned)(rdev->mc.gtt_size >> 20),
938 (unsigned long long)rdev->gart.table_addr);
939 rdev->gart.ready = true;
940 return 0;
941}
942
943static void rv770_pcie_gart_disable(struct radeon_device *rdev)
944{
945 u32 tmp;
946 int i;
947
948 /* Disable all tables */
949 for (i = 0; i < 7; i++)
950 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
951
952 /* Setup L2 cache */
953 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
954 EFFECTIVE_L2_QUEUE_SIZE(7));
955 WREG32(VM_L2_CNTL2, 0);
956 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
957 /* Setup TLB control */
958 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
959 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
960 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
961 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
962 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
963 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
964 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
965 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
966 radeon_gart_table_vram_unpin(rdev);
967}
968
969static void rv770_pcie_gart_fini(struct radeon_device *rdev)
970{
971 radeon_gart_fini(rdev);
972 rv770_pcie_gart_disable(rdev);
973 radeon_gart_table_vram_free(rdev);
974}
975
976
977static void rv770_agp_enable(struct radeon_device *rdev)
978{
979 u32 tmp;
980 int i;
981
982 /* Setup L2 cache */
983 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
984 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
985 EFFECTIVE_L2_QUEUE_SIZE(7));
986 WREG32(VM_L2_CNTL2, 0);
987 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
988 /* Setup TLB control */
989 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
990 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
991 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
992 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
993 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
994 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
995 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
996 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
997 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
998 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
999 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1000 for (i = 0; i < 7; i++)
1001 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1002}
1003
1004static void rv770_mc_program(struct radeon_device *rdev)
1005{
1006 struct rv515_mc_save save;
1007 u32 tmp;
1008 int i, j;
1009
1010 /* Initialize HDP */
1011 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1012 WREG32((0x2c14 + j), 0x00000000);
1013 WREG32((0x2c18 + j), 0x00000000);
1014 WREG32((0x2c1c + j), 0x00000000);
1015 WREG32((0x2c20 + j), 0x00000000);
1016 WREG32((0x2c24 + j), 0x00000000);
1017 }
1018 /* r7xx hw bug. Read from HDP_DEBUG1 rather
1019 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
1020 */
1021 tmp = RREG32(HDP_DEBUG1);
1022
1023 rv515_mc_stop(rdev, &save);
1024 if (r600_mc_wait_for_idle(rdev)) {
1025 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1026 }
1027 /* Lockout access through VGA aperture*/
1028 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1029 /* Update configuration */
1030 if (rdev->flags & RADEON_IS_AGP) {
1031 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1032 /* VRAM before AGP */
1033 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1034 rdev->mc.vram_start >> 12);
1035 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1036 rdev->mc.gtt_end >> 12);
1037 } else {
1038 /* VRAM after AGP */
1039 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1040 rdev->mc.gtt_start >> 12);
1041 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1042 rdev->mc.vram_end >> 12);
1043 }
1044 } else {
1045 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1046 rdev->mc.vram_start >> 12);
1047 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1048 rdev->mc.vram_end >> 12);
1049 }
1050 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1051 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1052 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1053 WREG32(MC_VM_FB_LOCATION, tmp);
1054 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1055 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1056 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1057 if (rdev->flags & RADEON_IS_AGP) {
1058 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1059 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1060 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1061 } else {
1062 WREG32(MC_VM_AGP_BASE, 0);
1063 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1064 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1065 }
1066 if (r600_mc_wait_for_idle(rdev)) {
1067 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1068 }
1069 rv515_mc_resume(rdev, &save);
1070 /* we need to own VRAM, so turn off the VGA renderer here
1071 * to stop it overwriting our objects */
1072 rv515_vga_render_disable(rdev);
1073}
1074
1075
1076/*
1077 * CP.
1078 */
1079void r700_cp_stop(struct radeon_device *rdev)
1080{
1081 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1082 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1083 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1084 WREG32(SCRATCH_UMSK, 0);
1085 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1086}
1087
1088static int rv770_cp_load_microcode(struct radeon_device *rdev)
1089{
1090 const __be32 *fw_data;
1091 int i;
1092
1093 if (!rdev->me_fw || !rdev->pfp_fw)
1094 return -EINVAL;
1095
1096 r700_cp_stop(rdev);
1097 WREG32(CP_RB_CNTL,
1098#ifdef __BIG_ENDIAN
1099 BUF_SWAP_32BIT |
1100#endif
1101 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1102
1103 /* Reset cp */
1104 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1105 RREG32(GRBM_SOFT_RESET);
1106 mdelay(15);
1107 WREG32(GRBM_SOFT_RESET, 0);
1108
1109 fw_data = (const __be32 *)rdev->pfp_fw->data;
1110 WREG32(CP_PFP_UCODE_ADDR, 0);
1111 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
1112 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1113 WREG32(CP_PFP_UCODE_ADDR, 0);
1114
1115 fw_data = (const __be32 *)rdev->me_fw->data;
1116 WREG32(CP_ME_RAM_WADDR, 0);
1117 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
1118 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1119
1120 WREG32(CP_PFP_UCODE_ADDR, 0);
1121 WREG32(CP_ME_RAM_WADDR, 0);
1122 WREG32(CP_ME_RAM_RADDR, 0);
1123 return 0;
1124}
1125
1126void r700_cp_fini(struct radeon_device *rdev)
1127{
1128 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1129 r700_cp_stop(rdev);
1130 radeon_ring_fini(rdev, ring);
1131 radeon_scratch_free(rdev, ring->rptr_save_reg);
1132}
1133
1134void rv770_set_clk_bypass_mode(struct radeon_device *rdev)
1135{
1136 u32 tmp, i;
1137
1138 if (rdev->flags & RADEON_IS_IGP)
1139 return;
1140
1141 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
1142 tmp &= SCLK_MUX_SEL_MASK;
1143 tmp |= SCLK_MUX_SEL(1) | SCLK_MUX_UPDATE;
1144 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
1145
1146 for (i = 0; i < rdev->usec_timeout; i++) {
1147 if (RREG32(CG_SPLL_STATUS) & SPLL_CHG_STATUS)
1148 break;
1149 udelay(1);
1150 }
1151
1152 tmp &= ~SCLK_MUX_UPDATE;
1153 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
1154
1155 tmp = RREG32(MPLL_CNTL_MODE);
1156 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1157 tmp &= ~RV730_MPLL_MCLK_SEL;
1158 else
1159 tmp &= ~MPLL_MCLK_SEL;
1160 WREG32(MPLL_CNTL_MODE, tmp);
1161}
1162
1163/*
1164 * Core functions
1165 */
1166static void rv770_gpu_init(struct radeon_device *rdev)
1167{
1168 int i, j, num_qd_pipes;
1169 u32 ta_aux_cntl;
1170 u32 sx_debug_1;
1171 u32 smx_dc_ctl0;
1172 u32 db_debug3;
1173 u32 num_gs_verts_per_thread;
1174 u32 vgt_gs_per_es;
1175 u32 gs_prim_buffer_depth = 0;
1176 u32 sq_ms_fifo_sizes;
1177 u32 sq_config;
1178 u32 sq_thread_resource_mgmt;
1179 u32 hdp_host_path_cntl;
1180 u32 sq_dyn_gpr_size_simd_ab_0;
1181 u32 gb_tiling_config = 0;
1182 u32 cc_gc_shader_pipe_config = 0;
1183 u32 mc_arb_ramcfg;
1184 u32 db_debug4, tmp;
1185 u32 inactive_pipes, shader_pipe_config;
1186 u32 disabled_rb_mask;
1187 unsigned active_number;
1188
1189 /* setup chip specs */
1190 rdev->config.rv770.tiling_group_size = 256;
1191 switch (rdev->family) {
1192 case CHIP_RV770:
1193 rdev->config.rv770.max_pipes = 4;
1194 rdev->config.rv770.max_tile_pipes = 8;
1195 rdev->config.rv770.max_simds = 10;
1196 rdev->config.rv770.max_backends = 4;
1197 rdev->config.rv770.max_gprs = 256;
1198 rdev->config.rv770.max_threads = 248;
1199 rdev->config.rv770.max_stack_entries = 512;
1200 rdev->config.rv770.max_hw_contexts = 8;
1201 rdev->config.rv770.max_gs_threads = 16 * 2;
1202 rdev->config.rv770.sx_max_export_size = 128;
1203 rdev->config.rv770.sx_max_export_pos_size = 16;
1204 rdev->config.rv770.sx_max_export_smx_size = 112;
1205 rdev->config.rv770.sq_num_cf_insts = 2;
1206
1207 rdev->config.rv770.sx_num_of_sets = 7;
1208 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
1209 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1210 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1211 break;
1212 case CHIP_RV730:
1213 rdev->config.rv770.max_pipes = 2;
1214 rdev->config.rv770.max_tile_pipes = 4;
1215 rdev->config.rv770.max_simds = 8;
1216 rdev->config.rv770.max_backends = 2;
1217 rdev->config.rv770.max_gprs = 128;
1218 rdev->config.rv770.max_threads = 248;
1219 rdev->config.rv770.max_stack_entries = 256;
1220 rdev->config.rv770.max_hw_contexts = 8;
1221 rdev->config.rv770.max_gs_threads = 16 * 2;
1222 rdev->config.rv770.sx_max_export_size = 256;
1223 rdev->config.rv770.sx_max_export_pos_size = 32;
1224 rdev->config.rv770.sx_max_export_smx_size = 224;
1225 rdev->config.rv770.sq_num_cf_insts = 2;
1226
1227 rdev->config.rv770.sx_num_of_sets = 7;
1228 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
1229 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1230 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1231 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
1232 rdev->config.rv770.sx_max_export_pos_size -= 16;
1233 rdev->config.rv770.sx_max_export_smx_size += 16;
1234 }
1235 break;
1236 case CHIP_RV710:
1237 rdev->config.rv770.max_pipes = 2;
1238 rdev->config.rv770.max_tile_pipes = 2;
1239 rdev->config.rv770.max_simds = 2;
1240 rdev->config.rv770.max_backends = 1;
1241 rdev->config.rv770.max_gprs = 256;
1242 rdev->config.rv770.max_threads = 192;
1243 rdev->config.rv770.max_stack_entries = 256;
1244 rdev->config.rv770.max_hw_contexts = 4;
1245 rdev->config.rv770.max_gs_threads = 8 * 2;
1246 rdev->config.rv770.sx_max_export_size = 128;
1247 rdev->config.rv770.sx_max_export_pos_size = 16;
1248 rdev->config.rv770.sx_max_export_smx_size = 112;
1249 rdev->config.rv770.sq_num_cf_insts = 1;
1250
1251 rdev->config.rv770.sx_num_of_sets = 7;
1252 rdev->config.rv770.sc_prim_fifo_size = 0x40;
1253 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1254 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1255 break;
1256 case CHIP_RV740:
1257 rdev->config.rv770.max_pipes = 4;
1258 rdev->config.rv770.max_tile_pipes = 4;
1259 rdev->config.rv770.max_simds = 8;
1260 rdev->config.rv770.max_backends = 4;
1261 rdev->config.rv770.max_gprs = 256;
1262 rdev->config.rv770.max_threads = 248;
1263 rdev->config.rv770.max_stack_entries = 512;
1264 rdev->config.rv770.max_hw_contexts = 8;
1265 rdev->config.rv770.max_gs_threads = 16 * 2;
1266 rdev->config.rv770.sx_max_export_size = 256;
1267 rdev->config.rv770.sx_max_export_pos_size = 32;
1268 rdev->config.rv770.sx_max_export_smx_size = 224;
1269 rdev->config.rv770.sq_num_cf_insts = 2;
1270
1271 rdev->config.rv770.sx_num_of_sets = 7;
1272 rdev->config.rv770.sc_prim_fifo_size = 0x100;
1273 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1274 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1275
1276 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
1277 rdev->config.rv770.sx_max_export_pos_size -= 16;
1278 rdev->config.rv770.sx_max_export_smx_size += 16;
1279 }
1280 break;
1281 default:
1282 break;
1283 }
1284
1285 /* Initialize HDP */
1286 j = 0;
1287 for (i = 0; i < 32; i++) {
1288 WREG32((0x2c14 + j), 0x00000000);
1289 WREG32((0x2c18 + j), 0x00000000);
1290 WREG32((0x2c1c + j), 0x00000000);
1291 WREG32((0x2c20 + j), 0x00000000);
1292 WREG32((0x2c24 + j), 0x00000000);
1293 j += 0x18;
1294 }
1295
1296 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1297
1298 /* setup tiling, simd, pipe config */
1299 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1300
1301 shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
1302 inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
1303 for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) {
1304 if (!(inactive_pipes & tmp)) {
1305 active_number++;
1306 }
1307 tmp <<= 1;
1308 }
1309 if (active_number == 1) {
1310 WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1);
1311 } else {
1312 WREG32(SPI_CONFIG_CNTL, 0);
1313 }
1314
1315 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1316 tmp = rdev->config.rv770.max_simds -
1317 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK);
1318 rdev->config.rv770.active_simds = tmp;
1319
1320 switch (rdev->config.rv770.max_tile_pipes) {
1321 case 1:
1322 default:
1323 gb_tiling_config = PIPE_TILING(0);
1324 break;
1325 case 2:
1326 gb_tiling_config = PIPE_TILING(1);
1327 break;
1328 case 4:
1329 gb_tiling_config = PIPE_TILING(2);
1330 break;
1331 case 8:
1332 gb_tiling_config = PIPE_TILING(3);
1333 break;
1334 }
1335 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
1336
1337 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK;
1338 tmp = 0;
1339 for (i = 0; i < rdev->config.rv770.max_backends; i++)
1340 tmp |= (1 << i);
1341 /* if all the backends are disabled, fix it up here */
1342 if ((disabled_rb_mask & tmp) == tmp) {
1343 for (i = 0; i < rdev->config.rv770.max_backends; i++)
1344 disabled_rb_mask &= ~(1 << i);
1345 }
1346 tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1347 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
1348 R7XX_MAX_BACKENDS, disabled_rb_mask);
1349 gb_tiling_config |= tmp << 16;
1350 rdev->config.rv770.backend_map = tmp;
1351
1352 if (rdev->family == CHIP_RV770)
1353 gb_tiling_config |= BANK_TILING(1);
1354 else {
1355 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
1356 gb_tiling_config |= BANK_TILING(1);
1357 else
1358 gb_tiling_config |= BANK_TILING(0);
1359 }
1360 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
1361 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1362 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
1363 gb_tiling_config |= ROW_TILING(3);
1364 gb_tiling_config |= SAMPLE_SPLIT(3);
1365 } else {
1366 gb_tiling_config |=
1367 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
1368 gb_tiling_config |=
1369 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
1370 }
1371
1372 gb_tiling_config |= BANK_SWAPS(1);
1373 rdev->config.rv770.tile_config = gb_tiling_config;
1374
1375 WREG32(GB_TILING_CONFIG, gb_tiling_config);
1376 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1377 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1378 WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
1379 WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
1380 if (rdev->family == CHIP_RV730) {
1381 WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff));
1382 WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff));
1383 WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff));
1384 }
1385
1386 WREG32(CGTS_SYS_TCC_DISABLE, 0);
1387 WREG32(CGTS_TCC_DISABLE, 0);
1388 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1389 WREG32(CGTS_USER_TCC_DISABLE, 0);
1390
1391
1392 num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1393 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
1394 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1395
1396 /* set HW defaults for 3D engine */
1397 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1398 ROQ_IB2_START(0x2b)));
1399
1400 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1401
1402 ta_aux_cntl = RREG32(TA_CNTL_AUX);
1403 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
1404
1405 sx_debug_1 = RREG32(SX_DEBUG_1);
1406 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1407 WREG32(SX_DEBUG_1, sx_debug_1);
1408
1409 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1410 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
1411 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
1412 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1413
1414 if (rdev->family != CHIP_RV740)
1415 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
1416 GS_FLUSH_CTL(4) |
1417 ACK_FLUSH_CTL(3) |
1418 SYNC_FLUSH_CTL));
1419
1420 if (rdev->family != CHIP_RV770)
1421 WREG32(SMX_SAR_CTL0, 0x00003f3f);
1422
1423 db_debug3 = RREG32(DB_DEBUG3);
1424 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
1425 switch (rdev->family) {
1426 case CHIP_RV770:
1427 case CHIP_RV740:
1428 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
1429 break;
1430 case CHIP_RV710:
1431 case CHIP_RV730:
1432 default:
1433 db_debug3 |= DB_CLK_OFF_DELAY(2);
1434 break;
1435 }
1436 WREG32(DB_DEBUG3, db_debug3);
1437
1438 if (rdev->family != CHIP_RV770) {
1439 db_debug4 = RREG32(DB_DEBUG4);
1440 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
1441 WREG32(DB_DEBUG4, db_debug4);
1442 }
1443
1444 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
1445 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
1446 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
1447
1448 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
1449 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
1450 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
1451
1452 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1453
1454 WREG32(VGT_NUM_INSTANCES, 1);
1455
1456 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1457
1458 WREG32(CP_PERFMON_CNTL, 0);
1459
1460 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
1461 DONE_FIFO_HIWATER(0xe0) |
1462 ALU_UPDATE_FIFO_HIWATER(0x8));
1463 switch (rdev->family) {
1464 case CHIP_RV770:
1465 case CHIP_RV730:
1466 case CHIP_RV710:
1467 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
1468 break;
1469 case CHIP_RV740:
1470 default:
1471 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
1472 break;
1473 }
1474 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1475
1476 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1477 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1478 */
1479 sq_config = RREG32(SQ_CONFIG);
1480 sq_config &= ~(PS_PRIO(3) |
1481 VS_PRIO(3) |
1482 GS_PRIO(3) |
1483 ES_PRIO(3));
1484 sq_config |= (DX9_CONSTS |
1485 VC_ENABLE |
1486 EXPORT_SRC_C |
1487 PS_PRIO(0) |
1488 VS_PRIO(1) |
1489 GS_PRIO(2) |
1490 ES_PRIO(3));
1491 if (rdev->family == CHIP_RV710)
1492 /* no vertex cache */
1493 sq_config &= ~VC_ENABLE;
1494
1495 WREG32(SQ_CONFIG, sq_config);
1496
1497 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
1498 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
1499 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
1500
1501 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
1502 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
1503
1504 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
1505 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
1506 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
1507 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
1508 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
1509 else
1510 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
1511 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1512
1513 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
1514 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
1515
1516 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
1517 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
1518
1519 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
1520 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
1521 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
1522 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
1523
1524 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1525 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1526 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1527 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1528 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1529 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1530 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1531 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1532
1533 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1534 FORCE_EOV_MAX_REZ_CNT(255)));
1535
1536 if (rdev->family == CHIP_RV710)
1537 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
1538 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
1539 else
1540 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
1541 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
1542
1543 switch (rdev->family) {
1544 case CHIP_RV770:
1545 case CHIP_RV730:
1546 case CHIP_RV740:
1547 gs_prim_buffer_depth = 384;
1548 break;
1549 case CHIP_RV710:
1550 gs_prim_buffer_depth = 128;
1551 break;
1552 default:
1553 break;
1554 }
1555
1556 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
1557 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1558 /* Max value for this is 256 */
1559 if (vgt_gs_per_es > 256)
1560 vgt_gs_per_es = 256;
1561
1562 WREG32(VGT_ES_PER_GS, 128);
1563 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
1564 WREG32(VGT_GS_PER_VS, 2);
1565
1566 /* more default values. 2D/3D driver should adjust as needed */
1567 WREG32(VGT_GS_VERTEX_REUSE, 16);
1568 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1569 WREG32(VGT_STRMOUT_EN, 0);
1570 WREG32(SX_MISC, 0);
1571 WREG32(PA_SC_MODE_CNTL, 0);
1572 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
1573 WREG32(PA_SC_AA_CONFIG, 0);
1574 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
1575 WREG32(PA_SC_LINE_STIPPLE, 0);
1576 WREG32(SPI_INPUT_Z, 0);
1577 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1578 WREG32(CB_COLOR7_FRAG, 0);
1579
1580 /* clear render buffer base addresses */
1581 WREG32(CB_COLOR0_BASE, 0);
1582 WREG32(CB_COLOR1_BASE, 0);
1583 WREG32(CB_COLOR2_BASE, 0);
1584 WREG32(CB_COLOR3_BASE, 0);
1585 WREG32(CB_COLOR4_BASE, 0);
1586 WREG32(CB_COLOR5_BASE, 0);
1587 WREG32(CB_COLOR6_BASE, 0);
1588 WREG32(CB_COLOR7_BASE, 0);
1589
1590 WREG32(TCP_CNTL, 0);
1591
1592 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1593 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1594
1595 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1596
1597 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1598 NUM_CLIP_SEQ(3)));
1599 WREG32(VC_ENHANCE, 0);
1600}
1601
1602void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1603{
1604 u64 size_bf, size_af;
1605
1606 if (mc->mc_vram_size > 0xE0000000) {
1607 /* leave room for at least 512M GTT */
1608 dev_warn(rdev->dev, "limiting VRAM\n");
1609 mc->real_vram_size = 0xE0000000;
1610 mc->mc_vram_size = 0xE0000000;
1611 }
1612 if (rdev->flags & RADEON_IS_AGP) {
1613 size_bf = mc->gtt_start;
1614 size_af = mc->mc_mask - mc->gtt_end;
1615 if (size_bf > size_af) {
1616 if (mc->mc_vram_size > size_bf) {
1617 dev_warn(rdev->dev, "limiting VRAM\n");
1618 mc->real_vram_size = size_bf;
1619 mc->mc_vram_size = size_bf;
1620 }
1621 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1622 } else {
1623 if (mc->mc_vram_size > size_af) {
1624 dev_warn(rdev->dev, "limiting VRAM\n");
1625 mc->real_vram_size = size_af;
1626 mc->mc_vram_size = size_af;
1627 }
1628 mc->vram_start = mc->gtt_end + 1;
1629 }
1630 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1631 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1632 mc->mc_vram_size >> 20, mc->vram_start,
1633 mc->vram_end, mc->real_vram_size >> 20);
1634 } else {
1635 radeon_vram_location(rdev, &rdev->mc, 0);
1636 rdev->mc.gtt_base_align = 0;
1637 radeon_gtt_location(rdev, mc);
1638 }
1639}
1640
1641static int rv770_mc_init(struct radeon_device *rdev)
1642{
1643 u32 tmp;
1644 int chansize, numchan;
1645
1646 /* Get VRAM informations */
1647 rdev->mc.vram_is_ddr = true;
1648 tmp = RREG32(MC_ARB_RAMCFG);
1649 if (tmp & CHANSIZE_OVERRIDE) {
1650 chansize = 16;
1651 } else if (tmp & CHANSIZE_MASK) {
1652 chansize = 64;
1653 } else {
1654 chansize = 32;
1655 }
1656 tmp = RREG32(MC_SHARED_CHMAP);
1657 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1658 case 0:
1659 default:
1660 numchan = 1;
1661 break;
1662 case 1:
1663 numchan = 2;
1664 break;
1665 case 2:
1666 numchan = 4;
1667 break;
1668 case 3:
1669 numchan = 8;
1670 break;
1671 }
1672 rdev->mc.vram_width = numchan * chansize;
1673 /* Could aper size report 0 ? */
1674 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1675 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1676 /* Setup GPU memory space */
1677 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1678 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1679 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1680 r700_vram_gtt_location(rdev, &rdev->mc);
1681 radeon_update_bandwidth_info(rdev);
1682
1683 return 0;
1684}
1685
1686static void rv770_uvd_init(struct radeon_device *rdev)
1687{
1688 int r;
1689
1690 if (!rdev->has_uvd)
1691 return;
1692
1693 r = radeon_uvd_init(rdev);
1694 if (r) {
1695 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
1696 /*
1697 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
1698 * to early fails uvd_v2_2_resume() and thus nothing happens
1699 * there. So it is pointless to try to go through that code
1700 * hence why we disable uvd here.
1701 */
1702 rdev->has_uvd = 0;
1703 return;
1704 }
1705 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
1706 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
1707}
1708
1709static void rv770_uvd_start(struct radeon_device *rdev)
1710{
1711 int r;
1712
1713 if (!rdev->has_uvd)
1714 return;
1715
1716 r = uvd_v2_2_resume(rdev);
1717 if (r) {
1718 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
1719 goto error;
1720 }
1721 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
1722 if (r) {
1723 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
1724 goto error;
1725 }
1726 return;
1727
1728error:
1729 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
1730}
1731
1732static void rv770_uvd_resume(struct radeon_device *rdev)
1733{
1734 struct radeon_ring *ring;
1735 int r;
1736
1737 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
1738 return;
1739
1740 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
1741 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
1742 if (r) {
1743 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
1744 return;
1745 }
1746 r = uvd_v1_0_init(rdev);
1747 if (r) {
1748 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
1749 return;
1750 }
1751}
1752
1753static int rv770_startup(struct radeon_device *rdev)
1754{
1755 struct radeon_ring *ring;
1756 int r;
1757
1758 /* enable pcie gen2 link */
1759 rv770_pcie_gen2_enable(rdev);
1760
1761 /* scratch needs to be initialized before MC */
1762 r = r600_vram_scratch_init(rdev);
1763 if (r)
1764 return r;
1765
1766 rv770_mc_program(rdev);
1767
1768 if (rdev->flags & RADEON_IS_AGP) {
1769 rv770_agp_enable(rdev);
1770 } else {
1771 r = rv770_pcie_gart_enable(rdev);
1772 if (r)
1773 return r;
1774 }
1775
1776 rv770_gpu_init(rdev);
1777
1778 /* allocate wb buffer */
1779 r = radeon_wb_init(rdev);
1780 if (r)
1781 return r;
1782
1783 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1784 if (r) {
1785 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1786 return r;
1787 }
1788
1789 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
1790 if (r) {
1791 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1792 return r;
1793 }
1794
1795 rv770_uvd_start(rdev);
1796
1797 /* Enable IRQ */
1798 if (!rdev->irq.installed) {
1799 r = radeon_irq_kms_init(rdev);
1800 if (r)
1801 return r;
1802 }
1803
1804 r = r600_irq_init(rdev);
1805 if (r) {
1806 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1807 radeon_irq_kms_fini(rdev);
1808 return r;
1809 }
1810 r600_irq_set(rdev);
1811
1812 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1813 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1814 RADEON_CP_PACKET2);
1815 if (r)
1816 return r;
1817
1818 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1819 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1820 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1821 if (r)
1822 return r;
1823
1824 r = rv770_cp_load_microcode(rdev);
1825 if (r)
1826 return r;
1827 r = r600_cp_resume(rdev);
1828 if (r)
1829 return r;
1830
1831 r = r600_dma_resume(rdev);
1832 if (r)
1833 return r;
1834
1835 rv770_uvd_resume(rdev);
1836
1837 r = radeon_ib_pool_init(rdev);
1838 if (r) {
1839 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1840 return r;
1841 }
1842
1843 r = radeon_audio_init(rdev);
1844 if (r) {
1845 DRM_ERROR("radeon: audio init failed\n");
1846 return r;
1847 }
1848
1849 return 0;
1850}
1851
1852int rv770_resume(struct radeon_device *rdev)
1853{
1854 int r;
1855
1856 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1857 * posting will perform necessary task to bring back GPU into good
1858 * shape.
1859 */
1860 /* post card */
1861 atom_asic_init(rdev->mode_info.atom_context);
1862
1863 /* init golden registers */
1864 rv770_init_golden_registers(rdev);
1865
1866 if (rdev->pm.pm_method == PM_METHOD_DPM)
1867 radeon_pm_resume(rdev);
1868
1869 rdev->accel_working = true;
1870 r = rv770_startup(rdev);
1871 if (r) {
1872 DRM_ERROR("r600 startup failed on resume\n");
1873 rdev->accel_working = false;
1874 return r;
1875 }
1876
1877 return r;
1878
1879}
1880
1881int rv770_suspend(struct radeon_device *rdev)
1882{
1883 radeon_pm_suspend(rdev);
1884 radeon_audio_fini(rdev);
1885 if (rdev->has_uvd) {
1886 uvd_v1_0_fini(rdev);
1887 radeon_uvd_suspend(rdev);
1888 }
1889 r700_cp_stop(rdev);
1890 r600_dma_stop(rdev);
1891 r600_irq_suspend(rdev);
1892 radeon_wb_disable(rdev);
1893 rv770_pcie_gart_disable(rdev);
1894
1895 return 0;
1896}
1897
1898/* Plan is to move initialization in that function and use
1899 * helper function so that radeon_device_init pretty much
1900 * do nothing more than calling asic specific function. This
1901 * should also allow to remove a bunch of callback function
1902 * like vram_info.
1903 */
1904int rv770_init(struct radeon_device *rdev)
1905{
1906 int r;
1907
1908 /* Read BIOS */
1909 if (!radeon_get_bios(rdev)) {
1910 if (ASIC_IS_AVIVO(rdev))
1911 return -EINVAL;
1912 }
1913 /* Must be an ATOMBIOS */
1914 if (!rdev->is_atom_bios) {
1915 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1916 return -EINVAL;
1917 }
1918 r = radeon_atombios_init(rdev);
1919 if (r)
1920 return r;
1921 /* Post card if necessary */
1922 if (!radeon_card_posted(rdev)) {
1923 if (!rdev->bios) {
1924 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1925 return -EINVAL;
1926 }
1927 DRM_INFO("GPU not posted. posting now...\n");
1928 atom_asic_init(rdev->mode_info.atom_context);
1929 }
1930 /* init golden registers */
1931 rv770_init_golden_registers(rdev);
1932 /* Initialize scratch registers */
1933 r600_scratch_init(rdev);
1934 /* Initialize surface registers */
1935 radeon_surface_init(rdev);
1936 /* Initialize clocks */
1937 radeon_get_clock_info(rdev->ddev);
1938 /* Fence driver */
1939 r = radeon_fence_driver_init(rdev);
1940 if (r)
1941 return r;
1942 /* initialize AGP */
1943 if (rdev->flags & RADEON_IS_AGP) {
1944 r = radeon_agp_init(rdev);
1945 if (r)
1946 radeon_agp_disable(rdev);
1947 }
1948 r = rv770_mc_init(rdev);
1949 if (r)
1950 return r;
1951 /* Memory manager */
1952 r = radeon_bo_init(rdev);
1953 if (r)
1954 return r;
1955
1956 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1957 r = r600_init_microcode(rdev);
1958 if (r) {
1959 DRM_ERROR("Failed to load firmware!\n");
1960 return r;
1961 }
1962 }
1963
1964 /* Initialize power management */
1965 radeon_pm_init(rdev);
1966
1967 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
1968 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
1969
1970 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
1971 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
1972
1973 rv770_uvd_init(rdev);
1974
1975 rdev->ih.ring_obj = NULL;
1976 r600_ih_ring_init(rdev, 64 * 1024);
1977
1978 r = r600_pcie_gart_init(rdev);
1979 if (r)
1980 return r;
1981
1982 rdev->accel_working = true;
1983 r = rv770_startup(rdev);
1984 if (r) {
1985 dev_err(rdev->dev, "disabling GPU acceleration\n");
1986 r700_cp_fini(rdev);
1987 r600_dma_fini(rdev);
1988 r600_irq_fini(rdev);
1989 radeon_wb_fini(rdev);
1990 radeon_ib_pool_fini(rdev);
1991 radeon_irq_kms_fini(rdev);
1992 rv770_pcie_gart_fini(rdev);
1993 rdev->accel_working = false;
1994 }
1995
1996 return 0;
1997}
1998
1999void rv770_fini(struct radeon_device *rdev)
2000{
2001 radeon_pm_fini(rdev);
2002 r700_cp_fini(rdev);
2003 r600_dma_fini(rdev);
2004 r600_irq_fini(rdev);
2005 radeon_wb_fini(rdev);
2006 radeon_ib_pool_fini(rdev);
2007 radeon_irq_kms_fini(rdev);
2008 uvd_v1_0_fini(rdev);
2009 radeon_uvd_fini(rdev);
2010 rv770_pcie_gart_fini(rdev);
2011 r600_vram_scratch_fini(rdev);
2012 radeon_gem_fini(rdev);
2013 radeon_fence_driver_fini(rdev);
2014 radeon_agp_fini(rdev);
2015 radeon_bo_fini(rdev);
2016 radeon_atombios_fini(rdev);
2017 kfree(rdev->bios);
2018 rdev->bios = NULL;
2019}
2020
2021static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
2022{
2023 u32 link_width_cntl, lanes, speed_cntl, tmp;
2024 u16 link_cntl2;
2025
2026 if (radeon_pcie_gen2 == 0)
2027 return;
2028
2029 if (rdev->flags & RADEON_IS_IGP)
2030 return;
2031
2032 if (!(rdev->flags & RADEON_IS_PCIE))
2033 return;
2034
2035 /* x2 cards have a special sequence */
2036 if (ASIC_IS_X2(rdev))
2037 return;
2038
2039 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
2040 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
2041 return;
2042
2043 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
2044
2045 /* advertise upconfig capability */
2046 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2047 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
2048 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2049 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2050 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
2051 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
2052 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
2053 LC_RECONFIG_ARC_MISSING_ESCAPE);
2054 link_width_cntl |= lanes | LC_RECONFIG_NOW |
2055 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
2056 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2057 } else {
2058 link_width_cntl |= LC_UPCONFIGURE_DIS;
2059 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2060 }
2061
2062 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2063 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
2064 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
2065
2066 tmp = RREG32(0x541c);
2067 WREG32(0x541c, tmp | 0x8);
2068 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
2069 link_cntl2 = RREG16(0x4088);
2070 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
2071 link_cntl2 |= 0x2;
2072 WREG16(0x4088, link_cntl2);
2073 WREG32(MM_CFGREGS_CNTL, 0);
2074
2075 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2076 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
2077 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2078
2079 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2080 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
2081 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2082
2083 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2084 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
2085 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2086
2087 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2088 speed_cntl |= LC_GEN2_EN_STRAP;
2089 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2090
2091 } else {
2092 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2093 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
2094 if (1)
2095 link_width_cntl |= LC_UPCONFIGURE_DIS;
2096 else
2097 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
2098 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2099 }
2100}