Loading...
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/firmware.h>
29#include <linux/platform_device.h>
30#include <linux/slab.h>
31#include "drmP.h"
32#include "radeon.h"
33#include "radeon_asic.h"
34#include "radeon_drm.h"
35#include "rv770d.h"
36#include "atom.h"
37#include "avivod.h"
38
39#define R700_PFP_UCODE_SIZE 848
40#define R700_PM4_UCODE_SIZE 1360
41
42static void rv770_gpu_init(struct radeon_device *rdev);
43void rv770_fini(struct radeon_device *rdev);
44static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
45
46u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
47{
48 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
49 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
50
51 /* Lock the graphics update lock */
52 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
53 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
54
55 /* update the scanout addresses */
56 if (radeon_crtc->crtc_id) {
57 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
58 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
59 } else {
60 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
61 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
62 }
63 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
64 (u32)crtc_base);
65 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
66 (u32)crtc_base);
67
68 /* Wait for update_pending to go high. */
69 while (!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING));
70 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
71
72 /* Unlock the lock, so double-buffering can take place inside vblank */
73 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
74 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
75
76 /* Return current update_pending status: */
77 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
78}
79
80/* get temperature in millidegrees */
81int rv770_get_temp(struct radeon_device *rdev)
82{
83 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
84 ASIC_T_SHIFT;
85 int actual_temp;
86
87 if (temp & 0x400)
88 actual_temp = -256;
89 else if (temp & 0x200)
90 actual_temp = 255;
91 else if (temp & 0x100) {
92 actual_temp = temp & 0x1ff;
93 actual_temp |= ~0x1ff;
94 } else
95 actual_temp = temp & 0xff;
96
97 return (actual_temp * 1000) / 2;
98}
99
100void rv770_pm_misc(struct radeon_device *rdev)
101{
102 int req_ps_idx = rdev->pm.requested_power_state_index;
103 int req_cm_idx = rdev->pm.requested_clock_mode_index;
104 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
105 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
106
107 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
108 /* 0xff01 is a flag rather then an actual voltage */
109 if (voltage->voltage == 0xff01)
110 return;
111 if (voltage->voltage != rdev->pm.current_vddc) {
112 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
113 rdev->pm.current_vddc = voltage->voltage;
114 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
115 }
116 }
117}
118
119/*
120 * GART
121 */
122int rv770_pcie_gart_enable(struct radeon_device *rdev)
123{
124 u32 tmp;
125 int r, i;
126
127 if (rdev->gart.table.vram.robj == NULL) {
128 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
129 return -EINVAL;
130 }
131 r = radeon_gart_table_vram_pin(rdev);
132 if (r)
133 return r;
134 radeon_gart_restore(rdev);
135 /* Setup L2 cache */
136 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
137 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
138 EFFECTIVE_L2_QUEUE_SIZE(7));
139 WREG32(VM_L2_CNTL2, 0);
140 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
141 /* Setup TLB control */
142 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
143 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
144 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
145 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
146 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
147 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
148 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
149 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
150 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
151 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
152 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
153 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
154 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
155 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
156 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
157 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
158 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
159 (u32)(rdev->dummy_page.addr >> 12));
160 for (i = 1; i < 7; i++)
161 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
162
163 r600_pcie_gart_tlb_flush(rdev);
164 rdev->gart.ready = true;
165 return 0;
166}
167
168void rv770_pcie_gart_disable(struct radeon_device *rdev)
169{
170 u32 tmp;
171 int i, r;
172
173 /* Disable all tables */
174 for (i = 0; i < 7; i++)
175 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
176
177 /* Setup L2 cache */
178 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
179 EFFECTIVE_L2_QUEUE_SIZE(7));
180 WREG32(VM_L2_CNTL2, 0);
181 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
182 /* Setup TLB control */
183 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
184 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
185 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
186 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
187 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
188 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
189 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
190 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
191 if (rdev->gart.table.vram.robj) {
192 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
193 if (likely(r == 0)) {
194 radeon_bo_kunmap(rdev->gart.table.vram.robj);
195 radeon_bo_unpin(rdev->gart.table.vram.robj);
196 radeon_bo_unreserve(rdev->gart.table.vram.robj);
197 }
198 }
199}
200
201void rv770_pcie_gart_fini(struct radeon_device *rdev)
202{
203 radeon_gart_fini(rdev);
204 rv770_pcie_gart_disable(rdev);
205 radeon_gart_table_vram_free(rdev);
206}
207
208
209void rv770_agp_enable(struct radeon_device *rdev)
210{
211 u32 tmp;
212 int i;
213
214 /* Setup L2 cache */
215 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
216 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
217 EFFECTIVE_L2_QUEUE_SIZE(7));
218 WREG32(VM_L2_CNTL2, 0);
219 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
220 /* Setup TLB control */
221 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
222 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
223 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
224 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
225 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
226 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
227 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
228 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
229 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
230 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
231 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
232 for (i = 0; i < 7; i++)
233 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
234}
235
236static void rv770_mc_program(struct radeon_device *rdev)
237{
238 struct rv515_mc_save save;
239 u32 tmp;
240 int i, j;
241
242 /* Initialize HDP */
243 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
244 WREG32((0x2c14 + j), 0x00000000);
245 WREG32((0x2c18 + j), 0x00000000);
246 WREG32((0x2c1c + j), 0x00000000);
247 WREG32((0x2c20 + j), 0x00000000);
248 WREG32((0x2c24 + j), 0x00000000);
249 }
250 /* r7xx hw bug. Read from HDP_DEBUG1 rather
251 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
252 */
253 tmp = RREG32(HDP_DEBUG1);
254
255 rv515_mc_stop(rdev, &save);
256 if (r600_mc_wait_for_idle(rdev)) {
257 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
258 }
259 /* Lockout access through VGA aperture*/
260 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
261 /* Update configuration */
262 if (rdev->flags & RADEON_IS_AGP) {
263 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
264 /* VRAM before AGP */
265 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
266 rdev->mc.vram_start >> 12);
267 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
268 rdev->mc.gtt_end >> 12);
269 } else {
270 /* VRAM after AGP */
271 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
272 rdev->mc.gtt_start >> 12);
273 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
274 rdev->mc.vram_end >> 12);
275 }
276 } else {
277 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
278 rdev->mc.vram_start >> 12);
279 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
280 rdev->mc.vram_end >> 12);
281 }
282 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
283 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
284 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
285 WREG32(MC_VM_FB_LOCATION, tmp);
286 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
287 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
288 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
289 if (rdev->flags & RADEON_IS_AGP) {
290 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
291 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
292 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
293 } else {
294 WREG32(MC_VM_AGP_BASE, 0);
295 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
296 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
297 }
298 if (r600_mc_wait_for_idle(rdev)) {
299 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
300 }
301 rv515_mc_resume(rdev, &save);
302 /* we need to own VRAM, so turn off the VGA renderer here
303 * to stop it overwriting our objects */
304 rv515_vga_render_disable(rdev);
305}
306
307
308/*
309 * CP.
310 */
311void r700_cp_stop(struct radeon_device *rdev)
312{
313 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
314 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
315 WREG32(SCRATCH_UMSK, 0);
316}
317
318static int rv770_cp_load_microcode(struct radeon_device *rdev)
319{
320 const __be32 *fw_data;
321 int i;
322
323 if (!rdev->me_fw || !rdev->pfp_fw)
324 return -EINVAL;
325
326 r700_cp_stop(rdev);
327 WREG32(CP_RB_CNTL,
328#ifdef __BIG_ENDIAN
329 BUF_SWAP_32BIT |
330#endif
331 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
332
333 /* Reset cp */
334 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
335 RREG32(GRBM_SOFT_RESET);
336 mdelay(15);
337 WREG32(GRBM_SOFT_RESET, 0);
338
339 fw_data = (const __be32 *)rdev->pfp_fw->data;
340 WREG32(CP_PFP_UCODE_ADDR, 0);
341 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
342 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
343 WREG32(CP_PFP_UCODE_ADDR, 0);
344
345 fw_data = (const __be32 *)rdev->me_fw->data;
346 WREG32(CP_ME_RAM_WADDR, 0);
347 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
348 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
349
350 WREG32(CP_PFP_UCODE_ADDR, 0);
351 WREG32(CP_ME_RAM_WADDR, 0);
352 WREG32(CP_ME_RAM_RADDR, 0);
353 return 0;
354}
355
356void r700_cp_fini(struct radeon_device *rdev)
357{
358 r700_cp_stop(rdev);
359 radeon_ring_fini(rdev);
360}
361
362/*
363 * Core functions
364 */
365static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
366 u32 num_tile_pipes,
367 u32 num_backends,
368 u32 backend_disable_mask)
369{
370 u32 backend_map = 0;
371 u32 enabled_backends_mask;
372 u32 enabled_backends_count;
373 u32 cur_pipe;
374 u32 swizzle_pipe[R7XX_MAX_PIPES];
375 u32 cur_backend;
376 u32 i;
377 bool force_no_swizzle;
378
379 if (num_tile_pipes > R7XX_MAX_PIPES)
380 num_tile_pipes = R7XX_MAX_PIPES;
381 if (num_tile_pipes < 1)
382 num_tile_pipes = 1;
383 if (num_backends > R7XX_MAX_BACKENDS)
384 num_backends = R7XX_MAX_BACKENDS;
385 if (num_backends < 1)
386 num_backends = 1;
387
388 enabled_backends_mask = 0;
389 enabled_backends_count = 0;
390 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
391 if (((backend_disable_mask >> i) & 1) == 0) {
392 enabled_backends_mask |= (1 << i);
393 ++enabled_backends_count;
394 }
395 if (enabled_backends_count == num_backends)
396 break;
397 }
398
399 if (enabled_backends_count == 0) {
400 enabled_backends_mask = 1;
401 enabled_backends_count = 1;
402 }
403
404 if (enabled_backends_count != num_backends)
405 num_backends = enabled_backends_count;
406
407 switch (rdev->family) {
408 case CHIP_RV770:
409 case CHIP_RV730:
410 force_no_swizzle = false;
411 break;
412 case CHIP_RV710:
413 case CHIP_RV740:
414 default:
415 force_no_swizzle = true;
416 break;
417 }
418
419 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
420 switch (num_tile_pipes) {
421 case 1:
422 swizzle_pipe[0] = 0;
423 break;
424 case 2:
425 swizzle_pipe[0] = 0;
426 swizzle_pipe[1] = 1;
427 break;
428 case 3:
429 if (force_no_swizzle) {
430 swizzle_pipe[0] = 0;
431 swizzle_pipe[1] = 1;
432 swizzle_pipe[2] = 2;
433 } else {
434 swizzle_pipe[0] = 0;
435 swizzle_pipe[1] = 2;
436 swizzle_pipe[2] = 1;
437 }
438 break;
439 case 4:
440 if (force_no_swizzle) {
441 swizzle_pipe[0] = 0;
442 swizzle_pipe[1] = 1;
443 swizzle_pipe[2] = 2;
444 swizzle_pipe[3] = 3;
445 } else {
446 swizzle_pipe[0] = 0;
447 swizzle_pipe[1] = 2;
448 swizzle_pipe[2] = 3;
449 swizzle_pipe[3] = 1;
450 }
451 break;
452 case 5:
453 if (force_no_swizzle) {
454 swizzle_pipe[0] = 0;
455 swizzle_pipe[1] = 1;
456 swizzle_pipe[2] = 2;
457 swizzle_pipe[3] = 3;
458 swizzle_pipe[4] = 4;
459 } else {
460 swizzle_pipe[0] = 0;
461 swizzle_pipe[1] = 2;
462 swizzle_pipe[2] = 4;
463 swizzle_pipe[3] = 1;
464 swizzle_pipe[4] = 3;
465 }
466 break;
467 case 6:
468 if (force_no_swizzle) {
469 swizzle_pipe[0] = 0;
470 swizzle_pipe[1] = 1;
471 swizzle_pipe[2] = 2;
472 swizzle_pipe[3] = 3;
473 swizzle_pipe[4] = 4;
474 swizzle_pipe[5] = 5;
475 } else {
476 swizzle_pipe[0] = 0;
477 swizzle_pipe[1] = 2;
478 swizzle_pipe[2] = 4;
479 swizzle_pipe[3] = 5;
480 swizzle_pipe[4] = 3;
481 swizzle_pipe[5] = 1;
482 }
483 break;
484 case 7:
485 if (force_no_swizzle) {
486 swizzle_pipe[0] = 0;
487 swizzle_pipe[1] = 1;
488 swizzle_pipe[2] = 2;
489 swizzle_pipe[3] = 3;
490 swizzle_pipe[4] = 4;
491 swizzle_pipe[5] = 5;
492 swizzle_pipe[6] = 6;
493 } else {
494 swizzle_pipe[0] = 0;
495 swizzle_pipe[1] = 2;
496 swizzle_pipe[2] = 4;
497 swizzle_pipe[3] = 6;
498 swizzle_pipe[4] = 3;
499 swizzle_pipe[5] = 1;
500 swizzle_pipe[6] = 5;
501 }
502 break;
503 case 8:
504 if (force_no_swizzle) {
505 swizzle_pipe[0] = 0;
506 swizzle_pipe[1] = 1;
507 swizzle_pipe[2] = 2;
508 swizzle_pipe[3] = 3;
509 swizzle_pipe[4] = 4;
510 swizzle_pipe[5] = 5;
511 swizzle_pipe[6] = 6;
512 swizzle_pipe[7] = 7;
513 } else {
514 swizzle_pipe[0] = 0;
515 swizzle_pipe[1] = 2;
516 swizzle_pipe[2] = 4;
517 swizzle_pipe[3] = 6;
518 swizzle_pipe[4] = 3;
519 swizzle_pipe[5] = 1;
520 swizzle_pipe[6] = 7;
521 swizzle_pipe[7] = 5;
522 }
523 break;
524 }
525
526 cur_backend = 0;
527 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
528 while (((1 << cur_backend) & enabled_backends_mask) == 0)
529 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
530
531 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
532
533 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
534 }
535
536 return backend_map;
537}
538
539static void rv770_gpu_init(struct radeon_device *rdev)
540{
541 int i, j, num_qd_pipes;
542 u32 ta_aux_cntl;
543 u32 sx_debug_1;
544 u32 smx_dc_ctl0;
545 u32 db_debug3;
546 u32 num_gs_verts_per_thread;
547 u32 vgt_gs_per_es;
548 u32 gs_prim_buffer_depth = 0;
549 u32 sq_ms_fifo_sizes;
550 u32 sq_config;
551 u32 sq_thread_resource_mgmt;
552 u32 hdp_host_path_cntl;
553 u32 sq_dyn_gpr_size_simd_ab_0;
554 u32 backend_map;
555 u32 gb_tiling_config = 0;
556 u32 cc_rb_backend_disable = 0;
557 u32 cc_gc_shader_pipe_config = 0;
558 u32 mc_arb_ramcfg;
559 u32 db_debug4;
560
561 /* setup chip specs */
562 switch (rdev->family) {
563 case CHIP_RV770:
564 rdev->config.rv770.max_pipes = 4;
565 rdev->config.rv770.max_tile_pipes = 8;
566 rdev->config.rv770.max_simds = 10;
567 rdev->config.rv770.max_backends = 4;
568 rdev->config.rv770.max_gprs = 256;
569 rdev->config.rv770.max_threads = 248;
570 rdev->config.rv770.max_stack_entries = 512;
571 rdev->config.rv770.max_hw_contexts = 8;
572 rdev->config.rv770.max_gs_threads = 16 * 2;
573 rdev->config.rv770.sx_max_export_size = 128;
574 rdev->config.rv770.sx_max_export_pos_size = 16;
575 rdev->config.rv770.sx_max_export_smx_size = 112;
576 rdev->config.rv770.sq_num_cf_insts = 2;
577
578 rdev->config.rv770.sx_num_of_sets = 7;
579 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
580 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
581 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
582 break;
583 case CHIP_RV730:
584 rdev->config.rv770.max_pipes = 2;
585 rdev->config.rv770.max_tile_pipes = 4;
586 rdev->config.rv770.max_simds = 8;
587 rdev->config.rv770.max_backends = 2;
588 rdev->config.rv770.max_gprs = 128;
589 rdev->config.rv770.max_threads = 248;
590 rdev->config.rv770.max_stack_entries = 256;
591 rdev->config.rv770.max_hw_contexts = 8;
592 rdev->config.rv770.max_gs_threads = 16 * 2;
593 rdev->config.rv770.sx_max_export_size = 256;
594 rdev->config.rv770.sx_max_export_pos_size = 32;
595 rdev->config.rv770.sx_max_export_smx_size = 224;
596 rdev->config.rv770.sq_num_cf_insts = 2;
597
598 rdev->config.rv770.sx_num_of_sets = 7;
599 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
600 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
601 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
602 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
603 rdev->config.rv770.sx_max_export_pos_size -= 16;
604 rdev->config.rv770.sx_max_export_smx_size += 16;
605 }
606 break;
607 case CHIP_RV710:
608 rdev->config.rv770.max_pipes = 2;
609 rdev->config.rv770.max_tile_pipes = 2;
610 rdev->config.rv770.max_simds = 2;
611 rdev->config.rv770.max_backends = 1;
612 rdev->config.rv770.max_gprs = 256;
613 rdev->config.rv770.max_threads = 192;
614 rdev->config.rv770.max_stack_entries = 256;
615 rdev->config.rv770.max_hw_contexts = 4;
616 rdev->config.rv770.max_gs_threads = 8 * 2;
617 rdev->config.rv770.sx_max_export_size = 128;
618 rdev->config.rv770.sx_max_export_pos_size = 16;
619 rdev->config.rv770.sx_max_export_smx_size = 112;
620 rdev->config.rv770.sq_num_cf_insts = 1;
621
622 rdev->config.rv770.sx_num_of_sets = 7;
623 rdev->config.rv770.sc_prim_fifo_size = 0x40;
624 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
625 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
626 break;
627 case CHIP_RV740:
628 rdev->config.rv770.max_pipes = 4;
629 rdev->config.rv770.max_tile_pipes = 4;
630 rdev->config.rv770.max_simds = 8;
631 rdev->config.rv770.max_backends = 4;
632 rdev->config.rv770.max_gprs = 256;
633 rdev->config.rv770.max_threads = 248;
634 rdev->config.rv770.max_stack_entries = 512;
635 rdev->config.rv770.max_hw_contexts = 8;
636 rdev->config.rv770.max_gs_threads = 16 * 2;
637 rdev->config.rv770.sx_max_export_size = 256;
638 rdev->config.rv770.sx_max_export_pos_size = 32;
639 rdev->config.rv770.sx_max_export_smx_size = 224;
640 rdev->config.rv770.sq_num_cf_insts = 2;
641
642 rdev->config.rv770.sx_num_of_sets = 7;
643 rdev->config.rv770.sc_prim_fifo_size = 0x100;
644 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
645 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
646
647 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
648 rdev->config.rv770.sx_max_export_pos_size -= 16;
649 rdev->config.rv770.sx_max_export_smx_size += 16;
650 }
651 break;
652 default:
653 break;
654 }
655
656 /* Initialize HDP */
657 j = 0;
658 for (i = 0; i < 32; i++) {
659 WREG32((0x2c14 + j), 0x00000000);
660 WREG32((0x2c18 + j), 0x00000000);
661 WREG32((0x2c1c + j), 0x00000000);
662 WREG32((0x2c20 + j), 0x00000000);
663 WREG32((0x2c24 + j), 0x00000000);
664 j += 0x18;
665 }
666
667 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
668
669 /* setup tiling, simd, pipe config */
670 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
671
672 switch (rdev->config.rv770.max_tile_pipes) {
673 case 1:
674 default:
675 gb_tiling_config |= PIPE_TILING(0);
676 break;
677 case 2:
678 gb_tiling_config |= PIPE_TILING(1);
679 break;
680 case 4:
681 gb_tiling_config |= PIPE_TILING(2);
682 break;
683 case 8:
684 gb_tiling_config |= PIPE_TILING(3);
685 break;
686 }
687 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
688
689 if (rdev->family == CHIP_RV770)
690 gb_tiling_config |= BANK_TILING(1);
691 else
692 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
693 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
694 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
695 if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
696 rdev->config.rv770.tiling_group_size = 512;
697 else
698 rdev->config.rv770.tiling_group_size = 256;
699 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
700 gb_tiling_config |= ROW_TILING(3);
701 gb_tiling_config |= SAMPLE_SPLIT(3);
702 } else {
703 gb_tiling_config |=
704 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
705 gb_tiling_config |=
706 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
707 }
708
709 gb_tiling_config |= BANK_SWAPS(1);
710
711 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
712 cc_rb_backend_disable |=
713 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
714
715 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
716 cc_gc_shader_pipe_config |=
717 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
718 cc_gc_shader_pipe_config |=
719 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
720
721 if (rdev->family == CHIP_RV740)
722 backend_map = 0x28;
723 else
724 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
725 rdev->config.rv770.max_tile_pipes,
726 (R7XX_MAX_BACKENDS -
727 r600_count_pipe_bits((cc_rb_backend_disable &
728 R7XX_MAX_BACKENDS_MASK) >> 16)),
729 (cc_rb_backend_disable >> 16));
730
731 rdev->config.rv770.tile_config = gb_tiling_config;
732 rdev->config.rv770.backend_map = backend_map;
733 gb_tiling_config |= BACKEND_MAP(backend_map);
734
735 WREG32(GB_TILING_CONFIG, gb_tiling_config);
736 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
737 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
738
739 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
740 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
741 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
742 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
743
744 WREG32(CGTS_SYS_TCC_DISABLE, 0);
745 WREG32(CGTS_TCC_DISABLE, 0);
746 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
747 WREG32(CGTS_USER_TCC_DISABLE, 0);
748
749 num_qd_pipes =
750 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
751 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
752 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
753
754 /* set HW defaults for 3D engine */
755 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
756 ROQ_IB2_START(0x2b)));
757
758 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
759
760 ta_aux_cntl = RREG32(TA_CNTL_AUX);
761 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
762
763 sx_debug_1 = RREG32(SX_DEBUG_1);
764 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
765 WREG32(SX_DEBUG_1, sx_debug_1);
766
767 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
768 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
769 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
770 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
771
772 if (rdev->family != CHIP_RV740)
773 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
774 GS_FLUSH_CTL(4) |
775 ACK_FLUSH_CTL(3) |
776 SYNC_FLUSH_CTL));
777
778 db_debug3 = RREG32(DB_DEBUG3);
779 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
780 switch (rdev->family) {
781 case CHIP_RV770:
782 case CHIP_RV740:
783 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
784 break;
785 case CHIP_RV710:
786 case CHIP_RV730:
787 default:
788 db_debug3 |= DB_CLK_OFF_DELAY(2);
789 break;
790 }
791 WREG32(DB_DEBUG3, db_debug3);
792
793 if (rdev->family != CHIP_RV770) {
794 db_debug4 = RREG32(DB_DEBUG4);
795 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
796 WREG32(DB_DEBUG4, db_debug4);
797 }
798
799 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
800 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
801 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
802
803 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
804 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
805 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
806
807 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
808
809 WREG32(VGT_NUM_INSTANCES, 1);
810
811 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
812
813 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
814
815 WREG32(CP_PERFMON_CNTL, 0);
816
817 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
818 DONE_FIFO_HIWATER(0xe0) |
819 ALU_UPDATE_FIFO_HIWATER(0x8));
820 switch (rdev->family) {
821 case CHIP_RV770:
822 case CHIP_RV730:
823 case CHIP_RV710:
824 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
825 break;
826 case CHIP_RV740:
827 default:
828 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
829 break;
830 }
831 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
832
833 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
834 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
835 */
836 sq_config = RREG32(SQ_CONFIG);
837 sq_config &= ~(PS_PRIO(3) |
838 VS_PRIO(3) |
839 GS_PRIO(3) |
840 ES_PRIO(3));
841 sq_config |= (DX9_CONSTS |
842 VC_ENABLE |
843 EXPORT_SRC_C |
844 PS_PRIO(0) |
845 VS_PRIO(1) |
846 GS_PRIO(2) |
847 ES_PRIO(3));
848 if (rdev->family == CHIP_RV710)
849 /* no vertex cache */
850 sq_config &= ~VC_ENABLE;
851
852 WREG32(SQ_CONFIG, sq_config);
853
854 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
855 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
856 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
857
858 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
859 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
860
861 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
862 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
863 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
864 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
865 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
866 else
867 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
868 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
869
870 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
871 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
872
873 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
874 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
875
876 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
877 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
878 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
879 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
880
881 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
882 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
883 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
884 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
885 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
886 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
887 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
888 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
889
890 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
891 FORCE_EOV_MAX_REZ_CNT(255)));
892
893 if (rdev->family == CHIP_RV710)
894 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
895 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
896 else
897 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
898 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
899
900 switch (rdev->family) {
901 case CHIP_RV770:
902 case CHIP_RV730:
903 case CHIP_RV740:
904 gs_prim_buffer_depth = 384;
905 break;
906 case CHIP_RV710:
907 gs_prim_buffer_depth = 128;
908 break;
909 default:
910 break;
911 }
912
913 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
914 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
915 /* Max value for this is 256 */
916 if (vgt_gs_per_es > 256)
917 vgt_gs_per_es = 256;
918
919 WREG32(VGT_ES_PER_GS, 128);
920 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
921 WREG32(VGT_GS_PER_VS, 2);
922
923 /* more default values. 2D/3D driver should adjust as needed */
924 WREG32(VGT_GS_VERTEX_REUSE, 16);
925 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
926 WREG32(VGT_STRMOUT_EN, 0);
927 WREG32(SX_MISC, 0);
928 WREG32(PA_SC_MODE_CNTL, 0);
929 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
930 WREG32(PA_SC_AA_CONFIG, 0);
931 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
932 WREG32(PA_SC_LINE_STIPPLE, 0);
933 WREG32(SPI_INPUT_Z, 0);
934 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
935 WREG32(CB_COLOR7_FRAG, 0);
936
937 /* clear render buffer base addresses */
938 WREG32(CB_COLOR0_BASE, 0);
939 WREG32(CB_COLOR1_BASE, 0);
940 WREG32(CB_COLOR2_BASE, 0);
941 WREG32(CB_COLOR3_BASE, 0);
942 WREG32(CB_COLOR4_BASE, 0);
943 WREG32(CB_COLOR5_BASE, 0);
944 WREG32(CB_COLOR6_BASE, 0);
945 WREG32(CB_COLOR7_BASE, 0);
946
947 WREG32(TCP_CNTL, 0);
948
949 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
950 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
951
952 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
953
954 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
955 NUM_CLIP_SEQ(3)));
956
957}
958
959static int rv770_vram_scratch_init(struct radeon_device *rdev)
960{
961 int r;
962 u64 gpu_addr;
963
964 if (rdev->vram_scratch.robj == NULL) {
965 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
966 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
967 &rdev->vram_scratch.robj);
968 if (r) {
969 return r;
970 }
971 }
972
973 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
974 if (unlikely(r != 0))
975 return r;
976 r = radeon_bo_pin(rdev->vram_scratch.robj,
977 RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
978 if (r) {
979 radeon_bo_unreserve(rdev->vram_scratch.robj);
980 return r;
981 }
982 r = radeon_bo_kmap(rdev->vram_scratch.robj,
983 (void **)&rdev->vram_scratch.ptr);
984 if (r)
985 radeon_bo_unpin(rdev->vram_scratch.robj);
986 radeon_bo_unreserve(rdev->vram_scratch.robj);
987
988 return r;
989}
990
991static void rv770_vram_scratch_fini(struct radeon_device *rdev)
992{
993 int r;
994
995 if (rdev->vram_scratch.robj == NULL) {
996 return;
997 }
998 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
999 if (likely(r == 0)) {
1000 radeon_bo_kunmap(rdev->vram_scratch.robj);
1001 radeon_bo_unpin(rdev->vram_scratch.robj);
1002 radeon_bo_unreserve(rdev->vram_scratch.robj);
1003 }
1004 radeon_bo_unref(&rdev->vram_scratch.robj);
1005}
1006
1007void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1008{
1009 u64 size_bf, size_af;
1010
1011 if (mc->mc_vram_size > 0xE0000000) {
1012 /* leave room for at least 512M GTT */
1013 dev_warn(rdev->dev, "limiting VRAM\n");
1014 mc->real_vram_size = 0xE0000000;
1015 mc->mc_vram_size = 0xE0000000;
1016 }
1017 if (rdev->flags & RADEON_IS_AGP) {
1018 size_bf = mc->gtt_start;
1019 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1020 if (size_bf > size_af) {
1021 if (mc->mc_vram_size > size_bf) {
1022 dev_warn(rdev->dev, "limiting VRAM\n");
1023 mc->real_vram_size = size_bf;
1024 mc->mc_vram_size = size_bf;
1025 }
1026 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1027 } else {
1028 if (mc->mc_vram_size > size_af) {
1029 dev_warn(rdev->dev, "limiting VRAM\n");
1030 mc->real_vram_size = size_af;
1031 mc->mc_vram_size = size_af;
1032 }
1033 mc->vram_start = mc->gtt_end;
1034 }
1035 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1036 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1037 mc->mc_vram_size >> 20, mc->vram_start,
1038 mc->vram_end, mc->real_vram_size >> 20);
1039 } else {
1040 radeon_vram_location(rdev, &rdev->mc, 0);
1041 rdev->mc.gtt_base_align = 0;
1042 radeon_gtt_location(rdev, mc);
1043 }
1044}
1045
1046int rv770_mc_init(struct radeon_device *rdev)
1047{
1048 u32 tmp;
1049 int chansize, numchan;
1050
1051 /* Get VRAM informations */
1052 rdev->mc.vram_is_ddr = true;
1053 tmp = RREG32(MC_ARB_RAMCFG);
1054 if (tmp & CHANSIZE_OVERRIDE) {
1055 chansize = 16;
1056 } else if (tmp & CHANSIZE_MASK) {
1057 chansize = 64;
1058 } else {
1059 chansize = 32;
1060 }
1061 tmp = RREG32(MC_SHARED_CHMAP);
1062 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1063 case 0:
1064 default:
1065 numchan = 1;
1066 break;
1067 case 1:
1068 numchan = 2;
1069 break;
1070 case 2:
1071 numchan = 4;
1072 break;
1073 case 3:
1074 numchan = 8;
1075 break;
1076 }
1077 rdev->mc.vram_width = numchan * chansize;
1078 /* Could aper size report 0 ? */
1079 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1080 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1081 /* Setup GPU memory space */
1082 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1083 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1084 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1085 r700_vram_gtt_location(rdev, &rdev->mc);
1086 radeon_update_bandwidth_info(rdev);
1087
1088 return 0;
1089}
1090
1091static int rv770_startup(struct radeon_device *rdev)
1092{
1093 int r;
1094
1095 /* enable pcie gen2 link */
1096 rv770_pcie_gen2_enable(rdev);
1097
1098 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1099 r = r600_init_microcode(rdev);
1100 if (r) {
1101 DRM_ERROR("Failed to load firmware!\n");
1102 return r;
1103 }
1104 }
1105
1106 rv770_mc_program(rdev);
1107 if (rdev->flags & RADEON_IS_AGP) {
1108 rv770_agp_enable(rdev);
1109 } else {
1110 r = rv770_pcie_gart_enable(rdev);
1111 if (r)
1112 return r;
1113 }
1114 r = rv770_vram_scratch_init(rdev);
1115 if (r)
1116 return r;
1117 rv770_gpu_init(rdev);
1118 r = r600_blit_init(rdev);
1119 if (r) {
1120 r600_blit_fini(rdev);
1121 rdev->asic->copy = NULL;
1122 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1123 }
1124
1125 /* allocate wb buffer */
1126 r = radeon_wb_init(rdev);
1127 if (r)
1128 return r;
1129
1130 /* Enable IRQ */
1131 r = r600_irq_init(rdev);
1132 if (r) {
1133 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1134 radeon_irq_kms_fini(rdev);
1135 return r;
1136 }
1137 r600_irq_set(rdev);
1138
1139 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1140 if (r)
1141 return r;
1142 r = rv770_cp_load_microcode(rdev);
1143 if (r)
1144 return r;
1145 r = r600_cp_resume(rdev);
1146 if (r)
1147 return r;
1148
1149 return 0;
1150}
1151
1152int rv770_resume(struct radeon_device *rdev)
1153{
1154 int r;
1155
1156 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1157 * posting will perform necessary task to bring back GPU into good
1158 * shape.
1159 */
1160 /* post card */
1161 atom_asic_init(rdev->mode_info.atom_context);
1162
1163 r = rv770_startup(rdev);
1164 if (r) {
1165 DRM_ERROR("r600 startup failed on resume\n");
1166 return r;
1167 }
1168
1169 r = r600_ib_test(rdev);
1170 if (r) {
1171 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1172 return r;
1173 }
1174
1175 r = r600_audio_init(rdev);
1176 if (r) {
1177 dev_err(rdev->dev, "radeon: audio init failed\n");
1178 return r;
1179 }
1180
1181 return r;
1182
1183}
1184
1185int rv770_suspend(struct radeon_device *rdev)
1186{
1187 int r;
1188
1189 r600_audio_fini(rdev);
1190 /* FIXME: we should wait for ring to be empty */
1191 r700_cp_stop(rdev);
1192 rdev->cp.ready = false;
1193 r600_irq_suspend(rdev);
1194 radeon_wb_disable(rdev);
1195 rv770_pcie_gart_disable(rdev);
1196 /* unpin shaders bo */
1197 if (rdev->r600_blit.shader_obj) {
1198 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1199 if (likely(r == 0)) {
1200 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1201 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1202 }
1203 }
1204 return 0;
1205}
1206
1207/* Plan is to move initialization in that function and use
1208 * helper function so that radeon_device_init pretty much
1209 * do nothing more than calling asic specific function. This
1210 * should also allow to remove a bunch of callback function
1211 * like vram_info.
1212 */
1213int rv770_init(struct radeon_device *rdev)
1214{
1215 int r;
1216
1217 /* This don't do much */
1218 r = radeon_gem_init(rdev);
1219 if (r)
1220 return r;
1221 /* Read BIOS */
1222 if (!radeon_get_bios(rdev)) {
1223 if (ASIC_IS_AVIVO(rdev))
1224 return -EINVAL;
1225 }
1226 /* Must be an ATOMBIOS */
1227 if (!rdev->is_atom_bios) {
1228 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1229 return -EINVAL;
1230 }
1231 r = radeon_atombios_init(rdev);
1232 if (r)
1233 return r;
1234 /* Post card if necessary */
1235 if (!radeon_card_posted(rdev)) {
1236 if (!rdev->bios) {
1237 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1238 return -EINVAL;
1239 }
1240 DRM_INFO("GPU not posted. posting now...\n");
1241 atom_asic_init(rdev->mode_info.atom_context);
1242 }
1243 /* Initialize scratch registers */
1244 r600_scratch_init(rdev);
1245 /* Initialize surface registers */
1246 radeon_surface_init(rdev);
1247 /* Initialize clocks */
1248 radeon_get_clock_info(rdev->ddev);
1249 /* Fence driver */
1250 r = radeon_fence_driver_init(rdev);
1251 if (r)
1252 return r;
1253 /* initialize AGP */
1254 if (rdev->flags & RADEON_IS_AGP) {
1255 r = radeon_agp_init(rdev);
1256 if (r)
1257 radeon_agp_disable(rdev);
1258 }
1259 r = rv770_mc_init(rdev);
1260 if (r)
1261 return r;
1262 /* Memory manager */
1263 r = radeon_bo_init(rdev);
1264 if (r)
1265 return r;
1266
1267 r = radeon_irq_kms_init(rdev);
1268 if (r)
1269 return r;
1270
1271 rdev->cp.ring_obj = NULL;
1272 r600_ring_init(rdev, 1024 * 1024);
1273
1274 rdev->ih.ring_obj = NULL;
1275 r600_ih_ring_init(rdev, 64 * 1024);
1276
1277 r = r600_pcie_gart_init(rdev);
1278 if (r)
1279 return r;
1280
1281 rdev->accel_working = true;
1282 r = rv770_startup(rdev);
1283 if (r) {
1284 dev_err(rdev->dev, "disabling GPU acceleration\n");
1285 r700_cp_fini(rdev);
1286 r600_irq_fini(rdev);
1287 radeon_wb_fini(rdev);
1288 radeon_irq_kms_fini(rdev);
1289 rv770_pcie_gart_fini(rdev);
1290 rdev->accel_working = false;
1291 }
1292 if (rdev->accel_working) {
1293 r = radeon_ib_pool_init(rdev);
1294 if (r) {
1295 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1296 rdev->accel_working = false;
1297 } else {
1298 r = r600_ib_test(rdev);
1299 if (r) {
1300 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1301 rdev->accel_working = false;
1302 }
1303 }
1304 }
1305
1306 r = r600_audio_init(rdev);
1307 if (r) {
1308 dev_err(rdev->dev, "radeon: audio init failed\n");
1309 return r;
1310 }
1311
1312 return 0;
1313}
1314
1315void rv770_fini(struct radeon_device *rdev)
1316{
1317 r600_blit_fini(rdev);
1318 r700_cp_fini(rdev);
1319 r600_irq_fini(rdev);
1320 radeon_wb_fini(rdev);
1321 radeon_ib_pool_fini(rdev);
1322 radeon_irq_kms_fini(rdev);
1323 rv770_pcie_gart_fini(rdev);
1324 rv770_vram_scratch_fini(rdev);
1325 radeon_gem_fini(rdev);
1326 radeon_fence_driver_fini(rdev);
1327 radeon_agp_fini(rdev);
1328 radeon_bo_fini(rdev);
1329 radeon_atombios_fini(rdev);
1330 kfree(rdev->bios);
1331 rdev->bios = NULL;
1332}
1333
1334static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1335{
1336 u32 link_width_cntl, lanes, speed_cntl, tmp;
1337 u16 link_cntl2;
1338
1339 if (radeon_pcie_gen2 == 0)
1340 return;
1341
1342 if (rdev->flags & RADEON_IS_IGP)
1343 return;
1344
1345 if (!(rdev->flags & RADEON_IS_PCIE))
1346 return;
1347
1348 /* x2 cards have a special sequence */
1349 if (ASIC_IS_X2(rdev))
1350 return;
1351
1352 /* advertise upconfig capability */
1353 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1354 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1355 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1356 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1357 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
1358 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1359 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
1360 LC_RECONFIG_ARC_MISSING_ESCAPE);
1361 link_width_cntl |= lanes | LC_RECONFIG_NOW |
1362 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
1363 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1364 } else {
1365 link_width_cntl |= LC_UPCONFIGURE_DIS;
1366 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1367 }
1368
1369 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1370 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1371 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1372
1373 tmp = RREG32(0x541c);
1374 WREG32(0x541c, tmp | 0x8);
1375 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
1376 link_cntl2 = RREG16(0x4088);
1377 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
1378 link_cntl2 |= 0x2;
1379 WREG16(0x4088, link_cntl2);
1380 WREG32(MM_CFGREGS_CNTL, 0);
1381
1382 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1383 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
1384 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1385
1386 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1387 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1388 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1389
1390 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1391 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1392 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1393
1394 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1395 speed_cntl |= LC_GEN2_EN_STRAP;
1396 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1397
1398 } else {
1399 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1400 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
1401 if (1)
1402 link_width_cntl |= LC_UPCONFIGURE_DIS;
1403 else
1404 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1405 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1406 }
1407}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/firmware.h>
29#include <linux/platform_device.h>
30#include <linux/slab.h>
31#include "drmP.h"
32#include "radeon.h"
33#include "radeon_asic.h"
34#include "radeon_drm.h"
35#include "rv770d.h"
36#include "atom.h"
37#include "avivod.h"
38
39#define R700_PFP_UCODE_SIZE 848
40#define R700_PM4_UCODE_SIZE 1360
41
42static void rv770_gpu_init(struct radeon_device *rdev);
43void rv770_fini(struct radeon_device *rdev);
44static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
45
46u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
47{
48 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
49 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
50 int i;
51
52 /* Lock the graphics update lock */
53 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
54 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
55
56 /* update the scanout addresses */
57 if (radeon_crtc->crtc_id) {
58 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
59 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
60 } else {
61 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
62 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
63 }
64 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
65 (u32)crtc_base);
66 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
67 (u32)crtc_base);
68
69 /* Wait for update_pending to go high. */
70 for (i = 0; i < rdev->usec_timeout; i++) {
71 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
72 break;
73 udelay(1);
74 }
75 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
76
77 /* Unlock the lock, so double-buffering can take place inside vblank */
78 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
79 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
80
81 /* Return current update_pending status: */
82 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
83}
84
85/* get temperature in millidegrees */
86int rv770_get_temp(struct radeon_device *rdev)
87{
88 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
89 ASIC_T_SHIFT;
90 int actual_temp;
91
92 if (temp & 0x400)
93 actual_temp = -256;
94 else if (temp & 0x200)
95 actual_temp = 255;
96 else if (temp & 0x100) {
97 actual_temp = temp & 0x1ff;
98 actual_temp |= ~0x1ff;
99 } else
100 actual_temp = temp & 0xff;
101
102 return (actual_temp * 1000) / 2;
103}
104
105void rv770_pm_misc(struct radeon_device *rdev)
106{
107 int req_ps_idx = rdev->pm.requested_power_state_index;
108 int req_cm_idx = rdev->pm.requested_clock_mode_index;
109 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
110 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
111
112 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
113 /* 0xff01 is a flag rather then an actual voltage */
114 if (voltage->voltage == 0xff01)
115 return;
116 if (voltage->voltage != rdev->pm.current_vddc) {
117 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
118 rdev->pm.current_vddc = voltage->voltage;
119 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
120 }
121 }
122}
123
124/*
125 * GART
126 */
127int rv770_pcie_gart_enable(struct radeon_device *rdev)
128{
129 u32 tmp;
130 int r, i;
131
132 if (rdev->gart.robj == NULL) {
133 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
134 return -EINVAL;
135 }
136 r = radeon_gart_table_vram_pin(rdev);
137 if (r)
138 return r;
139 radeon_gart_restore(rdev);
140 /* Setup L2 cache */
141 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
142 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
143 EFFECTIVE_L2_QUEUE_SIZE(7));
144 WREG32(VM_L2_CNTL2, 0);
145 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
146 /* Setup TLB control */
147 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
148 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
149 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
150 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
151 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
152 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
153 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
154 if (rdev->family == CHIP_RV740)
155 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
156 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
157 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
158 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
159 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
160 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
161 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
162 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
163 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
164 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
165 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
166 (u32)(rdev->dummy_page.addr >> 12));
167 for (i = 1; i < 7; i++)
168 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
169
170 r600_pcie_gart_tlb_flush(rdev);
171 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
172 (unsigned)(rdev->mc.gtt_size >> 20),
173 (unsigned long long)rdev->gart.table_addr);
174 rdev->gart.ready = true;
175 return 0;
176}
177
178void rv770_pcie_gart_disable(struct radeon_device *rdev)
179{
180 u32 tmp;
181 int i;
182
183 /* Disable all tables */
184 for (i = 0; i < 7; i++)
185 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
186
187 /* Setup L2 cache */
188 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
189 EFFECTIVE_L2_QUEUE_SIZE(7));
190 WREG32(VM_L2_CNTL2, 0);
191 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
192 /* Setup TLB control */
193 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
194 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
195 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
196 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
197 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
198 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
199 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
200 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
201 radeon_gart_table_vram_unpin(rdev);
202}
203
204void rv770_pcie_gart_fini(struct radeon_device *rdev)
205{
206 radeon_gart_fini(rdev);
207 rv770_pcie_gart_disable(rdev);
208 radeon_gart_table_vram_free(rdev);
209}
210
211
212void rv770_agp_enable(struct radeon_device *rdev)
213{
214 u32 tmp;
215 int i;
216
217 /* Setup L2 cache */
218 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
219 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
220 EFFECTIVE_L2_QUEUE_SIZE(7));
221 WREG32(VM_L2_CNTL2, 0);
222 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
223 /* Setup TLB control */
224 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
225 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
226 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
227 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
228 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
229 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
230 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
231 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
232 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
233 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
234 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
235 for (i = 0; i < 7; i++)
236 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
237}
238
239static void rv770_mc_program(struct radeon_device *rdev)
240{
241 struct rv515_mc_save save;
242 u32 tmp;
243 int i, j;
244
245 /* Initialize HDP */
246 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
247 WREG32((0x2c14 + j), 0x00000000);
248 WREG32((0x2c18 + j), 0x00000000);
249 WREG32((0x2c1c + j), 0x00000000);
250 WREG32((0x2c20 + j), 0x00000000);
251 WREG32((0x2c24 + j), 0x00000000);
252 }
253 /* r7xx hw bug. Read from HDP_DEBUG1 rather
254 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
255 */
256 tmp = RREG32(HDP_DEBUG1);
257
258 rv515_mc_stop(rdev, &save);
259 if (r600_mc_wait_for_idle(rdev)) {
260 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
261 }
262 /* Lockout access through VGA aperture*/
263 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
264 /* Update configuration */
265 if (rdev->flags & RADEON_IS_AGP) {
266 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
267 /* VRAM before AGP */
268 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
269 rdev->mc.vram_start >> 12);
270 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
271 rdev->mc.gtt_end >> 12);
272 } else {
273 /* VRAM after AGP */
274 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
275 rdev->mc.gtt_start >> 12);
276 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
277 rdev->mc.vram_end >> 12);
278 }
279 } else {
280 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
281 rdev->mc.vram_start >> 12);
282 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
283 rdev->mc.vram_end >> 12);
284 }
285 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
286 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
287 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
288 WREG32(MC_VM_FB_LOCATION, tmp);
289 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
290 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
291 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
292 if (rdev->flags & RADEON_IS_AGP) {
293 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
294 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
295 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
296 } else {
297 WREG32(MC_VM_AGP_BASE, 0);
298 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
299 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
300 }
301 if (r600_mc_wait_for_idle(rdev)) {
302 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
303 }
304 rv515_mc_resume(rdev, &save);
305 /* we need to own VRAM, so turn off the VGA renderer here
306 * to stop it overwriting our objects */
307 rv515_vga_render_disable(rdev);
308}
309
310
311/*
312 * CP.
313 */
314void r700_cp_stop(struct radeon_device *rdev)
315{
316 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
317 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
318 WREG32(SCRATCH_UMSK, 0);
319}
320
321static int rv770_cp_load_microcode(struct radeon_device *rdev)
322{
323 const __be32 *fw_data;
324 int i;
325
326 if (!rdev->me_fw || !rdev->pfp_fw)
327 return -EINVAL;
328
329 r700_cp_stop(rdev);
330 WREG32(CP_RB_CNTL,
331#ifdef __BIG_ENDIAN
332 BUF_SWAP_32BIT |
333#endif
334 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
335
336 /* Reset cp */
337 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
338 RREG32(GRBM_SOFT_RESET);
339 mdelay(15);
340 WREG32(GRBM_SOFT_RESET, 0);
341
342 fw_data = (const __be32 *)rdev->pfp_fw->data;
343 WREG32(CP_PFP_UCODE_ADDR, 0);
344 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
345 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
346 WREG32(CP_PFP_UCODE_ADDR, 0);
347
348 fw_data = (const __be32 *)rdev->me_fw->data;
349 WREG32(CP_ME_RAM_WADDR, 0);
350 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
351 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
352
353 WREG32(CP_PFP_UCODE_ADDR, 0);
354 WREG32(CP_ME_RAM_WADDR, 0);
355 WREG32(CP_ME_RAM_RADDR, 0);
356 return 0;
357}
358
359void r700_cp_fini(struct radeon_device *rdev)
360{
361 r700_cp_stop(rdev);
362 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
363}
364
365/*
366 * Core functions
367 */
368static void rv770_gpu_init(struct radeon_device *rdev)
369{
370 int i, j, num_qd_pipes;
371 u32 ta_aux_cntl;
372 u32 sx_debug_1;
373 u32 smx_dc_ctl0;
374 u32 db_debug3;
375 u32 num_gs_verts_per_thread;
376 u32 vgt_gs_per_es;
377 u32 gs_prim_buffer_depth = 0;
378 u32 sq_ms_fifo_sizes;
379 u32 sq_config;
380 u32 sq_thread_resource_mgmt;
381 u32 hdp_host_path_cntl;
382 u32 sq_dyn_gpr_size_simd_ab_0;
383 u32 gb_tiling_config = 0;
384 u32 cc_rb_backend_disable = 0;
385 u32 cc_gc_shader_pipe_config = 0;
386 u32 mc_arb_ramcfg;
387 u32 db_debug4, tmp;
388 u32 inactive_pipes, shader_pipe_config;
389 u32 disabled_rb_mask;
390 unsigned active_number;
391
392 /* setup chip specs */
393 rdev->config.rv770.tiling_group_size = 256;
394 switch (rdev->family) {
395 case CHIP_RV770:
396 rdev->config.rv770.max_pipes = 4;
397 rdev->config.rv770.max_tile_pipes = 8;
398 rdev->config.rv770.max_simds = 10;
399 rdev->config.rv770.max_backends = 4;
400 rdev->config.rv770.max_gprs = 256;
401 rdev->config.rv770.max_threads = 248;
402 rdev->config.rv770.max_stack_entries = 512;
403 rdev->config.rv770.max_hw_contexts = 8;
404 rdev->config.rv770.max_gs_threads = 16 * 2;
405 rdev->config.rv770.sx_max_export_size = 128;
406 rdev->config.rv770.sx_max_export_pos_size = 16;
407 rdev->config.rv770.sx_max_export_smx_size = 112;
408 rdev->config.rv770.sq_num_cf_insts = 2;
409
410 rdev->config.rv770.sx_num_of_sets = 7;
411 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
412 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
413 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
414 break;
415 case CHIP_RV730:
416 rdev->config.rv770.max_pipes = 2;
417 rdev->config.rv770.max_tile_pipes = 4;
418 rdev->config.rv770.max_simds = 8;
419 rdev->config.rv770.max_backends = 2;
420 rdev->config.rv770.max_gprs = 128;
421 rdev->config.rv770.max_threads = 248;
422 rdev->config.rv770.max_stack_entries = 256;
423 rdev->config.rv770.max_hw_contexts = 8;
424 rdev->config.rv770.max_gs_threads = 16 * 2;
425 rdev->config.rv770.sx_max_export_size = 256;
426 rdev->config.rv770.sx_max_export_pos_size = 32;
427 rdev->config.rv770.sx_max_export_smx_size = 224;
428 rdev->config.rv770.sq_num_cf_insts = 2;
429
430 rdev->config.rv770.sx_num_of_sets = 7;
431 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
432 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
433 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
434 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
435 rdev->config.rv770.sx_max_export_pos_size -= 16;
436 rdev->config.rv770.sx_max_export_smx_size += 16;
437 }
438 break;
439 case CHIP_RV710:
440 rdev->config.rv770.max_pipes = 2;
441 rdev->config.rv770.max_tile_pipes = 2;
442 rdev->config.rv770.max_simds = 2;
443 rdev->config.rv770.max_backends = 1;
444 rdev->config.rv770.max_gprs = 256;
445 rdev->config.rv770.max_threads = 192;
446 rdev->config.rv770.max_stack_entries = 256;
447 rdev->config.rv770.max_hw_contexts = 4;
448 rdev->config.rv770.max_gs_threads = 8 * 2;
449 rdev->config.rv770.sx_max_export_size = 128;
450 rdev->config.rv770.sx_max_export_pos_size = 16;
451 rdev->config.rv770.sx_max_export_smx_size = 112;
452 rdev->config.rv770.sq_num_cf_insts = 1;
453
454 rdev->config.rv770.sx_num_of_sets = 7;
455 rdev->config.rv770.sc_prim_fifo_size = 0x40;
456 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
457 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
458 break;
459 case CHIP_RV740:
460 rdev->config.rv770.max_pipes = 4;
461 rdev->config.rv770.max_tile_pipes = 4;
462 rdev->config.rv770.max_simds = 8;
463 rdev->config.rv770.max_backends = 4;
464 rdev->config.rv770.max_gprs = 256;
465 rdev->config.rv770.max_threads = 248;
466 rdev->config.rv770.max_stack_entries = 512;
467 rdev->config.rv770.max_hw_contexts = 8;
468 rdev->config.rv770.max_gs_threads = 16 * 2;
469 rdev->config.rv770.sx_max_export_size = 256;
470 rdev->config.rv770.sx_max_export_pos_size = 32;
471 rdev->config.rv770.sx_max_export_smx_size = 224;
472 rdev->config.rv770.sq_num_cf_insts = 2;
473
474 rdev->config.rv770.sx_num_of_sets = 7;
475 rdev->config.rv770.sc_prim_fifo_size = 0x100;
476 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
477 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
478
479 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
480 rdev->config.rv770.sx_max_export_pos_size -= 16;
481 rdev->config.rv770.sx_max_export_smx_size += 16;
482 }
483 break;
484 default:
485 break;
486 }
487
488 /* Initialize HDP */
489 j = 0;
490 for (i = 0; i < 32; i++) {
491 WREG32((0x2c14 + j), 0x00000000);
492 WREG32((0x2c18 + j), 0x00000000);
493 WREG32((0x2c1c + j), 0x00000000);
494 WREG32((0x2c20 + j), 0x00000000);
495 WREG32((0x2c24 + j), 0x00000000);
496 j += 0x18;
497 }
498
499 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
500
501 /* setup tiling, simd, pipe config */
502 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
503
504 shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
505 inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
506 for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) {
507 if (!(inactive_pipes & tmp)) {
508 active_number++;
509 }
510 tmp <<= 1;
511 }
512 if (active_number == 1) {
513 WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1);
514 } else {
515 WREG32(SPI_CONFIG_CNTL, 0);
516 }
517
518 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
519 tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16);
520 if (tmp < rdev->config.rv770.max_backends) {
521 rdev->config.rv770.max_backends = tmp;
522 }
523
524 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
525 tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK);
526 if (tmp < rdev->config.rv770.max_pipes) {
527 rdev->config.rv770.max_pipes = tmp;
528 }
529 tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK);
530 if (tmp < rdev->config.rv770.max_simds) {
531 rdev->config.rv770.max_simds = tmp;
532 }
533
534 switch (rdev->config.rv770.max_tile_pipes) {
535 case 1:
536 default:
537 gb_tiling_config = PIPE_TILING(0);
538 break;
539 case 2:
540 gb_tiling_config = PIPE_TILING(1);
541 break;
542 case 4:
543 gb_tiling_config = PIPE_TILING(2);
544 break;
545 case 8:
546 gb_tiling_config = PIPE_TILING(3);
547 break;
548 }
549 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
550
551 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK;
552 tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
553 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
554 R7XX_MAX_BACKENDS, disabled_rb_mask);
555 gb_tiling_config |= tmp << 16;
556 rdev->config.rv770.backend_map = tmp;
557
558 if (rdev->family == CHIP_RV770)
559 gb_tiling_config |= BANK_TILING(1);
560 else {
561 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
562 gb_tiling_config |= BANK_TILING(1);
563 else
564 gb_tiling_config |= BANK_TILING(0);
565 }
566 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
567 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
568 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
569 gb_tiling_config |= ROW_TILING(3);
570 gb_tiling_config |= SAMPLE_SPLIT(3);
571 } else {
572 gb_tiling_config |=
573 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
574 gb_tiling_config |=
575 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
576 }
577
578 gb_tiling_config |= BANK_SWAPS(1);
579 rdev->config.rv770.tile_config = gb_tiling_config;
580
581 WREG32(GB_TILING_CONFIG, gb_tiling_config);
582 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
583 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
584
585 WREG32(CGTS_SYS_TCC_DISABLE, 0);
586 WREG32(CGTS_TCC_DISABLE, 0);
587 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
588 WREG32(CGTS_USER_TCC_DISABLE, 0);
589
590
591 num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
592 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
593 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
594
595 /* set HW defaults for 3D engine */
596 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
597 ROQ_IB2_START(0x2b)));
598
599 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
600
601 ta_aux_cntl = RREG32(TA_CNTL_AUX);
602 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
603
604 sx_debug_1 = RREG32(SX_DEBUG_1);
605 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
606 WREG32(SX_DEBUG_1, sx_debug_1);
607
608 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
609 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
610 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
611 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
612
613 if (rdev->family != CHIP_RV740)
614 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
615 GS_FLUSH_CTL(4) |
616 ACK_FLUSH_CTL(3) |
617 SYNC_FLUSH_CTL));
618
619 if (rdev->family != CHIP_RV770)
620 WREG32(SMX_SAR_CTL0, 0x00003f3f);
621
622 db_debug3 = RREG32(DB_DEBUG3);
623 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
624 switch (rdev->family) {
625 case CHIP_RV770:
626 case CHIP_RV740:
627 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
628 break;
629 case CHIP_RV710:
630 case CHIP_RV730:
631 default:
632 db_debug3 |= DB_CLK_OFF_DELAY(2);
633 break;
634 }
635 WREG32(DB_DEBUG3, db_debug3);
636
637 if (rdev->family != CHIP_RV770) {
638 db_debug4 = RREG32(DB_DEBUG4);
639 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
640 WREG32(DB_DEBUG4, db_debug4);
641 }
642
643 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
644 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
645 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
646
647 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
648 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
649 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
650
651 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
652
653 WREG32(VGT_NUM_INSTANCES, 1);
654
655 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
656
657 WREG32(CP_PERFMON_CNTL, 0);
658
659 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
660 DONE_FIFO_HIWATER(0xe0) |
661 ALU_UPDATE_FIFO_HIWATER(0x8));
662 switch (rdev->family) {
663 case CHIP_RV770:
664 case CHIP_RV730:
665 case CHIP_RV710:
666 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
667 break;
668 case CHIP_RV740:
669 default:
670 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
671 break;
672 }
673 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
674
675 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
676 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
677 */
678 sq_config = RREG32(SQ_CONFIG);
679 sq_config &= ~(PS_PRIO(3) |
680 VS_PRIO(3) |
681 GS_PRIO(3) |
682 ES_PRIO(3));
683 sq_config |= (DX9_CONSTS |
684 VC_ENABLE |
685 EXPORT_SRC_C |
686 PS_PRIO(0) |
687 VS_PRIO(1) |
688 GS_PRIO(2) |
689 ES_PRIO(3));
690 if (rdev->family == CHIP_RV710)
691 /* no vertex cache */
692 sq_config &= ~VC_ENABLE;
693
694 WREG32(SQ_CONFIG, sq_config);
695
696 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
697 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
698 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
699
700 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
701 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
702
703 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
704 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
705 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
706 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
707 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
708 else
709 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
710 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
711
712 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
713 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
714
715 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
716 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
717
718 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
719 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
720 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
721 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
722
723 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
724 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
725 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
726 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
727 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
728 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
729 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
730 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
731
732 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
733 FORCE_EOV_MAX_REZ_CNT(255)));
734
735 if (rdev->family == CHIP_RV710)
736 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
737 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
738 else
739 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
740 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
741
742 switch (rdev->family) {
743 case CHIP_RV770:
744 case CHIP_RV730:
745 case CHIP_RV740:
746 gs_prim_buffer_depth = 384;
747 break;
748 case CHIP_RV710:
749 gs_prim_buffer_depth = 128;
750 break;
751 default:
752 break;
753 }
754
755 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
756 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
757 /* Max value for this is 256 */
758 if (vgt_gs_per_es > 256)
759 vgt_gs_per_es = 256;
760
761 WREG32(VGT_ES_PER_GS, 128);
762 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
763 WREG32(VGT_GS_PER_VS, 2);
764
765 /* more default values. 2D/3D driver should adjust as needed */
766 WREG32(VGT_GS_VERTEX_REUSE, 16);
767 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
768 WREG32(VGT_STRMOUT_EN, 0);
769 WREG32(SX_MISC, 0);
770 WREG32(PA_SC_MODE_CNTL, 0);
771 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
772 WREG32(PA_SC_AA_CONFIG, 0);
773 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
774 WREG32(PA_SC_LINE_STIPPLE, 0);
775 WREG32(SPI_INPUT_Z, 0);
776 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
777 WREG32(CB_COLOR7_FRAG, 0);
778
779 /* clear render buffer base addresses */
780 WREG32(CB_COLOR0_BASE, 0);
781 WREG32(CB_COLOR1_BASE, 0);
782 WREG32(CB_COLOR2_BASE, 0);
783 WREG32(CB_COLOR3_BASE, 0);
784 WREG32(CB_COLOR4_BASE, 0);
785 WREG32(CB_COLOR5_BASE, 0);
786 WREG32(CB_COLOR6_BASE, 0);
787 WREG32(CB_COLOR7_BASE, 0);
788
789 WREG32(TCP_CNTL, 0);
790
791 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
792 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
793
794 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
795
796 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
797 NUM_CLIP_SEQ(3)));
798 WREG32(VC_ENHANCE, 0);
799}
800
801void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
802{
803 u64 size_bf, size_af;
804
805 if (mc->mc_vram_size > 0xE0000000) {
806 /* leave room for at least 512M GTT */
807 dev_warn(rdev->dev, "limiting VRAM\n");
808 mc->real_vram_size = 0xE0000000;
809 mc->mc_vram_size = 0xE0000000;
810 }
811 if (rdev->flags & RADEON_IS_AGP) {
812 size_bf = mc->gtt_start;
813 size_af = 0xFFFFFFFF - mc->gtt_end;
814 if (size_bf > size_af) {
815 if (mc->mc_vram_size > size_bf) {
816 dev_warn(rdev->dev, "limiting VRAM\n");
817 mc->real_vram_size = size_bf;
818 mc->mc_vram_size = size_bf;
819 }
820 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
821 } else {
822 if (mc->mc_vram_size > size_af) {
823 dev_warn(rdev->dev, "limiting VRAM\n");
824 mc->real_vram_size = size_af;
825 mc->mc_vram_size = size_af;
826 }
827 mc->vram_start = mc->gtt_end + 1;
828 }
829 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
830 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
831 mc->mc_vram_size >> 20, mc->vram_start,
832 mc->vram_end, mc->real_vram_size >> 20);
833 } else {
834 radeon_vram_location(rdev, &rdev->mc, 0);
835 rdev->mc.gtt_base_align = 0;
836 radeon_gtt_location(rdev, mc);
837 }
838}
839
840int rv770_mc_init(struct radeon_device *rdev)
841{
842 u32 tmp;
843 int chansize, numchan;
844
845 /* Get VRAM informations */
846 rdev->mc.vram_is_ddr = true;
847 tmp = RREG32(MC_ARB_RAMCFG);
848 if (tmp & CHANSIZE_OVERRIDE) {
849 chansize = 16;
850 } else if (tmp & CHANSIZE_MASK) {
851 chansize = 64;
852 } else {
853 chansize = 32;
854 }
855 tmp = RREG32(MC_SHARED_CHMAP);
856 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
857 case 0:
858 default:
859 numchan = 1;
860 break;
861 case 1:
862 numchan = 2;
863 break;
864 case 2:
865 numchan = 4;
866 break;
867 case 3:
868 numchan = 8;
869 break;
870 }
871 rdev->mc.vram_width = numchan * chansize;
872 /* Could aper size report 0 ? */
873 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
874 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
875 /* Setup GPU memory space */
876 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
877 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
878 rdev->mc.visible_vram_size = rdev->mc.aper_size;
879 r700_vram_gtt_location(rdev, &rdev->mc);
880 radeon_update_bandwidth_info(rdev);
881
882 return 0;
883}
884
885static int rv770_startup(struct radeon_device *rdev)
886{
887 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
888 int r;
889
890 /* enable pcie gen2 link */
891 rv770_pcie_gen2_enable(rdev);
892
893 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
894 r = r600_init_microcode(rdev);
895 if (r) {
896 DRM_ERROR("Failed to load firmware!\n");
897 return r;
898 }
899 }
900
901 r = r600_vram_scratch_init(rdev);
902 if (r)
903 return r;
904
905 rv770_mc_program(rdev);
906 if (rdev->flags & RADEON_IS_AGP) {
907 rv770_agp_enable(rdev);
908 } else {
909 r = rv770_pcie_gart_enable(rdev);
910 if (r)
911 return r;
912 }
913
914 rv770_gpu_init(rdev);
915 r = r600_blit_init(rdev);
916 if (r) {
917 r600_blit_fini(rdev);
918 rdev->asic->copy.copy = NULL;
919 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
920 }
921
922 /* allocate wb buffer */
923 r = radeon_wb_init(rdev);
924 if (r)
925 return r;
926
927 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
928 if (r) {
929 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
930 return r;
931 }
932
933 /* Enable IRQ */
934 r = r600_irq_init(rdev);
935 if (r) {
936 DRM_ERROR("radeon: IH init failed (%d).\n", r);
937 radeon_irq_kms_fini(rdev);
938 return r;
939 }
940 r600_irq_set(rdev);
941
942 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
943 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
944 0, 0xfffff, RADEON_CP_PACKET2);
945 if (r)
946 return r;
947 r = rv770_cp_load_microcode(rdev);
948 if (r)
949 return r;
950 r = r600_cp_resume(rdev);
951 if (r)
952 return r;
953
954 r = radeon_ib_pool_start(rdev);
955 if (r)
956 return r;
957
958 r = radeon_ib_ring_tests(rdev);
959 if (r)
960 return r;
961
962 r = r600_audio_init(rdev);
963 if (r) {
964 DRM_ERROR("radeon: audio init failed\n");
965 return r;
966 }
967
968 return 0;
969}
970
971int rv770_resume(struct radeon_device *rdev)
972{
973 int r;
974
975 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
976 * posting will perform necessary task to bring back GPU into good
977 * shape.
978 */
979 /* post card */
980 atom_asic_init(rdev->mode_info.atom_context);
981
982 rdev->accel_working = true;
983 r = rv770_startup(rdev);
984 if (r) {
985 DRM_ERROR("r600 startup failed on resume\n");
986 rdev->accel_working = false;
987 return r;
988 }
989
990 return r;
991
992}
993
994int rv770_suspend(struct radeon_device *rdev)
995{
996 r600_audio_fini(rdev);
997 radeon_ib_pool_suspend(rdev);
998 r600_blit_suspend(rdev);
999 /* FIXME: we should wait for ring to be empty */
1000 r700_cp_stop(rdev);
1001 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1002 r600_irq_suspend(rdev);
1003 radeon_wb_disable(rdev);
1004 rv770_pcie_gart_disable(rdev);
1005
1006 return 0;
1007}
1008
1009/* Plan is to move initialization in that function and use
1010 * helper function so that radeon_device_init pretty much
1011 * do nothing more than calling asic specific function. This
1012 * should also allow to remove a bunch of callback function
1013 * like vram_info.
1014 */
1015int rv770_init(struct radeon_device *rdev)
1016{
1017 int r;
1018
1019 /* Read BIOS */
1020 if (!radeon_get_bios(rdev)) {
1021 if (ASIC_IS_AVIVO(rdev))
1022 return -EINVAL;
1023 }
1024 /* Must be an ATOMBIOS */
1025 if (!rdev->is_atom_bios) {
1026 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1027 return -EINVAL;
1028 }
1029 r = radeon_atombios_init(rdev);
1030 if (r)
1031 return r;
1032 /* Post card if necessary */
1033 if (!radeon_card_posted(rdev)) {
1034 if (!rdev->bios) {
1035 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1036 return -EINVAL;
1037 }
1038 DRM_INFO("GPU not posted. posting now...\n");
1039 atom_asic_init(rdev->mode_info.atom_context);
1040 }
1041 /* Initialize scratch registers */
1042 r600_scratch_init(rdev);
1043 /* Initialize surface registers */
1044 radeon_surface_init(rdev);
1045 /* Initialize clocks */
1046 radeon_get_clock_info(rdev->ddev);
1047 /* Fence driver */
1048 r = radeon_fence_driver_init(rdev);
1049 if (r)
1050 return r;
1051 /* initialize AGP */
1052 if (rdev->flags & RADEON_IS_AGP) {
1053 r = radeon_agp_init(rdev);
1054 if (r)
1055 radeon_agp_disable(rdev);
1056 }
1057 r = rv770_mc_init(rdev);
1058 if (r)
1059 return r;
1060 /* Memory manager */
1061 r = radeon_bo_init(rdev);
1062 if (r)
1063 return r;
1064
1065 r = radeon_irq_kms_init(rdev);
1066 if (r)
1067 return r;
1068
1069 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
1070 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
1071
1072 rdev->ih.ring_obj = NULL;
1073 r600_ih_ring_init(rdev, 64 * 1024);
1074
1075 r = r600_pcie_gart_init(rdev);
1076 if (r)
1077 return r;
1078
1079 r = radeon_ib_pool_init(rdev);
1080 rdev->accel_working = true;
1081 if (r) {
1082 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1083 rdev->accel_working = false;
1084 }
1085
1086 r = rv770_startup(rdev);
1087 if (r) {
1088 dev_err(rdev->dev, "disabling GPU acceleration\n");
1089 r700_cp_fini(rdev);
1090 r600_irq_fini(rdev);
1091 radeon_wb_fini(rdev);
1092 r100_ib_fini(rdev);
1093 radeon_irq_kms_fini(rdev);
1094 rv770_pcie_gart_fini(rdev);
1095 rdev->accel_working = false;
1096 }
1097
1098 return 0;
1099}
1100
1101void rv770_fini(struct radeon_device *rdev)
1102{
1103 r600_blit_fini(rdev);
1104 r700_cp_fini(rdev);
1105 r600_irq_fini(rdev);
1106 radeon_wb_fini(rdev);
1107 r100_ib_fini(rdev);
1108 radeon_irq_kms_fini(rdev);
1109 rv770_pcie_gart_fini(rdev);
1110 r600_vram_scratch_fini(rdev);
1111 radeon_gem_fini(rdev);
1112 radeon_fence_driver_fini(rdev);
1113 radeon_agp_fini(rdev);
1114 radeon_bo_fini(rdev);
1115 radeon_atombios_fini(rdev);
1116 kfree(rdev->bios);
1117 rdev->bios = NULL;
1118}
1119
1120static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1121{
1122 u32 link_width_cntl, lanes, speed_cntl, tmp;
1123 u16 link_cntl2;
1124
1125 if (radeon_pcie_gen2 == 0)
1126 return;
1127
1128 if (rdev->flags & RADEON_IS_IGP)
1129 return;
1130
1131 if (!(rdev->flags & RADEON_IS_PCIE))
1132 return;
1133
1134 /* x2 cards have a special sequence */
1135 if (ASIC_IS_X2(rdev))
1136 return;
1137
1138 /* advertise upconfig capability */
1139 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1140 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1141 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1142 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1143 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
1144 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1145 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
1146 LC_RECONFIG_ARC_MISSING_ESCAPE);
1147 link_width_cntl |= lanes | LC_RECONFIG_NOW |
1148 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
1149 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1150 } else {
1151 link_width_cntl |= LC_UPCONFIGURE_DIS;
1152 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1153 }
1154
1155 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1156 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1157 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1158
1159 tmp = RREG32(0x541c);
1160 WREG32(0x541c, tmp | 0x8);
1161 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
1162 link_cntl2 = RREG16(0x4088);
1163 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
1164 link_cntl2 |= 0x2;
1165 WREG16(0x4088, link_cntl2);
1166 WREG32(MM_CFGREGS_CNTL, 0);
1167
1168 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1169 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
1170 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1171
1172 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1173 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1174 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1175
1176 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1177 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1178 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1179
1180 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1181 speed_cntl |= LC_GEN2_EN_STRAP;
1182 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1183
1184 } else {
1185 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1186 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
1187 if (1)
1188 link_width_cntl |= LC_UPCONFIGURE_DIS;
1189 else
1190 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1191 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1192 }
1193}