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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
29#include "drm_sarea.h"
30#include "radeon.h"
31#include "radeon_drm.h"
32
33#include <linux/vga_switcheroo.h>
34#include <linux/slab.h>
35
36int radeon_driver_unload_kms(struct drm_device *dev)
37{
38 struct radeon_device *rdev = dev->dev_private;
39
40 if (rdev == NULL)
41 return 0;
42 radeon_modeset_fini(rdev);
43 radeon_device_fini(rdev);
44 kfree(rdev);
45 dev->dev_private = NULL;
46 return 0;
47}
48
49int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
50{
51 struct radeon_device *rdev;
52 int r, acpi_status;
53
54 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
55 if (rdev == NULL) {
56 return -ENOMEM;
57 }
58 dev->dev_private = (void *)rdev;
59
60 /* update BUS flag */
61 if (drm_pci_device_is_agp(dev)) {
62 flags |= RADEON_IS_AGP;
63 } else if (pci_is_pcie(dev->pdev)) {
64 flags |= RADEON_IS_PCIE;
65 } else {
66 flags |= RADEON_IS_PCI;
67 }
68
69 /* radeon_device_init should report only fatal error
70 * like memory allocation failure or iomapping failure,
71 * or memory manager initialization failure, it must
72 * properly initialize the GPU MC controller and permit
73 * VRAM allocation
74 */
75 r = radeon_device_init(rdev, dev, dev->pdev, flags);
76 if (r) {
77 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
78 goto out;
79 }
80
81 /* Call ACPI methods */
82 acpi_status = radeon_acpi_init(rdev);
83 if (acpi_status)
84 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
85
86 /* Again modeset_init should fail only on fatal error
87 * otherwise it should provide enough functionalities
88 * for shadowfb to run
89 */
90 r = radeon_modeset_init(rdev);
91 if (r)
92 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
93out:
94 if (r)
95 radeon_driver_unload_kms(dev);
96 return r;
97}
98
99static void radeon_set_filp_rights(struct drm_device *dev,
100 struct drm_file **owner,
101 struct drm_file *applier,
102 uint32_t *value)
103{
104 mutex_lock(&dev->struct_mutex);
105 if (*value == 1) {
106 /* wants rights */
107 if (!*owner)
108 *owner = applier;
109 } else if (*value == 0) {
110 /* revokes rights */
111 if (*owner == applier)
112 *owner = NULL;
113 }
114 *value = *owner == applier ? 1 : 0;
115 mutex_unlock(&dev->struct_mutex);
116}
117
118/*
119 * Userspace get information ioctl
120 */
121int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
122{
123 struct radeon_device *rdev = dev->dev_private;
124 struct drm_radeon_info *info;
125 struct radeon_mode_info *minfo = &rdev->mode_info;
126 uint32_t *value_ptr;
127 uint32_t value;
128 struct drm_crtc *crtc;
129 int i, found;
130
131 info = data;
132 value_ptr = (uint32_t *)((unsigned long)info->value);
133 if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value)))
134 return -EFAULT;
135
136 switch (info->request) {
137 case RADEON_INFO_DEVICE_ID:
138 value = dev->pci_device;
139 break;
140 case RADEON_INFO_NUM_GB_PIPES:
141 value = rdev->num_gb_pipes;
142 break;
143 case RADEON_INFO_NUM_Z_PIPES:
144 value = rdev->num_z_pipes;
145 break;
146 case RADEON_INFO_ACCEL_WORKING:
147 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
148 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
149 value = false;
150 else
151 value = rdev->accel_working;
152 break;
153 case RADEON_INFO_CRTC_FROM_ID:
154 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
155 crtc = (struct drm_crtc *)minfo->crtcs[i];
156 if (crtc && crtc->base.id == value) {
157 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
158 value = radeon_crtc->crtc_id;
159 found = 1;
160 break;
161 }
162 }
163 if (!found) {
164 DRM_DEBUG_KMS("unknown crtc id %d\n", value);
165 return -EINVAL;
166 }
167 break;
168 case RADEON_INFO_ACCEL_WORKING2:
169 value = rdev->accel_working;
170 break;
171 case RADEON_INFO_TILING_CONFIG:
172 if (rdev->family >= CHIP_CAYMAN)
173 value = rdev->config.cayman.tile_config;
174 else if (rdev->family >= CHIP_CEDAR)
175 value = rdev->config.evergreen.tile_config;
176 else if (rdev->family >= CHIP_RV770)
177 value = rdev->config.rv770.tile_config;
178 else if (rdev->family >= CHIP_R600)
179 value = rdev->config.r600.tile_config;
180 else {
181 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
182 return -EINVAL;
183 }
184 break;
185 case RADEON_INFO_WANT_HYPERZ:
186 /* The "value" here is both an input and output parameter.
187 * If the input value is 1, filp requests hyper-z access.
188 * If the input value is 0, filp revokes its hyper-z access.
189 *
190 * When returning, the value is 1 if filp owns hyper-z access,
191 * 0 otherwise. */
192 if (value >= 2) {
193 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
194 return -EINVAL;
195 }
196 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value);
197 break;
198 case RADEON_INFO_WANT_CMASK:
199 /* The same logic as Hyper-Z. */
200 if (value >= 2) {
201 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value);
202 return -EINVAL;
203 }
204 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value);
205 break;
206 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
207 /* return clock value in KHz */
208 value = rdev->clock.spll.reference_freq * 10;
209 break;
210 case RADEON_INFO_NUM_BACKENDS:
211 if (rdev->family >= CHIP_CAYMAN)
212 value = rdev->config.cayman.max_backends_per_se *
213 rdev->config.cayman.max_shader_engines;
214 else if (rdev->family >= CHIP_CEDAR)
215 value = rdev->config.evergreen.max_backends;
216 else if (rdev->family >= CHIP_RV770)
217 value = rdev->config.rv770.max_backends;
218 else if (rdev->family >= CHIP_R600)
219 value = rdev->config.r600.max_backends;
220 else {
221 return -EINVAL;
222 }
223 break;
224 case RADEON_INFO_NUM_TILE_PIPES:
225 if (rdev->family >= CHIP_CAYMAN)
226 value = rdev->config.cayman.max_tile_pipes;
227 else if (rdev->family >= CHIP_CEDAR)
228 value = rdev->config.evergreen.max_tile_pipes;
229 else if (rdev->family >= CHIP_RV770)
230 value = rdev->config.rv770.max_tile_pipes;
231 else if (rdev->family >= CHIP_R600)
232 value = rdev->config.r600.max_tile_pipes;
233 else {
234 return -EINVAL;
235 }
236 break;
237 case RADEON_INFO_FUSION_GART_WORKING:
238 value = 1;
239 break;
240 case RADEON_INFO_BACKEND_MAP:
241 if (rdev->family >= CHIP_CAYMAN)
242 value = rdev->config.cayman.backend_map;
243 else if (rdev->family >= CHIP_CEDAR)
244 value = rdev->config.evergreen.backend_map;
245 else if (rdev->family >= CHIP_RV770)
246 value = rdev->config.rv770.backend_map;
247 else if (rdev->family >= CHIP_R600)
248 value = rdev->config.r600.backend_map;
249 else {
250 return -EINVAL;
251 }
252 break;
253 default:
254 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
255 return -EINVAL;
256 }
257 if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
258 DRM_ERROR("copy_to_user\n");
259 return -EFAULT;
260 }
261 return 0;
262}
263
264
265/*
266 * Outdated mess for old drm with Xorg being in charge (void function now).
267 */
268int radeon_driver_firstopen_kms(struct drm_device *dev)
269{
270 return 0;
271}
272
273
274void radeon_driver_lastclose_kms(struct drm_device *dev)
275{
276 vga_switcheroo_process_delayed_switch();
277}
278
279int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
280{
281 return 0;
282}
283
284void radeon_driver_postclose_kms(struct drm_device *dev,
285 struct drm_file *file_priv)
286{
287}
288
289void radeon_driver_preclose_kms(struct drm_device *dev,
290 struct drm_file *file_priv)
291{
292 struct radeon_device *rdev = dev->dev_private;
293 if (rdev->hyperz_filp == file_priv)
294 rdev->hyperz_filp = NULL;
295 if (rdev->cmask_filp == file_priv)
296 rdev->cmask_filp = NULL;
297}
298
299/*
300 * VBlank related functions.
301 */
302u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
303{
304 struct radeon_device *rdev = dev->dev_private;
305
306 if (crtc < 0 || crtc >= rdev->num_crtc) {
307 DRM_ERROR("Invalid crtc %d\n", crtc);
308 return -EINVAL;
309 }
310
311 return radeon_get_vblank_counter(rdev, crtc);
312}
313
314int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
315{
316 struct radeon_device *rdev = dev->dev_private;
317
318 if (crtc < 0 || crtc >= rdev->num_crtc) {
319 DRM_ERROR("Invalid crtc %d\n", crtc);
320 return -EINVAL;
321 }
322
323 rdev->irq.crtc_vblank_int[crtc] = true;
324
325 return radeon_irq_set(rdev);
326}
327
328void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
329{
330 struct radeon_device *rdev = dev->dev_private;
331
332 if (crtc < 0 || crtc >= rdev->num_crtc) {
333 DRM_ERROR("Invalid crtc %d\n", crtc);
334 return;
335 }
336
337 rdev->irq.crtc_vblank_int[crtc] = false;
338
339 radeon_irq_set(rdev);
340}
341
342int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
343 int *max_error,
344 struct timeval *vblank_time,
345 unsigned flags)
346{
347 struct drm_crtc *drmcrtc;
348 struct radeon_device *rdev = dev->dev_private;
349
350 if (crtc < 0 || crtc >= dev->num_crtcs) {
351 DRM_ERROR("Invalid crtc %d\n", crtc);
352 return -EINVAL;
353 }
354
355 /* Get associated drm_crtc: */
356 drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
357
358 /* Helper routine in DRM core does all the work: */
359 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
360 vblank_time, flags,
361 drmcrtc);
362}
363
364/*
365 * IOCTL.
366 */
367int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
368 struct drm_file *file_priv)
369{
370 /* Not valid in KMS. */
371 return -EINVAL;
372}
373
374#define KMS_INVALID_IOCTL(name) \
375int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
376{ \
377 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
378 return -EINVAL; \
379}
380
381/*
382 * All these ioctls are invalid in kms world.
383 */
384KMS_INVALID_IOCTL(radeon_cp_init_kms)
385KMS_INVALID_IOCTL(radeon_cp_start_kms)
386KMS_INVALID_IOCTL(radeon_cp_stop_kms)
387KMS_INVALID_IOCTL(radeon_cp_reset_kms)
388KMS_INVALID_IOCTL(radeon_cp_idle_kms)
389KMS_INVALID_IOCTL(radeon_cp_resume_kms)
390KMS_INVALID_IOCTL(radeon_engine_reset_kms)
391KMS_INVALID_IOCTL(radeon_fullscreen_kms)
392KMS_INVALID_IOCTL(radeon_cp_swap_kms)
393KMS_INVALID_IOCTL(radeon_cp_clear_kms)
394KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
395KMS_INVALID_IOCTL(radeon_cp_indices_kms)
396KMS_INVALID_IOCTL(radeon_cp_texture_kms)
397KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
398KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
399KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
400KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
401KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
402KMS_INVALID_IOCTL(radeon_cp_flip_kms)
403KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
404KMS_INVALID_IOCTL(radeon_mem_free_kms)
405KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
406KMS_INVALID_IOCTL(radeon_irq_emit_kms)
407KMS_INVALID_IOCTL(radeon_irq_wait_kms)
408KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
409KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
410KMS_INVALID_IOCTL(radeon_surface_free_kms)
411
412
413struct drm_ioctl_desc radeon_ioctls_kms[] = {
414 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
415 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
416 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
417 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
418 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
419 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
420 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
421 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
422 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
423 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
424 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
425 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
426 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
427 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
428 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
429 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
430 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
431 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
432 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
433 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
434 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
435 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
436 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
437 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
438 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
439 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
440 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
441 /* KMS */
442 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
443 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
444 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
445 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
446 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
447 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
448 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
449 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
450 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
451 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
452 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
453 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
454};
455int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <drm/drmP.h>
29#include <drm/drm_fb_helper.h>
30#include "radeon.h"
31#include <drm/radeon_drm.h>
32#include "radeon_asic.h"
33
34#include <linux/vga_switcheroo.h>
35#include <linux/slab.h>
36#include <linux/pm_runtime.h>
37
38#if defined(CONFIG_VGA_SWITCHEROO)
39bool radeon_has_atpx(void);
40#else
41static inline bool radeon_has_atpx(void) { return false; }
42#endif
43
44/**
45 * radeon_driver_unload_kms - Main unload function for KMS.
46 *
47 * @dev: drm dev pointer
48 *
49 * This is the main unload function for KMS (all asics).
50 * It calls radeon_modeset_fini() to tear down the
51 * displays, and radeon_device_fini() to tear down
52 * the rest of the device (CP, writeback, etc.).
53 * Returns 0 on success.
54 */
55void radeon_driver_unload_kms(struct drm_device *dev)
56{
57 struct radeon_device *rdev = dev->dev_private;
58
59 if (rdev == NULL)
60 return;
61
62 if (rdev->rmmio == NULL)
63 goto done_free;
64
65 if (radeon_is_px(dev)) {
66 pm_runtime_get_sync(dev->dev);
67 pm_runtime_forbid(dev->dev);
68 }
69
70 radeon_acpi_fini(rdev);
71
72 radeon_modeset_fini(rdev);
73 radeon_device_fini(rdev);
74
75done_free:
76 kfree(rdev);
77 dev->dev_private = NULL;
78}
79
80/**
81 * radeon_driver_load_kms - Main load function for KMS.
82 *
83 * @dev: drm dev pointer
84 * @flags: device flags
85 *
86 * This is the main load function for KMS (all asics).
87 * It calls radeon_device_init() to set up the non-display
88 * parts of the chip (asic init, CP, writeback, etc.), and
89 * radeon_modeset_init() to set up the display parts
90 * (crtcs, encoders, hotplug detect, etc.).
91 * Returns 0 on success, error on failure.
92 */
93int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
94{
95 struct radeon_device *rdev;
96 int r, acpi_status;
97
98 if (!radeon_si_support) {
99 switch (flags & RADEON_FAMILY_MASK) {
100 case CHIP_TAHITI:
101 case CHIP_PITCAIRN:
102 case CHIP_VERDE:
103 case CHIP_OLAND:
104 case CHIP_HAINAN:
105 dev_info(dev->dev,
106 "SI support disabled by module param\n");
107 return -ENODEV;
108 }
109 }
110 if (!radeon_cik_support) {
111 switch (flags & RADEON_FAMILY_MASK) {
112 case CHIP_KAVERI:
113 case CHIP_BONAIRE:
114 case CHIP_HAWAII:
115 case CHIP_KABINI:
116 case CHIP_MULLINS:
117 dev_info(dev->dev,
118 "CIK support disabled by module param\n");
119 return -ENODEV;
120 }
121 }
122
123 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
124 if (rdev == NULL) {
125 return -ENOMEM;
126 }
127 dev->dev_private = (void *)rdev;
128
129 /* update BUS flag */
130 if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP)) {
131 flags |= RADEON_IS_AGP;
132 } else if (pci_is_pcie(dev->pdev)) {
133 flags |= RADEON_IS_PCIE;
134 } else {
135 flags |= RADEON_IS_PCI;
136 }
137
138 if ((radeon_runtime_pm != 0) &&
139 radeon_has_atpx() &&
140 ((flags & RADEON_IS_IGP) == 0) &&
141 !pci_is_thunderbolt_attached(dev->pdev))
142 flags |= RADEON_IS_PX;
143
144 /* radeon_device_init should report only fatal error
145 * like memory allocation failure or iomapping failure,
146 * or memory manager initialization failure, it must
147 * properly initialize the GPU MC controller and permit
148 * VRAM allocation
149 */
150 r = radeon_device_init(rdev, dev, dev->pdev, flags);
151 if (r) {
152 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
153 goto out;
154 }
155
156 /* Again modeset_init should fail only on fatal error
157 * otherwise it should provide enough functionalities
158 * for shadowfb to run
159 */
160 r = radeon_modeset_init(rdev);
161 if (r)
162 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
163
164 /* Call ACPI methods: require modeset init
165 * but failure is not fatal
166 */
167 if (!r) {
168 acpi_status = radeon_acpi_init(rdev);
169 if (acpi_status)
170 dev_dbg(&dev->pdev->dev,
171 "Error during ACPI methods call\n");
172 }
173
174 if (radeon_is_px(dev)) {
175 pm_runtime_use_autosuspend(dev->dev);
176 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
177 pm_runtime_set_active(dev->dev);
178 pm_runtime_allow(dev->dev);
179 pm_runtime_mark_last_busy(dev->dev);
180 pm_runtime_put_autosuspend(dev->dev);
181 }
182
183out:
184 if (r)
185 radeon_driver_unload_kms(dev);
186
187
188 return r;
189}
190
191/**
192 * radeon_set_filp_rights - Set filp right.
193 *
194 * @dev: drm dev pointer
195 * @owner: drm file
196 * @applier: drm file
197 * @value: value
198 *
199 * Sets the filp rights for the device (all asics).
200 */
201static void radeon_set_filp_rights(struct drm_device *dev,
202 struct drm_file **owner,
203 struct drm_file *applier,
204 uint32_t *value)
205{
206 struct radeon_device *rdev = dev->dev_private;
207
208 mutex_lock(&rdev->gem.mutex);
209 if (*value == 1) {
210 /* wants rights */
211 if (!*owner)
212 *owner = applier;
213 } else if (*value == 0) {
214 /* revokes rights */
215 if (*owner == applier)
216 *owner = NULL;
217 }
218 *value = *owner == applier ? 1 : 0;
219 mutex_unlock(&rdev->gem.mutex);
220}
221
222/*
223 * Userspace get information ioctl
224 */
225/**
226 * radeon_info_ioctl - answer a device specific request.
227 *
228 * @rdev: radeon device pointer
229 * @data: request object
230 * @filp: drm filp
231 *
232 * This function is used to pass device specific parameters to the userspace
233 * drivers. Examples include: pci device id, pipeline parms, tiling params,
234 * etc. (all asics).
235 * Returns 0 on success, -EINVAL on failure.
236 */
237static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
238{
239 struct radeon_device *rdev = dev->dev_private;
240 struct drm_radeon_info *info = data;
241 struct radeon_mode_info *minfo = &rdev->mode_info;
242 uint32_t *value, value_tmp, *value_ptr, value_size;
243 uint64_t value64;
244 struct drm_crtc *crtc;
245 int i, found;
246
247 value_ptr = (uint32_t *)((unsigned long)info->value);
248 value = &value_tmp;
249 value_size = sizeof(uint32_t);
250
251 switch (info->request) {
252 case RADEON_INFO_DEVICE_ID:
253 *value = dev->pdev->device;
254 break;
255 case RADEON_INFO_NUM_GB_PIPES:
256 *value = rdev->num_gb_pipes;
257 break;
258 case RADEON_INFO_NUM_Z_PIPES:
259 *value = rdev->num_z_pipes;
260 break;
261 case RADEON_INFO_ACCEL_WORKING:
262 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
263 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
264 *value = false;
265 else
266 *value = rdev->accel_working;
267 break;
268 case RADEON_INFO_CRTC_FROM_ID:
269 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
270 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
271 return -EFAULT;
272 }
273 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
274 crtc = (struct drm_crtc *)minfo->crtcs[i];
275 if (crtc && crtc->base.id == *value) {
276 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
277 *value = radeon_crtc->crtc_id;
278 found = 1;
279 break;
280 }
281 }
282 if (!found) {
283 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
284 return -EINVAL;
285 }
286 break;
287 case RADEON_INFO_ACCEL_WORKING2:
288 if (rdev->family == CHIP_HAWAII) {
289 if (rdev->accel_working) {
290 if (rdev->new_fw)
291 *value = 3;
292 else
293 *value = 2;
294 } else {
295 *value = 0;
296 }
297 } else {
298 *value = rdev->accel_working;
299 }
300 break;
301 case RADEON_INFO_TILING_CONFIG:
302 if (rdev->family >= CHIP_BONAIRE)
303 *value = rdev->config.cik.tile_config;
304 else if (rdev->family >= CHIP_TAHITI)
305 *value = rdev->config.si.tile_config;
306 else if (rdev->family >= CHIP_CAYMAN)
307 *value = rdev->config.cayman.tile_config;
308 else if (rdev->family >= CHIP_CEDAR)
309 *value = rdev->config.evergreen.tile_config;
310 else if (rdev->family >= CHIP_RV770)
311 *value = rdev->config.rv770.tile_config;
312 else if (rdev->family >= CHIP_R600)
313 *value = rdev->config.r600.tile_config;
314 else {
315 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
316 return -EINVAL;
317 }
318 break;
319 case RADEON_INFO_WANT_HYPERZ:
320 /* The "value" here is both an input and output parameter.
321 * If the input value is 1, filp requests hyper-z access.
322 * If the input value is 0, filp revokes its hyper-z access.
323 *
324 * When returning, the value is 1 if filp owns hyper-z access,
325 * 0 otherwise. */
326 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
327 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
328 return -EFAULT;
329 }
330 if (*value >= 2) {
331 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
332 return -EINVAL;
333 }
334 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
335 break;
336 case RADEON_INFO_WANT_CMASK:
337 /* The same logic as Hyper-Z. */
338 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
339 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
340 return -EFAULT;
341 }
342 if (*value >= 2) {
343 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
344 return -EINVAL;
345 }
346 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
347 break;
348 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
349 /* return clock value in KHz */
350 if (rdev->asic->get_xclk)
351 *value = radeon_get_xclk(rdev) * 10;
352 else
353 *value = rdev->clock.spll.reference_freq * 10;
354 break;
355 case RADEON_INFO_NUM_BACKENDS:
356 if (rdev->family >= CHIP_BONAIRE)
357 *value = rdev->config.cik.max_backends_per_se *
358 rdev->config.cik.max_shader_engines;
359 else if (rdev->family >= CHIP_TAHITI)
360 *value = rdev->config.si.max_backends_per_se *
361 rdev->config.si.max_shader_engines;
362 else if (rdev->family >= CHIP_CAYMAN)
363 *value = rdev->config.cayman.max_backends_per_se *
364 rdev->config.cayman.max_shader_engines;
365 else if (rdev->family >= CHIP_CEDAR)
366 *value = rdev->config.evergreen.max_backends;
367 else if (rdev->family >= CHIP_RV770)
368 *value = rdev->config.rv770.max_backends;
369 else if (rdev->family >= CHIP_R600)
370 *value = rdev->config.r600.max_backends;
371 else {
372 return -EINVAL;
373 }
374 break;
375 case RADEON_INFO_NUM_TILE_PIPES:
376 if (rdev->family >= CHIP_BONAIRE)
377 *value = rdev->config.cik.max_tile_pipes;
378 else if (rdev->family >= CHIP_TAHITI)
379 *value = rdev->config.si.max_tile_pipes;
380 else if (rdev->family >= CHIP_CAYMAN)
381 *value = rdev->config.cayman.max_tile_pipes;
382 else if (rdev->family >= CHIP_CEDAR)
383 *value = rdev->config.evergreen.max_tile_pipes;
384 else if (rdev->family >= CHIP_RV770)
385 *value = rdev->config.rv770.max_tile_pipes;
386 else if (rdev->family >= CHIP_R600)
387 *value = rdev->config.r600.max_tile_pipes;
388 else {
389 return -EINVAL;
390 }
391 break;
392 case RADEON_INFO_FUSION_GART_WORKING:
393 *value = 1;
394 break;
395 case RADEON_INFO_BACKEND_MAP:
396 if (rdev->family >= CHIP_BONAIRE)
397 *value = rdev->config.cik.backend_map;
398 else if (rdev->family >= CHIP_TAHITI)
399 *value = rdev->config.si.backend_map;
400 else if (rdev->family >= CHIP_CAYMAN)
401 *value = rdev->config.cayman.backend_map;
402 else if (rdev->family >= CHIP_CEDAR)
403 *value = rdev->config.evergreen.backend_map;
404 else if (rdev->family >= CHIP_RV770)
405 *value = rdev->config.rv770.backend_map;
406 else if (rdev->family >= CHIP_R600)
407 *value = rdev->config.r600.backend_map;
408 else {
409 return -EINVAL;
410 }
411 break;
412 case RADEON_INFO_VA_START:
413 /* this is where we report if vm is supported or not */
414 if (rdev->family < CHIP_CAYMAN)
415 return -EINVAL;
416 *value = RADEON_VA_RESERVED_SIZE;
417 break;
418 case RADEON_INFO_IB_VM_MAX_SIZE:
419 /* this is where we report if vm is supported or not */
420 if (rdev->family < CHIP_CAYMAN)
421 return -EINVAL;
422 *value = RADEON_IB_VM_MAX_SIZE;
423 break;
424 case RADEON_INFO_MAX_PIPES:
425 if (rdev->family >= CHIP_BONAIRE)
426 *value = rdev->config.cik.max_cu_per_sh;
427 else if (rdev->family >= CHIP_TAHITI)
428 *value = rdev->config.si.max_cu_per_sh;
429 else if (rdev->family >= CHIP_CAYMAN)
430 *value = rdev->config.cayman.max_pipes_per_simd;
431 else if (rdev->family >= CHIP_CEDAR)
432 *value = rdev->config.evergreen.max_pipes;
433 else if (rdev->family >= CHIP_RV770)
434 *value = rdev->config.rv770.max_pipes;
435 else if (rdev->family >= CHIP_R600)
436 *value = rdev->config.r600.max_pipes;
437 else {
438 return -EINVAL;
439 }
440 break;
441 case RADEON_INFO_TIMESTAMP:
442 if (rdev->family < CHIP_R600) {
443 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
444 return -EINVAL;
445 }
446 value = (uint32_t*)&value64;
447 value_size = sizeof(uint64_t);
448 value64 = radeon_get_gpu_clock_counter(rdev);
449 break;
450 case RADEON_INFO_MAX_SE:
451 if (rdev->family >= CHIP_BONAIRE)
452 *value = rdev->config.cik.max_shader_engines;
453 else if (rdev->family >= CHIP_TAHITI)
454 *value = rdev->config.si.max_shader_engines;
455 else if (rdev->family >= CHIP_CAYMAN)
456 *value = rdev->config.cayman.max_shader_engines;
457 else if (rdev->family >= CHIP_CEDAR)
458 *value = rdev->config.evergreen.num_ses;
459 else
460 *value = 1;
461 break;
462 case RADEON_INFO_MAX_SH_PER_SE:
463 if (rdev->family >= CHIP_BONAIRE)
464 *value = rdev->config.cik.max_sh_per_se;
465 else if (rdev->family >= CHIP_TAHITI)
466 *value = rdev->config.si.max_sh_per_se;
467 else
468 return -EINVAL;
469 break;
470 case RADEON_INFO_FASTFB_WORKING:
471 *value = rdev->fastfb_working;
472 break;
473 case RADEON_INFO_RING_WORKING:
474 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
475 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
476 return -EFAULT;
477 }
478 switch (*value) {
479 case RADEON_CS_RING_GFX:
480 case RADEON_CS_RING_COMPUTE:
481 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
482 break;
483 case RADEON_CS_RING_DMA:
484 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
485 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
486 break;
487 case RADEON_CS_RING_UVD:
488 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
489 break;
490 case RADEON_CS_RING_VCE:
491 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
492 break;
493 default:
494 return -EINVAL;
495 }
496 break;
497 case RADEON_INFO_SI_TILE_MODE_ARRAY:
498 if (rdev->family >= CHIP_BONAIRE) {
499 value = rdev->config.cik.tile_mode_array;
500 value_size = sizeof(uint32_t)*32;
501 } else if (rdev->family >= CHIP_TAHITI) {
502 value = rdev->config.si.tile_mode_array;
503 value_size = sizeof(uint32_t)*32;
504 } else {
505 DRM_DEBUG_KMS("tile mode array is si+ only!\n");
506 return -EINVAL;
507 }
508 break;
509 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
510 if (rdev->family >= CHIP_BONAIRE) {
511 value = rdev->config.cik.macrotile_mode_array;
512 value_size = sizeof(uint32_t)*16;
513 } else {
514 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
515 return -EINVAL;
516 }
517 break;
518 case RADEON_INFO_SI_CP_DMA_COMPUTE:
519 *value = 1;
520 break;
521 case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
522 if (rdev->family >= CHIP_BONAIRE) {
523 *value = rdev->config.cik.backend_enable_mask;
524 } else if (rdev->family >= CHIP_TAHITI) {
525 *value = rdev->config.si.backend_enable_mask;
526 } else {
527 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
528 }
529 break;
530 case RADEON_INFO_MAX_SCLK:
531 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
532 rdev->pm.dpm_enabled)
533 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
534 else
535 *value = rdev->pm.default_sclk * 10;
536 break;
537 case RADEON_INFO_VCE_FW_VERSION:
538 *value = rdev->vce.fw_version;
539 break;
540 case RADEON_INFO_VCE_FB_VERSION:
541 *value = rdev->vce.fb_version;
542 break;
543 case RADEON_INFO_NUM_BYTES_MOVED:
544 value = (uint32_t*)&value64;
545 value_size = sizeof(uint64_t);
546 value64 = atomic64_read(&rdev->num_bytes_moved);
547 break;
548 case RADEON_INFO_VRAM_USAGE:
549 value = (uint32_t*)&value64;
550 value_size = sizeof(uint64_t);
551 value64 = atomic64_read(&rdev->vram_usage);
552 break;
553 case RADEON_INFO_GTT_USAGE:
554 value = (uint32_t*)&value64;
555 value_size = sizeof(uint64_t);
556 value64 = atomic64_read(&rdev->gtt_usage);
557 break;
558 case RADEON_INFO_ACTIVE_CU_COUNT:
559 if (rdev->family >= CHIP_BONAIRE)
560 *value = rdev->config.cik.active_cus;
561 else if (rdev->family >= CHIP_TAHITI)
562 *value = rdev->config.si.active_cus;
563 else if (rdev->family >= CHIP_CAYMAN)
564 *value = rdev->config.cayman.active_simds;
565 else if (rdev->family >= CHIP_CEDAR)
566 *value = rdev->config.evergreen.active_simds;
567 else if (rdev->family >= CHIP_RV770)
568 *value = rdev->config.rv770.active_simds;
569 else if (rdev->family >= CHIP_R600)
570 *value = rdev->config.r600.active_simds;
571 else
572 *value = 1;
573 break;
574 case RADEON_INFO_CURRENT_GPU_TEMP:
575 /* get temperature in millidegrees C */
576 if (rdev->asic->pm.get_temperature)
577 *value = radeon_get_temperature(rdev);
578 else
579 *value = 0;
580 break;
581 case RADEON_INFO_CURRENT_GPU_SCLK:
582 /* get sclk in Mhz */
583 if (rdev->pm.dpm_enabled)
584 *value = radeon_dpm_get_current_sclk(rdev) / 100;
585 else
586 *value = rdev->pm.current_sclk / 100;
587 break;
588 case RADEON_INFO_CURRENT_GPU_MCLK:
589 /* get mclk in Mhz */
590 if (rdev->pm.dpm_enabled)
591 *value = radeon_dpm_get_current_mclk(rdev) / 100;
592 else
593 *value = rdev->pm.current_mclk / 100;
594 break;
595 case RADEON_INFO_READ_REG:
596 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
597 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
598 return -EFAULT;
599 }
600 if (radeon_get_allowed_info_register(rdev, *value, value))
601 return -EINVAL;
602 break;
603 case RADEON_INFO_VA_UNMAP_WORKING:
604 *value = true;
605 break;
606 case RADEON_INFO_GPU_RESET_COUNTER:
607 *value = atomic_read(&rdev->gpu_reset_counter);
608 break;
609 default:
610 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
611 return -EINVAL;
612 }
613 if (copy_to_user(value_ptr, (char*)value, value_size)) {
614 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
615 return -EFAULT;
616 }
617 return 0;
618}
619
620
621/*
622 * Outdated mess for old drm with Xorg being in charge (void function now).
623 */
624/**
625 * radeon_driver_lastclose_kms - drm callback for last close
626 *
627 * @dev: drm dev pointer
628 *
629 * Switch vga_switcheroo state after last close (all asics).
630 */
631void radeon_driver_lastclose_kms(struct drm_device *dev)
632{
633 drm_fb_helper_lastclose(dev);
634 vga_switcheroo_process_delayed_switch();
635}
636
637/**
638 * radeon_driver_open_kms - drm callback for open
639 *
640 * @dev: drm dev pointer
641 * @file_priv: drm file
642 *
643 * On device open, init vm on cayman+ (all asics).
644 * Returns 0 on success, error on failure.
645 */
646int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
647{
648 struct radeon_device *rdev = dev->dev_private;
649 int r;
650
651 file_priv->driver_priv = NULL;
652
653 r = pm_runtime_get_sync(dev->dev);
654 if (r < 0)
655 return r;
656
657 /* new gpu have virtual address space support */
658 if (rdev->family >= CHIP_CAYMAN) {
659 struct radeon_fpriv *fpriv;
660 struct radeon_vm *vm;
661
662 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
663 if (unlikely(!fpriv)) {
664 r = -ENOMEM;
665 goto out_suspend;
666 }
667
668 if (rdev->accel_working) {
669 vm = &fpriv->vm;
670 r = radeon_vm_init(rdev, vm);
671 if (r) {
672 kfree(fpriv);
673 goto out_suspend;
674 }
675
676 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
677 if (r) {
678 radeon_vm_fini(rdev, vm);
679 kfree(fpriv);
680 goto out_suspend;
681 }
682
683 /* map the ib pool buffer read only into
684 * virtual address space */
685 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
686 rdev->ring_tmp_bo.bo);
687 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
688 RADEON_VA_IB_OFFSET,
689 RADEON_VM_PAGE_READABLE |
690 RADEON_VM_PAGE_SNOOPED);
691 if (r) {
692 radeon_vm_fini(rdev, vm);
693 kfree(fpriv);
694 goto out_suspend;
695 }
696 }
697 file_priv->driver_priv = fpriv;
698 }
699
700out_suspend:
701 pm_runtime_mark_last_busy(dev->dev);
702 pm_runtime_put_autosuspend(dev->dev);
703 return r;
704}
705
706/**
707 * radeon_driver_postclose_kms - drm callback for post close
708 *
709 * @dev: drm dev pointer
710 * @file_priv: drm file
711 *
712 * On device close, tear down hyperz and cmask filps on r1xx-r5xx
713 * (all asics). And tear down vm on cayman+ (all asics).
714 */
715void radeon_driver_postclose_kms(struct drm_device *dev,
716 struct drm_file *file_priv)
717{
718 struct radeon_device *rdev = dev->dev_private;
719
720 pm_runtime_get_sync(dev->dev);
721
722 mutex_lock(&rdev->gem.mutex);
723 if (rdev->hyperz_filp == file_priv)
724 rdev->hyperz_filp = NULL;
725 if (rdev->cmask_filp == file_priv)
726 rdev->cmask_filp = NULL;
727 mutex_unlock(&rdev->gem.mutex);
728
729 radeon_uvd_free_handles(rdev, file_priv);
730 radeon_vce_free_handles(rdev, file_priv);
731
732 /* new gpu have virtual address space support */
733 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
734 struct radeon_fpriv *fpriv = file_priv->driver_priv;
735 struct radeon_vm *vm = &fpriv->vm;
736 int r;
737
738 if (rdev->accel_working) {
739 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
740 if (!r) {
741 if (vm->ib_bo_va)
742 radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
743 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
744 }
745 radeon_vm_fini(rdev, vm);
746 }
747
748 kfree(fpriv);
749 file_priv->driver_priv = NULL;
750 }
751 pm_runtime_mark_last_busy(dev->dev);
752 pm_runtime_put_autosuspend(dev->dev);
753}
754
755/*
756 * VBlank related functions.
757 */
758/**
759 * radeon_get_vblank_counter_kms - get frame count
760 *
761 * @dev: drm dev pointer
762 * @pipe: crtc to get the frame count from
763 *
764 * Gets the frame count on the requested crtc (all asics).
765 * Returns frame count on success, -EINVAL on failure.
766 */
767u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
768{
769 int vpos, hpos, stat;
770 u32 count;
771 struct radeon_device *rdev = dev->dev_private;
772
773 if (pipe >= rdev->num_crtc) {
774 DRM_ERROR("Invalid crtc %u\n", pipe);
775 return -EINVAL;
776 }
777
778 /* The hw increments its frame counter at start of vsync, not at start
779 * of vblank, as is required by DRM core vblank counter handling.
780 * Cook the hw count here to make it appear to the caller as if it
781 * incremented at start of vblank. We measure distance to start of
782 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
783 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
784 * result by 1 to give the proper appearance to caller.
785 */
786 if (rdev->mode_info.crtcs[pipe]) {
787 /* Repeat readout if needed to provide stable result if
788 * we cross start of vsync during the queries.
789 */
790 do {
791 count = radeon_get_vblank_counter(rdev, pipe);
792 /* Ask radeon_get_crtc_scanoutpos to return vpos as
793 * distance to start of vblank, instead of regular
794 * vertical scanout pos.
795 */
796 stat = radeon_get_crtc_scanoutpos(
797 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
798 &vpos, &hpos, NULL, NULL,
799 &rdev->mode_info.crtcs[pipe]->base.hwmode);
800 } while (count != radeon_get_vblank_counter(rdev, pipe));
801
802 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
803 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
804 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
805 }
806 else {
807 DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n",
808 pipe, vpos);
809
810 /* Bump counter if we are at >= leading edge of vblank,
811 * but before vsync where vpos would turn negative and
812 * the hw counter really increments.
813 */
814 if (vpos >= 0)
815 count++;
816 }
817 }
818 else {
819 /* Fallback to use value as is. */
820 count = radeon_get_vblank_counter(rdev, pipe);
821 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
822 }
823
824 return count;
825}
826
827/**
828 * radeon_enable_vblank_kms - enable vblank interrupt
829 *
830 * @dev: drm dev pointer
831 * @crtc: crtc to enable vblank interrupt for
832 *
833 * Enable the interrupt on the requested crtc (all asics).
834 * Returns 0 on success, -EINVAL on failure.
835 */
836int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
837{
838 struct radeon_device *rdev = dev->dev_private;
839 unsigned long irqflags;
840 int r;
841
842 if (crtc < 0 || crtc >= rdev->num_crtc) {
843 DRM_ERROR("Invalid crtc %d\n", crtc);
844 return -EINVAL;
845 }
846
847 spin_lock_irqsave(&rdev->irq.lock, irqflags);
848 rdev->irq.crtc_vblank_int[crtc] = true;
849 r = radeon_irq_set(rdev);
850 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
851 return r;
852}
853
854/**
855 * radeon_disable_vblank_kms - disable vblank interrupt
856 *
857 * @dev: drm dev pointer
858 * @crtc: crtc to disable vblank interrupt for
859 *
860 * Disable the interrupt on the requested crtc (all asics).
861 */
862void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
863{
864 struct radeon_device *rdev = dev->dev_private;
865 unsigned long irqflags;
866
867 if (crtc < 0 || crtc >= rdev->num_crtc) {
868 DRM_ERROR("Invalid crtc %d\n", crtc);
869 return;
870 }
871
872 spin_lock_irqsave(&rdev->irq.lock, irqflags);
873 rdev->irq.crtc_vblank_int[crtc] = false;
874 radeon_irq_set(rdev);
875 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
876}
877
878const struct drm_ioctl_desc radeon_ioctls_kms[] = {
879 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
880 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
881 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
882 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
883 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
884 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
885 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
886 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
887 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
888 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
889 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
890 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
891 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
892 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
893 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
894 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
895 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
896 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
897 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
898 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
899 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
900 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
901 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
902 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
903 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
904 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
905 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
906 /* KMS */
907 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
908 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
909 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
910 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
911 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
912 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
913 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
914 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
915 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
916 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
917 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
918 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
919 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
920 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
921 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
922};
923int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms);