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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
29#include "drm_sarea.h"
30#include "radeon.h"
31#include "radeon_drm.h"
32
33#include <linux/vga_switcheroo.h>
34#include <linux/slab.h>
35
36int radeon_driver_unload_kms(struct drm_device *dev)
37{
38 struct radeon_device *rdev = dev->dev_private;
39
40 if (rdev == NULL)
41 return 0;
42 radeon_modeset_fini(rdev);
43 radeon_device_fini(rdev);
44 kfree(rdev);
45 dev->dev_private = NULL;
46 return 0;
47}
48
49int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
50{
51 struct radeon_device *rdev;
52 int r, acpi_status;
53
54 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
55 if (rdev == NULL) {
56 return -ENOMEM;
57 }
58 dev->dev_private = (void *)rdev;
59
60 /* update BUS flag */
61 if (drm_pci_device_is_agp(dev)) {
62 flags |= RADEON_IS_AGP;
63 } else if (pci_is_pcie(dev->pdev)) {
64 flags |= RADEON_IS_PCIE;
65 } else {
66 flags |= RADEON_IS_PCI;
67 }
68
69 /* radeon_device_init should report only fatal error
70 * like memory allocation failure or iomapping failure,
71 * or memory manager initialization failure, it must
72 * properly initialize the GPU MC controller and permit
73 * VRAM allocation
74 */
75 r = radeon_device_init(rdev, dev, dev->pdev, flags);
76 if (r) {
77 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
78 goto out;
79 }
80
81 /* Call ACPI methods */
82 acpi_status = radeon_acpi_init(rdev);
83 if (acpi_status)
84 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
85
86 /* Again modeset_init should fail only on fatal error
87 * otherwise it should provide enough functionalities
88 * for shadowfb to run
89 */
90 r = radeon_modeset_init(rdev);
91 if (r)
92 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
93out:
94 if (r)
95 radeon_driver_unload_kms(dev);
96 return r;
97}
98
99static void radeon_set_filp_rights(struct drm_device *dev,
100 struct drm_file **owner,
101 struct drm_file *applier,
102 uint32_t *value)
103{
104 mutex_lock(&dev->struct_mutex);
105 if (*value == 1) {
106 /* wants rights */
107 if (!*owner)
108 *owner = applier;
109 } else if (*value == 0) {
110 /* revokes rights */
111 if (*owner == applier)
112 *owner = NULL;
113 }
114 *value = *owner == applier ? 1 : 0;
115 mutex_unlock(&dev->struct_mutex);
116}
117
118/*
119 * Userspace get information ioctl
120 */
121int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
122{
123 struct radeon_device *rdev = dev->dev_private;
124 struct drm_radeon_info *info;
125 struct radeon_mode_info *minfo = &rdev->mode_info;
126 uint32_t *value_ptr;
127 uint32_t value;
128 struct drm_crtc *crtc;
129 int i, found;
130
131 info = data;
132 value_ptr = (uint32_t *)((unsigned long)info->value);
133 if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value)))
134 return -EFAULT;
135
136 switch (info->request) {
137 case RADEON_INFO_DEVICE_ID:
138 value = dev->pci_device;
139 break;
140 case RADEON_INFO_NUM_GB_PIPES:
141 value = rdev->num_gb_pipes;
142 break;
143 case RADEON_INFO_NUM_Z_PIPES:
144 value = rdev->num_z_pipes;
145 break;
146 case RADEON_INFO_ACCEL_WORKING:
147 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
148 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
149 value = false;
150 else
151 value = rdev->accel_working;
152 break;
153 case RADEON_INFO_CRTC_FROM_ID:
154 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
155 crtc = (struct drm_crtc *)minfo->crtcs[i];
156 if (crtc && crtc->base.id == value) {
157 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
158 value = radeon_crtc->crtc_id;
159 found = 1;
160 break;
161 }
162 }
163 if (!found) {
164 DRM_DEBUG_KMS("unknown crtc id %d\n", value);
165 return -EINVAL;
166 }
167 break;
168 case RADEON_INFO_ACCEL_WORKING2:
169 value = rdev->accel_working;
170 break;
171 case RADEON_INFO_TILING_CONFIG:
172 if (rdev->family >= CHIP_CAYMAN)
173 value = rdev->config.cayman.tile_config;
174 else if (rdev->family >= CHIP_CEDAR)
175 value = rdev->config.evergreen.tile_config;
176 else if (rdev->family >= CHIP_RV770)
177 value = rdev->config.rv770.tile_config;
178 else if (rdev->family >= CHIP_R600)
179 value = rdev->config.r600.tile_config;
180 else {
181 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
182 return -EINVAL;
183 }
184 break;
185 case RADEON_INFO_WANT_HYPERZ:
186 /* The "value" here is both an input and output parameter.
187 * If the input value is 1, filp requests hyper-z access.
188 * If the input value is 0, filp revokes its hyper-z access.
189 *
190 * When returning, the value is 1 if filp owns hyper-z access,
191 * 0 otherwise. */
192 if (value >= 2) {
193 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
194 return -EINVAL;
195 }
196 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value);
197 break;
198 case RADEON_INFO_WANT_CMASK:
199 /* The same logic as Hyper-Z. */
200 if (value >= 2) {
201 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value);
202 return -EINVAL;
203 }
204 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value);
205 break;
206 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
207 /* return clock value in KHz */
208 value = rdev->clock.spll.reference_freq * 10;
209 break;
210 case RADEON_INFO_NUM_BACKENDS:
211 if (rdev->family >= CHIP_CAYMAN)
212 value = rdev->config.cayman.max_backends_per_se *
213 rdev->config.cayman.max_shader_engines;
214 else if (rdev->family >= CHIP_CEDAR)
215 value = rdev->config.evergreen.max_backends;
216 else if (rdev->family >= CHIP_RV770)
217 value = rdev->config.rv770.max_backends;
218 else if (rdev->family >= CHIP_R600)
219 value = rdev->config.r600.max_backends;
220 else {
221 return -EINVAL;
222 }
223 break;
224 case RADEON_INFO_NUM_TILE_PIPES:
225 if (rdev->family >= CHIP_CAYMAN)
226 value = rdev->config.cayman.max_tile_pipes;
227 else if (rdev->family >= CHIP_CEDAR)
228 value = rdev->config.evergreen.max_tile_pipes;
229 else if (rdev->family >= CHIP_RV770)
230 value = rdev->config.rv770.max_tile_pipes;
231 else if (rdev->family >= CHIP_R600)
232 value = rdev->config.r600.max_tile_pipes;
233 else {
234 return -EINVAL;
235 }
236 break;
237 case RADEON_INFO_FUSION_GART_WORKING:
238 value = 1;
239 break;
240 case RADEON_INFO_BACKEND_MAP:
241 if (rdev->family >= CHIP_CAYMAN)
242 value = rdev->config.cayman.backend_map;
243 else if (rdev->family >= CHIP_CEDAR)
244 value = rdev->config.evergreen.backend_map;
245 else if (rdev->family >= CHIP_RV770)
246 value = rdev->config.rv770.backend_map;
247 else if (rdev->family >= CHIP_R600)
248 value = rdev->config.r600.backend_map;
249 else {
250 return -EINVAL;
251 }
252 break;
253 default:
254 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
255 return -EINVAL;
256 }
257 if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
258 DRM_ERROR("copy_to_user\n");
259 return -EFAULT;
260 }
261 return 0;
262}
263
264
265/*
266 * Outdated mess for old drm with Xorg being in charge (void function now).
267 */
268int radeon_driver_firstopen_kms(struct drm_device *dev)
269{
270 return 0;
271}
272
273
274void radeon_driver_lastclose_kms(struct drm_device *dev)
275{
276 vga_switcheroo_process_delayed_switch();
277}
278
279int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
280{
281 return 0;
282}
283
284void radeon_driver_postclose_kms(struct drm_device *dev,
285 struct drm_file *file_priv)
286{
287}
288
289void radeon_driver_preclose_kms(struct drm_device *dev,
290 struct drm_file *file_priv)
291{
292 struct radeon_device *rdev = dev->dev_private;
293 if (rdev->hyperz_filp == file_priv)
294 rdev->hyperz_filp = NULL;
295 if (rdev->cmask_filp == file_priv)
296 rdev->cmask_filp = NULL;
297}
298
299/*
300 * VBlank related functions.
301 */
302u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
303{
304 struct radeon_device *rdev = dev->dev_private;
305
306 if (crtc < 0 || crtc >= rdev->num_crtc) {
307 DRM_ERROR("Invalid crtc %d\n", crtc);
308 return -EINVAL;
309 }
310
311 return radeon_get_vblank_counter(rdev, crtc);
312}
313
314int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
315{
316 struct radeon_device *rdev = dev->dev_private;
317
318 if (crtc < 0 || crtc >= rdev->num_crtc) {
319 DRM_ERROR("Invalid crtc %d\n", crtc);
320 return -EINVAL;
321 }
322
323 rdev->irq.crtc_vblank_int[crtc] = true;
324
325 return radeon_irq_set(rdev);
326}
327
328void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
329{
330 struct radeon_device *rdev = dev->dev_private;
331
332 if (crtc < 0 || crtc >= rdev->num_crtc) {
333 DRM_ERROR("Invalid crtc %d\n", crtc);
334 return;
335 }
336
337 rdev->irq.crtc_vblank_int[crtc] = false;
338
339 radeon_irq_set(rdev);
340}
341
342int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
343 int *max_error,
344 struct timeval *vblank_time,
345 unsigned flags)
346{
347 struct drm_crtc *drmcrtc;
348 struct radeon_device *rdev = dev->dev_private;
349
350 if (crtc < 0 || crtc >= dev->num_crtcs) {
351 DRM_ERROR("Invalid crtc %d\n", crtc);
352 return -EINVAL;
353 }
354
355 /* Get associated drm_crtc: */
356 drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
357
358 /* Helper routine in DRM core does all the work: */
359 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
360 vblank_time, flags,
361 drmcrtc);
362}
363
364/*
365 * IOCTL.
366 */
367int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
368 struct drm_file *file_priv)
369{
370 /* Not valid in KMS. */
371 return -EINVAL;
372}
373
374#define KMS_INVALID_IOCTL(name) \
375int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
376{ \
377 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
378 return -EINVAL; \
379}
380
381/*
382 * All these ioctls are invalid in kms world.
383 */
384KMS_INVALID_IOCTL(radeon_cp_init_kms)
385KMS_INVALID_IOCTL(radeon_cp_start_kms)
386KMS_INVALID_IOCTL(radeon_cp_stop_kms)
387KMS_INVALID_IOCTL(radeon_cp_reset_kms)
388KMS_INVALID_IOCTL(radeon_cp_idle_kms)
389KMS_INVALID_IOCTL(radeon_cp_resume_kms)
390KMS_INVALID_IOCTL(radeon_engine_reset_kms)
391KMS_INVALID_IOCTL(radeon_fullscreen_kms)
392KMS_INVALID_IOCTL(radeon_cp_swap_kms)
393KMS_INVALID_IOCTL(radeon_cp_clear_kms)
394KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
395KMS_INVALID_IOCTL(radeon_cp_indices_kms)
396KMS_INVALID_IOCTL(radeon_cp_texture_kms)
397KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
398KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
399KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
400KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
401KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
402KMS_INVALID_IOCTL(radeon_cp_flip_kms)
403KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
404KMS_INVALID_IOCTL(radeon_mem_free_kms)
405KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
406KMS_INVALID_IOCTL(radeon_irq_emit_kms)
407KMS_INVALID_IOCTL(radeon_irq_wait_kms)
408KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
409KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
410KMS_INVALID_IOCTL(radeon_surface_free_kms)
411
412
413struct drm_ioctl_desc radeon_ioctls_kms[] = {
414 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
415 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
416 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
417 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
418 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
419 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
420 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
421 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
422 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
423 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
424 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
425 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
426 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
427 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
428 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
429 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
430 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
431 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
432 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
433 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
434 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
435 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
436 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
437 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
438 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
439 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
440 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
441 /* KMS */
442 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
443 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
444 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
445 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
446 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
447 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
448 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
449 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
450 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
451 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
452 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
453 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
454};
455int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/pci.h>
30#include <linux/pm_runtime.h>
31#include <linux/slab.h>
32#include <linux/uaccess.h>
33#include <linux/vga_switcheroo.h>
34
35#include <drm/drm_fb_helper.h>
36#include <drm/drm_file.h>
37#include <drm/drm_ioctl.h>
38#include <drm/radeon_drm.h>
39
40#include "radeon.h"
41#include "radeon_asic.h"
42#include "radeon_drv.h"
43#include "radeon_kms.h"
44
45#if defined(CONFIG_VGA_SWITCHEROO)
46bool radeon_has_atpx(void);
47#else
48static inline bool radeon_has_atpx(void) { return false; }
49#endif
50
51/**
52 * radeon_driver_unload_kms - Main unload function for KMS.
53 *
54 * @dev: drm dev pointer
55 *
56 * This is the main unload function for KMS (all asics).
57 * It calls radeon_modeset_fini() to tear down the
58 * displays, and radeon_device_fini() to tear down
59 * the rest of the device (CP, writeback, etc.).
60 * Returns 0 on success.
61 */
62void radeon_driver_unload_kms(struct drm_device *dev)
63{
64 struct radeon_device *rdev = dev->dev_private;
65
66 if (rdev == NULL)
67 return;
68
69 if (rdev->rmmio == NULL)
70 goto done_free;
71
72 if (radeon_is_px(dev)) {
73 pm_runtime_get_sync(dev->dev);
74 pm_runtime_forbid(dev->dev);
75 }
76
77 radeon_acpi_fini(rdev);
78
79 radeon_modeset_fini(rdev);
80 radeon_device_fini(rdev);
81
82 if (rdev->agp)
83 arch_phys_wc_del(rdev->agp->agp_mtrr);
84 kfree(rdev->agp);
85 rdev->agp = NULL;
86
87done_free:
88 kfree(rdev);
89 dev->dev_private = NULL;
90}
91
92/**
93 * radeon_driver_load_kms - Main load function for KMS.
94 *
95 * @dev: drm dev pointer
96 * @flags: device flags
97 *
98 * This is the main load function for KMS (all asics).
99 * It calls radeon_device_init() to set up the non-display
100 * parts of the chip (asic init, CP, writeback, etc.), and
101 * radeon_modeset_init() to set up the display parts
102 * (crtcs, encoders, hotplug detect, etc.).
103 * Returns 0 on success, error on failure.
104 */
105int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
106{
107 struct pci_dev *pdev = to_pci_dev(dev->dev);
108 struct radeon_device *rdev;
109 int r, acpi_status;
110
111 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
112 if (rdev == NULL) {
113 return -ENOMEM;
114 }
115 dev->dev_private = (void *)rdev;
116
117#ifdef __alpha__
118 rdev->hose = pdev->sysdata;
119#endif
120
121 if (pci_find_capability(pdev, PCI_CAP_ID_AGP))
122 rdev->agp = radeon_agp_head_init(dev);
123 if (rdev->agp) {
124 rdev->agp->agp_mtrr = arch_phys_wc_add(
125 rdev->agp->agp_info.aper_base,
126 rdev->agp->agp_info.aper_size *
127 1024 * 1024);
128 }
129
130 /* update BUS flag */
131 if (pci_find_capability(pdev, PCI_CAP_ID_AGP)) {
132 flags |= RADEON_IS_AGP;
133 } else if (pci_is_pcie(pdev)) {
134 flags |= RADEON_IS_PCIE;
135 } else {
136 flags |= RADEON_IS_PCI;
137 }
138
139 if ((radeon_runtime_pm != 0) &&
140 radeon_has_atpx() &&
141 ((flags & RADEON_IS_IGP) == 0) &&
142 !pci_is_thunderbolt_attached(pdev))
143 flags |= RADEON_IS_PX;
144
145 /* radeon_device_init should report only fatal error
146 * like memory allocation failure or iomapping failure,
147 * or memory manager initialization failure, it must
148 * properly initialize the GPU MC controller and permit
149 * VRAM allocation
150 */
151 r = radeon_device_init(rdev, dev, pdev, flags);
152 if (r) {
153 dev_err(dev->dev, "Fatal error during GPU init\n");
154 goto out;
155 }
156
157 /* Again modeset_init should fail only on fatal error
158 * otherwise it should provide enough functionalities
159 * for shadowfb to run
160 */
161 r = radeon_modeset_init(rdev);
162 if (r)
163 dev_err(dev->dev, "Fatal error during modeset init\n");
164
165 /* Call ACPI methods: require modeset init
166 * but failure is not fatal
167 */
168 if (!r) {
169 acpi_status = radeon_acpi_init(rdev);
170 if (acpi_status)
171 dev_dbg(dev->dev, "Error during ACPI methods call\n");
172 }
173
174 if (radeon_is_px(dev)) {
175 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
176 pm_runtime_use_autosuspend(dev->dev);
177 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
178 pm_runtime_set_active(dev->dev);
179 pm_runtime_allow(dev->dev);
180 pm_runtime_mark_last_busy(dev->dev);
181 pm_runtime_put_autosuspend(dev->dev);
182 }
183
184out:
185 if (r)
186 radeon_driver_unload_kms(dev);
187
188
189 return r;
190}
191
192/**
193 * radeon_set_filp_rights - Set filp right.
194 *
195 * @dev: drm dev pointer
196 * @owner: drm file
197 * @applier: drm file
198 * @value: value
199 *
200 * Sets the filp rights for the device (all asics).
201 */
202static void radeon_set_filp_rights(struct drm_device *dev,
203 struct drm_file **owner,
204 struct drm_file *applier,
205 uint32_t *value)
206{
207 struct radeon_device *rdev = dev->dev_private;
208
209 mutex_lock(&rdev->gem.mutex);
210 if (*value == 1) {
211 /* wants rights */
212 if (!*owner)
213 *owner = applier;
214 } else if (*value == 0) {
215 /* revokes rights */
216 if (*owner == applier)
217 *owner = NULL;
218 }
219 *value = *owner == applier ? 1 : 0;
220 mutex_unlock(&rdev->gem.mutex);
221}
222
223/*
224 * Userspace get information ioctl
225 */
226/**
227 * radeon_info_ioctl - answer a device specific request.
228 *
229 * @dev: drm device pointer
230 * @data: request object
231 * @filp: drm filp
232 *
233 * This function is used to pass device specific parameters to the userspace
234 * drivers. Examples include: pci device id, pipeline parms, tiling params,
235 * etc. (all asics).
236 * Returns 0 on success, -EINVAL on failure.
237 */
238int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
239{
240 struct radeon_device *rdev = dev->dev_private;
241 struct drm_radeon_info *info = data;
242 struct radeon_mode_info *minfo = &rdev->mode_info;
243 uint32_t *value, value_tmp, *value_ptr, value_size;
244 uint64_t value64;
245 struct drm_crtc *crtc;
246 int i, found;
247
248 value_ptr = (uint32_t *)((unsigned long)info->value);
249 value = &value_tmp;
250 value_size = sizeof(uint32_t);
251
252 switch (info->request) {
253 case RADEON_INFO_DEVICE_ID:
254 *value = to_pci_dev(dev->dev)->device;
255 break;
256 case RADEON_INFO_NUM_GB_PIPES:
257 *value = rdev->num_gb_pipes;
258 break;
259 case RADEON_INFO_NUM_Z_PIPES:
260 *value = rdev->num_z_pipes;
261 break;
262 case RADEON_INFO_ACCEL_WORKING:
263 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
264 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
265 *value = false;
266 else
267 *value = rdev->accel_working;
268 break;
269 case RADEON_INFO_CRTC_FROM_ID:
270 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
271 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
272 return -EFAULT;
273 }
274 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
275 crtc = (struct drm_crtc *)minfo->crtcs[i];
276 if (crtc && crtc->base.id == *value) {
277 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
278 *value = radeon_crtc->crtc_id;
279 found = 1;
280 break;
281 }
282 }
283 if (!found) {
284 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
285 return -EINVAL;
286 }
287 break;
288 case RADEON_INFO_ACCEL_WORKING2:
289 if (rdev->family == CHIP_HAWAII) {
290 if (rdev->accel_working) {
291 if (rdev->new_fw)
292 *value = 3;
293 else
294 *value = 2;
295 } else {
296 *value = 0;
297 }
298 } else {
299 *value = rdev->accel_working;
300 }
301 break;
302 case RADEON_INFO_TILING_CONFIG:
303 if (rdev->family >= CHIP_BONAIRE)
304 *value = rdev->config.cik.tile_config;
305 else if (rdev->family >= CHIP_TAHITI)
306 *value = rdev->config.si.tile_config;
307 else if (rdev->family >= CHIP_CAYMAN)
308 *value = rdev->config.cayman.tile_config;
309 else if (rdev->family >= CHIP_CEDAR)
310 *value = rdev->config.evergreen.tile_config;
311 else if (rdev->family >= CHIP_RV770)
312 *value = rdev->config.rv770.tile_config;
313 else if (rdev->family >= CHIP_R600)
314 *value = rdev->config.r600.tile_config;
315 else {
316 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
317 return -EINVAL;
318 }
319 break;
320 case RADEON_INFO_WANT_HYPERZ:
321 /* The "value" here is both an input and output parameter.
322 * If the input value is 1, filp requests hyper-z access.
323 * If the input value is 0, filp revokes its hyper-z access.
324 *
325 * When returning, the value is 1 if filp owns hyper-z access,
326 * 0 otherwise. */
327 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
328 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
329 return -EFAULT;
330 }
331 if (*value >= 2) {
332 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
333 return -EINVAL;
334 }
335 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
336 break;
337 case RADEON_INFO_WANT_CMASK:
338 /* The same logic as Hyper-Z. */
339 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
340 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
341 return -EFAULT;
342 }
343 if (*value >= 2) {
344 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
345 return -EINVAL;
346 }
347 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
348 break;
349 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
350 /* return clock value in KHz */
351 if (rdev->asic->get_xclk)
352 *value = radeon_get_xclk(rdev) * 10;
353 else
354 *value = rdev->clock.spll.reference_freq * 10;
355 break;
356 case RADEON_INFO_NUM_BACKENDS:
357 if (rdev->family >= CHIP_BONAIRE)
358 *value = rdev->config.cik.max_backends_per_se *
359 rdev->config.cik.max_shader_engines;
360 else if (rdev->family >= CHIP_TAHITI)
361 *value = rdev->config.si.max_backends_per_se *
362 rdev->config.si.max_shader_engines;
363 else if (rdev->family >= CHIP_CAYMAN)
364 *value = rdev->config.cayman.max_backends_per_se *
365 rdev->config.cayman.max_shader_engines;
366 else if (rdev->family >= CHIP_CEDAR)
367 *value = rdev->config.evergreen.max_backends;
368 else if (rdev->family >= CHIP_RV770)
369 *value = rdev->config.rv770.max_backends;
370 else if (rdev->family >= CHIP_R600)
371 *value = rdev->config.r600.max_backends;
372 else {
373 return -EINVAL;
374 }
375 break;
376 case RADEON_INFO_NUM_TILE_PIPES:
377 if (rdev->family >= CHIP_BONAIRE)
378 *value = rdev->config.cik.max_tile_pipes;
379 else if (rdev->family >= CHIP_TAHITI)
380 *value = rdev->config.si.max_tile_pipes;
381 else if (rdev->family >= CHIP_CAYMAN)
382 *value = rdev->config.cayman.max_tile_pipes;
383 else if (rdev->family >= CHIP_CEDAR)
384 *value = rdev->config.evergreen.max_tile_pipes;
385 else if (rdev->family >= CHIP_RV770)
386 *value = rdev->config.rv770.max_tile_pipes;
387 else if (rdev->family >= CHIP_R600)
388 *value = rdev->config.r600.max_tile_pipes;
389 else {
390 return -EINVAL;
391 }
392 break;
393 case RADEON_INFO_FUSION_GART_WORKING:
394 *value = 1;
395 break;
396 case RADEON_INFO_BACKEND_MAP:
397 if (rdev->family >= CHIP_BONAIRE)
398 *value = rdev->config.cik.backend_map;
399 else if (rdev->family >= CHIP_TAHITI)
400 *value = rdev->config.si.backend_map;
401 else if (rdev->family >= CHIP_CAYMAN)
402 *value = rdev->config.cayman.backend_map;
403 else if (rdev->family >= CHIP_CEDAR)
404 *value = rdev->config.evergreen.backend_map;
405 else if (rdev->family >= CHIP_RV770)
406 *value = rdev->config.rv770.backend_map;
407 else if (rdev->family >= CHIP_R600)
408 *value = rdev->config.r600.backend_map;
409 else {
410 return -EINVAL;
411 }
412 break;
413 case RADEON_INFO_VA_START:
414 /* this is where we report if vm is supported or not */
415 if (rdev->family < CHIP_CAYMAN)
416 return -EINVAL;
417 *value = RADEON_VA_RESERVED_SIZE;
418 break;
419 case RADEON_INFO_IB_VM_MAX_SIZE:
420 /* this is where we report if vm is supported or not */
421 if (rdev->family < CHIP_CAYMAN)
422 return -EINVAL;
423 *value = RADEON_IB_VM_MAX_SIZE;
424 break;
425 case RADEON_INFO_MAX_PIPES:
426 if (rdev->family >= CHIP_BONAIRE)
427 *value = rdev->config.cik.max_cu_per_sh;
428 else if (rdev->family >= CHIP_TAHITI)
429 *value = rdev->config.si.max_cu_per_sh;
430 else if (rdev->family >= CHIP_CAYMAN)
431 *value = rdev->config.cayman.max_pipes_per_simd;
432 else if (rdev->family >= CHIP_CEDAR)
433 *value = rdev->config.evergreen.max_pipes;
434 else if (rdev->family >= CHIP_RV770)
435 *value = rdev->config.rv770.max_pipes;
436 else if (rdev->family >= CHIP_R600)
437 *value = rdev->config.r600.max_pipes;
438 else {
439 return -EINVAL;
440 }
441 break;
442 case RADEON_INFO_TIMESTAMP:
443 if (rdev->family < CHIP_R600) {
444 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
445 return -EINVAL;
446 }
447 value = (uint32_t*)&value64;
448 value_size = sizeof(uint64_t);
449 value64 = radeon_get_gpu_clock_counter(rdev);
450 break;
451 case RADEON_INFO_MAX_SE:
452 if (rdev->family >= CHIP_BONAIRE)
453 *value = rdev->config.cik.max_shader_engines;
454 else if (rdev->family >= CHIP_TAHITI)
455 *value = rdev->config.si.max_shader_engines;
456 else if (rdev->family >= CHIP_CAYMAN)
457 *value = rdev->config.cayman.max_shader_engines;
458 else if (rdev->family >= CHIP_CEDAR)
459 *value = rdev->config.evergreen.num_ses;
460 else
461 *value = 1;
462 break;
463 case RADEON_INFO_MAX_SH_PER_SE:
464 if (rdev->family >= CHIP_BONAIRE)
465 *value = rdev->config.cik.max_sh_per_se;
466 else if (rdev->family >= CHIP_TAHITI)
467 *value = rdev->config.si.max_sh_per_se;
468 else
469 return -EINVAL;
470 break;
471 case RADEON_INFO_FASTFB_WORKING:
472 *value = rdev->fastfb_working;
473 break;
474 case RADEON_INFO_RING_WORKING:
475 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
476 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
477 return -EFAULT;
478 }
479 switch (*value) {
480 case RADEON_CS_RING_GFX:
481 case RADEON_CS_RING_COMPUTE:
482 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
483 break;
484 case RADEON_CS_RING_DMA:
485 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
486 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
487 break;
488 case RADEON_CS_RING_UVD:
489 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
490 break;
491 case RADEON_CS_RING_VCE:
492 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
493 break;
494 default:
495 return -EINVAL;
496 }
497 break;
498 case RADEON_INFO_SI_TILE_MODE_ARRAY:
499 if (rdev->family >= CHIP_BONAIRE) {
500 value = rdev->config.cik.tile_mode_array;
501 value_size = sizeof(uint32_t)*32;
502 } else if (rdev->family >= CHIP_TAHITI) {
503 value = rdev->config.si.tile_mode_array;
504 value_size = sizeof(uint32_t)*32;
505 } else {
506 DRM_DEBUG_KMS("tile mode array is si+ only!\n");
507 return -EINVAL;
508 }
509 break;
510 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
511 if (rdev->family >= CHIP_BONAIRE) {
512 value = rdev->config.cik.macrotile_mode_array;
513 value_size = sizeof(uint32_t)*16;
514 } else {
515 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
516 return -EINVAL;
517 }
518 break;
519 case RADEON_INFO_SI_CP_DMA_COMPUTE:
520 *value = 1;
521 break;
522 case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
523 if (rdev->family >= CHIP_BONAIRE) {
524 *value = rdev->config.cik.backend_enable_mask;
525 } else if (rdev->family >= CHIP_TAHITI) {
526 *value = rdev->config.si.backend_enable_mask;
527 } else {
528 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
529 return -EINVAL;
530 }
531 break;
532 case RADEON_INFO_MAX_SCLK:
533 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
534 rdev->pm.dpm_enabled)
535 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
536 else
537 *value = rdev->pm.default_sclk * 10;
538 break;
539 case RADEON_INFO_VCE_FW_VERSION:
540 *value = rdev->vce.fw_version;
541 break;
542 case RADEON_INFO_VCE_FB_VERSION:
543 *value = rdev->vce.fb_version;
544 break;
545 case RADEON_INFO_NUM_BYTES_MOVED:
546 value = (uint32_t*)&value64;
547 value_size = sizeof(uint64_t);
548 value64 = atomic64_read(&rdev->num_bytes_moved);
549 break;
550 case RADEON_INFO_VRAM_USAGE:
551 value = (uint32_t*)&value64;
552 value_size = sizeof(uint64_t);
553 value64 = atomic64_read(&rdev->vram_usage);
554 break;
555 case RADEON_INFO_GTT_USAGE:
556 value = (uint32_t*)&value64;
557 value_size = sizeof(uint64_t);
558 value64 = atomic64_read(&rdev->gtt_usage);
559 break;
560 case RADEON_INFO_ACTIVE_CU_COUNT:
561 if (rdev->family >= CHIP_BONAIRE)
562 *value = rdev->config.cik.active_cus;
563 else if (rdev->family >= CHIP_TAHITI)
564 *value = rdev->config.si.active_cus;
565 else if (rdev->family >= CHIP_CAYMAN)
566 *value = rdev->config.cayman.active_simds;
567 else if (rdev->family >= CHIP_CEDAR)
568 *value = rdev->config.evergreen.active_simds;
569 else if (rdev->family >= CHIP_RV770)
570 *value = rdev->config.rv770.active_simds;
571 else if (rdev->family >= CHIP_R600)
572 *value = rdev->config.r600.active_simds;
573 else
574 *value = 1;
575 break;
576 case RADEON_INFO_CURRENT_GPU_TEMP:
577 /* get temperature in millidegrees C */
578 if (rdev->asic->pm.get_temperature)
579 *value = radeon_get_temperature(rdev);
580 else
581 *value = 0;
582 break;
583 case RADEON_INFO_CURRENT_GPU_SCLK:
584 /* get sclk in Mhz */
585 if (rdev->pm.dpm_enabled)
586 *value = radeon_dpm_get_current_sclk(rdev) / 100;
587 else
588 *value = rdev->pm.current_sclk / 100;
589 break;
590 case RADEON_INFO_CURRENT_GPU_MCLK:
591 /* get mclk in Mhz */
592 if (rdev->pm.dpm_enabled)
593 *value = radeon_dpm_get_current_mclk(rdev) / 100;
594 else
595 *value = rdev->pm.current_mclk / 100;
596 break;
597 case RADEON_INFO_READ_REG:
598 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
599 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
600 return -EFAULT;
601 }
602 if (radeon_get_allowed_info_register(rdev, *value, value))
603 return -EINVAL;
604 break;
605 case RADEON_INFO_VA_UNMAP_WORKING:
606 *value = true;
607 break;
608 case RADEON_INFO_GPU_RESET_COUNTER:
609 *value = atomic_read(&rdev->gpu_reset_counter);
610 break;
611 default:
612 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
613 return -EINVAL;
614 }
615 if (copy_to_user(value_ptr, (char*)value, value_size)) {
616 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
617 return -EFAULT;
618 }
619 return 0;
620}
621
622
623/*
624 * Outdated mess for old drm with Xorg being in charge (void function now).
625 */
626/**
627 * radeon_driver_lastclose_kms - drm callback for last close
628 *
629 * @dev: drm dev pointer
630 *
631 * Switch vga_switcheroo state after last close (all asics).
632 */
633void radeon_driver_lastclose_kms(struct drm_device *dev)
634{
635 drm_fb_helper_lastclose(dev);
636 vga_switcheroo_process_delayed_switch();
637}
638
639/**
640 * radeon_driver_open_kms - drm callback for open
641 *
642 * @dev: drm dev pointer
643 * @file_priv: drm file
644 *
645 * On device open, init vm on cayman+ (all asics).
646 * Returns 0 on success, error on failure.
647 */
648int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
649{
650 struct radeon_device *rdev = dev->dev_private;
651 int r;
652
653 file_priv->driver_priv = NULL;
654
655 r = pm_runtime_get_sync(dev->dev);
656 if (r < 0) {
657 pm_runtime_put_autosuspend(dev->dev);
658 return r;
659 }
660
661 /* new gpu have virtual address space support */
662 if (rdev->family >= CHIP_CAYMAN) {
663 struct radeon_fpriv *fpriv;
664 struct radeon_vm *vm;
665
666 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
667 if (unlikely(!fpriv)) {
668 r = -ENOMEM;
669 goto out_suspend;
670 }
671
672 if (rdev->accel_working) {
673 vm = &fpriv->vm;
674 r = radeon_vm_init(rdev, vm);
675 if (r) {
676 kfree(fpriv);
677 goto out_suspend;
678 }
679
680 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
681 if (r) {
682 radeon_vm_fini(rdev, vm);
683 kfree(fpriv);
684 goto out_suspend;
685 }
686
687 /* map the ib pool buffer read only into
688 * virtual address space */
689 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
690 rdev->ring_tmp_bo.bo);
691 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
692 RADEON_VA_IB_OFFSET,
693 RADEON_VM_PAGE_READABLE |
694 RADEON_VM_PAGE_SNOOPED);
695 if (r) {
696 radeon_vm_fini(rdev, vm);
697 kfree(fpriv);
698 goto out_suspend;
699 }
700 }
701 file_priv->driver_priv = fpriv;
702 }
703
704out_suspend:
705 pm_runtime_mark_last_busy(dev->dev);
706 pm_runtime_put_autosuspend(dev->dev);
707 return r;
708}
709
710/**
711 * radeon_driver_postclose_kms - drm callback for post close
712 *
713 * @dev: drm dev pointer
714 * @file_priv: drm file
715 *
716 * On device close, tear down hyperz and cmask filps on r1xx-r5xx
717 * (all asics). And tear down vm on cayman+ (all asics).
718 */
719void radeon_driver_postclose_kms(struct drm_device *dev,
720 struct drm_file *file_priv)
721{
722 struct radeon_device *rdev = dev->dev_private;
723
724 pm_runtime_get_sync(dev->dev);
725
726 mutex_lock(&rdev->gem.mutex);
727 if (rdev->hyperz_filp == file_priv)
728 rdev->hyperz_filp = NULL;
729 if (rdev->cmask_filp == file_priv)
730 rdev->cmask_filp = NULL;
731 mutex_unlock(&rdev->gem.mutex);
732
733 radeon_uvd_free_handles(rdev, file_priv);
734 radeon_vce_free_handles(rdev, file_priv);
735
736 /* new gpu have virtual address space support */
737 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
738 struct radeon_fpriv *fpriv = file_priv->driver_priv;
739 struct radeon_vm *vm = &fpriv->vm;
740 int r;
741
742 if (rdev->accel_working) {
743 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
744 if (!r) {
745 if (vm->ib_bo_va)
746 radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
747 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
748 }
749 radeon_vm_fini(rdev, vm);
750 }
751
752 kfree(fpriv);
753 file_priv->driver_priv = NULL;
754 }
755 pm_runtime_mark_last_busy(dev->dev);
756 pm_runtime_put_autosuspend(dev->dev);
757}
758
759/*
760 * VBlank related functions.
761 */
762/**
763 * radeon_get_vblank_counter_kms - get frame count
764 *
765 * @crtc: crtc to get the frame count from
766 *
767 * Gets the frame count on the requested crtc (all asics).
768 * Returns frame count on success, -EINVAL on failure.
769 */
770u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc)
771{
772 struct drm_device *dev = crtc->dev;
773 unsigned int pipe = crtc->index;
774 int vpos, hpos, stat;
775 u32 count;
776 struct radeon_device *rdev = dev->dev_private;
777
778 if (pipe >= rdev->num_crtc) {
779 DRM_ERROR("Invalid crtc %u\n", pipe);
780 return -EINVAL;
781 }
782
783 /* The hw increments its frame counter at start of vsync, not at start
784 * of vblank, as is required by DRM core vblank counter handling.
785 * Cook the hw count here to make it appear to the caller as if it
786 * incremented at start of vblank. We measure distance to start of
787 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
788 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
789 * result by 1 to give the proper appearance to caller.
790 */
791 if (rdev->mode_info.crtcs[pipe]) {
792 /* Repeat readout if needed to provide stable result if
793 * we cross start of vsync during the queries.
794 */
795 do {
796 count = radeon_get_vblank_counter(rdev, pipe);
797 /* Ask radeon_get_crtc_scanoutpos to return vpos as
798 * distance to start of vblank, instead of regular
799 * vertical scanout pos.
800 */
801 stat = radeon_get_crtc_scanoutpos(
802 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
803 &vpos, &hpos, NULL, NULL,
804 &rdev->mode_info.crtcs[pipe]->base.hwmode);
805 } while (count != radeon_get_vblank_counter(rdev, pipe));
806
807 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
808 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
809 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
810 }
811 else {
812 DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n",
813 pipe, vpos);
814
815 /* Bump counter if we are at >= leading edge of vblank,
816 * but before vsync where vpos would turn negative and
817 * the hw counter really increments.
818 */
819 if (vpos >= 0)
820 count++;
821 }
822 }
823 else {
824 /* Fallback to use value as is. */
825 count = radeon_get_vblank_counter(rdev, pipe);
826 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
827 }
828
829 return count;
830}
831
832/**
833 * radeon_enable_vblank_kms - enable vblank interrupt
834 *
835 * @crtc: crtc to enable vblank interrupt for
836 *
837 * Enable the interrupt on the requested crtc (all asics).
838 * Returns 0 on success, -EINVAL on failure.
839 */
840int radeon_enable_vblank_kms(struct drm_crtc *crtc)
841{
842 struct drm_device *dev = crtc->dev;
843 unsigned int pipe = crtc->index;
844 struct radeon_device *rdev = dev->dev_private;
845 unsigned long irqflags;
846 int r;
847
848 if (pipe >= rdev->num_crtc) {
849 DRM_ERROR("Invalid crtc %d\n", pipe);
850 return -EINVAL;
851 }
852
853 spin_lock_irqsave(&rdev->irq.lock, irqflags);
854 rdev->irq.crtc_vblank_int[pipe] = true;
855 r = radeon_irq_set(rdev);
856 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
857 return r;
858}
859
860/**
861 * radeon_disable_vblank_kms - disable vblank interrupt
862 *
863 * @crtc: crtc to disable vblank interrupt for
864 *
865 * Disable the interrupt on the requested crtc (all asics).
866 */
867void radeon_disable_vblank_kms(struct drm_crtc *crtc)
868{
869 struct drm_device *dev = crtc->dev;
870 unsigned int pipe = crtc->index;
871 struct radeon_device *rdev = dev->dev_private;
872 unsigned long irqflags;
873
874 if (pipe >= rdev->num_crtc) {
875 DRM_ERROR("Invalid crtc %d\n", pipe);
876 return;
877 }
878
879 spin_lock_irqsave(&rdev->irq.lock, irqflags);
880 rdev->irq.crtc_vblank_int[pipe] = false;
881 radeon_irq_set(rdev);
882 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
883}