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1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
29#include "i915_drv.h"
30#include "drm_crtc.h"
31#include "drm_crtc_helper.h"
32#include "drm_fb_helper.h"
33
34#define _wait_for(COND, MS, W) ({ \
35 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
36 int ret__ = 0; \
37 while (! (COND)) { \
38 if (time_after(jiffies, timeout__)) { \
39 ret__ = -ETIMEDOUT; \
40 break; \
41 } \
42 if (W && !(in_atomic() || in_dbg_master())) msleep(W); \
43 } \
44 ret__; \
45})
46
47#define wait_for(COND, MS) _wait_for(COND, MS, 1)
48#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
49
50#define MSLEEP(x) do { \
51 if (in_dbg_master()) \
52 mdelay(x); \
53 else \
54 msleep(x); \
55} while(0)
56
57#define KHz(x) (1000*x)
58#define MHz(x) KHz(1000*x)
59
60/*
61 * Display related stuff
62 */
63
64/* store information about an Ixxx DVO */
65/* The i830->i865 use multiple DVOs with multiple i2cs */
66/* the i915, i945 have a single sDVO i2c bus - which is different */
67#define MAX_OUTPUTS 6
68/* maximum connectors per crtcs in the mode set */
69#define INTELFB_CONN_LIMIT 4
70
71#define INTEL_I2C_BUS_DVO 1
72#define INTEL_I2C_BUS_SDVO 2
73
74/* these are outputs from the chip - integrated only
75 external chips are via DVO or SDVO output */
76#define INTEL_OUTPUT_UNUSED 0
77#define INTEL_OUTPUT_ANALOG 1
78#define INTEL_OUTPUT_DVO 2
79#define INTEL_OUTPUT_SDVO 3
80#define INTEL_OUTPUT_LVDS 4
81#define INTEL_OUTPUT_TVOUT 5
82#define INTEL_OUTPUT_HDMI 6
83#define INTEL_OUTPUT_DISPLAYPORT 7
84#define INTEL_OUTPUT_EDP 8
85
86/* Intel Pipe Clone Bit */
87#define INTEL_HDMIB_CLONE_BIT 1
88#define INTEL_HDMIC_CLONE_BIT 2
89#define INTEL_HDMID_CLONE_BIT 3
90#define INTEL_HDMIE_CLONE_BIT 4
91#define INTEL_HDMIF_CLONE_BIT 5
92#define INTEL_SDVO_NON_TV_CLONE_BIT 6
93#define INTEL_SDVO_TV_CLONE_BIT 7
94#define INTEL_SDVO_LVDS_CLONE_BIT 8
95#define INTEL_ANALOG_CLONE_BIT 9
96#define INTEL_TV_CLONE_BIT 10
97#define INTEL_DP_B_CLONE_BIT 11
98#define INTEL_DP_C_CLONE_BIT 12
99#define INTEL_DP_D_CLONE_BIT 13
100#define INTEL_LVDS_CLONE_BIT 14
101#define INTEL_DVO_TMDS_CLONE_BIT 15
102#define INTEL_DVO_LVDS_CLONE_BIT 16
103#define INTEL_EDP_CLONE_BIT 17
104
105#define INTEL_DVO_CHIP_NONE 0
106#define INTEL_DVO_CHIP_LVDS 1
107#define INTEL_DVO_CHIP_TMDS 2
108#define INTEL_DVO_CHIP_TVOUT 4
109
110/* drm_display_mode->private_flags */
111#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
112#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
113
114static inline void
115intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
116 int multiplier)
117{
118 mode->clock *= multiplier;
119 mode->private_flags |= multiplier;
120}
121
122static inline int
123intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
124{
125 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
126}
127
128struct intel_framebuffer {
129 struct drm_framebuffer base;
130 struct drm_i915_gem_object *obj;
131};
132
133struct intel_fbdev {
134 struct drm_fb_helper helper;
135 struct intel_framebuffer ifb;
136 struct list_head fbdev_list;
137 struct drm_display_mode *our_mode;
138};
139
140struct intel_encoder {
141 struct drm_encoder base;
142 int type;
143 bool needs_tv_clock;
144 void (*hot_plug)(struct intel_encoder *);
145 int crtc_mask;
146 int clone_mask;
147};
148
149struct intel_connector {
150 struct drm_connector base;
151 struct intel_encoder *encoder;
152};
153
154struct intel_crtc {
155 struct drm_crtc base;
156 enum pipe pipe;
157 enum plane plane;
158 u8 lut_r[256], lut_g[256], lut_b[256];
159 int dpms_mode;
160 bool active; /* is the crtc on? independent of the dpms mode */
161 bool busy; /* is scanout buffer being updated frequently? */
162 struct timer_list idle_timer;
163 bool lowfreq_avail;
164 struct intel_overlay *overlay;
165 struct intel_unpin_work *unpin_work;
166 int fdi_lanes;
167
168 struct drm_i915_gem_object *cursor_bo;
169 uint32_t cursor_addr;
170 int16_t cursor_x, cursor_y;
171 int16_t cursor_width, cursor_height;
172 bool cursor_visible;
173 unsigned int bpp;
174};
175
176#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
177#define to_intel_connector(x) container_of(x, struct intel_connector, base)
178#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
179#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
180
181#define DIP_HEADER_SIZE 5
182
183#define DIP_TYPE_AVI 0x82
184#define DIP_VERSION_AVI 0x2
185#define DIP_LEN_AVI 13
186
187#define DIP_TYPE_SPD 0x3
188#define DIP_VERSION_SPD 0x1
189#define DIP_LEN_SPD 25
190#define DIP_SPD_UNKNOWN 0
191#define DIP_SPD_DSTB 0x1
192#define DIP_SPD_DVDP 0x2
193#define DIP_SPD_DVHS 0x3
194#define DIP_SPD_HDDVR 0x4
195#define DIP_SPD_DVC 0x5
196#define DIP_SPD_DSC 0x6
197#define DIP_SPD_VCD 0x7
198#define DIP_SPD_GAME 0x8
199#define DIP_SPD_PC 0x9
200#define DIP_SPD_BD 0xa
201#define DIP_SPD_SCD 0xb
202
203struct dip_infoframe {
204 uint8_t type; /* HB0 */
205 uint8_t ver; /* HB1 */
206 uint8_t len; /* HB2 - body len, not including checksum */
207 uint8_t ecc; /* Header ECC */
208 uint8_t checksum; /* PB0 */
209 union {
210 struct {
211 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
212 uint8_t Y_A_B_S;
213 /* PB2 - C 7:6, M 5:4, R 3:0 */
214 uint8_t C_M_R;
215 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
216 uint8_t ITC_EC_Q_SC;
217 /* PB4 - VIC 6:0 */
218 uint8_t VIC;
219 /* PB5 - PR 3:0 */
220 uint8_t PR;
221 /* PB6 to PB13 */
222 uint16_t top_bar_end;
223 uint16_t bottom_bar_start;
224 uint16_t left_bar_end;
225 uint16_t right_bar_start;
226 } avi;
227 struct {
228 uint8_t vn[8];
229 uint8_t pd[16];
230 uint8_t sdi;
231 } spd;
232 uint8_t payload[27];
233 } __attribute__ ((packed)) body;
234} __attribute__((packed));
235
236static inline struct drm_crtc *
237intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
238{
239 struct drm_i915_private *dev_priv = dev->dev_private;
240 return dev_priv->pipe_to_crtc_mapping[pipe];
241}
242
243static inline struct drm_crtc *
244intel_get_crtc_for_plane(struct drm_device *dev, int plane)
245{
246 struct drm_i915_private *dev_priv = dev->dev_private;
247 return dev_priv->plane_to_crtc_mapping[plane];
248}
249
250struct intel_unpin_work {
251 struct work_struct work;
252 struct drm_device *dev;
253 struct drm_i915_gem_object *old_fb_obj;
254 struct drm_i915_gem_object *pending_flip_obj;
255 struct drm_pending_vblank_event *event;
256 int pending;
257 bool enable_stall_check;
258};
259
260struct intel_fbc_work {
261 struct delayed_work work;
262 struct drm_crtc *crtc;
263 struct drm_framebuffer *fb;
264 int interval;
265};
266
267int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
268extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus);
269
270extern void intel_attach_force_audio_property(struct drm_connector *connector);
271extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
272
273extern void intel_crt_init(struct drm_device *dev);
274extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg);
275void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
276extern bool intel_sdvo_init(struct drm_device *dev, int output_device);
277extern void intel_dvo_init(struct drm_device *dev);
278extern void intel_tv_init(struct drm_device *dev);
279extern void intel_mark_busy(struct drm_device *dev,
280 struct drm_i915_gem_object *obj);
281extern bool intel_lvds_init(struct drm_device *dev);
282extern void intel_dp_init(struct drm_device *dev, int dp_reg);
283void
284intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
285 struct drm_display_mode *adjusted_mode);
286extern bool intel_dpd_is_edp(struct drm_device *dev);
287extern void intel_edp_link_config (struct intel_encoder *, int *, int *);
288extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
289
290/* intel_panel.c */
291extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
292 struct drm_display_mode *adjusted_mode);
293extern void intel_pch_panel_fitting(struct drm_device *dev,
294 int fitting_mode,
295 struct drm_display_mode *mode,
296 struct drm_display_mode *adjusted_mode);
297extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
298extern u32 intel_panel_get_backlight(struct drm_device *dev);
299extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
300extern int intel_panel_setup_backlight(struct drm_device *dev);
301extern void intel_panel_enable_backlight(struct drm_device *dev);
302extern void intel_panel_disable_backlight(struct drm_device *dev);
303extern void intel_panel_destroy_backlight(struct drm_device *dev);
304extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
305
306extern void intel_crtc_load_lut(struct drm_crtc *crtc);
307extern void intel_encoder_prepare (struct drm_encoder *encoder);
308extern void intel_encoder_commit (struct drm_encoder *encoder);
309extern void intel_encoder_destroy(struct drm_encoder *encoder);
310
311static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
312{
313 return to_intel_connector(connector)->encoder;
314}
315
316extern void intel_connector_attach_encoder(struct intel_connector *connector,
317 struct intel_encoder *encoder);
318extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
319
320extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
321 struct drm_crtc *crtc);
322int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
323 struct drm_file *file_priv);
324extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
325extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
326
327struct intel_load_detect_pipe {
328 struct drm_framebuffer *release_fb;
329 bool load_detect_temp;
330 int dpms_mode;
331};
332extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
333 struct drm_connector *connector,
334 struct drm_display_mode *mode,
335 struct intel_load_detect_pipe *old);
336extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
337 struct drm_connector *connector,
338 struct intel_load_detect_pipe *old);
339
340extern void intelfb_restore(void);
341extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
342 u16 blue, int regno);
343extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
344 u16 *blue, int regno);
345extern void intel_enable_clock_gating(struct drm_device *dev);
346extern void ironlake_enable_drps(struct drm_device *dev);
347extern void ironlake_disable_drps(struct drm_device *dev);
348extern void gen6_enable_rps(struct drm_i915_private *dev_priv);
349extern void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
350extern void gen6_disable_rps(struct drm_device *dev);
351extern void intel_init_emon(struct drm_device *dev);
352
353extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
354 struct drm_i915_gem_object *obj,
355 struct intel_ring_buffer *pipelined);
356
357extern int intel_framebuffer_init(struct drm_device *dev,
358 struct intel_framebuffer *ifb,
359 struct drm_mode_fb_cmd *mode_cmd,
360 struct drm_i915_gem_object *obj);
361extern int intel_fbdev_init(struct drm_device *dev);
362extern void intel_fbdev_fini(struct drm_device *dev);
363
364extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
365extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
366extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
367
368extern void intel_setup_overlay(struct drm_device *dev);
369extern void intel_cleanup_overlay(struct drm_device *dev);
370extern int intel_overlay_switch_off(struct intel_overlay *overlay);
371extern int intel_overlay_put_image(struct drm_device *dev, void *data,
372 struct drm_file *file_priv);
373extern int intel_overlay_attrs(struct drm_device *dev, void *data,
374 struct drm_file *file_priv);
375
376extern void intel_fb_output_poll_changed(struct drm_device *dev);
377extern void intel_fb_restore_mode(struct drm_device *dev);
378
379extern void intel_init_clock_gating(struct drm_device *dev);
380#endif /* __INTEL_DRV_H__ */
1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/async.h>
29#include <linux/i2c.h>
30#include <linux/hdmi.h>
31#include <linux/sched/clock.h>
32#include <drm/i915_drm.h>
33#include "i915_drv.h"
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_encoder.h>
37#include <drm/drm_fb_helper.h>
38#include <drm/drm_dp_dual_mode_helper.h>
39#include <drm/drm_dp_mst_helper.h>
40#include <drm/drm_rect.h>
41#include <drm/drm_atomic.h>
42
43/**
44 * __wait_for - magic wait macro
45 *
46 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
47 * important that we check the condition again after having timed out, since the
48 * timeout could be due to preemption or similar and we've never had a chance to
49 * check the condition before the timeout.
50 */
51#define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
52 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
53 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
54 int ret__; \
55 might_sleep(); \
56 for (;;) { \
57 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
58 OP; \
59 if (COND) { \
60 ret__ = 0; \
61 break; \
62 } \
63 if (expired__) { \
64 ret__ = -ETIMEDOUT; \
65 break; \
66 } \
67 usleep_range(wait__, wait__ * 2); \
68 if (wait__ < (Wmax)) \
69 wait__ <<= 1; \
70 } \
71 ret__; \
72})
73
74#define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
75 (Wmax))
76#define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
77
78/* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
79#if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
80# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
81#else
82# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
83#endif
84
85#define _wait_for_atomic(COND, US, ATOMIC) \
86({ \
87 int cpu, ret, timeout = (US) * 1000; \
88 u64 base; \
89 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
90 if (!(ATOMIC)) { \
91 preempt_disable(); \
92 cpu = smp_processor_id(); \
93 } \
94 base = local_clock(); \
95 for (;;) { \
96 u64 now = local_clock(); \
97 if (!(ATOMIC)) \
98 preempt_enable(); \
99 if (COND) { \
100 ret = 0; \
101 break; \
102 } \
103 if (now - base >= timeout) { \
104 ret = -ETIMEDOUT; \
105 break; \
106 } \
107 cpu_relax(); \
108 if (!(ATOMIC)) { \
109 preempt_disable(); \
110 if (unlikely(cpu != smp_processor_id())) { \
111 timeout -= now - base; \
112 cpu = smp_processor_id(); \
113 base = local_clock(); \
114 } \
115 } \
116 } \
117 ret; \
118})
119
120#define wait_for_us(COND, US) \
121({ \
122 int ret__; \
123 BUILD_BUG_ON(!__builtin_constant_p(US)); \
124 if ((US) > 10) \
125 ret__ = _wait_for((COND), (US), 10, 10); \
126 else \
127 ret__ = _wait_for_atomic((COND), (US), 0); \
128 ret__; \
129})
130
131#define wait_for_atomic_us(COND, US) \
132({ \
133 BUILD_BUG_ON(!__builtin_constant_p(US)); \
134 BUILD_BUG_ON((US) > 50000); \
135 _wait_for_atomic((COND), (US), 1); \
136})
137
138#define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
139
140#define KHz(x) (1000 * (x))
141#define MHz(x) KHz(1000 * (x))
142
143/*
144 * Display related stuff
145 */
146
147/* store information about an Ixxx DVO */
148/* The i830->i865 use multiple DVOs with multiple i2cs */
149/* the i915, i945 have a single sDVO i2c bus - which is different */
150#define MAX_OUTPUTS 6
151/* maximum connectors per crtcs in the mode set */
152
153/* Maximum cursor sizes */
154#define GEN2_CURSOR_WIDTH 64
155#define GEN2_CURSOR_HEIGHT 64
156#define MAX_CURSOR_WIDTH 256
157#define MAX_CURSOR_HEIGHT 256
158
159#define INTEL_I2C_BUS_DVO 1
160#define INTEL_I2C_BUS_SDVO 2
161
162/* these are outputs from the chip - integrated only
163 external chips are via DVO or SDVO output */
164enum intel_output_type {
165 INTEL_OUTPUT_UNUSED = 0,
166 INTEL_OUTPUT_ANALOG = 1,
167 INTEL_OUTPUT_DVO = 2,
168 INTEL_OUTPUT_SDVO = 3,
169 INTEL_OUTPUT_LVDS = 4,
170 INTEL_OUTPUT_TVOUT = 5,
171 INTEL_OUTPUT_HDMI = 6,
172 INTEL_OUTPUT_DP = 7,
173 INTEL_OUTPUT_EDP = 8,
174 INTEL_OUTPUT_DSI = 9,
175 INTEL_OUTPUT_DDI = 10,
176 INTEL_OUTPUT_DP_MST = 11,
177};
178
179#define INTEL_DVO_CHIP_NONE 0
180#define INTEL_DVO_CHIP_LVDS 1
181#define INTEL_DVO_CHIP_TMDS 2
182#define INTEL_DVO_CHIP_TVOUT 4
183
184#define INTEL_DSI_VIDEO_MODE 0
185#define INTEL_DSI_COMMAND_MODE 1
186
187struct intel_framebuffer {
188 struct drm_framebuffer base;
189 struct drm_i915_gem_object *obj;
190 struct intel_rotation_info rot_info;
191
192 /* for each plane in the normal GTT view */
193 struct {
194 unsigned int x, y;
195 } normal[2];
196 /* for each plane in the rotated GTT view */
197 struct {
198 unsigned int x, y;
199 unsigned int pitch; /* pixels */
200 } rotated[2];
201};
202
203struct intel_fbdev {
204 struct drm_fb_helper helper;
205 struct intel_framebuffer *fb;
206 struct i915_vma *vma;
207 unsigned long vma_flags;
208 async_cookie_t cookie;
209 int preferred_bpp;
210};
211
212struct intel_encoder {
213 struct drm_encoder base;
214
215 enum intel_output_type type;
216 enum port port;
217 unsigned int cloneable;
218 bool (*hotplug)(struct intel_encoder *encoder,
219 struct intel_connector *connector);
220 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
221 struct intel_crtc_state *,
222 struct drm_connector_state *);
223 bool (*compute_config)(struct intel_encoder *,
224 struct intel_crtc_state *,
225 struct drm_connector_state *);
226 void (*pre_pll_enable)(struct intel_encoder *,
227 const struct intel_crtc_state *,
228 const struct drm_connector_state *);
229 void (*pre_enable)(struct intel_encoder *,
230 const struct intel_crtc_state *,
231 const struct drm_connector_state *);
232 void (*enable)(struct intel_encoder *,
233 const struct intel_crtc_state *,
234 const struct drm_connector_state *);
235 void (*disable)(struct intel_encoder *,
236 const struct intel_crtc_state *,
237 const struct drm_connector_state *);
238 void (*post_disable)(struct intel_encoder *,
239 const struct intel_crtc_state *,
240 const struct drm_connector_state *);
241 void (*post_pll_disable)(struct intel_encoder *,
242 const struct intel_crtc_state *,
243 const struct drm_connector_state *);
244 /* Read out the current hw state of this connector, returning true if
245 * the encoder is active. If the encoder is enabled it also set the pipe
246 * it is connected to in the pipe parameter. */
247 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
248 /* Reconstructs the equivalent mode flags for the current hardware
249 * state. This must be called _after_ display->get_pipe_config has
250 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
251 * be set correctly before calling this function. */
252 void (*get_config)(struct intel_encoder *,
253 struct intel_crtc_state *pipe_config);
254 /* Returns a mask of power domains that need to be referenced as part
255 * of the hardware state readout code. */
256 u64 (*get_power_domains)(struct intel_encoder *encoder);
257 /*
258 * Called during system suspend after all pending requests for the
259 * encoder are flushed (for example for DP AUX transactions) and
260 * device interrupts are disabled.
261 */
262 void (*suspend)(struct intel_encoder *);
263 int crtc_mask;
264 enum hpd_pin hpd_pin;
265 enum intel_display_power_domain power_domain;
266 /* for communication with audio component; protected by av_mutex */
267 const struct drm_connector *audio_connector;
268};
269
270struct intel_panel {
271 struct drm_display_mode *fixed_mode;
272 struct drm_display_mode *alt_fixed_mode;
273 struct drm_display_mode *downclock_mode;
274
275 /* backlight */
276 struct {
277 bool present;
278 u32 level;
279 u32 min;
280 u32 max;
281 bool enabled;
282 bool combination_mode; /* gen 2/4 only */
283 bool active_low_pwm;
284 bool alternate_pwm_increment; /* lpt+ */
285
286 /* PWM chip */
287 bool util_pin_active_low; /* bxt+ */
288 u8 controller; /* bxt+ only */
289 struct pwm_device *pwm;
290
291 struct backlight_device *device;
292
293 /* Connector and platform specific backlight functions */
294 int (*setup)(struct intel_connector *connector, enum pipe pipe);
295 uint32_t (*get)(struct intel_connector *connector);
296 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
297 void (*disable)(const struct drm_connector_state *conn_state);
298 void (*enable)(const struct intel_crtc_state *crtc_state,
299 const struct drm_connector_state *conn_state);
300 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
301 uint32_t hz);
302 void (*power)(struct intel_connector *, bool enable);
303 } backlight;
304};
305
306/*
307 * This structure serves as a translation layer between the generic HDCP code
308 * and the bus-specific code. What that means is that HDCP over HDMI differs
309 * from HDCP over DP, so to account for these differences, we need to
310 * communicate with the receiver through this shim.
311 *
312 * For completeness, the 2 buses differ in the following ways:
313 * - DP AUX vs. DDC
314 * HDCP registers on the receiver are set via DP AUX for DP, and
315 * they are set via DDC for HDMI.
316 * - Receiver register offsets
317 * The offsets of the registers are different for DP vs. HDMI
318 * - Receiver register masks/offsets
319 * For instance, the ready bit for the KSV fifo is in a different
320 * place on DP vs HDMI
321 * - Receiver register names
322 * Seriously. In the DP spec, the 16-bit register containing
323 * downstream information is called BINFO, on HDMI it's called
324 * BSTATUS. To confuse matters further, DP has a BSTATUS register
325 * with a completely different definition.
326 * - KSV FIFO
327 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
328 * be read 3 keys at a time
329 * - Aksv output
330 * Since Aksv is hidden in hardware, there's different procedures
331 * to send it over DP AUX vs DDC
332 */
333struct intel_hdcp_shim {
334 /* Outputs the transmitter's An and Aksv values to the receiver. */
335 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
336
337 /* Reads the receiver's key selection vector */
338 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
339
340 /*
341 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
342 * definitions are the same in the respective specs, but the names are
343 * different. Call it BSTATUS since that's the name the HDMI spec
344 * uses and it was there first.
345 */
346 int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
347 u8 *bstatus);
348
349 /* Determines whether a repeater is present downstream */
350 int (*repeater_present)(struct intel_digital_port *intel_dig_port,
351 bool *repeater_present);
352
353 /* Reads the receiver's Ri' value */
354 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
355
356 /* Determines if the receiver's KSV FIFO is ready for consumption */
357 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
358 bool *ksv_ready);
359
360 /* Reads the ksv fifo for num_downstream devices */
361 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
362 int num_downstream, u8 *ksv_fifo);
363
364 /* Reads a 32-bit part of V' from the receiver */
365 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
366 int i, u32 *part);
367
368 /* Enables HDCP signalling on the port */
369 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
370 bool enable);
371
372 /* Ensures the link is still protected */
373 bool (*check_link)(struct intel_digital_port *intel_dig_port);
374
375 /* Detects panel's hdcp capability. This is optional for HDMI. */
376 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
377 bool *hdcp_capable);
378};
379
380struct intel_connector {
381 struct drm_connector base;
382 /*
383 * The fixed encoder this connector is connected to.
384 */
385 struct intel_encoder *encoder;
386
387 /* ACPI device id for ACPI and driver cooperation */
388 u32 acpi_device_id;
389
390 /* Reads out the current hw, returning true if the connector is enabled
391 * and active (i.e. dpms ON state). */
392 bool (*get_hw_state)(struct intel_connector *);
393
394 /* Panel info for eDP and LVDS */
395 struct intel_panel panel;
396
397 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
398 struct edid *edid;
399 struct edid *detect_edid;
400
401 /* since POLL and HPD connectors may use the same HPD line keep the native
402 state of connector->polled in case hotplug storm detection changes it */
403 u8 polled;
404
405 void *port; /* store this opaque as its illegal to dereference it */
406
407 struct intel_dp *mst_port;
408
409 /* Work struct to schedule a uevent on link train failure */
410 struct work_struct modeset_retry_work;
411
412 const struct intel_hdcp_shim *hdcp_shim;
413 struct mutex hdcp_mutex;
414 uint64_t hdcp_value; /* protected by hdcp_mutex */
415 struct delayed_work hdcp_check_work;
416 struct work_struct hdcp_prop_work;
417};
418
419struct intel_digital_connector_state {
420 struct drm_connector_state base;
421
422 enum hdmi_force_audio force_audio;
423 int broadcast_rgb;
424};
425
426#define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
427
428struct dpll {
429 /* given values */
430 int n;
431 int m1, m2;
432 int p1, p2;
433 /* derived values */
434 int dot;
435 int vco;
436 int m;
437 int p;
438};
439
440struct intel_atomic_state {
441 struct drm_atomic_state base;
442
443 struct {
444 /*
445 * Logical state of cdclk (used for all scaling, watermark,
446 * etc. calculations and checks). This is computed as if all
447 * enabled crtcs were active.
448 */
449 struct intel_cdclk_state logical;
450
451 /*
452 * Actual state of cdclk, can be different from the logical
453 * state only when all crtc's are DPMS off.
454 */
455 struct intel_cdclk_state actual;
456 } cdclk;
457
458 bool dpll_set, modeset;
459
460 /*
461 * Does this transaction change the pipes that are active? This mask
462 * tracks which CRTC's have changed their active state at the end of
463 * the transaction (not counting the temporary disable during modesets).
464 * This mask should only be non-zero when intel_state->modeset is true,
465 * but the converse is not necessarily true; simply changing a mode may
466 * not flip the final active status of any CRTC's
467 */
468 unsigned int active_pipe_changes;
469
470 unsigned int active_crtcs;
471 /* minimum acceptable cdclk for each pipe */
472 int min_cdclk[I915_MAX_PIPES];
473 /* minimum acceptable voltage level for each pipe */
474 u8 min_voltage_level[I915_MAX_PIPES];
475
476 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
477
478 /*
479 * Current watermarks can't be trusted during hardware readout, so
480 * don't bother calculating intermediate watermarks.
481 */
482 bool skip_intermediate_wm;
483
484 /* Gen9+ only */
485 struct skl_wm_values wm_results;
486
487 struct i915_sw_fence commit_ready;
488
489 struct llist_node freed;
490};
491
492struct intel_plane_state {
493 struct drm_plane_state base;
494 struct i915_vma *vma;
495 unsigned long flags;
496#define PLANE_HAS_FENCE BIT(0)
497
498 struct {
499 u32 offset;
500 int x, y;
501 } main;
502 struct {
503 u32 offset;
504 int x, y;
505 } aux;
506
507 /* plane control register */
508 u32 ctl;
509
510 /* plane color control register */
511 u32 color_ctl;
512
513 /*
514 * scaler_id
515 * = -1 : not using a scaler
516 * >= 0 : using a scalers
517 *
518 * plane requiring a scaler:
519 * - During check_plane, its bit is set in
520 * crtc_state->scaler_state.scaler_users by calling helper function
521 * update_scaler_plane.
522 * - scaler_id indicates the scaler it got assigned.
523 *
524 * plane doesn't require a scaler:
525 * - this can happen when scaling is no more required or plane simply
526 * got disabled.
527 * - During check_plane, corresponding bit is reset in
528 * crtc_state->scaler_state.scaler_users by calling helper function
529 * update_scaler_plane.
530 */
531 int scaler_id;
532
533 struct drm_intel_sprite_colorkey ckey;
534};
535
536struct intel_initial_plane_config {
537 struct intel_framebuffer *fb;
538 unsigned int tiling;
539 int size;
540 u32 base;
541};
542
543#define SKL_MIN_SRC_W 8
544#define SKL_MAX_SRC_W 4096
545#define SKL_MIN_SRC_H 8
546#define SKL_MAX_SRC_H 4096
547#define SKL_MIN_DST_W 8
548#define SKL_MAX_DST_W 4096
549#define SKL_MIN_DST_H 8
550#define SKL_MAX_DST_H 4096
551
552struct intel_scaler {
553 int in_use;
554 uint32_t mode;
555};
556
557struct intel_crtc_scaler_state {
558#define SKL_NUM_SCALERS 2
559 struct intel_scaler scalers[SKL_NUM_SCALERS];
560
561 /*
562 * scaler_users: keeps track of users requesting scalers on this crtc.
563 *
564 * If a bit is set, a user is using a scaler.
565 * Here user can be a plane or crtc as defined below:
566 * bits 0-30 - plane (bit position is index from drm_plane_index)
567 * bit 31 - crtc
568 *
569 * Instead of creating a new index to cover planes and crtc, using
570 * existing drm_plane_index for planes which is well less than 31
571 * planes and bit 31 for crtc. This should be fine to cover all
572 * our platforms.
573 *
574 * intel_atomic_setup_scalers will setup available scalers to users
575 * requesting scalers. It will gracefully fail if request exceeds
576 * avilability.
577 */
578#define SKL_CRTC_INDEX 31
579 unsigned scaler_users;
580
581 /* scaler used by crtc for panel fitting purpose */
582 int scaler_id;
583};
584
585/* drm_mode->private_flags */
586#define I915_MODE_FLAG_INHERITED 1
587/* Flag to get scanline using frame time stamps */
588#define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
589
590struct intel_pipe_wm {
591 struct intel_wm_level wm[5];
592 uint32_t linetime;
593 bool fbc_wm_enabled;
594 bool pipe_enabled;
595 bool sprites_enabled;
596 bool sprites_scaled;
597};
598
599struct skl_plane_wm {
600 struct skl_wm_level wm[8];
601 struct skl_wm_level trans_wm;
602};
603
604struct skl_pipe_wm {
605 struct skl_plane_wm planes[I915_MAX_PLANES];
606 uint32_t linetime;
607};
608
609enum vlv_wm_level {
610 VLV_WM_LEVEL_PM2,
611 VLV_WM_LEVEL_PM5,
612 VLV_WM_LEVEL_DDR_DVFS,
613 NUM_VLV_WM_LEVELS,
614};
615
616struct vlv_wm_state {
617 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
618 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
619 uint8_t num_levels;
620 bool cxsr;
621};
622
623struct vlv_fifo_state {
624 u16 plane[I915_MAX_PLANES];
625};
626
627enum g4x_wm_level {
628 G4X_WM_LEVEL_NORMAL,
629 G4X_WM_LEVEL_SR,
630 G4X_WM_LEVEL_HPLL,
631 NUM_G4X_WM_LEVELS,
632};
633
634struct g4x_wm_state {
635 struct g4x_pipe_wm wm;
636 struct g4x_sr_wm sr;
637 struct g4x_sr_wm hpll;
638 bool cxsr;
639 bool hpll_en;
640 bool fbc_en;
641};
642
643struct intel_crtc_wm_state {
644 union {
645 struct {
646 /*
647 * Intermediate watermarks; these can be
648 * programmed immediately since they satisfy
649 * both the current configuration we're
650 * switching away from and the new
651 * configuration we're switching to.
652 */
653 struct intel_pipe_wm intermediate;
654
655 /*
656 * Optimal watermarks, programmed post-vblank
657 * when this state is committed.
658 */
659 struct intel_pipe_wm optimal;
660 } ilk;
661
662 struct {
663 /* gen9+ only needs 1-step wm programming */
664 struct skl_pipe_wm optimal;
665 struct skl_ddb_entry ddb;
666 } skl;
667
668 struct {
669 /* "raw" watermarks (not inverted) */
670 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
671 /* intermediate watermarks (inverted) */
672 struct vlv_wm_state intermediate;
673 /* optimal watermarks (inverted) */
674 struct vlv_wm_state optimal;
675 /* display FIFO split */
676 struct vlv_fifo_state fifo_state;
677 } vlv;
678
679 struct {
680 /* "raw" watermarks */
681 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
682 /* intermediate watermarks */
683 struct g4x_wm_state intermediate;
684 /* optimal watermarks */
685 struct g4x_wm_state optimal;
686 } g4x;
687 };
688
689 /*
690 * Platforms with two-step watermark programming will need to
691 * update watermark programming post-vblank to switch from the
692 * safe intermediate watermarks to the optimal final
693 * watermarks.
694 */
695 bool need_postvbl_update;
696};
697
698struct intel_crtc_state {
699 struct drm_crtc_state base;
700
701 /**
702 * quirks - bitfield with hw state readout quirks
703 *
704 * For various reasons the hw state readout code might not be able to
705 * completely faithfully read out the current state. These cases are
706 * tracked with quirk flags so that fastboot and state checker can act
707 * accordingly.
708 */
709#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
710 unsigned long quirks;
711
712 unsigned fb_bits; /* framebuffers to flip */
713 bool update_pipe; /* can a fast modeset be performed? */
714 bool disable_cxsr;
715 bool update_wm_pre, update_wm_post; /* watermarks are updated */
716 bool fb_changed; /* fb on any of the planes is changed */
717 bool fifo_changed; /* FIFO split is changed */
718
719 /* Pipe source size (ie. panel fitter input size)
720 * All planes will be positioned inside this space,
721 * and get clipped at the edges. */
722 int pipe_src_w, pipe_src_h;
723
724 /*
725 * Pipe pixel rate, adjusted for
726 * panel fitter/pipe scaler downscaling.
727 */
728 unsigned int pixel_rate;
729
730 /* Whether to set up the PCH/FDI. Note that we never allow sharing
731 * between pch encoders and cpu encoders. */
732 bool has_pch_encoder;
733
734 /* Are we sending infoframes on the attached port */
735 bool has_infoframe;
736
737 /* CPU Transcoder for the pipe. Currently this can only differ from the
738 * pipe on Haswell and later (where we have a special eDP transcoder)
739 * and Broxton (where we have special DSI transcoders). */
740 enum transcoder cpu_transcoder;
741
742 /*
743 * Use reduced/limited/broadcast rbg range, compressing from the full
744 * range fed into the crtcs.
745 */
746 bool limited_color_range;
747
748 /* Bitmask of encoder types (enum intel_output_type)
749 * driven by the pipe.
750 */
751 unsigned int output_types;
752
753 /* Whether we should send NULL infoframes. Required for audio. */
754 bool has_hdmi_sink;
755
756 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
757 * has_dp_encoder is set. */
758 bool has_audio;
759
760 /*
761 * Enable dithering, used when the selected pipe bpp doesn't match the
762 * plane bpp.
763 */
764 bool dither;
765
766 /*
767 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
768 * compliance video pattern tests.
769 * Disable dither only if it is a compliance test request for
770 * 18bpp.
771 */
772 bool dither_force_disable;
773
774 /* Controls for the clock computation, to override various stages. */
775 bool clock_set;
776
777 /* SDVO TV has a bunch of special case. To make multifunction encoders
778 * work correctly, we need to track this at runtime.*/
779 bool sdvo_tv_clock;
780
781 /*
782 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
783 * required. This is set in the 2nd loop of calling encoder's
784 * ->compute_config if the first pick doesn't work out.
785 */
786 bool bw_constrained;
787
788 /* Settings for the intel dpll used on pretty much everything but
789 * haswell. */
790 struct dpll dpll;
791
792 /* Selected dpll when shared or NULL. */
793 struct intel_shared_dpll *shared_dpll;
794
795 /* Actual register state of the dpll, for shared dpll cross-checking. */
796 struct intel_dpll_hw_state dpll_hw_state;
797
798 /* DSI PLL registers */
799 struct {
800 u32 ctrl, div;
801 } dsi_pll;
802
803 int pipe_bpp;
804 struct intel_link_m_n dp_m_n;
805
806 /* m2_n2 for eDP downclock */
807 struct intel_link_m_n dp_m2_n2;
808 bool has_drrs;
809
810 bool has_psr;
811 bool has_psr2;
812
813 /*
814 * Frequence the dpll for the port should run at. Differs from the
815 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
816 * already multiplied by pixel_multiplier.
817 */
818 int port_clock;
819
820 /* Used by SDVO (and if we ever fix it, HDMI). */
821 unsigned pixel_multiplier;
822
823 uint8_t lane_count;
824
825 /*
826 * Used by platforms having DP/HDMI PHY with programmable lane
827 * latency optimization.
828 */
829 uint8_t lane_lat_optim_mask;
830
831 /* minimum acceptable voltage level */
832 u8 min_voltage_level;
833
834 /* Panel fitter controls for gen2-gen4 + VLV */
835 struct {
836 u32 control;
837 u32 pgm_ratios;
838 u32 lvds_border_bits;
839 } gmch_pfit;
840
841 /* Panel fitter placement and size for Ironlake+ */
842 struct {
843 u32 pos;
844 u32 size;
845 bool enabled;
846 bool force_thru;
847 } pch_pfit;
848
849 /* FDI configuration, only valid if has_pch_encoder is set. */
850 int fdi_lanes;
851 struct intel_link_m_n fdi_m_n;
852
853 bool ips_enabled;
854 bool ips_force_disable;
855
856 bool enable_fbc;
857
858 bool double_wide;
859
860 int pbn;
861
862 struct intel_crtc_scaler_state scaler_state;
863
864 /* w/a for waiting 2 vblanks during crtc enable */
865 enum pipe hsw_workaround_pipe;
866
867 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
868 bool disable_lp_wm;
869
870 struct intel_crtc_wm_state wm;
871
872 /* Gamma mode programmed on the pipe */
873 uint32_t gamma_mode;
874
875 /* bitmask of visible planes (enum plane_id) */
876 u8 active_planes;
877
878 /* HDMI scrambling status */
879 bool hdmi_scrambling;
880
881 /* HDMI High TMDS char rate ratio */
882 bool hdmi_high_tmds_clock_ratio;
883
884 /* output format is YCBCR 4:2:0 */
885 bool ycbcr420;
886};
887
888struct intel_crtc {
889 struct drm_crtc base;
890 enum pipe pipe;
891 /*
892 * Whether the crtc and the connected output pipeline is active. Implies
893 * that crtc->enabled is set, i.e. the current mode configuration has
894 * some outputs connected to this crtc.
895 */
896 bool active;
897 u8 plane_ids_mask;
898 unsigned long long enabled_power_domains;
899 struct intel_overlay *overlay;
900
901 struct intel_crtc_state *config;
902
903 /* global reset count when the last flip was submitted */
904 unsigned int reset_count;
905
906 /* Access to these should be protected by dev_priv->irq_lock. */
907 bool cpu_fifo_underrun_disabled;
908 bool pch_fifo_underrun_disabled;
909
910 /* per-pipe watermark state */
911 struct {
912 /* watermarks currently being used */
913 union {
914 struct intel_pipe_wm ilk;
915 struct vlv_wm_state vlv;
916 struct g4x_wm_state g4x;
917 } active;
918 } wm;
919
920 int scanline_offset;
921
922 struct {
923 unsigned start_vbl_count;
924 ktime_t start_vbl_time;
925 int min_vbl, max_vbl;
926 int scanline_start;
927 } debug;
928
929 /* scalers available on this crtc */
930 int num_scalers;
931};
932
933struct intel_plane {
934 struct drm_plane base;
935 enum i9xx_plane_id i9xx_plane;
936 enum plane_id id;
937 enum pipe pipe;
938 bool can_scale;
939 bool has_fbc;
940 int max_downscale;
941 uint32_t frontbuffer_bit;
942
943 struct {
944 u32 base, cntl, size;
945 } cursor;
946
947 /*
948 * NOTE: Do not place new plane state fields here (e.g., when adding
949 * new plane properties). New runtime state should now be placed in
950 * the intel_plane_state structure and accessed via plane_state.
951 */
952
953 void (*update_plane)(struct intel_plane *plane,
954 const struct intel_crtc_state *crtc_state,
955 const struct intel_plane_state *plane_state);
956 void (*disable_plane)(struct intel_plane *plane,
957 struct intel_crtc *crtc);
958 bool (*get_hw_state)(struct intel_plane *plane);
959 int (*check_plane)(struct intel_plane *plane,
960 struct intel_crtc_state *crtc_state,
961 struct intel_plane_state *state);
962};
963
964struct intel_watermark_params {
965 u16 fifo_size;
966 u16 max_wm;
967 u8 default_wm;
968 u8 guard_size;
969 u8 cacheline_size;
970};
971
972struct cxsr_latency {
973 bool is_desktop : 1;
974 bool is_ddr3 : 1;
975 u16 fsb_freq;
976 u16 mem_freq;
977 u16 display_sr;
978 u16 display_hpll_disable;
979 u16 cursor_sr;
980 u16 cursor_hpll_disable;
981};
982
983#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
984#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
985#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
986#define to_intel_connector(x) container_of(x, struct intel_connector, base)
987#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
988#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
989#define to_intel_plane(x) container_of(x, struct intel_plane, base)
990#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
991#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
992
993struct intel_hdmi {
994 i915_reg_t hdmi_reg;
995 int ddc_bus;
996 struct {
997 enum drm_dp_dual_mode_type type;
998 int max_tmds_clock;
999 } dp_dual_mode;
1000 bool has_hdmi_sink;
1001 bool has_audio;
1002 bool rgb_quant_range_selectable;
1003 struct intel_connector *attached_connector;
1004};
1005
1006struct intel_dp_mst_encoder;
1007#define DP_MAX_DOWNSTREAM_PORTS 0x10
1008
1009/*
1010 * enum link_m_n_set:
1011 * When platform provides two set of M_N registers for dp, we can
1012 * program them and switch between them incase of DRRS.
1013 * But When only one such register is provided, we have to program the
1014 * required divider value on that registers itself based on the DRRS state.
1015 *
1016 * M1_N1 : Program dp_m_n on M1_N1 registers
1017 * dp_m2_n2 on M2_N2 registers (If supported)
1018 *
1019 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1020 * M2_N2 registers are not supported
1021 */
1022
1023enum link_m_n_set {
1024 /* Sets the m1_n1 and m2_n2 */
1025 M1_N1 = 0,
1026 M2_N2
1027};
1028
1029struct intel_dp_compliance_data {
1030 unsigned long edid;
1031 uint8_t video_pattern;
1032 uint16_t hdisplay, vdisplay;
1033 uint8_t bpc;
1034};
1035
1036struct intel_dp_compliance {
1037 unsigned long test_type;
1038 struct intel_dp_compliance_data test_data;
1039 bool test_active;
1040 int test_link_rate;
1041 u8 test_lane_count;
1042};
1043
1044struct intel_dp {
1045 i915_reg_t output_reg;
1046 uint32_t DP;
1047 int link_rate;
1048 uint8_t lane_count;
1049 uint8_t sink_count;
1050 bool link_mst;
1051 bool link_trained;
1052 bool has_audio;
1053 bool detect_done;
1054 bool reset_link_params;
1055 enum aux_ch aux_ch;
1056 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1057 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1058 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1059 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1060 /* source rates */
1061 int num_source_rates;
1062 const int *source_rates;
1063 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1064 int num_sink_rates;
1065 int sink_rates[DP_MAX_SUPPORTED_RATES];
1066 bool use_rate_select;
1067 /* intersection of source and sink rates */
1068 int num_common_rates;
1069 int common_rates[DP_MAX_SUPPORTED_RATES];
1070 /* Max lane count for the current link */
1071 int max_link_lane_count;
1072 /* Max rate for the current link */
1073 int max_link_rate;
1074 /* sink or branch descriptor */
1075 struct drm_dp_desc desc;
1076 struct drm_dp_aux aux;
1077 enum intel_display_power_domain aux_power_domain;
1078 uint8_t train_set[4];
1079 int panel_power_up_delay;
1080 int panel_power_down_delay;
1081 int panel_power_cycle_delay;
1082 int backlight_on_delay;
1083 int backlight_off_delay;
1084 struct delayed_work panel_vdd_work;
1085 bool want_panel_vdd;
1086 unsigned long last_power_on;
1087 unsigned long last_backlight_off;
1088 ktime_t panel_power_off_time;
1089
1090 struct notifier_block edp_notifier;
1091
1092 /*
1093 * Pipe whose power sequencer is currently locked into
1094 * this port. Only relevant on VLV/CHV.
1095 */
1096 enum pipe pps_pipe;
1097 /*
1098 * Pipe currently driving the port. Used for preventing
1099 * the use of the PPS for any pipe currentrly driving
1100 * external DP as that will mess things up on VLV.
1101 */
1102 enum pipe active_pipe;
1103 /*
1104 * Set if the sequencer may be reset due to a power transition,
1105 * requiring a reinitialization. Only relevant on BXT.
1106 */
1107 bool pps_reset;
1108 struct edp_power_seq pps_delays;
1109
1110 bool can_mst; /* this port supports mst */
1111 bool is_mst;
1112 int active_mst_links;
1113 /* connector directly attached - won't be use for modeset in mst world */
1114 struct intel_connector *attached_connector;
1115
1116 /* mst connector list */
1117 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1118 struct drm_dp_mst_topology_mgr mst_mgr;
1119
1120 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1121 /*
1122 * This function returns the value we have to program the AUX_CTL
1123 * register with to kick off an AUX transaction.
1124 */
1125 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1126 bool has_aux_irq,
1127 int send_bytes,
1128 uint32_t aux_clock_divider);
1129
1130 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1131 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1132
1133 /* This is called before a link training is starterd */
1134 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1135
1136 /* Displayport compliance testing */
1137 struct intel_dp_compliance compliance;
1138};
1139
1140struct intel_lspcon {
1141 bool active;
1142 enum drm_lspcon_mode mode;
1143};
1144
1145struct intel_digital_port {
1146 struct intel_encoder base;
1147 u32 saved_port_bits;
1148 struct intel_dp dp;
1149 struct intel_hdmi hdmi;
1150 struct intel_lspcon lspcon;
1151 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1152 bool release_cl2_override;
1153 uint8_t max_lanes;
1154 enum intel_display_power_domain ddi_io_power_domain;
1155
1156 void (*write_infoframe)(struct drm_encoder *encoder,
1157 const struct intel_crtc_state *crtc_state,
1158 unsigned int type,
1159 const void *frame, ssize_t len);
1160 void (*set_infoframes)(struct drm_encoder *encoder,
1161 bool enable,
1162 const struct intel_crtc_state *crtc_state,
1163 const struct drm_connector_state *conn_state);
1164 bool (*infoframe_enabled)(struct drm_encoder *encoder,
1165 const struct intel_crtc_state *pipe_config);
1166};
1167
1168struct intel_dp_mst_encoder {
1169 struct intel_encoder base;
1170 enum pipe pipe;
1171 struct intel_digital_port *primary;
1172 struct intel_connector *connector;
1173};
1174
1175static inline enum dpio_channel
1176vlv_dport_to_channel(struct intel_digital_port *dport)
1177{
1178 switch (dport->base.port) {
1179 case PORT_B:
1180 case PORT_D:
1181 return DPIO_CH0;
1182 case PORT_C:
1183 return DPIO_CH1;
1184 default:
1185 BUG();
1186 }
1187}
1188
1189static inline enum dpio_phy
1190vlv_dport_to_phy(struct intel_digital_port *dport)
1191{
1192 switch (dport->base.port) {
1193 case PORT_B:
1194 case PORT_C:
1195 return DPIO_PHY0;
1196 case PORT_D:
1197 return DPIO_PHY1;
1198 default:
1199 BUG();
1200 }
1201}
1202
1203static inline enum dpio_channel
1204vlv_pipe_to_channel(enum pipe pipe)
1205{
1206 switch (pipe) {
1207 case PIPE_A:
1208 case PIPE_C:
1209 return DPIO_CH0;
1210 case PIPE_B:
1211 return DPIO_CH1;
1212 default:
1213 BUG();
1214 }
1215}
1216
1217static inline struct intel_crtc *
1218intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1219{
1220 return dev_priv->pipe_to_crtc_mapping[pipe];
1221}
1222
1223static inline struct intel_crtc *
1224intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1225{
1226 return dev_priv->plane_to_crtc_mapping[plane];
1227}
1228
1229struct intel_load_detect_pipe {
1230 struct drm_atomic_state *restore_state;
1231};
1232
1233static inline struct intel_encoder *
1234intel_attached_encoder(struct drm_connector *connector)
1235{
1236 return to_intel_connector(connector)->encoder;
1237}
1238
1239static inline struct intel_digital_port *
1240enc_to_dig_port(struct drm_encoder *encoder)
1241{
1242 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1243
1244 switch (intel_encoder->type) {
1245 case INTEL_OUTPUT_DDI:
1246 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1247 case INTEL_OUTPUT_DP:
1248 case INTEL_OUTPUT_EDP:
1249 case INTEL_OUTPUT_HDMI:
1250 return container_of(encoder, struct intel_digital_port,
1251 base.base);
1252 default:
1253 return NULL;
1254 }
1255}
1256
1257static inline struct intel_dp_mst_encoder *
1258enc_to_mst(struct drm_encoder *encoder)
1259{
1260 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1261}
1262
1263static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1264{
1265 return &enc_to_dig_port(encoder)->dp;
1266}
1267
1268static inline struct intel_digital_port *
1269dp_to_dig_port(struct intel_dp *intel_dp)
1270{
1271 return container_of(intel_dp, struct intel_digital_port, dp);
1272}
1273
1274static inline struct intel_lspcon *
1275dp_to_lspcon(struct intel_dp *intel_dp)
1276{
1277 return &dp_to_dig_port(intel_dp)->lspcon;
1278}
1279
1280static inline struct intel_digital_port *
1281hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1282{
1283 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1284}
1285
1286static inline struct intel_plane_state *
1287intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1288 struct intel_plane *plane)
1289{
1290 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1291 &plane->base));
1292}
1293
1294static inline struct intel_crtc_state *
1295intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1296 struct intel_crtc *crtc)
1297{
1298 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1299 &crtc->base));
1300}
1301
1302static inline struct intel_crtc_state *
1303intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1304 struct intel_crtc *crtc)
1305{
1306 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1307 &crtc->base));
1308}
1309
1310/* intel_fifo_underrun.c */
1311bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1312 enum pipe pipe, bool enable);
1313bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1314 enum pipe pch_transcoder,
1315 bool enable);
1316void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1317 enum pipe pipe);
1318void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1319 enum pipe pch_transcoder);
1320void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1321void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1322
1323/* i915_irq.c */
1324void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1325void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1326void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1327void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1328void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1329void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1330void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1331
1332static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1333 u32 mask)
1334{
1335 return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1336}
1337
1338void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1339void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1340static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1341{
1342 /*
1343 * We only use drm_irq_uninstall() at unload and VT switch, so
1344 * this is the only thing we need to check.
1345 */
1346 return dev_priv->runtime_pm.irqs_enabled;
1347}
1348
1349int intel_get_crtc_scanline(struct intel_crtc *crtc);
1350void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1351 u8 pipe_mask);
1352void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1353 u8 pipe_mask);
1354void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1355void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1356void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1357
1358/* intel_crt.c */
1359void intel_crt_init(struct drm_i915_private *dev_priv);
1360void intel_crt_reset(struct drm_encoder *encoder);
1361
1362/* intel_ddi.c */
1363void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1364 const struct intel_crtc_state *old_crtc_state,
1365 const struct drm_connector_state *old_conn_state);
1366void hsw_fdi_link_train(struct intel_crtc *crtc,
1367 const struct intel_crtc_state *crtc_state);
1368void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1369bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1370void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1371void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1372 enum transcoder cpu_transcoder);
1373void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1374void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state);
1375struct intel_encoder *
1376intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1377void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1378void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1379bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1380void intel_ddi_get_config(struct intel_encoder *encoder,
1381 struct intel_crtc_state *pipe_config);
1382
1383void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1384 bool state);
1385void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1386 struct intel_crtc_state *crtc_state);
1387u32 bxt_signal_levels(struct intel_dp *intel_dp);
1388uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1389u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1390int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1391 bool enable);
1392
1393unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1394 int plane, unsigned int height);
1395
1396/* intel_audio.c */
1397void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1398void intel_audio_codec_enable(struct intel_encoder *encoder,
1399 const struct intel_crtc_state *crtc_state,
1400 const struct drm_connector_state *conn_state);
1401void intel_audio_codec_disable(struct intel_encoder *encoder,
1402 const struct intel_crtc_state *old_crtc_state,
1403 const struct drm_connector_state *old_conn_state);
1404void i915_audio_component_init(struct drm_i915_private *dev_priv);
1405void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1406void intel_audio_init(struct drm_i915_private *dev_priv);
1407void intel_audio_deinit(struct drm_i915_private *dev_priv);
1408
1409/* intel_cdclk.c */
1410int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1411void skl_init_cdclk(struct drm_i915_private *dev_priv);
1412void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1413void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1414void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1415void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1416void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1417void icl_init_cdclk(struct drm_i915_private *dev_priv);
1418void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1419void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1420void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1421void intel_update_cdclk(struct drm_i915_private *dev_priv);
1422void intel_update_rawclk(struct drm_i915_private *dev_priv);
1423bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1424 const struct intel_cdclk_state *b);
1425bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1426 const struct intel_cdclk_state *b);
1427void intel_set_cdclk(struct drm_i915_private *dev_priv,
1428 const struct intel_cdclk_state *cdclk_state);
1429void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1430 const char *context);
1431
1432/* intel_display.c */
1433void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1434void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1435enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1436void intel_update_rawclk(struct drm_i915_private *dev_priv);
1437int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1438int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1439 const char *name, u32 reg, int ref_freq);
1440int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1441 const char *name, u32 reg);
1442void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1443void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1444void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1445unsigned int intel_fb_xy_to_linear(int x, int y,
1446 const struct intel_plane_state *state,
1447 int plane);
1448void intel_add_fb_offsets(int *x, int *y,
1449 const struct intel_plane_state *state, int plane);
1450unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1451bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1452void intel_mark_busy(struct drm_i915_private *dev_priv);
1453void intel_mark_idle(struct drm_i915_private *dev_priv);
1454int intel_display_suspend(struct drm_device *dev);
1455void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1456void intel_encoder_destroy(struct drm_encoder *encoder);
1457int intel_connector_init(struct intel_connector *);
1458struct intel_connector *intel_connector_alloc(void);
1459void intel_connector_free(struct intel_connector *connector);
1460bool intel_connector_get_hw_state(struct intel_connector *connector);
1461void intel_connector_attach_encoder(struct intel_connector *connector,
1462 struct intel_encoder *encoder);
1463struct drm_display_mode *
1464intel_encoder_current_mode(struct intel_encoder *encoder);
1465
1466enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1467int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1468 struct drm_file *file_priv);
1469enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1470 enum pipe pipe);
1471static inline bool
1472intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1473 enum intel_output_type type)
1474{
1475 return crtc_state->output_types & (1 << type);
1476}
1477static inline bool
1478intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1479{
1480 return crtc_state->output_types &
1481 ((1 << INTEL_OUTPUT_DP) |
1482 (1 << INTEL_OUTPUT_DP_MST) |
1483 (1 << INTEL_OUTPUT_EDP));
1484}
1485static inline void
1486intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1487{
1488 drm_wait_one_vblank(&dev_priv->drm, pipe);
1489}
1490static inline void
1491intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1492{
1493 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1494
1495 if (crtc->active)
1496 intel_wait_for_vblank(dev_priv, pipe);
1497}
1498
1499u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1500
1501int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1502void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1503 struct intel_digital_port *dport,
1504 unsigned int expected_mask);
1505int intel_get_load_detect_pipe(struct drm_connector *connector,
1506 const struct drm_display_mode *mode,
1507 struct intel_load_detect_pipe *old,
1508 struct drm_modeset_acquire_ctx *ctx);
1509void intel_release_load_detect_pipe(struct drm_connector *connector,
1510 struct intel_load_detect_pipe *old,
1511 struct drm_modeset_acquire_ctx *ctx);
1512struct i915_vma *
1513intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1514 unsigned int rotation,
1515 bool uses_fence,
1516 unsigned long *out_flags);
1517void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1518struct drm_framebuffer *
1519intel_framebuffer_create(struct drm_i915_gem_object *obj,
1520 struct drm_mode_fb_cmd2 *mode_cmd);
1521int intel_prepare_plane_fb(struct drm_plane *plane,
1522 struct drm_plane_state *new_state);
1523void intel_cleanup_plane_fb(struct drm_plane *plane,
1524 struct drm_plane_state *old_state);
1525int intel_plane_atomic_get_property(struct drm_plane *plane,
1526 const struct drm_plane_state *state,
1527 struct drm_property *property,
1528 uint64_t *val);
1529int intel_plane_atomic_set_property(struct drm_plane *plane,
1530 struct drm_plane_state *state,
1531 struct drm_property *property,
1532 uint64_t val);
1533int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1534 struct drm_crtc_state *crtc_state,
1535 const struct intel_plane_state *old_plane_state,
1536 struct drm_plane_state *plane_state);
1537
1538void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1539 enum pipe pipe);
1540
1541int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1542 const struct dpll *dpll);
1543void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1544int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1545
1546/* modesetting asserts */
1547void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1548 enum pipe pipe);
1549void assert_pll(struct drm_i915_private *dev_priv,
1550 enum pipe pipe, bool state);
1551#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1552#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1553void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1554#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1555#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1556void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1557 enum pipe pipe, bool state);
1558#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1559#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1560void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1561#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1562#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1563u32 intel_compute_tile_offset(int *x, int *y,
1564 const struct intel_plane_state *state, int plane);
1565void intel_prepare_reset(struct drm_i915_private *dev_priv);
1566void intel_finish_reset(struct drm_i915_private *dev_priv);
1567void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1568void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1569void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1570void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1571void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1572void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1573unsigned int skl_cdclk_get_vco(unsigned int freq);
1574void skl_enable_dc6(struct drm_i915_private *dev_priv);
1575void skl_disable_dc6(struct drm_i915_private *dev_priv);
1576void intel_dp_get_m_n(struct intel_crtc *crtc,
1577 struct intel_crtc_state *pipe_config);
1578void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1579int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1580bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1581 struct dpll *best_clock);
1582int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1583
1584bool intel_crtc_active(struct intel_crtc *crtc);
1585bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1586void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1587void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1588enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1589void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1590 struct intel_crtc_state *pipe_config);
1591
1592int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1593int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1594
1595static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1596{
1597 return i915_ggtt_offset(state->vma);
1598}
1599
1600u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1601 const struct intel_plane_state *plane_state);
1602u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1603 const struct intel_plane_state *plane_state);
1604u32 glk_color_ctl(const struct intel_plane_state *plane_state);
1605u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1606 unsigned int rotation);
1607int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
1608 struct intel_plane_state *plane_state);
1609int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1610
1611/* intel_csr.c */
1612void intel_csr_ucode_init(struct drm_i915_private *);
1613void intel_csr_load_program(struct drm_i915_private *);
1614void intel_csr_ucode_fini(struct drm_i915_private *);
1615void intel_csr_ucode_suspend(struct drm_i915_private *);
1616void intel_csr_ucode_resume(struct drm_i915_private *);
1617
1618/* intel_dp.c */
1619bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1620 enum port port);
1621bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1622 struct intel_connector *intel_connector);
1623void intel_dp_set_link_params(struct intel_dp *intel_dp,
1624 int link_rate, uint8_t lane_count,
1625 bool link_mst);
1626int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1627 int link_rate, uint8_t lane_count);
1628void intel_dp_start_link_train(struct intel_dp *intel_dp);
1629void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1630int intel_dp_retrain_link(struct intel_encoder *encoder,
1631 struct drm_modeset_acquire_ctx *ctx);
1632void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1633void intel_dp_encoder_reset(struct drm_encoder *encoder);
1634void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1635void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1636int intel_dp_sink_crc(struct intel_dp *intel_dp,
1637 struct intel_crtc_state *crtc_state, u8 *crc);
1638bool intel_dp_compute_config(struct intel_encoder *encoder,
1639 struct intel_crtc_state *pipe_config,
1640 struct drm_connector_state *conn_state);
1641bool intel_dp_is_edp(struct intel_dp *intel_dp);
1642bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1643enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1644 bool long_hpd);
1645void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1646 const struct drm_connector_state *conn_state);
1647void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1648void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1649void intel_edp_panel_on(struct intel_dp *intel_dp);
1650void intel_edp_panel_off(struct intel_dp *intel_dp);
1651void intel_dp_mst_suspend(struct drm_device *dev);
1652void intel_dp_mst_resume(struct drm_device *dev);
1653int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1654int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1655int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1656void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1657void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1658uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1659void intel_plane_destroy(struct drm_plane *plane);
1660void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1661 const struct intel_crtc_state *crtc_state);
1662void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1663 const struct intel_crtc_state *crtc_state);
1664void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1665 unsigned int frontbuffer_bits);
1666void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1667 unsigned int frontbuffer_bits);
1668
1669void
1670intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1671 uint8_t dp_train_pat);
1672void
1673intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1674void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1675uint8_t
1676intel_dp_voltage_max(struct intel_dp *intel_dp);
1677uint8_t
1678intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1679void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1680 uint8_t *link_bw, uint8_t *rate_select);
1681bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1682bool
1683intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1684
1685static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1686{
1687 return ~((1 << lane_count) - 1) & 0xf;
1688}
1689
1690bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1691int intel_dp_link_required(int pixel_clock, int bpp);
1692int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1693bool intel_digital_port_connected(struct intel_encoder *encoder);
1694
1695/* intel_dp_aux_backlight.c */
1696int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1697
1698/* intel_dp_mst.c */
1699int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1700void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1701/* intel_dsi.c */
1702void intel_dsi_init(struct drm_i915_private *dev_priv);
1703
1704/* intel_dsi_dcs_backlight.c */
1705int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1706
1707/* intel_dvo.c */
1708void intel_dvo_init(struct drm_i915_private *dev_priv);
1709/* intel_hotplug.c */
1710void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1711bool intel_encoder_hotplug(struct intel_encoder *encoder,
1712 struct intel_connector *connector);
1713
1714/* legacy fbdev emulation in intel_fbdev.c */
1715#ifdef CONFIG_DRM_FBDEV_EMULATION
1716extern int intel_fbdev_init(struct drm_device *dev);
1717extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1718extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1719extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1720extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1721extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1722extern void intel_fbdev_restore_mode(struct drm_device *dev);
1723#else
1724static inline int intel_fbdev_init(struct drm_device *dev)
1725{
1726 return 0;
1727}
1728
1729static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1730{
1731}
1732
1733static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1734{
1735}
1736
1737static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1738{
1739}
1740
1741static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1742{
1743}
1744
1745static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1746{
1747}
1748
1749static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1750{
1751}
1752#endif
1753
1754/* intel_fbc.c */
1755void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1756 struct intel_atomic_state *state);
1757bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1758void intel_fbc_pre_update(struct intel_crtc *crtc,
1759 struct intel_crtc_state *crtc_state,
1760 struct intel_plane_state *plane_state);
1761void intel_fbc_post_update(struct intel_crtc *crtc);
1762void intel_fbc_init(struct drm_i915_private *dev_priv);
1763void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1764void intel_fbc_enable(struct intel_crtc *crtc,
1765 struct intel_crtc_state *crtc_state,
1766 struct intel_plane_state *plane_state);
1767void intel_fbc_disable(struct intel_crtc *crtc);
1768void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1769void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1770 unsigned int frontbuffer_bits,
1771 enum fb_op_origin origin);
1772void intel_fbc_flush(struct drm_i915_private *dev_priv,
1773 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1774void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1775void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1776
1777/* intel_hdmi.c */
1778void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1779 enum port port);
1780void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1781 struct intel_connector *intel_connector);
1782struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1783bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1784 struct intel_crtc_state *pipe_config,
1785 struct drm_connector_state *conn_state);
1786void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
1787 struct drm_connector *connector,
1788 bool high_tmds_clock_ratio,
1789 bool scrambling);
1790void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1791void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1792
1793
1794/* intel_lvds.c */
1795void intel_lvds_init(struct drm_i915_private *dev_priv);
1796struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1797bool intel_is_dual_link_lvds(struct drm_device *dev);
1798
1799
1800/* intel_modes.c */
1801int intel_connector_update_modes(struct drm_connector *connector,
1802 struct edid *edid);
1803int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1804void intel_attach_force_audio_property(struct drm_connector *connector);
1805void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1806void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1807
1808
1809/* intel_overlay.c */
1810void intel_setup_overlay(struct drm_i915_private *dev_priv);
1811void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1812int intel_overlay_switch_off(struct intel_overlay *overlay);
1813int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1814 struct drm_file *file_priv);
1815int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1816 struct drm_file *file_priv);
1817void intel_overlay_reset(struct drm_i915_private *dev_priv);
1818
1819
1820/* intel_panel.c */
1821int intel_panel_init(struct intel_panel *panel,
1822 struct drm_display_mode *fixed_mode,
1823 struct drm_display_mode *alt_fixed_mode,
1824 struct drm_display_mode *downclock_mode);
1825void intel_panel_fini(struct intel_panel *panel);
1826void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1827 struct drm_display_mode *adjusted_mode);
1828void intel_pch_panel_fitting(struct intel_crtc *crtc,
1829 struct intel_crtc_state *pipe_config,
1830 int fitting_mode);
1831void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1832 struct intel_crtc_state *pipe_config,
1833 int fitting_mode);
1834void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1835 u32 level, u32 max);
1836int intel_panel_setup_backlight(struct drm_connector *connector,
1837 enum pipe pipe);
1838void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1839 const struct drm_connector_state *conn_state);
1840void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1841void intel_panel_destroy_backlight(struct drm_connector *connector);
1842enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1843extern struct drm_display_mode *intel_find_panel_downclock(
1844 struct drm_i915_private *dev_priv,
1845 struct drm_display_mode *fixed_mode,
1846 struct drm_connector *connector);
1847
1848#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1849int intel_backlight_device_register(struct intel_connector *connector);
1850void intel_backlight_device_unregister(struct intel_connector *connector);
1851#else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1852static inline int intel_backlight_device_register(struct intel_connector *connector)
1853{
1854 return 0;
1855}
1856static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1857{
1858}
1859#endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1860
1861/* intel_hdcp.c */
1862void intel_hdcp_atomic_check(struct drm_connector *connector,
1863 struct drm_connector_state *old_state,
1864 struct drm_connector_state *new_state);
1865int intel_hdcp_init(struct intel_connector *connector,
1866 const struct intel_hdcp_shim *hdcp_shim);
1867int intel_hdcp_enable(struct intel_connector *connector);
1868int intel_hdcp_disable(struct intel_connector *connector);
1869int intel_hdcp_check_link(struct intel_connector *connector);
1870bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
1871
1872/* intel_psr.c */
1873#define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
1874void intel_psr_init_dpcd(struct intel_dp *intel_dp);
1875void intel_psr_enable(struct intel_dp *intel_dp,
1876 const struct intel_crtc_state *crtc_state);
1877void intel_psr_disable(struct intel_dp *intel_dp,
1878 const struct intel_crtc_state *old_crtc_state);
1879void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1880 unsigned frontbuffer_bits);
1881void intel_psr_flush(struct drm_i915_private *dev_priv,
1882 unsigned frontbuffer_bits,
1883 enum fb_op_origin origin);
1884void intel_psr_init(struct drm_i915_private *dev_priv);
1885void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1886 unsigned frontbuffer_bits);
1887void intel_psr_compute_config(struct intel_dp *intel_dp,
1888 struct intel_crtc_state *crtc_state);
1889
1890/* intel_runtime_pm.c */
1891int intel_power_domains_init(struct drm_i915_private *);
1892void intel_power_domains_fini(struct drm_i915_private *);
1893void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1894void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1895void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1896void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1897void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1898void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1899const char *
1900intel_display_power_domain_str(enum intel_display_power_domain domain);
1901
1902bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1903 enum intel_display_power_domain domain);
1904bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1905 enum intel_display_power_domain domain);
1906void intel_display_power_get(struct drm_i915_private *dev_priv,
1907 enum intel_display_power_domain domain);
1908bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1909 enum intel_display_power_domain domain);
1910void intel_display_power_put(struct drm_i915_private *dev_priv,
1911 enum intel_display_power_domain domain);
1912
1913static inline void
1914assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1915{
1916 WARN_ONCE(dev_priv->runtime_pm.suspended,
1917 "Device suspended during HW access\n");
1918}
1919
1920static inline void
1921assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1922{
1923 assert_rpm_device_not_suspended(dev_priv);
1924 WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
1925 "RPM wakelock ref not held during HW access");
1926}
1927
1928/**
1929 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1930 * @dev_priv: i915 device instance
1931 *
1932 * This function disable asserts that check if we hold an RPM wakelock
1933 * reference, while keeping the device-not-suspended checks still enabled.
1934 * It's meant to be used only in special circumstances where our rule about
1935 * the wakelock refcount wrt. the device power state doesn't hold. According
1936 * to this rule at any point where we access the HW or want to keep the HW in
1937 * an active state we must hold an RPM wakelock reference acquired via one of
1938 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1939 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1940 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1941 * users should avoid using this function.
1942 *
1943 * Any calls to this function must have a symmetric call to
1944 * enable_rpm_wakeref_asserts().
1945 */
1946static inline void
1947disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1948{
1949 atomic_inc(&dev_priv->runtime_pm.wakeref_count);
1950}
1951
1952/**
1953 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1954 * @dev_priv: i915 device instance
1955 *
1956 * This function re-enables the RPM assert checks after disabling them with
1957 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1958 * circumstances otherwise its use should be avoided.
1959 *
1960 * Any calls to this function must have a symmetric call to
1961 * disable_rpm_wakeref_asserts().
1962 */
1963static inline void
1964enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1965{
1966 atomic_dec(&dev_priv->runtime_pm.wakeref_count);
1967}
1968
1969void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1970bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1971void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1972void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1973
1974void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1975
1976void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1977 bool override, unsigned int mask);
1978bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1979 enum dpio_channel ch, bool override);
1980
1981
1982/* intel_pm.c */
1983void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1984void intel_suspend_hw(struct drm_i915_private *dev_priv);
1985int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1986void intel_update_watermarks(struct intel_crtc *crtc);
1987void intel_init_pm(struct drm_i915_private *dev_priv);
1988void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1989void intel_pm_setup(struct drm_i915_private *dev_priv);
1990void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1991void intel_gpu_ips_teardown(void);
1992void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1993void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1994void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1995void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1996void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1997void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1998void gen6_rps_busy(struct drm_i915_private *dev_priv);
1999void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2000void gen6_rps_idle(struct drm_i915_private *dev_priv);
2001void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2002void g4x_wm_get_hw_state(struct drm_device *dev);
2003void vlv_wm_get_hw_state(struct drm_device *dev);
2004void ilk_wm_get_hw_state(struct drm_device *dev);
2005void skl_wm_get_hw_state(struct drm_device *dev);
2006void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2007 struct skl_ddb_allocation *ddb /* out */);
2008void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
2009 struct skl_pipe_wm *out);
2010void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2011void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2012bool intel_can_enable_sagv(struct drm_atomic_state *state);
2013int intel_enable_sagv(struct drm_i915_private *dev_priv);
2014int intel_disable_sagv(struct drm_i915_private *dev_priv);
2015bool skl_wm_level_equals(const struct skl_wm_level *l1,
2016 const struct skl_wm_level *l2);
2017bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
2018 const struct skl_ddb_entry **entries,
2019 const struct skl_ddb_entry *ddb,
2020 int ignore);
2021bool ilk_disable_lp_wm(struct drm_device *dev);
2022int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2023 struct intel_crtc_state *cstate);
2024void intel_init_ipc(struct drm_i915_private *dev_priv);
2025void intel_enable_ipc(struct drm_i915_private *dev_priv);
2026
2027/* intel_sdvo.c */
2028bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2029 i915_reg_t reg, enum port port);
2030
2031
2032/* intel_sprite.c */
2033bool intel_format_is_yuv(u32 format);
2034int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2035 int usecs);
2036struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2037 enum pipe pipe, int plane);
2038int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2039 struct drm_file *file_priv);
2040void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2041void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2042void skl_update_plane(struct intel_plane *plane,
2043 const struct intel_crtc_state *crtc_state,
2044 const struct intel_plane_state *plane_state);
2045void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
2046bool skl_plane_get_hw_state(struct intel_plane *plane);
2047bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
2048 enum pipe pipe, enum plane_id plane_id);
2049
2050/* intel_tv.c */
2051void intel_tv_init(struct drm_i915_private *dev_priv);
2052
2053/* intel_atomic.c */
2054int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2055 const struct drm_connector_state *state,
2056 struct drm_property *property,
2057 uint64_t *val);
2058int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2059 struct drm_connector_state *state,
2060 struct drm_property *property,
2061 uint64_t val);
2062int intel_digital_connector_atomic_check(struct drm_connector *conn,
2063 struct drm_connector_state *new_state);
2064struct drm_connector_state *
2065intel_digital_connector_duplicate_state(struct drm_connector *connector);
2066
2067struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2068void intel_crtc_destroy_state(struct drm_crtc *crtc,
2069 struct drm_crtc_state *state);
2070struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2071void intel_atomic_state_clear(struct drm_atomic_state *);
2072
2073static inline struct intel_crtc_state *
2074intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2075 struct intel_crtc *crtc)
2076{
2077 struct drm_crtc_state *crtc_state;
2078 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2079 if (IS_ERR(crtc_state))
2080 return ERR_CAST(crtc_state);
2081
2082 return to_intel_crtc_state(crtc_state);
2083}
2084
2085static inline struct intel_crtc_state *
2086intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
2087 struct intel_crtc *crtc)
2088{
2089 struct drm_crtc_state *crtc_state;
2090
2091 crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
2092
2093 if (crtc_state)
2094 return to_intel_crtc_state(crtc_state);
2095 else
2096 return NULL;
2097}
2098
2099static inline struct intel_plane_state *
2100intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
2101 struct intel_plane *plane)
2102{
2103 struct drm_plane_state *plane_state;
2104
2105 plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
2106
2107 return to_intel_plane_state(plane_state);
2108}
2109
2110int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2111 struct intel_crtc *intel_crtc,
2112 struct intel_crtc_state *crtc_state);
2113
2114/* intel_atomic_plane.c */
2115struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
2116struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2117void intel_plane_destroy_state(struct drm_plane *plane,
2118 struct drm_plane_state *state);
2119extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2120int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2121 struct intel_crtc_state *crtc_state,
2122 const struct intel_plane_state *old_plane_state,
2123 struct intel_plane_state *intel_state);
2124
2125/* intel_color.c */
2126void intel_color_init(struct drm_crtc *crtc);
2127int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2128void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2129void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2130
2131/* intel_lspcon.c */
2132bool lspcon_init(struct intel_digital_port *intel_dig_port);
2133void lspcon_resume(struct intel_lspcon *lspcon);
2134void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2135
2136/* intel_pipe_crc.c */
2137int intel_pipe_crc_create(struct drm_minor *minor);
2138#ifdef CONFIG_DEBUG_FS
2139int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
2140 size_t *values_cnt);
2141#else
2142#define intel_crtc_set_crc_source NULL
2143#endif
2144extern const struct file_operations i915_display_crc_ctl_fops;
2145#endif /* __INTEL_DRV_H__ */