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1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
29#include "i915_drv.h"
30#include "drm_crtc.h"
31#include "drm_crtc_helper.h"
32#include "drm_fb_helper.h"
33
34#define _wait_for(COND, MS, W) ({ \
35 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
36 int ret__ = 0; \
37 while (! (COND)) { \
38 if (time_after(jiffies, timeout__)) { \
39 ret__ = -ETIMEDOUT; \
40 break; \
41 } \
42 if (W && !(in_atomic() || in_dbg_master())) msleep(W); \
43 } \
44 ret__; \
45})
46
47#define wait_for(COND, MS) _wait_for(COND, MS, 1)
48#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
49
50#define MSLEEP(x) do { \
51 if (in_dbg_master()) \
52 mdelay(x); \
53 else \
54 msleep(x); \
55} while(0)
56
57#define KHz(x) (1000*x)
58#define MHz(x) KHz(1000*x)
59
60/*
61 * Display related stuff
62 */
63
64/* store information about an Ixxx DVO */
65/* The i830->i865 use multiple DVOs with multiple i2cs */
66/* the i915, i945 have a single sDVO i2c bus - which is different */
67#define MAX_OUTPUTS 6
68/* maximum connectors per crtcs in the mode set */
69#define INTELFB_CONN_LIMIT 4
70
71#define INTEL_I2C_BUS_DVO 1
72#define INTEL_I2C_BUS_SDVO 2
73
74/* these are outputs from the chip - integrated only
75 external chips are via DVO or SDVO output */
76#define INTEL_OUTPUT_UNUSED 0
77#define INTEL_OUTPUT_ANALOG 1
78#define INTEL_OUTPUT_DVO 2
79#define INTEL_OUTPUT_SDVO 3
80#define INTEL_OUTPUT_LVDS 4
81#define INTEL_OUTPUT_TVOUT 5
82#define INTEL_OUTPUT_HDMI 6
83#define INTEL_OUTPUT_DISPLAYPORT 7
84#define INTEL_OUTPUT_EDP 8
85
86/* Intel Pipe Clone Bit */
87#define INTEL_HDMIB_CLONE_BIT 1
88#define INTEL_HDMIC_CLONE_BIT 2
89#define INTEL_HDMID_CLONE_BIT 3
90#define INTEL_HDMIE_CLONE_BIT 4
91#define INTEL_HDMIF_CLONE_BIT 5
92#define INTEL_SDVO_NON_TV_CLONE_BIT 6
93#define INTEL_SDVO_TV_CLONE_BIT 7
94#define INTEL_SDVO_LVDS_CLONE_BIT 8
95#define INTEL_ANALOG_CLONE_BIT 9
96#define INTEL_TV_CLONE_BIT 10
97#define INTEL_DP_B_CLONE_BIT 11
98#define INTEL_DP_C_CLONE_BIT 12
99#define INTEL_DP_D_CLONE_BIT 13
100#define INTEL_LVDS_CLONE_BIT 14
101#define INTEL_DVO_TMDS_CLONE_BIT 15
102#define INTEL_DVO_LVDS_CLONE_BIT 16
103#define INTEL_EDP_CLONE_BIT 17
104
105#define INTEL_DVO_CHIP_NONE 0
106#define INTEL_DVO_CHIP_LVDS 1
107#define INTEL_DVO_CHIP_TMDS 2
108#define INTEL_DVO_CHIP_TVOUT 4
109
110/* drm_display_mode->private_flags */
111#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
112#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
113
114static inline void
115intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
116 int multiplier)
117{
118 mode->clock *= multiplier;
119 mode->private_flags |= multiplier;
120}
121
122static inline int
123intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
124{
125 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
126}
127
128struct intel_framebuffer {
129 struct drm_framebuffer base;
130 struct drm_i915_gem_object *obj;
131};
132
133struct intel_fbdev {
134 struct drm_fb_helper helper;
135 struct intel_framebuffer ifb;
136 struct list_head fbdev_list;
137 struct drm_display_mode *our_mode;
138};
139
140struct intel_encoder {
141 struct drm_encoder base;
142 int type;
143 bool needs_tv_clock;
144 void (*hot_plug)(struct intel_encoder *);
145 int crtc_mask;
146 int clone_mask;
147};
148
149struct intel_connector {
150 struct drm_connector base;
151 struct intel_encoder *encoder;
152};
153
154struct intel_crtc {
155 struct drm_crtc base;
156 enum pipe pipe;
157 enum plane plane;
158 u8 lut_r[256], lut_g[256], lut_b[256];
159 int dpms_mode;
160 bool active; /* is the crtc on? independent of the dpms mode */
161 bool busy; /* is scanout buffer being updated frequently? */
162 struct timer_list idle_timer;
163 bool lowfreq_avail;
164 struct intel_overlay *overlay;
165 struct intel_unpin_work *unpin_work;
166 int fdi_lanes;
167
168 struct drm_i915_gem_object *cursor_bo;
169 uint32_t cursor_addr;
170 int16_t cursor_x, cursor_y;
171 int16_t cursor_width, cursor_height;
172 bool cursor_visible;
173 unsigned int bpp;
174};
175
176#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
177#define to_intel_connector(x) container_of(x, struct intel_connector, base)
178#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
179#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
180
181#define DIP_HEADER_SIZE 5
182
183#define DIP_TYPE_AVI 0x82
184#define DIP_VERSION_AVI 0x2
185#define DIP_LEN_AVI 13
186
187#define DIP_TYPE_SPD 0x3
188#define DIP_VERSION_SPD 0x1
189#define DIP_LEN_SPD 25
190#define DIP_SPD_UNKNOWN 0
191#define DIP_SPD_DSTB 0x1
192#define DIP_SPD_DVDP 0x2
193#define DIP_SPD_DVHS 0x3
194#define DIP_SPD_HDDVR 0x4
195#define DIP_SPD_DVC 0x5
196#define DIP_SPD_DSC 0x6
197#define DIP_SPD_VCD 0x7
198#define DIP_SPD_GAME 0x8
199#define DIP_SPD_PC 0x9
200#define DIP_SPD_BD 0xa
201#define DIP_SPD_SCD 0xb
202
203struct dip_infoframe {
204 uint8_t type; /* HB0 */
205 uint8_t ver; /* HB1 */
206 uint8_t len; /* HB2 - body len, not including checksum */
207 uint8_t ecc; /* Header ECC */
208 uint8_t checksum; /* PB0 */
209 union {
210 struct {
211 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
212 uint8_t Y_A_B_S;
213 /* PB2 - C 7:6, M 5:4, R 3:0 */
214 uint8_t C_M_R;
215 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
216 uint8_t ITC_EC_Q_SC;
217 /* PB4 - VIC 6:0 */
218 uint8_t VIC;
219 /* PB5 - PR 3:0 */
220 uint8_t PR;
221 /* PB6 to PB13 */
222 uint16_t top_bar_end;
223 uint16_t bottom_bar_start;
224 uint16_t left_bar_end;
225 uint16_t right_bar_start;
226 } avi;
227 struct {
228 uint8_t vn[8];
229 uint8_t pd[16];
230 uint8_t sdi;
231 } spd;
232 uint8_t payload[27];
233 } __attribute__ ((packed)) body;
234} __attribute__((packed));
235
236static inline struct drm_crtc *
237intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
238{
239 struct drm_i915_private *dev_priv = dev->dev_private;
240 return dev_priv->pipe_to_crtc_mapping[pipe];
241}
242
243static inline struct drm_crtc *
244intel_get_crtc_for_plane(struct drm_device *dev, int plane)
245{
246 struct drm_i915_private *dev_priv = dev->dev_private;
247 return dev_priv->plane_to_crtc_mapping[plane];
248}
249
250struct intel_unpin_work {
251 struct work_struct work;
252 struct drm_device *dev;
253 struct drm_i915_gem_object *old_fb_obj;
254 struct drm_i915_gem_object *pending_flip_obj;
255 struct drm_pending_vblank_event *event;
256 int pending;
257 bool enable_stall_check;
258};
259
260struct intel_fbc_work {
261 struct delayed_work work;
262 struct drm_crtc *crtc;
263 struct drm_framebuffer *fb;
264 int interval;
265};
266
267int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
268extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus);
269
270extern void intel_attach_force_audio_property(struct drm_connector *connector);
271extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
272
273extern void intel_crt_init(struct drm_device *dev);
274extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg);
275void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
276extern bool intel_sdvo_init(struct drm_device *dev, int output_device);
277extern void intel_dvo_init(struct drm_device *dev);
278extern void intel_tv_init(struct drm_device *dev);
279extern void intel_mark_busy(struct drm_device *dev,
280 struct drm_i915_gem_object *obj);
281extern bool intel_lvds_init(struct drm_device *dev);
282extern void intel_dp_init(struct drm_device *dev, int dp_reg);
283void
284intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
285 struct drm_display_mode *adjusted_mode);
286extern bool intel_dpd_is_edp(struct drm_device *dev);
287extern void intel_edp_link_config (struct intel_encoder *, int *, int *);
288extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
289
290/* intel_panel.c */
291extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
292 struct drm_display_mode *adjusted_mode);
293extern void intel_pch_panel_fitting(struct drm_device *dev,
294 int fitting_mode,
295 struct drm_display_mode *mode,
296 struct drm_display_mode *adjusted_mode);
297extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
298extern u32 intel_panel_get_backlight(struct drm_device *dev);
299extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
300extern int intel_panel_setup_backlight(struct drm_device *dev);
301extern void intel_panel_enable_backlight(struct drm_device *dev);
302extern void intel_panel_disable_backlight(struct drm_device *dev);
303extern void intel_panel_destroy_backlight(struct drm_device *dev);
304extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
305
306extern void intel_crtc_load_lut(struct drm_crtc *crtc);
307extern void intel_encoder_prepare (struct drm_encoder *encoder);
308extern void intel_encoder_commit (struct drm_encoder *encoder);
309extern void intel_encoder_destroy(struct drm_encoder *encoder);
310
311static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
312{
313 return to_intel_connector(connector)->encoder;
314}
315
316extern void intel_connector_attach_encoder(struct intel_connector *connector,
317 struct intel_encoder *encoder);
318extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
319
320extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
321 struct drm_crtc *crtc);
322int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
323 struct drm_file *file_priv);
324extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
325extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
326
327struct intel_load_detect_pipe {
328 struct drm_framebuffer *release_fb;
329 bool load_detect_temp;
330 int dpms_mode;
331};
332extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
333 struct drm_connector *connector,
334 struct drm_display_mode *mode,
335 struct intel_load_detect_pipe *old);
336extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
337 struct drm_connector *connector,
338 struct intel_load_detect_pipe *old);
339
340extern void intelfb_restore(void);
341extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
342 u16 blue, int regno);
343extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
344 u16 *blue, int regno);
345extern void intel_enable_clock_gating(struct drm_device *dev);
346extern void ironlake_enable_drps(struct drm_device *dev);
347extern void ironlake_disable_drps(struct drm_device *dev);
348extern void gen6_enable_rps(struct drm_i915_private *dev_priv);
349extern void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
350extern void gen6_disable_rps(struct drm_device *dev);
351extern void intel_init_emon(struct drm_device *dev);
352
353extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
354 struct drm_i915_gem_object *obj,
355 struct intel_ring_buffer *pipelined);
356
357extern int intel_framebuffer_init(struct drm_device *dev,
358 struct intel_framebuffer *ifb,
359 struct drm_mode_fb_cmd *mode_cmd,
360 struct drm_i915_gem_object *obj);
361extern int intel_fbdev_init(struct drm_device *dev);
362extern void intel_fbdev_fini(struct drm_device *dev);
363
364extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
365extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
366extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
367
368extern void intel_setup_overlay(struct drm_device *dev);
369extern void intel_cleanup_overlay(struct drm_device *dev);
370extern int intel_overlay_switch_off(struct intel_overlay *overlay);
371extern int intel_overlay_put_image(struct drm_device *dev, void *data,
372 struct drm_file *file_priv);
373extern int intel_overlay_attrs(struct drm_device *dev, void *data,
374 struct drm_file *file_priv);
375
376extern void intel_fb_output_poll_changed(struct drm_device *dev);
377extern void intel_fb_restore_mode(struct drm_device *dev);
378
379extern void intel_init_clock_gating(struct drm_device *dev);
380#endif /* __INTEL_DRV_H__ */
1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/async.h>
29#include <linux/i2c.h>
30#include <linux/hdmi.h>
31#include <drm/i915_drm.h>
32#include "i915_drv.h"
33#include <drm/drm_crtc.h>
34#include <drm/drm_crtc_helper.h>
35#include <drm/drm_fb_helper.h>
36#include <drm/drm_dp_dual_mode_helper.h>
37#include <drm/drm_dp_mst_helper.h>
38#include <drm/drm_rect.h>
39#include <drm/drm_atomic.h>
40
41/**
42 * _wait_for - magic (register) wait macro
43 *
44 * Does the right thing for modeset paths when run under kdgb or similar atomic
45 * contexts. Note that it's important that we check the condition again after
46 * having timed out, since the timeout could be due to preemption or similar and
47 * we've never had a chance to check the condition before the timeout.
48 *
49 * TODO: When modesetting has fully transitioned to atomic, the below
50 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
51 * added.
52 */
53#define _wait_for(COND, US, W) ({ \
54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
55 int ret__; \
56 for (;;) { \
57 bool expired__ = time_after(jiffies, timeout__); \
58 if (COND) { \
59 ret__ = 0; \
60 break; \
61 } \
62 if (expired__) { \
63 ret__ = -ETIMEDOUT; \
64 break; \
65 } \
66 if ((W) && drm_can_sleep()) { \
67 usleep_range((W), (W)*2); \
68 } else { \
69 cpu_relax(); \
70 } \
71 } \
72 ret__; \
73})
74
75#define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
76
77/* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
78#if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
79# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
80#else
81# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
82#endif
83
84#define _wait_for_atomic(COND, US, ATOMIC) \
85({ \
86 int cpu, ret, timeout = (US) * 1000; \
87 u64 base; \
88 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
89 BUILD_BUG_ON((US) > 50000); \
90 if (!(ATOMIC)) { \
91 preempt_disable(); \
92 cpu = smp_processor_id(); \
93 } \
94 base = local_clock(); \
95 for (;;) { \
96 u64 now = local_clock(); \
97 if (!(ATOMIC)) \
98 preempt_enable(); \
99 if (COND) { \
100 ret = 0; \
101 break; \
102 } \
103 if (now - base >= timeout) { \
104 ret = -ETIMEDOUT; \
105 break; \
106 } \
107 cpu_relax(); \
108 if (!(ATOMIC)) { \
109 preempt_disable(); \
110 if (unlikely(cpu != smp_processor_id())) { \
111 timeout -= now - base; \
112 cpu = smp_processor_id(); \
113 base = local_clock(); \
114 } \
115 } \
116 } \
117 ret; \
118})
119
120#define wait_for_us(COND, US) \
121({ \
122 int ret__; \
123 BUILD_BUG_ON(!__builtin_constant_p(US)); \
124 if ((US) > 10) \
125 ret__ = _wait_for((COND), (US), 10); \
126 else \
127 ret__ = _wait_for_atomic((COND), (US), 0); \
128 ret__; \
129})
130
131#define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000, 1)
132#define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US), 1)
133
134#define KHz(x) (1000 * (x))
135#define MHz(x) KHz(1000 * (x))
136
137/*
138 * Display related stuff
139 */
140
141/* store information about an Ixxx DVO */
142/* The i830->i865 use multiple DVOs with multiple i2cs */
143/* the i915, i945 have a single sDVO i2c bus - which is different */
144#define MAX_OUTPUTS 6
145/* maximum connectors per crtcs in the mode set */
146
147/* Maximum cursor sizes */
148#define GEN2_CURSOR_WIDTH 64
149#define GEN2_CURSOR_HEIGHT 64
150#define MAX_CURSOR_WIDTH 256
151#define MAX_CURSOR_HEIGHT 256
152
153#define INTEL_I2C_BUS_DVO 1
154#define INTEL_I2C_BUS_SDVO 2
155
156/* these are outputs from the chip - integrated only
157 external chips are via DVO or SDVO output */
158enum intel_output_type {
159 INTEL_OUTPUT_UNUSED = 0,
160 INTEL_OUTPUT_ANALOG = 1,
161 INTEL_OUTPUT_DVO = 2,
162 INTEL_OUTPUT_SDVO = 3,
163 INTEL_OUTPUT_LVDS = 4,
164 INTEL_OUTPUT_TVOUT = 5,
165 INTEL_OUTPUT_HDMI = 6,
166 INTEL_OUTPUT_DP = 7,
167 INTEL_OUTPUT_EDP = 8,
168 INTEL_OUTPUT_DSI = 9,
169 INTEL_OUTPUT_UNKNOWN = 10,
170 INTEL_OUTPUT_DP_MST = 11,
171};
172
173#define INTEL_DVO_CHIP_NONE 0
174#define INTEL_DVO_CHIP_LVDS 1
175#define INTEL_DVO_CHIP_TMDS 2
176#define INTEL_DVO_CHIP_TVOUT 4
177
178#define INTEL_DSI_VIDEO_MODE 0
179#define INTEL_DSI_COMMAND_MODE 1
180
181struct intel_framebuffer {
182 struct drm_framebuffer base;
183 struct drm_i915_gem_object *obj;
184 struct intel_rotation_info rot_info;
185
186 /* for each plane in the normal GTT view */
187 struct {
188 unsigned int x, y;
189 } normal[2];
190 /* for each plane in the rotated GTT view */
191 struct {
192 unsigned int x, y;
193 unsigned int pitch; /* pixels */
194 } rotated[2];
195};
196
197struct intel_fbdev {
198 struct drm_fb_helper helper;
199 struct intel_framebuffer *fb;
200 struct i915_vma *vma;
201 async_cookie_t cookie;
202 int preferred_bpp;
203};
204
205struct intel_encoder {
206 struct drm_encoder base;
207
208 enum intel_output_type type;
209 enum port port;
210 unsigned int cloneable;
211 void (*hot_plug)(struct intel_encoder *);
212 bool (*compute_config)(struct intel_encoder *,
213 struct intel_crtc_state *,
214 struct drm_connector_state *);
215 void (*pre_pll_enable)(struct intel_encoder *,
216 struct intel_crtc_state *,
217 struct drm_connector_state *);
218 void (*pre_enable)(struct intel_encoder *,
219 struct intel_crtc_state *,
220 struct drm_connector_state *);
221 void (*enable)(struct intel_encoder *,
222 struct intel_crtc_state *,
223 struct drm_connector_state *);
224 void (*disable)(struct intel_encoder *,
225 struct intel_crtc_state *,
226 struct drm_connector_state *);
227 void (*post_disable)(struct intel_encoder *,
228 struct intel_crtc_state *,
229 struct drm_connector_state *);
230 void (*post_pll_disable)(struct intel_encoder *,
231 struct intel_crtc_state *,
232 struct drm_connector_state *);
233 /* Read out the current hw state of this connector, returning true if
234 * the encoder is active. If the encoder is enabled it also set the pipe
235 * it is connected to in the pipe parameter. */
236 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
237 /* Reconstructs the equivalent mode flags for the current hardware
238 * state. This must be called _after_ display->get_pipe_config has
239 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
240 * be set correctly before calling this function. */
241 void (*get_config)(struct intel_encoder *,
242 struct intel_crtc_state *pipe_config);
243 /*
244 * Called during system suspend after all pending requests for the
245 * encoder are flushed (for example for DP AUX transactions) and
246 * device interrupts are disabled.
247 */
248 void (*suspend)(struct intel_encoder *);
249 int crtc_mask;
250 enum hpd_pin hpd_pin;
251 /* for communication with audio component; protected by av_mutex */
252 const struct drm_connector *audio_connector;
253};
254
255struct intel_panel {
256 struct drm_display_mode *fixed_mode;
257 struct drm_display_mode *downclock_mode;
258 int fitting_mode;
259
260 /* backlight */
261 struct {
262 bool present;
263 u32 level;
264 u32 min;
265 u32 max;
266 bool enabled;
267 bool combination_mode; /* gen 2/4 only */
268 bool active_low_pwm;
269 bool alternate_pwm_increment; /* lpt+ */
270
271 /* PWM chip */
272 bool util_pin_active_low; /* bxt+ */
273 u8 controller; /* bxt+ only */
274 struct pwm_device *pwm;
275
276 struct backlight_device *device;
277
278 /* Connector and platform specific backlight functions */
279 int (*setup)(struct intel_connector *connector, enum pipe pipe);
280 uint32_t (*get)(struct intel_connector *connector);
281 void (*set)(struct intel_connector *connector, uint32_t level);
282 void (*disable)(struct intel_connector *connector);
283 void (*enable)(struct intel_connector *connector);
284 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
285 uint32_t hz);
286 void (*power)(struct intel_connector *, bool enable);
287 } backlight;
288};
289
290struct intel_connector {
291 struct drm_connector base;
292 /*
293 * The fixed encoder this connector is connected to.
294 */
295 struct intel_encoder *encoder;
296
297 /* ACPI device id for ACPI and driver cooperation */
298 u32 acpi_device_id;
299
300 /* Reads out the current hw, returning true if the connector is enabled
301 * and active (i.e. dpms ON state). */
302 bool (*get_hw_state)(struct intel_connector *);
303
304 /* Panel info for eDP and LVDS */
305 struct intel_panel panel;
306
307 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
308 struct edid *edid;
309 struct edid *detect_edid;
310
311 /* since POLL and HPD connectors may use the same HPD line keep the native
312 state of connector->polled in case hotplug storm detection changes it */
313 u8 polled;
314
315 void *port; /* store this opaque as its illegal to dereference it */
316
317 struct intel_dp *mst_port;
318};
319
320struct dpll {
321 /* given values */
322 int n;
323 int m1, m2;
324 int p1, p2;
325 /* derived values */
326 int dot;
327 int vco;
328 int m;
329 int p;
330};
331
332struct intel_atomic_state {
333 struct drm_atomic_state base;
334
335 unsigned int cdclk;
336
337 /*
338 * Calculated device cdclk, can be different from cdclk
339 * only when all crtc's are DPMS off.
340 */
341 unsigned int dev_cdclk;
342
343 bool dpll_set, modeset;
344
345 /*
346 * Does this transaction change the pipes that are active? This mask
347 * tracks which CRTC's have changed their active state at the end of
348 * the transaction (not counting the temporary disable during modesets).
349 * This mask should only be non-zero when intel_state->modeset is true,
350 * but the converse is not necessarily true; simply changing a mode may
351 * not flip the final active status of any CRTC's
352 */
353 unsigned int active_pipe_changes;
354
355 unsigned int active_crtcs;
356 unsigned int min_pixclk[I915_MAX_PIPES];
357
358 /* SKL/KBL Only */
359 unsigned int cdclk_pll_vco;
360
361 struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
362
363 /*
364 * Current watermarks can't be trusted during hardware readout, so
365 * don't bother calculating intermediate watermarks.
366 */
367 bool skip_intermediate_wm;
368
369 /* Gen9+ only */
370 struct skl_wm_values wm_results;
371
372 struct i915_sw_fence commit_ready;
373
374 struct llist_node freed;
375};
376
377struct intel_plane_state {
378 struct drm_plane_state base;
379 struct drm_rect clip;
380 struct i915_vma *vma;
381
382 struct {
383 u32 offset;
384 int x, y;
385 } main;
386 struct {
387 u32 offset;
388 int x, y;
389 } aux;
390
391 /*
392 * scaler_id
393 * = -1 : not using a scaler
394 * >= 0 : using a scalers
395 *
396 * plane requiring a scaler:
397 * - During check_plane, its bit is set in
398 * crtc_state->scaler_state.scaler_users by calling helper function
399 * update_scaler_plane.
400 * - scaler_id indicates the scaler it got assigned.
401 *
402 * plane doesn't require a scaler:
403 * - this can happen when scaling is no more required or plane simply
404 * got disabled.
405 * - During check_plane, corresponding bit is reset in
406 * crtc_state->scaler_state.scaler_users by calling helper function
407 * update_scaler_plane.
408 */
409 int scaler_id;
410
411 struct drm_intel_sprite_colorkey ckey;
412};
413
414struct intel_initial_plane_config {
415 struct intel_framebuffer *fb;
416 unsigned int tiling;
417 int size;
418 u32 base;
419};
420
421#define SKL_MIN_SRC_W 8
422#define SKL_MAX_SRC_W 4096
423#define SKL_MIN_SRC_H 8
424#define SKL_MAX_SRC_H 4096
425#define SKL_MIN_DST_W 8
426#define SKL_MAX_DST_W 4096
427#define SKL_MIN_DST_H 8
428#define SKL_MAX_DST_H 4096
429
430struct intel_scaler {
431 int in_use;
432 uint32_t mode;
433};
434
435struct intel_crtc_scaler_state {
436#define SKL_NUM_SCALERS 2
437 struct intel_scaler scalers[SKL_NUM_SCALERS];
438
439 /*
440 * scaler_users: keeps track of users requesting scalers on this crtc.
441 *
442 * If a bit is set, a user is using a scaler.
443 * Here user can be a plane or crtc as defined below:
444 * bits 0-30 - plane (bit position is index from drm_plane_index)
445 * bit 31 - crtc
446 *
447 * Instead of creating a new index to cover planes and crtc, using
448 * existing drm_plane_index for planes which is well less than 31
449 * planes and bit 31 for crtc. This should be fine to cover all
450 * our platforms.
451 *
452 * intel_atomic_setup_scalers will setup available scalers to users
453 * requesting scalers. It will gracefully fail if request exceeds
454 * avilability.
455 */
456#define SKL_CRTC_INDEX 31
457 unsigned scaler_users;
458
459 /* scaler used by crtc for panel fitting purpose */
460 int scaler_id;
461};
462
463/* drm_mode->private_flags */
464#define I915_MODE_FLAG_INHERITED 1
465
466struct intel_pipe_wm {
467 struct intel_wm_level wm[5];
468 struct intel_wm_level raw_wm[5];
469 uint32_t linetime;
470 bool fbc_wm_enabled;
471 bool pipe_enabled;
472 bool sprites_enabled;
473 bool sprites_scaled;
474};
475
476struct skl_plane_wm {
477 struct skl_wm_level wm[8];
478 struct skl_wm_level trans_wm;
479};
480
481struct skl_pipe_wm {
482 struct skl_plane_wm planes[I915_MAX_PLANES];
483 uint32_t linetime;
484};
485
486struct intel_crtc_wm_state {
487 union {
488 struct {
489 /*
490 * Intermediate watermarks; these can be
491 * programmed immediately since they satisfy
492 * both the current configuration we're
493 * switching away from and the new
494 * configuration we're switching to.
495 */
496 struct intel_pipe_wm intermediate;
497
498 /*
499 * Optimal watermarks, programmed post-vblank
500 * when this state is committed.
501 */
502 struct intel_pipe_wm optimal;
503 } ilk;
504
505 struct {
506 /* gen9+ only needs 1-step wm programming */
507 struct skl_pipe_wm optimal;
508 struct skl_ddb_entry ddb;
509 } skl;
510 };
511
512 /*
513 * Platforms with two-step watermark programming will need to
514 * update watermark programming post-vblank to switch from the
515 * safe intermediate watermarks to the optimal final
516 * watermarks.
517 */
518 bool need_postvbl_update;
519};
520
521struct intel_crtc_state {
522 struct drm_crtc_state base;
523
524 /**
525 * quirks - bitfield with hw state readout quirks
526 *
527 * For various reasons the hw state readout code might not be able to
528 * completely faithfully read out the current state. These cases are
529 * tracked with quirk flags so that fastboot and state checker can act
530 * accordingly.
531 */
532#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
533 unsigned long quirks;
534
535 unsigned fb_bits; /* framebuffers to flip */
536 bool update_pipe; /* can a fast modeset be performed? */
537 bool disable_cxsr;
538 bool update_wm_pre, update_wm_post; /* watermarks are updated */
539 bool fb_changed; /* fb on any of the planes is changed */
540
541 /* Pipe source size (ie. panel fitter input size)
542 * All planes will be positioned inside this space,
543 * and get clipped at the edges. */
544 int pipe_src_w, pipe_src_h;
545
546 /* Whether to set up the PCH/FDI. Note that we never allow sharing
547 * between pch encoders and cpu encoders. */
548 bool has_pch_encoder;
549
550 /* Are we sending infoframes on the attached port */
551 bool has_infoframe;
552
553 /* CPU Transcoder for the pipe. Currently this can only differ from the
554 * pipe on Haswell and later (where we have a special eDP transcoder)
555 * and Broxton (where we have special DSI transcoders). */
556 enum transcoder cpu_transcoder;
557
558 /*
559 * Use reduced/limited/broadcast rbg range, compressing from the full
560 * range fed into the crtcs.
561 */
562 bool limited_color_range;
563
564 /* Bitmask of encoder types (enum intel_output_type)
565 * driven by the pipe.
566 */
567 unsigned int output_types;
568
569 /* Whether we should send NULL infoframes. Required for audio. */
570 bool has_hdmi_sink;
571
572 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
573 * has_dp_encoder is set. */
574 bool has_audio;
575
576 /*
577 * Enable dithering, used when the selected pipe bpp doesn't match the
578 * plane bpp.
579 */
580 bool dither;
581
582 /* Controls for the clock computation, to override various stages. */
583 bool clock_set;
584
585 /* SDVO TV has a bunch of special case. To make multifunction encoders
586 * work correctly, we need to track this at runtime.*/
587 bool sdvo_tv_clock;
588
589 /*
590 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
591 * required. This is set in the 2nd loop of calling encoder's
592 * ->compute_config if the first pick doesn't work out.
593 */
594 bool bw_constrained;
595
596 /* Settings for the intel dpll used on pretty much everything but
597 * haswell. */
598 struct dpll dpll;
599
600 /* Selected dpll when shared or NULL. */
601 struct intel_shared_dpll *shared_dpll;
602
603 /* Actual register state of the dpll, for shared dpll cross-checking. */
604 struct intel_dpll_hw_state dpll_hw_state;
605
606 /* DSI PLL registers */
607 struct {
608 u32 ctrl, div;
609 } dsi_pll;
610
611 int pipe_bpp;
612 struct intel_link_m_n dp_m_n;
613
614 /* m2_n2 for eDP downclock */
615 struct intel_link_m_n dp_m2_n2;
616 bool has_drrs;
617
618 /*
619 * Frequence the dpll for the port should run at. Differs from the
620 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
621 * already multiplied by pixel_multiplier.
622 */
623 int port_clock;
624
625 /* Used by SDVO (and if we ever fix it, HDMI). */
626 unsigned pixel_multiplier;
627
628 uint8_t lane_count;
629
630 /*
631 * Used by platforms having DP/HDMI PHY with programmable lane
632 * latency optimization.
633 */
634 uint8_t lane_lat_optim_mask;
635
636 /* Panel fitter controls for gen2-gen4 + VLV */
637 struct {
638 u32 control;
639 u32 pgm_ratios;
640 u32 lvds_border_bits;
641 } gmch_pfit;
642
643 /* Panel fitter placement and size for Ironlake+ */
644 struct {
645 u32 pos;
646 u32 size;
647 bool enabled;
648 bool force_thru;
649 } pch_pfit;
650
651 /* FDI configuration, only valid if has_pch_encoder is set. */
652 int fdi_lanes;
653 struct intel_link_m_n fdi_m_n;
654
655 bool ips_enabled;
656
657 bool enable_fbc;
658
659 bool double_wide;
660
661 int pbn;
662
663 struct intel_crtc_scaler_state scaler_state;
664
665 /* w/a for waiting 2 vblanks during crtc enable */
666 enum pipe hsw_workaround_pipe;
667
668 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
669 bool disable_lp_wm;
670
671 struct intel_crtc_wm_state wm;
672
673 /* Gamma mode programmed on the pipe */
674 uint32_t gamma_mode;
675};
676
677struct vlv_wm_state {
678 struct vlv_pipe_wm wm[3];
679 struct vlv_sr_wm sr[3];
680 uint8_t num_active_planes;
681 uint8_t num_levels;
682 uint8_t level;
683 bool cxsr;
684};
685
686struct intel_crtc {
687 struct drm_crtc base;
688 enum pipe pipe;
689 enum plane plane;
690 u8 lut_r[256], lut_g[256], lut_b[256];
691 /*
692 * Whether the crtc and the connected output pipeline is active. Implies
693 * that crtc->enabled is set, i.e. the current mode configuration has
694 * some outputs connected to this crtc.
695 */
696 bool active;
697 unsigned long enabled_power_domains;
698 bool lowfreq_avail;
699 struct intel_overlay *overlay;
700 struct intel_flip_work *flip_work;
701
702 atomic_t unpin_work_count;
703
704 /* Display surface base address adjustement for pageflips. Note that on
705 * gen4+ this only adjusts up to a tile, offsets within a tile are
706 * handled in the hw itself (with the TILEOFF register). */
707 u32 dspaddr_offset;
708 int adjusted_x;
709 int adjusted_y;
710
711 uint32_t cursor_addr;
712 uint32_t cursor_cntl;
713 uint32_t cursor_size;
714 uint32_t cursor_base;
715
716 struct intel_crtc_state *config;
717
718 /* global reset count when the last flip was submitted */
719 unsigned int reset_count;
720
721 /* Access to these should be protected by dev_priv->irq_lock. */
722 bool cpu_fifo_underrun_disabled;
723 bool pch_fifo_underrun_disabled;
724
725 /* per-pipe watermark state */
726 struct {
727 /* watermarks currently being used */
728 union {
729 struct intel_pipe_wm ilk;
730 } active;
731
732 /* allow CxSR on this pipe */
733 bool cxsr_allowed;
734 } wm;
735
736 int scanline_offset;
737
738 struct {
739 unsigned start_vbl_count;
740 ktime_t start_vbl_time;
741 int min_vbl, max_vbl;
742 int scanline_start;
743 } debug;
744
745 /* scalers available on this crtc */
746 int num_scalers;
747
748 struct vlv_wm_state wm_state;
749};
750
751struct intel_plane_wm_parameters {
752 uint32_t horiz_pixels;
753 uint32_t vert_pixels;
754 /*
755 * For packed pixel formats:
756 * bytes_per_pixel - holds bytes per pixel
757 * For planar pixel formats:
758 * bytes_per_pixel - holds bytes per pixel for uv-plane
759 * y_bytes_per_pixel - holds bytes per pixel for y-plane
760 */
761 uint8_t bytes_per_pixel;
762 uint8_t y_bytes_per_pixel;
763 bool enabled;
764 bool scaled;
765 u64 tiling;
766 unsigned int rotation;
767 uint16_t fifo_size;
768};
769
770struct intel_plane {
771 struct drm_plane base;
772 int plane;
773 enum pipe pipe;
774 bool can_scale;
775 int max_downscale;
776 uint32_t frontbuffer_bit;
777
778 /* Since we need to change the watermarks before/after
779 * enabling/disabling the planes, we need to store the parameters here
780 * as the other pieces of the struct may not reflect the values we want
781 * for the watermark calculations. Currently only Haswell uses this.
782 */
783 struct intel_plane_wm_parameters wm;
784
785 /*
786 * NOTE: Do not place new plane state fields here (e.g., when adding
787 * new plane properties). New runtime state should now be placed in
788 * the intel_plane_state structure and accessed via plane_state.
789 */
790
791 void (*update_plane)(struct drm_plane *plane,
792 const struct intel_crtc_state *crtc_state,
793 const struct intel_plane_state *plane_state);
794 void (*disable_plane)(struct drm_plane *plane,
795 struct drm_crtc *crtc);
796 int (*check_plane)(struct drm_plane *plane,
797 struct intel_crtc_state *crtc_state,
798 struct intel_plane_state *state);
799};
800
801struct intel_watermark_params {
802 u16 fifo_size;
803 u16 max_wm;
804 u8 default_wm;
805 u8 guard_size;
806 u8 cacheline_size;
807};
808
809struct cxsr_latency {
810 bool is_desktop : 1;
811 bool is_ddr3 : 1;
812 u16 fsb_freq;
813 u16 mem_freq;
814 u16 display_sr;
815 u16 display_hpll_disable;
816 u16 cursor_sr;
817 u16 cursor_hpll_disable;
818};
819
820#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
821#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
822#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
823#define to_intel_connector(x) container_of(x, struct intel_connector, base)
824#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
825#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
826#define to_intel_plane(x) container_of(x, struct intel_plane, base)
827#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
828#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
829
830struct intel_hdmi {
831 i915_reg_t hdmi_reg;
832 int ddc_bus;
833 struct {
834 enum drm_dp_dual_mode_type type;
835 int max_tmds_clock;
836 } dp_dual_mode;
837 bool limited_color_range;
838 bool color_range_auto;
839 bool has_hdmi_sink;
840 bool has_audio;
841 enum hdmi_force_audio force_audio;
842 bool rgb_quant_range_selectable;
843 enum hdmi_picture_aspect aspect_ratio;
844 struct intel_connector *attached_connector;
845 void (*write_infoframe)(struct drm_encoder *encoder,
846 enum hdmi_infoframe_type type,
847 const void *frame, ssize_t len);
848 void (*set_infoframes)(struct drm_encoder *encoder,
849 bool enable,
850 const struct drm_display_mode *adjusted_mode);
851 bool (*infoframe_enabled)(struct drm_encoder *encoder,
852 const struct intel_crtc_state *pipe_config);
853};
854
855struct intel_dp_mst_encoder;
856#define DP_MAX_DOWNSTREAM_PORTS 0x10
857
858/*
859 * enum link_m_n_set:
860 * When platform provides two set of M_N registers for dp, we can
861 * program them and switch between them incase of DRRS.
862 * But When only one such register is provided, we have to program the
863 * required divider value on that registers itself based on the DRRS state.
864 *
865 * M1_N1 : Program dp_m_n on M1_N1 registers
866 * dp_m2_n2 on M2_N2 registers (If supported)
867 *
868 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
869 * M2_N2 registers are not supported
870 */
871
872enum link_m_n_set {
873 /* Sets the m1_n1 and m2_n2 */
874 M1_N1 = 0,
875 M2_N2
876};
877
878struct intel_dp_desc {
879 u8 oui[3];
880 u8 device_id[6];
881 u8 hw_rev;
882 u8 sw_major_rev;
883 u8 sw_minor_rev;
884} __packed;
885
886struct intel_dp {
887 i915_reg_t output_reg;
888 i915_reg_t aux_ch_ctl_reg;
889 i915_reg_t aux_ch_data_reg[5];
890 uint32_t DP;
891 int link_rate;
892 uint8_t lane_count;
893 uint8_t sink_count;
894 bool link_mst;
895 bool has_audio;
896 bool detect_done;
897 bool channel_eq_status;
898 enum hdmi_force_audio force_audio;
899 bool limited_color_range;
900 bool color_range_auto;
901 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
902 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
903 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
904 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
905 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
906 uint8_t num_sink_rates;
907 int sink_rates[DP_MAX_SUPPORTED_RATES];
908 /* sink or branch descriptor */
909 struct intel_dp_desc desc;
910 struct drm_dp_aux aux;
911 uint8_t train_set[4];
912 int panel_power_up_delay;
913 int panel_power_down_delay;
914 int panel_power_cycle_delay;
915 int backlight_on_delay;
916 int backlight_off_delay;
917 struct delayed_work panel_vdd_work;
918 bool want_panel_vdd;
919 unsigned long last_power_on;
920 unsigned long last_backlight_off;
921 ktime_t panel_power_off_time;
922
923 struct notifier_block edp_notifier;
924
925 /*
926 * Pipe whose power sequencer is currently locked into
927 * this port. Only relevant on VLV/CHV.
928 */
929 enum pipe pps_pipe;
930 /*
931 * Set if the sequencer may be reset due to a power transition,
932 * requiring a reinitialization. Only relevant on BXT.
933 */
934 bool pps_reset;
935 struct edp_power_seq pps_delays;
936
937 bool can_mst; /* this port supports mst */
938 bool is_mst;
939 int active_mst_links;
940 /* connector directly attached - won't be use for modeset in mst world */
941 struct intel_connector *attached_connector;
942
943 /* mst connector list */
944 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
945 struct drm_dp_mst_topology_mgr mst_mgr;
946
947 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
948 /*
949 * This function returns the value we have to program the AUX_CTL
950 * register with to kick off an AUX transaction.
951 */
952 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
953 bool has_aux_irq,
954 int send_bytes,
955 uint32_t aux_clock_divider);
956
957 /* This is called before a link training is starterd */
958 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
959
960 /* Displayport compliance testing */
961 unsigned long compliance_test_type;
962 unsigned long compliance_test_data;
963 bool compliance_test_active;
964};
965
966struct intel_lspcon {
967 bool active;
968 enum drm_lspcon_mode mode;
969 bool desc_valid;
970};
971
972struct intel_digital_port {
973 struct intel_encoder base;
974 enum port port;
975 u32 saved_port_bits;
976 struct intel_dp dp;
977 struct intel_hdmi hdmi;
978 struct intel_lspcon lspcon;
979 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
980 bool release_cl2_override;
981 uint8_t max_lanes;
982};
983
984struct intel_dp_mst_encoder {
985 struct intel_encoder base;
986 enum pipe pipe;
987 struct intel_digital_port *primary;
988 struct intel_connector *connector;
989};
990
991static inline enum dpio_channel
992vlv_dport_to_channel(struct intel_digital_port *dport)
993{
994 switch (dport->port) {
995 case PORT_B:
996 case PORT_D:
997 return DPIO_CH0;
998 case PORT_C:
999 return DPIO_CH1;
1000 default:
1001 BUG();
1002 }
1003}
1004
1005static inline enum dpio_phy
1006vlv_dport_to_phy(struct intel_digital_port *dport)
1007{
1008 switch (dport->port) {
1009 case PORT_B:
1010 case PORT_C:
1011 return DPIO_PHY0;
1012 case PORT_D:
1013 return DPIO_PHY1;
1014 default:
1015 BUG();
1016 }
1017}
1018
1019static inline enum dpio_channel
1020vlv_pipe_to_channel(enum pipe pipe)
1021{
1022 switch (pipe) {
1023 case PIPE_A:
1024 case PIPE_C:
1025 return DPIO_CH0;
1026 case PIPE_B:
1027 return DPIO_CH1;
1028 default:
1029 BUG();
1030 }
1031}
1032
1033static inline struct intel_crtc *
1034intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1035{
1036 return dev_priv->pipe_to_crtc_mapping[pipe];
1037}
1038
1039static inline struct intel_crtc *
1040intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1041{
1042 return dev_priv->plane_to_crtc_mapping[plane];
1043}
1044
1045struct intel_flip_work {
1046 struct work_struct unpin_work;
1047 struct work_struct mmio_work;
1048
1049 struct drm_crtc *crtc;
1050 struct i915_vma *old_vma;
1051 struct drm_framebuffer *old_fb;
1052 struct drm_i915_gem_object *pending_flip_obj;
1053 struct drm_pending_vblank_event *event;
1054 atomic_t pending;
1055 u32 flip_count;
1056 u32 gtt_offset;
1057 struct drm_i915_gem_request *flip_queued_req;
1058 u32 flip_queued_vblank;
1059 u32 flip_ready_vblank;
1060 unsigned int rotation;
1061};
1062
1063struct intel_load_detect_pipe {
1064 struct drm_atomic_state *restore_state;
1065};
1066
1067static inline struct intel_encoder *
1068intel_attached_encoder(struct drm_connector *connector)
1069{
1070 return to_intel_connector(connector)->encoder;
1071}
1072
1073static inline struct intel_digital_port *
1074enc_to_dig_port(struct drm_encoder *encoder)
1075{
1076 return container_of(encoder, struct intel_digital_port, base.base);
1077}
1078
1079static inline struct intel_dp_mst_encoder *
1080enc_to_mst(struct drm_encoder *encoder)
1081{
1082 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1083}
1084
1085static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1086{
1087 return &enc_to_dig_port(encoder)->dp;
1088}
1089
1090static inline struct intel_digital_port *
1091dp_to_dig_port(struct intel_dp *intel_dp)
1092{
1093 return container_of(intel_dp, struct intel_digital_port, dp);
1094}
1095
1096static inline struct intel_digital_port *
1097hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1098{
1099 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1100}
1101
1102/* intel_fifo_underrun.c */
1103bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1104 enum pipe pipe, bool enable);
1105bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1106 enum transcoder pch_transcoder,
1107 bool enable);
1108void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1109 enum pipe pipe);
1110void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1111 enum transcoder pch_transcoder);
1112void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1113void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1114
1115/* i915_irq.c */
1116void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1117void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1118void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1119void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1120void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1121void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1122void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1123void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1124void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1125void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1126u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1127void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1128void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1129static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1130{
1131 /*
1132 * We only use drm_irq_uninstall() at unload and VT switch, so
1133 * this is the only thing we need to check.
1134 */
1135 return dev_priv->pm.irqs_enabled;
1136}
1137
1138int intel_get_crtc_scanline(struct intel_crtc *crtc);
1139void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1140 unsigned int pipe_mask);
1141void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1142 unsigned int pipe_mask);
1143void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1144void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1145void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1146
1147/* intel_crt.c */
1148void intel_crt_init(struct drm_device *dev);
1149void intel_crt_reset(struct drm_encoder *encoder);
1150
1151/* intel_ddi.c */
1152void intel_ddi_clk_select(struct intel_encoder *encoder,
1153 struct intel_shared_dpll *pll);
1154void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1155 struct intel_crtc_state *old_crtc_state,
1156 struct drm_connector_state *old_conn_state);
1157void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
1158void hsw_fdi_link_train(struct drm_crtc *crtc);
1159void intel_ddi_init(struct drm_device *dev, enum port port);
1160enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1161bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1162void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1163void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1164 enum transcoder cpu_transcoder);
1165void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1166void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1167bool intel_ddi_pll_select(struct intel_crtc *crtc,
1168 struct intel_crtc_state *crtc_state);
1169void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1170void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1171bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1172void intel_ddi_get_config(struct intel_encoder *encoder,
1173 struct intel_crtc_state *pipe_config);
1174struct intel_encoder *
1175intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1176
1177void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1178void intel_ddi_clock_get(struct intel_encoder *encoder,
1179 struct intel_crtc_state *pipe_config);
1180void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1181uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1182struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp *intel_dp,
1183 int clock);
1184unsigned int intel_fb_align_height(struct drm_device *dev,
1185 unsigned int height,
1186 uint32_t pixel_format,
1187 uint64_t fb_format_modifier);
1188u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1189 uint64_t fb_modifier, uint32_t pixel_format);
1190
1191/* intel_audio.c */
1192void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1193void intel_audio_codec_enable(struct intel_encoder *encoder,
1194 const struct intel_crtc_state *crtc_state,
1195 const struct drm_connector_state *conn_state);
1196void intel_audio_codec_disable(struct intel_encoder *encoder);
1197void i915_audio_component_init(struct drm_i915_private *dev_priv);
1198void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1199
1200/* intel_display.c */
1201enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1202void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1203void intel_update_rawclk(struct drm_i915_private *dev_priv);
1204int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1205 const char *name, u32 reg, int ref_freq);
1206void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1207void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1208extern const struct drm_plane_funcs intel_plane_funcs;
1209void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1210unsigned int intel_fb_xy_to_linear(int x, int y,
1211 const struct intel_plane_state *state,
1212 int plane);
1213void intel_add_fb_offsets(int *x, int *y,
1214 const struct intel_plane_state *state, int plane);
1215unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1216bool intel_has_pending_fb_unpin(struct drm_device *dev);
1217void intel_mark_busy(struct drm_i915_private *dev_priv);
1218void intel_mark_idle(struct drm_i915_private *dev_priv);
1219void intel_crtc_restore_mode(struct drm_crtc *crtc);
1220int intel_display_suspend(struct drm_device *dev);
1221void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1222void intel_encoder_destroy(struct drm_encoder *encoder);
1223int intel_connector_init(struct intel_connector *);
1224struct intel_connector *intel_connector_alloc(void);
1225bool intel_connector_get_hw_state(struct intel_connector *connector);
1226void intel_connector_attach_encoder(struct intel_connector *connector,
1227 struct intel_encoder *encoder);
1228struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1229 struct drm_crtc *crtc);
1230enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1231int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1232 struct drm_file *file_priv);
1233enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1234 enum pipe pipe);
1235static inline bool
1236intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1237 enum intel_output_type type)
1238{
1239 return crtc_state->output_types & (1 << type);
1240}
1241static inline bool
1242intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1243{
1244 return crtc_state->output_types &
1245 ((1 << INTEL_OUTPUT_DP) |
1246 (1 << INTEL_OUTPUT_DP_MST) |
1247 (1 << INTEL_OUTPUT_EDP));
1248}
1249static inline void
1250intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1251{
1252 drm_wait_one_vblank(&dev_priv->drm, pipe);
1253}
1254static inline void
1255intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1256{
1257 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1258
1259 if (crtc->active)
1260 intel_wait_for_vblank(dev_priv, pipe);
1261}
1262
1263u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1264
1265int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1266void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1267 struct intel_digital_port *dport,
1268 unsigned int expected_mask);
1269bool intel_get_load_detect_pipe(struct drm_connector *connector,
1270 struct drm_display_mode *mode,
1271 struct intel_load_detect_pipe *old,
1272 struct drm_modeset_acquire_ctx *ctx);
1273void intel_release_load_detect_pipe(struct drm_connector *connector,
1274 struct intel_load_detect_pipe *old,
1275 struct drm_modeset_acquire_ctx *ctx);
1276struct i915_vma *
1277intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1278void intel_unpin_fb_vma(struct i915_vma *vma);
1279struct drm_framebuffer *
1280__intel_framebuffer_create(struct drm_device *dev,
1281 struct drm_mode_fb_cmd2 *mode_cmd,
1282 struct drm_i915_gem_object *obj);
1283void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1284void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1285void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1286int intel_prepare_plane_fb(struct drm_plane *plane,
1287 struct drm_plane_state *new_state);
1288void intel_cleanup_plane_fb(struct drm_plane *plane,
1289 struct drm_plane_state *old_state);
1290int intel_plane_atomic_get_property(struct drm_plane *plane,
1291 const struct drm_plane_state *state,
1292 struct drm_property *property,
1293 uint64_t *val);
1294int intel_plane_atomic_set_property(struct drm_plane *plane,
1295 struct drm_plane_state *state,
1296 struct drm_property *property,
1297 uint64_t val);
1298int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1299 struct drm_plane_state *plane_state);
1300
1301unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1302 uint64_t fb_modifier, unsigned int cpp);
1303
1304void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1305 enum pipe pipe);
1306
1307int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1308 const struct dpll *dpll);
1309void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1310int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1311
1312/* modesetting asserts */
1313void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1314 enum pipe pipe);
1315void assert_pll(struct drm_i915_private *dev_priv,
1316 enum pipe pipe, bool state);
1317#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1318#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1319void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1320#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1321#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1322void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, bool state);
1324#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1325#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1326void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1327#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1328#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1329u32 intel_compute_tile_offset(int *x, int *y,
1330 const struct intel_plane_state *state, int plane);
1331void intel_prepare_reset(struct drm_i915_private *dev_priv);
1332void intel_finish_reset(struct drm_i915_private *dev_priv);
1333void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1334void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1335void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1336void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1337void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1338void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1339void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1340void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1341void skl_init_cdclk(struct drm_i915_private *dev_priv);
1342void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1343unsigned int skl_cdclk_get_vco(unsigned int freq);
1344void skl_enable_dc6(struct drm_i915_private *dev_priv);
1345void skl_disable_dc6(struct drm_i915_private *dev_priv);
1346void intel_dp_get_m_n(struct intel_crtc *crtc,
1347 struct intel_crtc_state *pipe_config);
1348void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1349int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1350bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1351 struct dpll *best_clock);
1352int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1353
1354bool intel_crtc_active(struct intel_crtc *crtc);
1355void hsw_enable_ips(struct intel_crtc *crtc);
1356void hsw_disable_ips(struct intel_crtc *crtc);
1357enum intel_display_power_domain
1358intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1359enum intel_display_power_domain
1360intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1361void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1362 struct intel_crtc_state *pipe_config);
1363
1364int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1365int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1366
1367static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1368{
1369 return i915_ggtt_offset(state->vma);
1370}
1371
1372u32 skl_plane_ctl_format(uint32_t pixel_format);
1373u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1374u32 skl_plane_ctl_rotation(unsigned int rotation);
1375u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1376 unsigned int rotation);
1377int skl_check_plane_surface(struct intel_plane_state *plane_state);
1378
1379/* intel_csr.c */
1380void intel_csr_ucode_init(struct drm_i915_private *);
1381void intel_csr_load_program(struct drm_i915_private *);
1382void intel_csr_ucode_fini(struct drm_i915_private *);
1383void intel_csr_ucode_suspend(struct drm_i915_private *);
1384void intel_csr_ucode_resume(struct drm_i915_private *);
1385
1386/* intel_dp.c */
1387bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1388bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1389 struct intel_connector *intel_connector);
1390void intel_dp_set_link_params(struct intel_dp *intel_dp,
1391 int link_rate, uint8_t lane_count,
1392 bool link_mst);
1393void intel_dp_start_link_train(struct intel_dp *intel_dp);
1394void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1395void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1396void intel_dp_encoder_reset(struct drm_encoder *encoder);
1397void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1398void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1399int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1400bool intel_dp_compute_config(struct intel_encoder *encoder,
1401 struct intel_crtc_state *pipe_config,
1402 struct drm_connector_state *conn_state);
1403bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
1404enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1405 bool long_hpd);
1406void intel_edp_backlight_on(struct intel_dp *intel_dp);
1407void intel_edp_backlight_off(struct intel_dp *intel_dp);
1408void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1409void intel_edp_panel_on(struct intel_dp *intel_dp);
1410void intel_edp_panel_off(struct intel_dp *intel_dp);
1411void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1412void intel_dp_mst_suspend(struct drm_device *dev);
1413void intel_dp_mst_resume(struct drm_device *dev);
1414int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1415int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1416void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1417void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1418uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1419void intel_plane_destroy(struct drm_plane *plane);
1420void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1421 struct intel_crtc_state *crtc_state);
1422void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1423 struct intel_crtc_state *crtc_state);
1424void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1425 unsigned int frontbuffer_bits);
1426void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1427 unsigned int frontbuffer_bits);
1428
1429void
1430intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1431 uint8_t dp_train_pat);
1432void
1433intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1434void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1435uint8_t
1436intel_dp_voltage_max(struct intel_dp *intel_dp);
1437uint8_t
1438intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1439void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1440 uint8_t *link_bw, uint8_t *rate_select);
1441bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1442bool
1443intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1444
1445static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1446{
1447 return ~((1 << lane_count) - 1) & 0xf;
1448}
1449
1450bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1451bool __intel_dp_read_desc(struct intel_dp *intel_dp,
1452 struct intel_dp_desc *desc);
1453bool intel_dp_read_desc(struct intel_dp *intel_dp);
1454bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1455 struct intel_digital_port *port);
1456
1457/* intel_dp_aux_backlight.c */
1458int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1459
1460/* intel_dp_mst.c */
1461int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1462void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1463/* intel_dsi.c */
1464void intel_dsi_init(struct drm_device *dev);
1465
1466/* intel_dsi_dcs_backlight.c */
1467int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1468
1469/* intel_dvo.c */
1470void intel_dvo_init(struct drm_device *dev);
1471/* intel_hotplug.c */
1472void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1473
1474
1475/* legacy fbdev emulation in intel_fbdev.c */
1476#ifdef CONFIG_DRM_FBDEV_EMULATION
1477extern int intel_fbdev_init(struct drm_device *dev);
1478extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1479extern void intel_fbdev_fini(struct drm_device *dev);
1480extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1481extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1482extern void intel_fbdev_restore_mode(struct drm_device *dev);
1483#else
1484static inline int intel_fbdev_init(struct drm_device *dev)
1485{
1486 return 0;
1487}
1488
1489static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1490{
1491}
1492
1493static inline void intel_fbdev_fini(struct drm_device *dev)
1494{
1495}
1496
1497static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1498{
1499}
1500
1501static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1502{
1503}
1504
1505static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1506{
1507}
1508#endif
1509
1510/* intel_fbc.c */
1511void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1512 struct drm_atomic_state *state);
1513bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1514void intel_fbc_pre_update(struct intel_crtc *crtc,
1515 struct intel_crtc_state *crtc_state,
1516 struct intel_plane_state *plane_state);
1517void intel_fbc_post_update(struct intel_crtc *crtc);
1518void intel_fbc_init(struct drm_i915_private *dev_priv);
1519void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1520void intel_fbc_enable(struct intel_crtc *crtc,
1521 struct intel_crtc_state *crtc_state,
1522 struct intel_plane_state *plane_state);
1523void intel_fbc_disable(struct intel_crtc *crtc);
1524void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1525void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1526 unsigned int frontbuffer_bits,
1527 enum fb_op_origin origin);
1528void intel_fbc_flush(struct drm_i915_private *dev_priv,
1529 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1530void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1531void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1532
1533/* intel_hdmi.c */
1534void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1535void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1536 struct intel_connector *intel_connector);
1537struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1538bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1539 struct intel_crtc_state *pipe_config,
1540 struct drm_connector_state *conn_state);
1541void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1542
1543
1544/* intel_lvds.c */
1545void intel_lvds_init(struct drm_device *dev);
1546struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1547bool intel_is_dual_link_lvds(struct drm_device *dev);
1548
1549
1550/* intel_modes.c */
1551int intel_connector_update_modes(struct drm_connector *connector,
1552 struct edid *edid);
1553int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1554void intel_attach_force_audio_property(struct drm_connector *connector);
1555void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1556void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1557
1558
1559/* intel_overlay.c */
1560void intel_setup_overlay(struct drm_i915_private *dev_priv);
1561void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1562int intel_overlay_switch_off(struct intel_overlay *overlay);
1563int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1564 struct drm_file *file_priv);
1565int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1566 struct drm_file *file_priv);
1567void intel_overlay_reset(struct drm_i915_private *dev_priv);
1568
1569
1570/* intel_panel.c */
1571int intel_panel_init(struct intel_panel *panel,
1572 struct drm_display_mode *fixed_mode,
1573 struct drm_display_mode *downclock_mode);
1574void intel_panel_fini(struct intel_panel *panel);
1575void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1576 struct drm_display_mode *adjusted_mode);
1577void intel_pch_panel_fitting(struct intel_crtc *crtc,
1578 struct intel_crtc_state *pipe_config,
1579 int fitting_mode);
1580void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1581 struct intel_crtc_state *pipe_config,
1582 int fitting_mode);
1583void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1584 u32 level, u32 max);
1585int intel_panel_setup_backlight(struct drm_connector *connector,
1586 enum pipe pipe);
1587void intel_panel_enable_backlight(struct intel_connector *connector);
1588void intel_panel_disable_backlight(struct intel_connector *connector);
1589void intel_panel_destroy_backlight(struct drm_connector *connector);
1590enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1591extern struct drm_display_mode *intel_find_panel_downclock(
1592 struct drm_device *dev,
1593 struct drm_display_mode *fixed_mode,
1594 struct drm_connector *connector);
1595
1596#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1597int intel_backlight_device_register(struct intel_connector *connector);
1598void intel_backlight_device_unregister(struct intel_connector *connector);
1599#else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1600static int intel_backlight_device_register(struct intel_connector *connector)
1601{
1602 return 0;
1603}
1604static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1605{
1606}
1607#endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1608
1609
1610/* intel_psr.c */
1611void intel_psr_enable(struct intel_dp *intel_dp);
1612void intel_psr_disable(struct intel_dp *intel_dp);
1613void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1614 unsigned frontbuffer_bits);
1615void intel_psr_flush(struct drm_i915_private *dev_priv,
1616 unsigned frontbuffer_bits,
1617 enum fb_op_origin origin);
1618void intel_psr_init(struct drm_device *dev);
1619void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1620 unsigned frontbuffer_bits);
1621
1622/* intel_runtime_pm.c */
1623int intel_power_domains_init(struct drm_i915_private *);
1624void intel_power_domains_fini(struct drm_i915_private *);
1625void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1626void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1627void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1628void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1629void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1630const char *
1631intel_display_power_domain_str(enum intel_display_power_domain domain);
1632
1633bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1634 enum intel_display_power_domain domain);
1635bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1636 enum intel_display_power_domain domain);
1637void intel_display_power_get(struct drm_i915_private *dev_priv,
1638 enum intel_display_power_domain domain);
1639bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1640 enum intel_display_power_domain domain);
1641void intel_display_power_put(struct drm_i915_private *dev_priv,
1642 enum intel_display_power_domain domain);
1643
1644static inline void
1645assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1646{
1647 WARN_ONCE(dev_priv->pm.suspended,
1648 "Device suspended during HW access\n");
1649}
1650
1651static inline void
1652assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1653{
1654 assert_rpm_device_not_suspended(dev_priv);
1655 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1656 * too much noise. */
1657 if (!atomic_read(&dev_priv->pm.wakeref_count))
1658 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1659}
1660
1661/**
1662 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1663 * @dev_priv: i915 device instance
1664 *
1665 * This function disable asserts that check if we hold an RPM wakelock
1666 * reference, while keeping the device-not-suspended checks still enabled.
1667 * It's meant to be used only in special circumstances where our rule about
1668 * the wakelock refcount wrt. the device power state doesn't hold. According
1669 * to this rule at any point where we access the HW or want to keep the HW in
1670 * an active state we must hold an RPM wakelock reference acquired via one of
1671 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1672 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1673 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1674 * users should avoid using this function.
1675 *
1676 * Any calls to this function must have a symmetric call to
1677 * enable_rpm_wakeref_asserts().
1678 */
1679static inline void
1680disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1681{
1682 atomic_inc(&dev_priv->pm.wakeref_count);
1683}
1684
1685/**
1686 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1687 * @dev_priv: i915 device instance
1688 *
1689 * This function re-enables the RPM assert checks after disabling them with
1690 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1691 * circumstances otherwise its use should be avoided.
1692 *
1693 * Any calls to this function must have a symmetric call to
1694 * disable_rpm_wakeref_asserts().
1695 */
1696static inline void
1697enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1698{
1699 atomic_dec(&dev_priv->pm.wakeref_count);
1700}
1701
1702void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1703bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1704void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1705void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1706
1707void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1708
1709void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1710 bool override, unsigned int mask);
1711bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1712 enum dpio_channel ch, bool override);
1713
1714
1715/* intel_pm.c */
1716void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1717void intel_suspend_hw(struct drm_i915_private *dev_priv);
1718int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1719void intel_update_watermarks(struct intel_crtc *crtc);
1720void intel_init_pm(struct drm_i915_private *dev_priv);
1721void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1722void intel_pm_setup(struct drm_device *dev);
1723void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1724void intel_gpu_ips_teardown(void);
1725void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1726void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1727void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1728void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1729void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1730void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1731void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1732void gen6_rps_busy(struct drm_i915_private *dev_priv);
1733void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1734void gen6_rps_idle(struct drm_i915_private *dev_priv);
1735void gen6_rps_boost(struct drm_i915_private *dev_priv,
1736 struct intel_rps_client *rps,
1737 unsigned long submitted);
1738void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1739void vlv_wm_get_hw_state(struct drm_device *dev);
1740void ilk_wm_get_hw_state(struct drm_device *dev);
1741void skl_wm_get_hw_state(struct drm_device *dev);
1742void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1743 struct skl_ddb_allocation *ddb /* out */);
1744void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1745 struct skl_pipe_wm *out);
1746bool intel_can_enable_sagv(struct drm_atomic_state *state);
1747int intel_enable_sagv(struct drm_i915_private *dev_priv);
1748int intel_disable_sagv(struct drm_i915_private *dev_priv);
1749bool skl_wm_level_equals(const struct skl_wm_level *l1,
1750 const struct skl_wm_level *l2);
1751bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
1752 const struct skl_ddb_entry *ddb,
1753 int ignore);
1754uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1755bool ilk_disable_lp_wm(struct drm_device *dev);
1756int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1757static inline int intel_enable_rc6(void)
1758{
1759 return i915.enable_rc6;
1760}
1761
1762/* intel_sdvo.c */
1763bool intel_sdvo_init(struct drm_device *dev,
1764 i915_reg_t reg, enum port port);
1765
1766
1767/* intel_sprite.c */
1768int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1769 int usecs);
1770struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1771 enum pipe pipe, int plane);
1772int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1773 struct drm_file *file_priv);
1774void intel_pipe_update_start(struct intel_crtc *crtc);
1775void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1776
1777/* intel_tv.c */
1778void intel_tv_init(struct drm_device *dev);
1779
1780/* intel_atomic.c */
1781int intel_connector_atomic_get_property(struct drm_connector *connector,
1782 const struct drm_connector_state *state,
1783 struct drm_property *property,
1784 uint64_t *val);
1785struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1786void intel_crtc_destroy_state(struct drm_crtc *crtc,
1787 struct drm_crtc_state *state);
1788struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1789void intel_atomic_state_clear(struct drm_atomic_state *);
1790struct intel_shared_dpll_config *
1791intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1792
1793static inline struct intel_crtc_state *
1794intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1795 struct intel_crtc *crtc)
1796{
1797 struct drm_crtc_state *crtc_state;
1798 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1799 if (IS_ERR(crtc_state))
1800 return ERR_CAST(crtc_state);
1801
1802 return to_intel_crtc_state(crtc_state);
1803}
1804
1805static inline struct intel_plane_state *
1806intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1807 struct intel_plane *plane)
1808{
1809 struct drm_plane_state *plane_state;
1810
1811 plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1812
1813 return to_intel_plane_state(plane_state);
1814}
1815
1816int intel_atomic_setup_scalers(struct drm_device *dev,
1817 struct intel_crtc *intel_crtc,
1818 struct intel_crtc_state *crtc_state);
1819
1820/* intel_atomic_plane.c */
1821struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1822struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1823void intel_plane_destroy_state(struct drm_plane *plane,
1824 struct drm_plane_state *state);
1825extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1826
1827/* intel_color.c */
1828void intel_color_init(struct drm_crtc *crtc);
1829int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1830void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1831void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1832
1833/* intel_lspcon.c */
1834bool lspcon_init(struct intel_digital_port *intel_dig_port);
1835void lspcon_resume(struct intel_lspcon *lspcon);
1836#endif /* __INTEL_DRV_H__ */