1/*
  2 * Copyright 2015 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 */
 22
 23#ifndef __AMD_SHARED_H__
 24#define __AMD_SHARED_H__
 25
 26#include <drm/amd_asic_type.h>
 27
 28
 29#define AMD_MAX_USEC_TIMEOUT		200000  /* 200 ms */
 30
 31/*
 32 * Chip flags
 33 */
 34enum amd_chip_flags {
 35	AMD_ASIC_MASK = 0x0000ffffUL,
 36	AMD_FLAGS_MASK  = 0xffff0000UL,
 37	AMD_IS_MOBILITY = 0x00010000UL,
 38	AMD_IS_APU      = 0x00020000UL,
 39	AMD_IS_PX       = 0x00040000UL,
 40	AMD_EXP_HW_SUPPORT = 0x00080000UL,
 41};
 42
 43enum amd_ip_block_type {
 44	AMD_IP_BLOCK_TYPE_COMMON,
 45	AMD_IP_BLOCK_TYPE_GMC,
 46	AMD_IP_BLOCK_TYPE_IH,
 47	AMD_IP_BLOCK_TYPE_SMC,
 48	AMD_IP_BLOCK_TYPE_PSP,
 49	AMD_IP_BLOCK_TYPE_DCE,
 50	AMD_IP_BLOCK_TYPE_GFX,
 51	AMD_IP_BLOCK_TYPE_SDMA,
 52	AMD_IP_BLOCK_TYPE_UVD,
 53	AMD_IP_BLOCK_TYPE_VCE,
 54	AMD_IP_BLOCK_TYPE_ACP,
 55	AMD_IP_BLOCK_TYPE_VCN
 56};
 57
 58enum amd_clockgating_state {
 59	AMD_CG_STATE_GATE = 0,
 60	AMD_CG_STATE_UNGATE,
 61};
 62
 63
 64enum amd_powergating_state {
 65	AMD_PG_STATE_GATE = 0,
 66	AMD_PG_STATE_UNGATE,
 67};
 68
 69
 70/* CG flags */
 71#define AMD_CG_SUPPORT_GFX_MGCG			(1 << 0)
 72#define AMD_CG_SUPPORT_GFX_MGLS			(1 << 1)
 73#define AMD_CG_SUPPORT_GFX_CGCG			(1 << 2)
 74#define AMD_CG_SUPPORT_GFX_CGLS			(1 << 3)
 75#define AMD_CG_SUPPORT_GFX_CGTS			(1 << 4)
 76#define AMD_CG_SUPPORT_GFX_CGTS_LS		(1 << 5)
 77#define AMD_CG_SUPPORT_GFX_CP_LS		(1 << 6)
 78#define AMD_CG_SUPPORT_GFX_RLC_LS		(1 << 7)
 79#define AMD_CG_SUPPORT_MC_LS			(1 << 8)
 80#define AMD_CG_SUPPORT_MC_MGCG			(1 << 9)
 81#define AMD_CG_SUPPORT_SDMA_LS			(1 << 10)
 82#define AMD_CG_SUPPORT_SDMA_MGCG		(1 << 11)
 83#define AMD_CG_SUPPORT_BIF_LS			(1 << 12)
 84#define AMD_CG_SUPPORT_UVD_MGCG			(1 << 13)
 85#define AMD_CG_SUPPORT_VCE_MGCG			(1 << 14)
 86#define AMD_CG_SUPPORT_HDP_LS			(1 << 15)
 87#define AMD_CG_SUPPORT_HDP_MGCG			(1 << 16)
 88#define AMD_CG_SUPPORT_ROM_MGCG			(1 << 17)
 89#define AMD_CG_SUPPORT_DRM_LS			(1 << 18)
 90#define AMD_CG_SUPPORT_BIF_MGCG			(1 << 19)
 91#define AMD_CG_SUPPORT_GFX_3D_CGCG		(1 << 20)
 92#define AMD_CG_SUPPORT_GFX_3D_CGLS		(1 << 21)
 93#define AMD_CG_SUPPORT_DRM_MGCG			(1 << 22)
 94#define AMD_CG_SUPPORT_DF_MGCG			(1 << 23)
 95
 96/* PG flags */
 97#define AMD_PG_SUPPORT_GFX_PG			(1 << 0)
 98#define AMD_PG_SUPPORT_GFX_SMG			(1 << 1)
 99#define AMD_PG_SUPPORT_GFX_DMG			(1 << 2)
100#define AMD_PG_SUPPORT_UVD			(1 << 3)
101#define AMD_PG_SUPPORT_VCE			(1 << 4)
102#define AMD_PG_SUPPORT_CP			(1 << 5)
103#define AMD_PG_SUPPORT_GDS			(1 << 6)
104#define AMD_PG_SUPPORT_RLC_SMU_HS		(1 << 7)
105#define AMD_PG_SUPPORT_SDMA			(1 << 8)
106#define AMD_PG_SUPPORT_ACP			(1 << 9)
107#define AMD_PG_SUPPORT_SAMU			(1 << 10)
108#define AMD_PG_SUPPORT_GFX_QUICK_MG		(1 << 11)
109#define AMD_PG_SUPPORT_GFX_PIPELINE		(1 << 12)
110#define AMD_PG_SUPPORT_MMHUB			(1 << 13)
111
112struct amd_ip_funcs {
113	/* Name of IP block */
114	char *name;
115	/* sets up early driver state (pre sw_init), does not configure hw - Optional */
116	int (*early_init)(void *handle);
117	/* sets up late driver/hw state (post hw_init) - Optional */
118	int (*late_init)(void *handle);
119	/* sets up driver state, does not configure hw */
120	int (*sw_init)(void *handle);
121	/* tears down driver state, does not configure hw */
122	int (*sw_fini)(void *handle);
123	/* sets up the hw state */
124	int (*hw_init)(void *handle);
125	/* tears down the hw state */
126	int (*hw_fini)(void *handle);
127	void (*late_fini)(void *handle);
128	/* handles IP specific hw/sw changes for suspend */
129	int (*suspend)(void *handle);
130	/* handles IP specific hw/sw changes for resume */
131	int (*resume)(void *handle);
132	/* returns current IP block idle status */
133	bool (*is_idle)(void *handle);
134	/* poll for idle */
135	int (*wait_for_idle)(void *handle);
136	/* check soft reset the IP block */
137	bool (*check_soft_reset)(void *handle);
138	/* pre soft reset the IP block */
139	int (*pre_soft_reset)(void *handle);
140	/* soft reset the IP block */
141	int (*soft_reset)(void *handle);
142	/* post soft reset the IP block */
143	int (*post_soft_reset)(void *handle);
144	/* enable/disable cg for the IP block */
145	int (*set_clockgating_state)(void *handle,
146				     enum amd_clockgating_state state);
147	/* enable/disable pg for the IP block */
148	int (*set_powergating_state)(void *handle,
149				     enum amd_powergating_state state);
150	/* get current clockgating status */
151	void (*get_clockgating_state)(void *handle, u32 *flags);
152};
153
154
155#endif /* __AMD_SHARED_H__ */