1/* Common header for intel-gtt.ko and i915.ko */
 2
 3#ifndef _DRM_INTEL_GTT_H
 4#define	_DRM_INTEL_GTT_H
 5
 6const struct intel_gtt {
 7	/* Size of memory reserved for graphics by the BIOS */
 8	unsigned int stolen_size;
 9	/* Total number of gtt entries. */
10	unsigned int gtt_total_entries;
11	/* Part of the gtt that is mappable by the cpu, for those chips where
12	 * this is not the full gtt. */
13	unsigned int gtt_mappable_entries;
14	/* Whether i915 needs to use the dmar apis or not. */
15	unsigned int needs_dmar : 1;
16} *intel_gtt_get(void);
17
18void intel_gtt_chipset_flush(void);
19void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg);
20void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries);
21int intel_gtt_map_memory(struct page **pages, unsigned int num_entries,
22			 struct scatterlist **sg_list, int *num_sg);
23void intel_gtt_insert_sg_entries(struct scatterlist *sg_list,
24				 unsigned int sg_len,
25				 unsigned int pg_start,
26				 unsigned int flags);
27void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries,
28			    struct page **pages, unsigned int flags);
29
30/* Special gtt memory types */
31#define AGP_DCACHE_MEMORY	1
32#define AGP_PHYS_MEMORY		2
33
34/* New caching attributes for gen6/sandybridge */
35#define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2)
36#define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4)
37
38/* flag for GFDT type */
39#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
 
 
 
 
40
41#endif

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/* Common header for intel-gtt.ko and i915.ko */
 3
 4#ifndef _DRM_INTEL_GTT_H
 5#define	_DRM_INTEL_GTT_H
 6
 7void intel_gtt_get(u64 *gtt_total,
 8		   phys_addr_t *mappable_base,
 9		   resource_size_t *mappable_end);
10
11int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
12		     struct agp_bridge_data *bridge);
13void intel_gmch_remove(void);
14
15bool intel_enable_gtt(void);
 
 
16
17void intel_gtt_chipset_flush(void);
18void intel_gtt_insert_page(dma_addr_t addr,
19			   unsigned int pg,
20			   unsigned int flags);
21void intel_gtt_insert_sg_entries(struct sg_table *st,
 
 
22				 unsigned int pg_start,
23				 unsigned int flags);
24void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries);
 
25
26/* Special gtt memory types */
27#define AGP_DCACHE_MEMORY	1
28#define AGP_PHYS_MEMORY		2
29
 
 
 
 
30/* flag for GFDT type */
31#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
32
33#ifdef CONFIG_INTEL_IOMMU
34extern int intel_iommu_gfx_mapped;
35#endif
36
37#endif