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1/*
2 * Freescale STMP37XX/STMP378X Application UART driver
3 *
4 * Author: dmitry pervushin <dimka@embeddedalley.com>
5 *
6 * Copyright 2008-2010 Freescale Semiconductor, Inc.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/init.h>
20#include <linux/console.h>
21#include <linux/interrupt.h>
22#include <linux/module.h>
23#include <linux/slab.h>
24#include <linux/wait.h>
25#include <linux/tty.h>
26#include <linux/tty_driver.h>
27#include <linux/tty_flip.h>
28#include <linux/serial.h>
29#include <linux/serial_core.h>
30#include <linux/platform_device.h>
31#include <linux/device.h>
32#include <linux/clk.h>
33#include <linux/delay.h>
34#include <linux/io.h>
35
36#include <asm/cacheflush.h>
37
38#define MXS_AUART_PORTS 5
39
40#define AUART_CTRL0 0x00000000
41#define AUART_CTRL0_SET 0x00000004
42#define AUART_CTRL0_CLR 0x00000008
43#define AUART_CTRL0_TOG 0x0000000c
44#define AUART_CTRL1 0x00000010
45#define AUART_CTRL1_SET 0x00000014
46#define AUART_CTRL1_CLR 0x00000018
47#define AUART_CTRL1_TOG 0x0000001c
48#define AUART_CTRL2 0x00000020
49#define AUART_CTRL2_SET 0x00000024
50#define AUART_CTRL2_CLR 0x00000028
51#define AUART_CTRL2_TOG 0x0000002c
52#define AUART_LINECTRL 0x00000030
53#define AUART_LINECTRL_SET 0x00000034
54#define AUART_LINECTRL_CLR 0x00000038
55#define AUART_LINECTRL_TOG 0x0000003c
56#define AUART_LINECTRL2 0x00000040
57#define AUART_LINECTRL2_SET 0x00000044
58#define AUART_LINECTRL2_CLR 0x00000048
59#define AUART_LINECTRL2_TOG 0x0000004c
60#define AUART_INTR 0x00000050
61#define AUART_INTR_SET 0x00000054
62#define AUART_INTR_CLR 0x00000058
63#define AUART_INTR_TOG 0x0000005c
64#define AUART_DATA 0x00000060
65#define AUART_STAT 0x00000070
66#define AUART_DEBUG 0x00000080
67#define AUART_VERSION 0x00000090
68#define AUART_AUTOBAUD 0x000000a0
69
70#define AUART_CTRL0_SFTRST (1 << 31)
71#define AUART_CTRL0_CLKGATE (1 << 30)
72
73#define AUART_CTRL2_CTSEN (1 << 15)
74#define AUART_CTRL2_RTS (1 << 11)
75#define AUART_CTRL2_RXE (1 << 9)
76#define AUART_CTRL2_TXE (1 << 8)
77#define AUART_CTRL2_UARTEN (1 << 0)
78
79#define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
80#define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
81#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
82#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
83#define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
84#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
85#define AUART_LINECTRL_WLEN_MASK 0x00000060
86#define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
87#define AUART_LINECTRL_FEN (1 << 4)
88#define AUART_LINECTRL_STP2 (1 << 3)
89#define AUART_LINECTRL_EPS (1 << 2)
90#define AUART_LINECTRL_PEN (1 << 1)
91#define AUART_LINECTRL_BRK (1 << 0)
92
93#define AUART_INTR_RTIEN (1 << 22)
94#define AUART_INTR_TXIEN (1 << 21)
95#define AUART_INTR_RXIEN (1 << 20)
96#define AUART_INTR_CTSMIEN (1 << 17)
97#define AUART_INTR_RTIS (1 << 6)
98#define AUART_INTR_TXIS (1 << 5)
99#define AUART_INTR_RXIS (1 << 4)
100#define AUART_INTR_CTSMIS (1 << 1)
101
102#define AUART_STAT_BUSY (1 << 29)
103#define AUART_STAT_CTS (1 << 28)
104#define AUART_STAT_TXFE (1 << 27)
105#define AUART_STAT_TXFF (1 << 25)
106#define AUART_STAT_RXFE (1 << 24)
107#define AUART_STAT_OERR (1 << 19)
108#define AUART_STAT_BERR (1 << 18)
109#define AUART_STAT_PERR (1 << 17)
110#define AUART_STAT_FERR (1 << 16)
111
112static struct uart_driver auart_driver;
113
114struct mxs_auart_port {
115 struct uart_port port;
116
117 unsigned int flags;
118 unsigned int ctrl;
119
120 unsigned int irq;
121
122 struct clk *clk;
123 struct device *dev;
124};
125
126static void mxs_auart_stop_tx(struct uart_port *u);
127
128#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
129
130static inline void mxs_auart_tx_chars(struct mxs_auart_port *s)
131{
132 struct circ_buf *xmit = &s->port.state->xmit;
133
134 while (!(readl(s->port.membase + AUART_STAT) &
135 AUART_STAT_TXFF)) {
136 if (s->port.x_char) {
137 s->port.icount.tx++;
138 writel(s->port.x_char,
139 s->port.membase + AUART_DATA);
140 s->port.x_char = 0;
141 continue;
142 }
143 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
144 s->port.icount.tx++;
145 writel(xmit->buf[xmit->tail],
146 s->port.membase + AUART_DATA);
147 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
148 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
149 uart_write_wakeup(&s->port);
150 } else
151 break;
152 }
153 if (uart_circ_empty(&(s->port.state->xmit)))
154 writel(AUART_INTR_TXIEN,
155 s->port.membase + AUART_INTR_CLR);
156 else
157 writel(AUART_INTR_TXIEN,
158 s->port.membase + AUART_INTR_SET);
159
160 if (uart_tx_stopped(&s->port))
161 mxs_auart_stop_tx(&s->port);
162}
163
164static void mxs_auart_rx_char(struct mxs_auart_port *s)
165{
166 int flag;
167 u32 stat;
168 u8 c;
169
170 c = readl(s->port.membase + AUART_DATA);
171 stat = readl(s->port.membase + AUART_STAT);
172
173 flag = TTY_NORMAL;
174 s->port.icount.rx++;
175
176 if (stat & AUART_STAT_BERR) {
177 s->port.icount.brk++;
178 if (uart_handle_break(&s->port))
179 goto out;
180 } else if (stat & AUART_STAT_PERR) {
181 s->port.icount.parity++;
182 } else if (stat & AUART_STAT_FERR) {
183 s->port.icount.frame++;
184 }
185
186 /*
187 * Mask off conditions which should be ingored.
188 */
189 stat &= s->port.read_status_mask;
190
191 if (stat & AUART_STAT_BERR) {
192 flag = TTY_BREAK;
193 } else if (stat & AUART_STAT_PERR)
194 flag = TTY_PARITY;
195 else if (stat & AUART_STAT_FERR)
196 flag = TTY_FRAME;
197
198 if (stat & AUART_STAT_OERR)
199 s->port.icount.overrun++;
200
201 if (uart_handle_sysrq_char(&s->port, c))
202 goto out;
203
204 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
205out:
206 writel(stat, s->port.membase + AUART_STAT);
207}
208
209static void mxs_auart_rx_chars(struct mxs_auart_port *s)
210{
211 struct tty_struct *tty = s->port.state->port.tty;
212 u32 stat = 0;
213
214 for (;;) {
215 stat = readl(s->port.membase + AUART_STAT);
216 if (stat & AUART_STAT_RXFE)
217 break;
218 mxs_auart_rx_char(s);
219 }
220
221 writel(stat, s->port.membase + AUART_STAT);
222 tty_flip_buffer_push(tty);
223}
224
225static int mxs_auart_request_port(struct uart_port *u)
226{
227 return 0;
228}
229
230static int mxs_auart_verify_port(struct uart_port *u,
231 struct serial_struct *ser)
232{
233 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
234 return -EINVAL;
235 return 0;
236}
237
238static void mxs_auart_config_port(struct uart_port *u, int flags)
239{
240}
241
242static const char *mxs_auart_type(struct uart_port *u)
243{
244 struct mxs_auart_port *s = to_auart_port(u);
245
246 return dev_name(s->dev);
247}
248
249static void mxs_auart_release_port(struct uart_port *u)
250{
251}
252
253static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
254{
255 struct mxs_auart_port *s = to_auart_port(u);
256
257 u32 ctrl = readl(u->membase + AUART_CTRL2);
258
259 ctrl &= ~AUART_CTRL2_RTS;
260 if (mctrl & TIOCM_RTS)
261 ctrl |= AUART_CTRL2_RTS;
262 s->ctrl = mctrl;
263 writel(ctrl, u->membase + AUART_CTRL2);
264}
265
266static u32 mxs_auart_get_mctrl(struct uart_port *u)
267{
268 struct mxs_auart_port *s = to_auart_port(u);
269 u32 stat = readl(u->membase + AUART_STAT);
270 int ctrl2 = readl(u->membase + AUART_CTRL2);
271 u32 mctrl = s->ctrl;
272
273 mctrl &= ~TIOCM_CTS;
274 if (stat & AUART_STAT_CTS)
275 mctrl |= TIOCM_CTS;
276
277 if (ctrl2 & AUART_CTRL2_RTS)
278 mctrl |= TIOCM_RTS;
279
280 return mctrl;
281}
282
283static void mxs_auart_settermios(struct uart_port *u,
284 struct ktermios *termios,
285 struct ktermios *old)
286{
287 u32 bm, ctrl, ctrl2, div;
288 unsigned int cflag, baud;
289
290 cflag = termios->c_cflag;
291
292 ctrl = AUART_LINECTRL_FEN;
293 ctrl2 = readl(u->membase + AUART_CTRL2);
294
295 /* byte size */
296 switch (cflag & CSIZE) {
297 case CS5:
298 bm = 0;
299 break;
300 case CS6:
301 bm = 1;
302 break;
303 case CS7:
304 bm = 2;
305 break;
306 case CS8:
307 bm = 3;
308 break;
309 default:
310 return;
311 }
312
313 ctrl |= AUART_LINECTRL_WLEN(bm);
314
315 /* parity */
316 if (cflag & PARENB) {
317 ctrl |= AUART_LINECTRL_PEN;
318 if ((cflag & PARODD) == 0)
319 ctrl |= AUART_LINECTRL_EPS;
320 }
321
322 u->read_status_mask = 0;
323
324 if (termios->c_iflag & INPCK)
325 u->read_status_mask |= AUART_STAT_PERR;
326 if (termios->c_iflag & (BRKINT | PARMRK))
327 u->read_status_mask |= AUART_STAT_BERR;
328
329 /*
330 * Characters to ignore
331 */
332 u->ignore_status_mask = 0;
333 if (termios->c_iflag & IGNPAR)
334 u->ignore_status_mask |= AUART_STAT_PERR;
335 if (termios->c_iflag & IGNBRK) {
336 u->ignore_status_mask |= AUART_STAT_BERR;
337 /*
338 * If we're ignoring parity and break indicators,
339 * ignore overruns too (for real raw support).
340 */
341 if (termios->c_iflag & IGNPAR)
342 u->ignore_status_mask |= AUART_STAT_OERR;
343 }
344
345 /*
346 * ignore all characters if CREAD is not set
347 */
348 if (cflag & CREAD)
349 ctrl2 |= AUART_CTRL2_RXE;
350 else
351 ctrl2 &= ~AUART_CTRL2_RXE;
352
353 /* figure out the stop bits requested */
354 if (cflag & CSTOPB)
355 ctrl |= AUART_LINECTRL_STP2;
356
357 /* figure out the hardware flow control settings */
358 if (cflag & CRTSCTS)
359 ctrl2 |= AUART_CTRL2_CTSEN;
360 else
361 ctrl2 &= ~AUART_CTRL2_CTSEN;
362
363 /* set baud rate */
364 baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
365 div = u->uartclk * 32 / baud;
366 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
367 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
368
369 writel(ctrl, u->membase + AUART_LINECTRL);
370 writel(ctrl2, u->membase + AUART_CTRL2);
371}
372
373static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
374{
375 u32 istatus, istat;
376 struct mxs_auart_port *s = context;
377 u32 stat = readl(s->port.membase + AUART_STAT);
378
379 istatus = istat = readl(s->port.membase + AUART_INTR);
380
381 if (istat & AUART_INTR_CTSMIS) {
382 uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS);
383 writel(AUART_INTR_CTSMIS,
384 s->port.membase + AUART_INTR_CLR);
385 istat &= ~AUART_INTR_CTSMIS;
386 }
387
388 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
389 mxs_auart_rx_chars(s);
390 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
391 }
392
393 if (istat & AUART_INTR_TXIS) {
394 mxs_auart_tx_chars(s);
395 istat &= ~AUART_INTR_TXIS;
396 }
397
398 writel(istatus & (AUART_INTR_RTIS
399 | AUART_INTR_TXIS
400 | AUART_INTR_RXIS
401 | AUART_INTR_CTSMIS),
402 s->port.membase + AUART_INTR_CLR);
403
404 return IRQ_HANDLED;
405}
406
407static void mxs_auart_reset(struct uart_port *u)
408{
409 int i;
410 unsigned int reg;
411
412 writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
413
414 for (i = 0; i < 10000; i++) {
415 reg = readl(u->membase + AUART_CTRL0);
416 if (!(reg & AUART_CTRL0_SFTRST))
417 break;
418 udelay(3);
419 }
420 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
421}
422
423static int mxs_auart_startup(struct uart_port *u)
424{
425 struct mxs_auart_port *s = to_auart_port(u);
426
427 clk_enable(s->clk);
428
429 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
430
431 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
432
433 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
434 u->membase + AUART_INTR);
435
436 /*
437 * Enable fifo so all four bytes of a DMA word are written to
438 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
439 */
440 writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
441
442 return 0;
443}
444
445static void mxs_auart_shutdown(struct uart_port *u)
446{
447 struct mxs_auart_port *s = to_auart_port(u);
448
449 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
450
451 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
452
453 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
454 u->membase + AUART_INTR_CLR);
455
456 clk_disable(s->clk);
457}
458
459static unsigned int mxs_auart_tx_empty(struct uart_port *u)
460{
461 if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE)
462 return TIOCSER_TEMT;
463 else
464 return 0;
465}
466
467static void mxs_auart_start_tx(struct uart_port *u)
468{
469 struct mxs_auart_port *s = to_auart_port(u);
470
471 /* enable transmitter */
472 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
473
474 mxs_auart_tx_chars(s);
475}
476
477static void mxs_auart_stop_tx(struct uart_port *u)
478{
479 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
480}
481
482static void mxs_auart_stop_rx(struct uart_port *u)
483{
484 writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
485}
486
487static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
488{
489 if (ctl)
490 writel(AUART_LINECTRL_BRK,
491 u->membase + AUART_LINECTRL_SET);
492 else
493 writel(AUART_LINECTRL_BRK,
494 u->membase + AUART_LINECTRL_CLR);
495}
496
497static void mxs_auart_enable_ms(struct uart_port *port)
498{
499 /* just empty */
500}
501
502static struct uart_ops mxs_auart_ops = {
503 .tx_empty = mxs_auart_tx_empty,
504 .start_tx = mxs_auart_start_tx,
505 .stop_tx = mxs_auart_stop_tx,
506 .stop_rx = mxs_auart_stop_rx,
507 .enable_ms = mxs_auart_enable_ms,
508 .break_ctl = mxs_auart_break_ctl,
509 .set_mctrl = mxs_auart_set_mctrl,
510 .get_mctrl = mxs_auart_get_mctrl,
511 .startup = mxs_auart_startup,
512 .shutdown = mxs_auart_shutdown,
513 .set_termios = mxs_auart_settermios,
514 .type = mxs_auart_type,
515 .release_port = mxs_auart_release_port,
516 .request_port = mxs_auart_request_port,
517 .config_port = mxs_auart_config_port,
518 .verify_port = mxs_auart_verify_port,
519};
520
521static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
522
523#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
524static void mxs_auart_console_putchar(struct uart_port *port, int ch)
525{
526 unsigned int to = 1000;
527
528 while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
529 if (!to--)
530 break;
531 udelay(1);
532 }
533
534 writel(ch, port->membase + AUART_DATA);
535}
536
537static void
538auart_console_write(struct console *co, const char *str, unsigned int count)
539{
540 struct mxs_auart_port *s;
541 struct uart_port *port;
542 unsigned int old_ctrl0, old_ctrl2;
543 unsigned int to = 1000;
544
545 if (co->index > MXS_AUART_PORTS || co->index < 0)
546 return;
547
548 s = auart_port[co->index];
549 port = &s->port;
550
551 clk_enable(s->clk);
552
553 /* First save the CR then disable the interrupts */
554 old_ctrl2 = readl(port->membase + AUART_CTRL2);
555 old_ctrl0 = readl(port->membase + AUART_CTRL0);
556
557 writel(AUART_CTRL0_CLKGATE,
558 port->membase + AUART_CTRL0_CLR);
559 writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
560 port->membase + AUART_CTRL2_SET);
561
562 uart_console_write(port, str, count, mxs_auart_console_putchar);
563
564 /*
565 * Finally, wait for transmitter to become empty
566 * and restore the TCR
567 */
568 while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
569 if (!to--)
570 break;
571 udelay(1);
572 }
573
574 writel(old_ctrl0, port->membase + AUART_CTRL0);
575 writel(old_ctrl2, port->membase + AUART_CTRL2);
576
577 clk_disable(s->clk);
578}
579
580static void __init
581auart_console_get_options(struct uart_port *port, int *baud,
582 int *parity, int *bits)
583{
584 unsigned int lcr_h, quot;
585
586 if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
587 return;
588
589 lcr_h = readl(port->membase + AUART_LINECTRL);
590
591 *parity = 'n';
592 if (lcr_h & AUART_LINECTRL_PEN) {
593 if (lcr_h & AUART_LINECTRL_EPS)
594 *parity = 'e';
595 else
596 *parity = 'o';
597 }
598
599 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
600 *bits = 7;
601 else
602 *bits = 8;
603
604 quot = ((readl(port->membase + AUART_LINECTRL)
605 & AUART_LINECTRL_BAUD_DIVINT_MASK))
606 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
607 quot |= ((readl(port->membase + AUART_LINECTRL)
608 & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
609 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
610 if (quot == 0)
611 quot = 1;
612
613 *baud = (port->uartclk << 2) / quot;
614}
615
616static int __init
617auart_console_setup(struct console *co, char *options)
618{
619 struct mxs_auart_port *s;
620 int baud = 9600;
621 int bits = 8;
622 int parity = 'n';
623 int flow = 'n';
624 int ret;
625
626 /*
627 * Check whether an invalid uart number has been specified, and
628 * if so, search for the first available port that does have
629 * console support.
630 */
631 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
632 co->index = 0;
633 s = auart_port[co->index];
634 if (!s)
635 return -ENODEV;
636
637 clk_enable(s->clk);
638
639 if (options)
640 uart_parse_options(options, &baud, &parity, &bits, &flow);
641 else
642 auart_console_get_options(&s->port, &baud, &parity, &bits);
643
644 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
645
646 clk_disable(s->clk);
647
648 return ret;
649}
650
651static struct console auart_console = {
652 .name = "ttyAPP",
653 .write = auart_console_write,
654 .device = uart_console_device,
655 .setup = auart_console_setup,
656 .flags = CON_PRINTBUFFER,
657 .index = -1,
658 .data = &auart_driver,
659};
660#endif
661
662static struct uart_driver auart_driver = {
663 .owner = THIS_MODULE,
664 .driver_name = "ttyAPP",
665 .dev_name = "ttyAPP",
666 .major = 0,
667 .minor = 0,
668 .nr = MXS_AUART_PORTS,
669#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
670 .cons = &auart_console,
671#endif
672};
673
674static int __devinit mxs_auart_probe(struct platform_device *pdev)
675{
676 struct mxs_auart_port *s;
677 u32 version;
678 int ret = 0;
679 struct resource *r;
680
681 s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
682 if (!s) {
683 ret = -ENOMEM;
684 goto out;
685 }
686
687 s->clk = clk_get(&pdev->dev, NULL);
688 if (IS_ERR(s->clk)) {
689 ret = PTR_ERR(s->clk);
690 goto out_free;
691 }
692
693 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
694 if (!r) {
695 ret = -ENXIO;
696 goto out_free_clk;
697 }
698
699 s->port.mapbase = r->start;
700 s->port.membase = ioremap(r->start, resource_size(r));
701 s->port.ops = &mxs_auart_ops;
702 s->port.iotype = UPIO_MEM;
703 s->port.line = pdev->id < 0 ? 0 : pdev->id;
704 s->port.fifosize = 16;
705 s->port.uartclk = clk_get_rate(s->clk);
706 s->port.type = PORT_IMX;
707 s->port.dev = s->dev = get_device(&pdev->dev);
708
709 s->flags = 0;
710 s->ctrl = 0;
711
712 s->irq = platform_get_irq(pdev, 0);
713 s->port.irq = s->irq;
714 ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s);
715 if (ret)
716 goto out_free_clk;
717
718 platform_set_drvdata(pdev, s);
719
720 auart_port[pdev->id] = s;
721
722 mxs_auart_reset(&s->port);
723
724 ret = uart_add_one_port(&auart_driver, &s->port);
725 if (ret)
726 goto out_free_irq;
727
728 version = readl(s->port.membase + AUART_VERSION);
729 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
730 (version >> 24) & 0xff,
731 (version >> 16) & 0xff, version & 0xffff);
732
733 return 0;
734
735out_free_irq:
736 auart_port[pdev->id] = NULL;
737 free_irq(s->irq, s);
738out_free_clk:
739 clk_put(s->clk);
740out_free:
741 kfree(s);
742out:
743 return ret;
744}
745
746static int __devexit mxs_auart_remove(struct platform_device *pdev)
747{
748 struct mxs_auart_port *s = platform_get_drvdata(pdev);
749
750 uart_remove_one_port(&auart_driver, &s->port);
751
752 auart_port[pdev->id] = NULL;
753
754 clk_put(s->clk);
755 free_irq(s->irq, s);
756 kfree(s);
757
758 return 0;
759}
760
761static struct platform_driver mxs_auart_driver = {
762 .probe = mxs_auart_probe,
763 .remove = __devexit_p(mxs_auart_remove),
764 .driver = {
765 .name = "mxs-auart",
766 .owner = THIS_MODULE,
767 },
768};
769
770static int __init mxs_auart_init(void)
771{
772 int r;
773
774 r = uart_register_driver(&auart_driver);
775 if (r)
776 goto out;
777
778 r = platform_driver_register(&mxs_auart_driver);
779 if (r)
780 goto out_err;
781
782 return 0;
783out_err:
784 uart_unregister_driver(&auart_driver);
785out:
786 return r;
787}
788
789static void __exit mxs_auart_exit(void)
790{
791 platform_driver_unregister(&mxs_auart_driver);
792 uart_unregister_driver(&auart_driver);
793}
794
795module_init(mxs_auart_init);
796module_exit(mxs_auart_exit);
797MODULE_LICENSE("GPL");
798MODULE_DESCRIPTION("Freescale MXS application uart driver");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Application UART driver for:
4 * Freescale STMP37XX/STMP378X
5 * Alphascale ASM9260
6 *
7 * Author: dmitry pervushin <dimka@embeddedalley.com>
8 *
9 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
10 * Provide Alphascale ASM9260 support.
11 * Copyright 2008-2010 Freescale Semiconductor, Inc.
12 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
13 */
14
15#if defined(CONFIG_SERIAL_MXS_AUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
16#define SUPPORT_SYSRQ
17#endif
18
19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/console.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/slab.h>
26#include <linux/wait.h>
27#include <linux/tty.h>
28#include <linux/tty_driver.h>
29#include <linux/tty_flip.h>
30#include <linux/serial.h>
31#include <linux/serial_core.h>
32#include <linux/platform_device.h>
33#include <linux/device.h>
34#include <linux/clk.h>
35#include <linux/delay.h>
36#include <linux/io.h>
37#include <linux/of_device.h>
38#include <linux/dma-mapping.h>
39#include <linux/dmaengine.h>
40
41#include <asm/cacheflush.h>
42
43#include <linux/gpio/consumer.h>
44#include <linux/err.h>
45#include <linux/irq.h>
46#include "serial_mctrl_gpio.h"
47
48#define MXS_AUART_PORTS 5
49#define MXS_AUART_FIFO_SIZE 16
50
51#define SET_REG 0x4
52#define CLR_REG 0x8
53#define TOG_REG 0xc
54
55#define AUART_CTRL0 0x00000000
56#define AUART_CTRL1 0x00000010
57#define AUART_CTRL2 0x00000020
58#define AUART_LINECTRL 0x00000030
59#define AUART_LINECTRL2 0x00000040
60#define AUART_INTR 0x00000050
61#define AUART_DATA 0x00000060
62#define AUART_STAT 0x00000070
63#define AUART_DEBUG 0x00000080
64#define AUART_VERSION 0x00000090
65#define AUART_AUTOBAUD 0x000000a0
66
67#define AUART_CTRL0_SFTRST (1 << 31)
68#define AUART_CTRL0_CLKGATE (1 << 30)
69#define AUART_CTRL0_RXTO_ENABLE (1 << 27)
70#define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
71#define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
72
73#define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
74
75#define AUART_CTRL2_DMAONERR (1 << 26)
76#define AUART_CTRL2_TXDMAE (1 << 25)
77#define AUART_CTRL2_RXDMAE (1 << 24)
78
79#define AUART_CTRL2_CTSEN (1 << 15)
80#define AUART_CTRL2_RTSEN (1 << 14)
81#define AUART_CTRL2_RTS (1 << 11)
82#define AUART_CTRL2_RXE (1 << 9)
83#define AUART_CTRL2_TXE (1 << 8)
84#define AUART_CTRL2_UARTEN (1 << 0)
85
86#define AUART_LINECTRL_BAUD_DIV_MAX 0x003fffc0
87#define AUART_LINECTRL_BAUD_DIV_MIN 0x000000ec
88#define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
89#define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
90#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
91#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
92#define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
93#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
94#define AUART_LINECTRL_SPS (1 << 7)
95#define AUART_LINECTRL_WLEN_MASK 0x00000060
96#define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
97#define AUART_LINECTRL_FEN (1 << 4)
98#define AUART_LINECTRL_STP2 (1 << 3)
99#define AUART_LINECTRL_EPS (1 << 2)
100#define AUART_LINECTRL_PEN (1 << 1)
101#define AUART_LINECTRL_BRK (1 << 0)
102
103#define AUART_INTR_RTIEN (1 << 22)
104#define AUART_INTR_TXIEN (1 << 21)
105#define AUART_INTR_RXIEN (1 << 20)
106#define AUART_INTR_CTSMIEN (1 << 17)
107#define AUART_INTR_RTIS (1 << 6)
108#define AUART_INTR_TXIS (1 << 5)
109#define AUART_INTR_RXIS (1 << 4)
110#define AUART_INTR_CTSMIS (1 << 1)
111
112#define AUART_STAT_BUSY (1 << 29)
113#define AUART_STAT_CTS (1 << 28)
114#define AUART_STAT_TXFE (1 << 27)
115#define AUART_STAT_TXFF (1 << 25)
116#define AUART_STAT_RXFE (1 << 24)
117#define AUART_STAT_OERR (1 << 19)
118#define AUART_STAT_BERR (1 << 18)
119#define AUART_STAT_PERR (1 << 17)
120#define AUART_STAT_FERR (1 << 16)
121#define AUART_STAT_RXCOUNT_MASK 0xffff
122
123/*
124 * Start of Alphascale asm9260 defines
125 * This list contains only differences of existing bits
126 * between imx2x and asm9260
127 */
128#define ASM9260_HW_CTRL0 0x0000
129/*
130 * RW. Tell the UART to execute the RX DMA Command. The
131 * UART will clear this bit at the end of receive execution.
132 */
133#define ASM9260_BM_CTRL0_RXDMA_RUN BIT(28)
134/* RW. 0 use FIFO for status register; 1 use DMA */
135#define ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS BIT(25)
136/*
137 * RW. RX TIMEOUT Enable. Valid for FIFO and DMA.
138 * Warning: If this bit is set to 0, the RX timeout will not affect receive DMA
139 * operation. If this bit is set to 1, a receive timeout will cause the receive
140 * DMA logic to terminate by filling the remaining DMA bytes with garbage data.
141 */
142#define ASM9260_BM_CTRL0_RXTO_ENABLE BIT(24)
143/*
144 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before
145 * asserting timeout on the RX input. If the RXFIFO is not empty and the RX
146 * input is idle, then the watchdog counter will decrement each bit-time. Note
147 * 7-bit-time is added to the programmed value, so a value of zero will set
148 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also
149 * note that the counter is reloaded at the end of each frame, so if the frame
150 * is 10 bits long and the timeout counter value is zero, then timeout will
151 * occur (when FIFO is not empty) even if the RX input is not idle. The default
152 * value is 0x3 (31 bit-time).
153 */
154#define ASM9260_BM_CTRL0_RXTO_MASK (0xff << 16)
155/* TIMEOUT = (100*7+1)*(1/BAUD) */
156#define ASM9260_BM_CTRL0_DEFAULT_RXTIMEOUT (20 << 16)
157
158/* TX ctrl register */
159#define ASM9260_HW_CTRL1 0x0010
160/*
161 * RW. Tell the UART to execute the TX DMA Command. The
162 * UART will clear this bit at the end of transmit execution.
163 */
164#define ASM9260_BM_CTRL1_TXDMA_RUN BIT(28)
165
166#define ASM9260_HW_CTRL2 0x0020
167/*
168 * RW. Receive Interrupt FIFO Level Select.
169 * The trigger points for the receive interrupt are as follows:
170 * ONE_EIGHTHS = 0x0 Trigger on FIFO full to at least 2 of 16 entries.
171 * ONE_QUARTER = 0x1 Trigger on FIFO full to at least 4 of 16 entries.
172 * ONE_HALF = 0x2 Trigger on FIFO full to at least 8 of 16 entries.
173 * THREE_QUARTERS = 0x3 Trigger on FIFO full to at least 12 of 16 entries.
174 * SEVEN_EIGHTHS = 0x4 Trigger on FIFO full to at least 14 of 16 entries.
175 */
176#define ASM9260_BM_CTRL2_RXIFLSEL (7 << 20)
177#define ASM9260_BM_CTRL2_DEFAULT_RXIFLSEL (3 << 20)
178/* RW. Same as RXIFLSEL */
179#define ASM9260_BM_CTRL2_TXIFLSEL (7 << 16)
180#define ASM9260_BM_CTRL2_DEFAULT_TXIFLSEL (2 << 16)
181/* RW. Set DTR. When this bit is 1, the output is 0. */
182#define ASM9260_BM_CTRL2_DTR BIT(10)
183/* RW. Loop Back Enable */
184#define ASM9260_BM_CTRL2_LBE BIT(7)
185#define ASM9260_BM_CTRL2_PORT_ENABLE BIT(0)
186
187#define ASM9260_HW_LINECTRL 0x0030
188/*
189 * RW. Stick Parity Select. When bits 1, 2, and 7 of this register are set, the
190 * parity bit is transmitted and checked as a 0. When bits 1 and 7 are set,
191 * and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this
192 * bit is cleared stick parity is disabled.
193 */
194#define ASM9260_BM_LCTRL_SPS BIT(7)
195/* RW. Word length */
196#define ASM9260_BM_LCTRL_WLEN (3 << 5)
197#define ASM9260_BM_LCTRL_CHRL_5 (0 << 5)
198#define ASM9260_BM_LCTRL_CHRL_6 (1 << 5)
199#define ASM9260_BM_LCTRL_CHRL_7 (2 << 5)
200#define ASM9260_BM_LCTRL_CHRL_8 (3 << 5)
201
202/*
203 * Interrupt register.
204 * contains the interrupt enables and the interrupt status bits
205 */
206#define ASM9260_HW_INTR 0x0040
207/* Tx FIFO EMPTY Raw Interrupt enable */
208#define ASM9260_BM_INTR_TFEIEN BIT(27)
209/* Overrun Error Interrupt Enable. */
210#define ASM9260_BM_INTR_OEIEN BIT(26)
211/* Break Error Interrupt Enable. */
212#define ASM9260_BM_INTR_BEIEN BIT(25)
213/* Parity Error Interrupt Enable. */
214#define ASM9260_BM_INTR_PEIEN BIT(24)
215/* Framing Error Interrupt Enable. */
216#define ASM9260_BM_INTR_FEIEN BIT(23)
217
218/* nUARTDSR Modem Interrupt Enable. */
219#define ASM9260_BM_INTR_DSRMIEN BIT(19)
220/* nUARTDCD Modem Interrupt Enable. */
221#define ASM9260_BM_INTR_DCDMIEN BIT(18)
222/* nUARTRI Modem Interrupt Enable. */
223#define ASM9260_BM_INTR_RIMIEN BIT(16)
224/* Auto-Boud Timeout */
225#define ASM9260_BM_INTR_ABTO BIT(13)
226#define ASM9260_BM_INTR_ABEO BIT(12)
227/* Tx FIFO EMPTY Raw Interrupt state */
228#define ASM9260_BM_INTR_TFEIS BIT(11)
229/* Overrun Error */
230#define ASM9260_BM_INTR_OEIS BIT(10)
231/* Break Error */
232#define ASM9260_BM_INTR_BEIS BIT(9)
233/* Parity Error */
234#define ASM9260_BM_INTR_PEIS BIT(8)
235/* Framing Error */
236#define ASM9260_BM_INTR_FEIS BIT(7)
237#define ASM9260_BM_INTR_DSRMIS BIT(3)
238#define ASM9260_BM_INTR_DCDMIS BIT(2)
239#define ASM9260_BM_INTR_RIMIS BIT(0)
240
241/*
242 * RW. In DMA mode, up to 4 Received/Transmit characters can be accessed at a
243 * time. In PIO mode, only one character can be accessed at a time. The status
244 * register contains the receive data flags and valid bits.
245 */
246#define ASM9260_HW_DATA 0x0050
247
248#define ASM9260_HW_STAT 0x0060
249/* RO. If 1, UARTAPP is present in this product. */
250#define ASM9260_BM_STAT_PRESENT BIT(31)
251/* RO. If 1, HISPEED is present in this product. */
252#define ASM9260_BM_STAT_HISPEED BIT(30)
253/* RO. Receive FIFO Full. */
254#define ASM9260_BM_STAT_RXFULL BIT(26)
255
256/* RO. The UART Debug Register contains the state of the DMA signals. */
257#define ASM9260_HW_DEBUG 0x0070
258/* DMA Command Run Status */
259#define ASM9260_BM_DEBUG_TXDMARUN BIT(5)
260#define ASM9260_BM_DEBUG_RXDMARUN BIT(4)
261/* DMA Command End Status */
262#define ASM9260_BM_DEBUG_TXCMDEND BIT(3)
263#define ASM9260_BM_DEBUG_RXCMDEND BIT(2)
264/* DMA Request Status */
265#define ASM9260_BM_DEBUG_TXDMARQ BIT(1)
266#define ASM9260_BM_DEBUG_RXDMARQ BIT(0)
267
268#define ASM9260_HW_ILPR 0x0080
269
270#define ASM9260_HW_RS485CTRL 0x0090
271/*
272 * RW. This bit reverses the polarity of the direction control signal on the RTS
273 * (or DTR) pin.
274 * If 0, The direction control pin will be driven to logic ‘0’ when the
275 * transmitter has data to be sent. It will be driven to logic ‘1’ after the
276 * last bit of data has been transmitted.
277 */
278#define ASM9260_BM_RS485CTRL_ONIV BIT(5)
279/* RW. Enable Auto Direction Control. */
280#define ASM9260_BM_RS485CTRL_DIR_CTRL BIT(4)
281/*
282 * RW. If 0 and DIR_CTRL = 1, pin RTS is used for direction control.
283 * If 1 and DIR_CTRL = 1, pin DTR is used for direction control.
284 */
285#define ASM9260_BM_RS485CTRL_PINSEL BIT(3)
286/* RW. Enable Auto Address Detect (AAD). */
287#define ASM9260_BM_RS485CTRL_AADEN BIT(2)
288/* RW. Disable receiver. */
289#define ASM9260_BM_RS485CTRL_RXDIS BIT(1)
290/* RW. Enable RS-485/EIA-485 Normal Multidrop Mode (NMM) */
291#define ASM9260_BM_RS485CTRL_RS485EN BIT(0)
292
293#define ASM9260_HW_RS485ADRMATCH 0x00a0
294/* Contains the address match value. */
295#define ASM9260_BM_RS485ADRMATCH_MASK (0xff << 0)
296
297#define ASM9260_HW_RS485DLY 0x00b0
298/*
299 * RW. Contains the direction control (RTS or DTR) delay value. This delay time
300 * is in periods of the baud clock.
301 */
302#define ASM9260_BM_RS485DLY_MASK (0xff << 0)
303
304#define ASM9260_HW_AUTOBAUD 0x00c0
305/* WO. Auto-baud time-out interrupt clear bit. */
306#define ASM9260_BM_AUTOBAUD_TO_INT_CLR BIT(9)
307/* WO. End of auto-baud interrupt clear bit. */
308#define ASM9260_BM_AUTOBAUD_EO_INT_CLR BIT(8)
309/* Restart in case of timeout (counter restarts at next UART Rx falling edge) */
310#define ASM9260_BM_AUTOBAUD_AUTORESTART BIT(2)
311/* Auto-baud mode select bit. 0 - Mode 0, 1 - Mode 1. */
312#define ASM9260_BM_AUTOBAUD_MODE BIT(1)
313/*
314 * Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
315 * automatically cleared after auto-baud completion.
316 */
317#define ASM9260_BM_AUTOBAUD_START BIT(0)
318
319#define ASM9260_HW_CTRL3 0x00d0
320#define ASM9260_BM_CTRL3_OUTCLK_DIV_MASK (0xffff << 16)
321/*
322 * RW. Provide clk over OUTCLK pin. In case of asm9260 it can be configured on
323 * pins 137 and 144.
324 */
325#define ASM9260_BM_CTRL3_MASTERMODE BIT(6)
326/* RW. Baud Rate Mode: 1 - Enable sync mode. 0 - async mode. */
327#define ASM9260_BM_CTRL3_SYNCMODE BIT(4)
328/* RW. 1 - MSB bit send frist; 0 - LSB bit frist. */
329#define ASM9260_BM_CTRL3_MSBF BIT(2)
330/* RW. 1 - sample rate = 8 x Baudrate; 0 - sample rate = 16 x Baudrate. */
331#define ASM9260_BM_CTRL3_BAUD8 BIT(1)
332/* RW. 1 - Set word length to 9bit. 0 - use ASM9260_BM_LCTRL_WLEN */
333#define ASM9260_BM_CTRL3_9BIT BIT(0)
334
335#define ASM9260_HW_ISO7816_CTRL 0x00e0
336/* RW. Enable High Speed mode. */
337#define ASM9260_BM_ISO7816CTRL_HS BIT(12)
338/* Disable Successive Receive NACK */
339#define ASM9260_BM_ISO7816CTRL_DS_NACK BIT(8)
340#define ASM9260_BM_ISO7816CTRL_MAX_ITER_MASK (0xff << 4)
341/* Receive NACK Inhibit */
342#define ASM9260_BM_ISO7816CTRL_INACK BIT(3)
343#define ASM9260_BM_ISO7816CTRL_NEG_DATA BIT(2)
344/* RW. 1 - ISO7816 mode; 0 - USART mode */
345#define ASM9260_BM_ISO7816CTRL_ENABLE BIT(0)
346
347#define ASM9260_HW_ISO7816_ERRCNT 0x00f0
348/* Parity error counter. Will be cleared after reading */
349#define ASM9260_BM_ISO7816_NB_ERRORS_MASK (0xff << 0)
350
351#define ASM9260_HW_ISO7816_STATUS 0x0100
352/* Max number of Repetitions Reached */
353#define ASM9260_BM_ISO7816_STAT_ITERATION BIT(0)
354
355/* End of Alphascale asm9260 defines */
356
357static struct uart_driver auart_driver;
358
359enum mxs_auart_type {
360 IMX23_AUART,
361 IMX28_AUART,
362 ASM9260_AUART,
363};
364
365struct vendor_data {
366 const u16 *reg_offset;
367};
368
369enum {
370 REG_CTRL0,
371 REG_CTRL1,
372 REG_CTRL2,
373 REG_LINECTRL,
374 REG_LINECTRL2,
375 REG_INTR,
376 REG_DATA,
377 REG_STAT,
378 REG_DEBUG,
379 REG_VERSION,
380 REG_AUTOBAUD,
381
382 /* The size of the array - must be last */
383 REG_ARRAY_SIZE,
384};
385
386static const u16 mxs_asm9260_offsets[REG_ARRAY_SIZE] = {
387 [REG_CTRL0] = ASM9260_HW_CTRL0,
388 [REG_CTRL1] = ASM9260_HW_CTRL1,
389 [REG_CTRL2] = ASM9260_HW_CTRL2,
390 [REG_LINECTRL] = ASM9260_HW_LINECTRL,
391 [REG_INTR] = ASM9260_HW_INTR,
392 [REG_DATA] = ASM9260_HW_DATA,
393 [REG_STAT] = ASM9260_HW_STAT,
394 [REG_DEBUG] = ASM9260_HW_DEBUG,
395 [REG_AUTOBAUD] = ASM9260_HW_AUTOBAUD,
396};
397
398static const u16 mxs_stmp37xx_offsets[REG_ARRAY_SIZE] = {
399 [REG_CTRL0] = AUART_CTRL0,
400 [REG_CTRL1] = AUART_CTRL1,
401 [REG_CTRL2] = AUART_CTRL2,
402 [REG_LINECTRL] = AUART_LINECTRL,
403 [REG_LINECTRL2] = AUART_LINECTRL2,
404 [REG_INTR] = AUART_INTR,
405 [REG_DATA] = AUART_DATA,
406 [REG_STAT] = AUART_STAT,
407 [REG_DEBUG] = AUART_DEBUG,
408 [REG_VERSION] = AUART_VERSION,
409 [REG_AUTOBAUD] = AUART_AUTOBAUD,
410};
411
412static const struct vendor_data vendor_alphascale_asm9260 = {
413 .reg_offset = mxs_asm9260_offsets,
414};
415
416static const struct vendor_data vendor_freescale_stmp37xx = {
417 .reg_offset = mxs_stmp37xx_offsets,
418};
419
420struct mxs_auart_port {
421 struct uart_port port;
422
423#define MXS_AUART_DMA_ENABLED 0x2
424#define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
425#define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
426#define MXS_AUART_RTSCTS 4 /* bit 4 */
427 unsigned long flags;
428 unsigned int mctrl_prev;
429 enum mxs_auart_type devtype;
430 const struct vendor_data *vendor;
431
432 struct clk *clk;
433 struct clk *clk_ahb;
434 struct device *dev;
435
436 /* for DMA */
437 struct scatterlist tx_sgl;
438 struct dma_chan *tx_dma_chan;
439 void *tx_dma_buf;
440
441 struct scatterlist rx_sgl;
442 struct dma_chan *rx_dma_chan;
443 void *rx_dma_buf;
444
445 struct mctrl_gpios *gpios;
446 int gpio_irq[UART_GPIO_MAX];
447 bool ms_irq_enabled;
448};
449
450static const struct platform_device_id mxs_auart_devtype[] = {
451 { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART },
452 { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART },
453 { .name = "as-auart-asm9260", .driver_data = ASM9260_AUART },
454 { /* sentinel */ }
455};
456MODULE_DEVICE_TABLE(platform, mxs_auart_devtype);
457
458static const struct of_device_id mxs_auart_dt_ids[] = {
459 {
460 .compatible = "fsl,imx28-auart",
461 .data = &mxs_auart_devtype[IMX28_AUART]
462 }, {
463 .compatible = "fsl,imx23-auart",
464 .data = &mxs_auart_devtype[IMX23_AUART]
465 }, {
466 .compatible = "alphascale,asm9260-auart",
467 .data = &mxs_auart_devtype[ASM9260_AUART]
468 }, { /* sentinel */ }
469};
470MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
471
472static inline int is_imx28_auart(struct mxs_auart_port *s)
473{
474 return s->devtype == IMX28_AUART;
475}
476
477static inline int is_asm9260_auart(struct mxs_auart_port *s)
478{
479 return s->devtype == ASM9260_AUART;
480}
481
482static inline bool auart_dma_enabled(struct mxs_auart_port *s)
483{
484 return s->flags & MXS_AUART_DMA_ENABLED;
485}
486
487static unsigned int mxs_reg_to_offset(const struct mxs_auart_port *uap,
488 unsigned int reg)
489{
490 return uap->vendor->reg_offset[reg];
491}
492
493static unsigned int mxs_read(const struct mxs_auart_port *uap,
494 unsigned int reg)
495{
496 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
497
498 return readl_relaxed(addr);
499}
500
501static void mxs_write(unsigned int val, struct mxs_auart_port *uap,
502 unsigned int reg)
503{
504 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
505
506 writel_relaxed(val, addr);
507}
508
509static void mxs_set(unsigned int val, struct mxs_auart_port *uap,
510 unsigned int reg)
511{
512 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
513
514 writel_relaxed(val, addr + SET_REG);
515}
516
517static void mxs_clr(unsigned int val, struct mxs_auart_port *uap,
518 unsigned int reg)
519{
520 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
521
522 writel_relaxed(val, addr + CLR_REG);
523}
524
525static void mxs_auart_stop_tx(struct uart_port *u);
526
527#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
528
529static void mxs_auart_tx_chars(struct mxs_auart_port *s);
530
531static void dma_tx_callback(void *param)
532{
533 struct mxs_auart_port *s = param;
534 struct circ_buf *xmit = &s->port.state->xmit;
535
536 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
537
538 /* clear the bit used to serialize the DMA tx. */
539 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
540 smp_mb__after_atomic();
541
542 /* wake up the possible processes. */
543 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
544 uart_write_wakeup(&s->port);
545
546 mxs_auart_tx_chars(s);
547}
548
549static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
550{
551 struct dma_async_tx_descriptor *desc;
552 struct scatterlist *sgl = &s->tx_sgl;
553 struct dma_chan *channel = s->tx_dma_chan;
554 u32 pio;
555
556 /* [1] : send PIO. Note, the first pio word is CTRL1. */
557 pio = AUART_CTRL1_XFER_COUNT(size);
558 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
559 1, DMA_TRANS_NONE, 0);
560 if (!desc) {
561 dev_err(s->dev, "step 1 error\n");
562 return -EINVAL;
563 }
564
565 /* [2] : set DMA buffer. */
566 sg_init_one(sgl, s->tx_dma_buf, size);
567 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
568 desc = dmaengine_prep_slave_sg(channel, sgl,
569 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
570 if (!desc) {
571 dev_err(s->dev, "step 2 error\n");
572 return -EINVAL;
573 }
574
575 /* [3] : submit the DMA */
576 desc->callback = dma_tx_callback;
577 desc->callback_param = s;
578 dmaengine_submit(desc);
579 dma_async_issue_pending(channel);
580 return 0;
581}
582
583static void mxs_auart_tx_chars(struct mxs_auart_port *s)
584{
585 struct circ_buf *xmit = &s->port.state->xmit;
586
587 if (auart_dma_enabled(s)) {
588 u32 i = 0;
589 int size;
590 void *buffer = s->tx_dma_buf;
591
592 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
593 return;
594
595 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
596 size = min_t(u32, UART_XMIT_SIZE - i,
597 CIRC_CNT_TO_END(xmit->head,
598 xmit->tail,
599 UART_XMIT_SIZE));
600 memcpy(buffer + i, xmit->buf + xmit->tail, size);
601 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
602
603 i += size;
604 if (i >= UART_XMIT_SIZE)
605 break;
606 }
607
608 if (uart_tx_stopped(&s->port))
609 mxs_auart_stop_tx(&s->port);
610
611 if (i) {
612 mxs_auart_dma_tx(s, i);
613 } else {
614 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
615 smp_mb__after_atomic();
616 }
617 return;
618 }
619
620
621 while (!(mxs_read(s, REG_STAT) & AUART_STAT_TXFF)) {
622 if (s->port.x_char) {
623 s->port.icount.tx++;
624 mxs_write(s->port.x_char, s, REG_DATA);
625 s->port.x_char = 0;
626 continue;
627 }
628 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
629 s->port.icount.tx++;
630 mxs_write(xmit->buf[xmit->tail], s, REG_DATA);
631 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
632 } else
633 break;
634 }
635 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
636 uart_write_wakeup(&s->port);
637
638 if (uart_circ_empty(&(s->port.state->xmit)))
639 mxs_clr(AUART_INTR_TXIEN, s, REG_INTR);
640 else
641 mxs_set(AUART_INTR_TXIEN, s, REG_INTR);
642
643 if (uart_tx_stopped(&s->port))
644 mxs_auart_stop_tx(&s->port);
645}
646
647static void mxs_auart_rx_char(struct mxs_auart_port *s)
648{
649 int flag;
650 u32 stat;
651 u8 c;
652
653 c = mxs_read(s, REG_DATA);
654 stat = mxs_read(s, REG_STAT);
655
656 flag = TTY_NORMAL;
657 s->port.icount.rx++;
658
659 if (stat & AUART_STAT_BERR) {
660 s->port.icount.brk++;
661 if (uart_handle_break(&s->port))
662 goto out;
663 } else if (stat & AUART_STAT_PERR) {
664 s->port.icount.parity++;
665 } else if (stat & AUART_STAT_FERR) {
666 s->port.icount.frame++;
667 }
668
669 /*
670 * Mask off conditions which should be ingored.
671 */
672 stat &= s->port.read_status_mask;
673
674 if (stat & AUART_STAT_BERR) {
675 flag = TTY_BREAK;
676 } else if (stat & AUART_STAT_PERR)
677 flag = TTY_PARITY;
678 else if (stat & AUART_STAT_FERR)
679 flag = TTY_FRAME;
680
681 if (stat & AUART_STAT_OERR)
682 s->port.icount.overrun++;
683
684 if (uart_handle_sysrq_char(&s->port, c))
685 goto out;
686
687 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
688out:
689 mxs_write(stat, s, REG_STAT);
690}
691
692static void mxs_auart_rx_chars(struct mxs_auart_port *s)
693{
694 u32 stat = 0;
695
696 for (;;) {
697 stat = mxs_read(s, REG_STAT);
698 if (stat & AUART_STAT_RXFE)
699 break;
700 mxs_auart_rx_char(s);
701 }
702
703 mxs_write(stat, s, REG_STAT);
704 tty_flip_buffer_push(&s->port.state->port);
705}
706
707static int mxs_auart_request_port(struct uart_port *u)
708{
709 return 0;
710}
711
712static int mxs_auart_verify_port(struct uart_port *u,
713 struct serial_struct *ser)
714{
715 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
716 return -EINVAL;
717 return 0;
718}
719
720static void mxs_auart_config_port(struct uart_port *u, int flags)
721{
722}
723
724static const char *mxs_auart_type(struct uart_port *u)
725{
726 struct mxs_auart_port *s = to_auart_port(u);
727
728 return dev_name(s->dev);
729}
730
731static void mxs_auart_release_port(struct uart_port *u)
732{
733}
734
735static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
736{
737 struct mxs_auart_port *s = to_auart_port(u);
738
739 u32 ctrl = mxs_read(s, REG_CTRL2);
740
741 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
742 if (mctrl & TIOCM_RTS) {
743 if (uart_cts_enabled(u))
744 ctrl |= AUART_CTRL2_RTSEN;
745 else
746 ctrl |= AUART_CTRL2_RTS;
747 }
748
749 mxs_write(ctrl, s, REG_CTRL2);
750
751 mctrl_gpio_set(s->gpios, mctrl);
752}
753
754#define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS)
755static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl)
756{
757 u32 mctrl_diff;
758
759 mctrl_diff = mctrl ^ s->mctrl_prev;
760 s->mctrl_prev = mctrl;
761 if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled &&
762 s->port.state != NULL) {
763 if (mctrl_diff & TIOCM_RI)
764 s->port.icount.rng++;
765 if (mctrl_diff & TIOCM_DSR)
766 s->port.icount.dsr++;
767 if (mctrl_diff & TIOCM_CD)
768 uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD);
769 if (mctrl_diff & TIOCM_CTS)
770 uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS);
771
772 wake_up_interruptible(&s->port.state->port.delta_msr_wait);
773 }
774 return mctrl;
775}
776
777static u32 mxs_auart_get_mctrl(struct uart_port *u)
778{
779 struct mxs_auart_port *s = to_auart_port(u);
780 u32 stat = mxs_read(s, REG_STAT);
781 u32 mctrl = 0;
782
783 if (stat & AUART_STAT_CTS)
784 mctrl |= TIOCM_CTS;
785
786 return mctrl_gpio_get(s->gpios, &mctrl);
787}
788
789/*
790 * Enable modem status interrupts
791 */
792static void mxs_auart_enable_ms(struct uart_port *port)
793{
794 struct mxs_auart_port *s = to_auart_port(port);
795
796 /*
797 * Interrupt should not be enabled twice
798 */
799 if (s->ms_irq_enabled)
800 return;
801
802 s->ms_irq_enabled = true;
803
804 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
805 enable_irq(s->gpio_irq[UART_GPIO_CTS]);
806 /* TODO: enable AUART_INTR_CTSMIEN otherwise */
807
808 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
809 enable_irq(s->gpio_irq[UART_GPIO_DSR]);
810
811 if (s->gpio_irq[UART_GPIO_RI] >= 0)
812 enable_irq(s->gpio_irq[UART_GPIO_RI]);
813
814 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
815 enable_irq(s->gpio_irq[UART_GPIO_DCD]);
816}
817
818/*
819 * Disable modem status interrupts
820 */
821static void mxs_auart_disable_ms(struct uart_port *port)
822{
823 struct mxs_auart_port *s = to_auart_port(port);
824
825 /*
826 * Interrupt should not be disabled twice
827 */
828 if (!s->ms_irq_enabled)
829 return;
830
831 s->ms_irq_enabled = false;
832
833 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
834 disable_irq(s->gpio_irq[UART_GPIO_CTS]);
835 /* TODO: disable AUART_INTR_CTSMIEN otherwise */
836
837 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
838 disable_irq(s->gpio_irq[UART_GPIO_DSR]);
839
840 if (s->gpio_irq[UART_GPIO_RI] >= 0)
841 disable_irq(s->gpio_irq[UART_GPIO_RI]);
842
843 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
844 disable_irq(s->gpio_irq[UART_GPIO_DCD]);
845}
846
847static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
848static void dma_rx_callback(void *arg)
849{
850 struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
851 struct tty_port *port = &s->port.state->port;
852 int count;
853 u32 stat;
854
855 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
856
857 stat = mxs_read(s, REG_STAT);
858 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
859 AUART_STAT_PERR | AUART_STAT_FERR);
860
861 count = stat & AUART_STAT_RXCOUNT_MASK;
862 tty_insert_flip_string(port, s->rx_dma_buf, count);
863
864 mxs_write(stat, s, REG_STAT);
865 tty_flip_buffer_push(port);
866
867 /* start the next DMA for RX. */
868 mxs_auart_dma_prep_rx(s);
869}
870
871static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
872{
873 struct dma_async_tx_descriptor *desc;
874 struct scatterlist *sgl = &s->rx_sgl;
875 struct dma_chan *channel = s->rx_dma_chan;
876 u32 pio[1];
877
878 /* [1] : send PIO */
879 pio[0] = AUART_CTRL0_RXTO_ENABLE
880 | AUART_CTRL0_RXTIMEOUT(0x80)
881 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
882 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
883 1, DMA_TRANS_NONE, 0);
884 if (!desc) {
885 dev_err(s->dev, "step 1 error\n");
886 return -EINVAL;
887 }
888
889 /* [2] : send DMA request */
890 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
891 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
892 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
893 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
894 if (!desc) {
895 dev_err(s->dev, "step 2 error\n");
896 return -1;
897 }
898
899 /* [3] : submit the DMA, but do not issue it. */
900 desc->callback = dma_rx_callback;
901 desc->callback_param = s;
902 dmaengine_submit(desc);
903 dma_async_issue_pending(channel);
904 return 0;
905}
906
907static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
908{
909 if (s->tx_dma_chan) {
910 dma_release_channel(s->tx_dma_chan);
911 s->tx_dma_chan = NULL;
912 }
913 if (s->rx_dma_chan) {
914 dma_release_channel(s->rx_dma_chan);
915 s->rx_dma_chan = NULL;
916 }
917
918 kfree(s->tx_dma_buf);
919 kfree(s->rx_dma_buf);
920 s->tx_dma_buf = NULL;
921 s->rx_dma_buf = NULL;
922}
923
924static void mxs_auart_dma_exit(struct mxs_auart_port *s)
925{
926
927 mxs_clr(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
928 s, REG_CTRL2);
929
930 mxs_auart_dma_exit_channel(s);
931 s->flags &= ~MXS_AUART_DMA_ENABLED;
932 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
933 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
934}
935
936static int mxs_auart_dma_init(struct mxs_auart_port *s)
937{
938 if (auart_dma_enabled(s))
939 return 0;
940
941 /* init for RX */
942 s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx");
943 if (!s->rx_dma_chan)
944 goto err_out;
945 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
946 if (!s->rx_dma_buf)
947 goto err_out;
948
949 /* init for TX */
950 s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx");
951 if (!s->tx_dma_chan)
952 goto err_out;
953 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
954 if (!s->tx_dma_buf)
955 goto err_out;
956
957 /* set the flags */
958 s->flags |= MXS_AUART_DMA_ENABLED;
959 dev_dbg(s->dev, "enabled the DMA support.");
960
961 /* The DMA buffer is now the FIFO the TTY subsystem can use */
962 s->port.fifosize = UART_XMIT_SIZE;
963
964 return 0;
965
966err_out:
967 mxs_auart_dma_exit_channel(s);
968 return -EINVAL;
969
970}
971
972#define RTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \
973 UART_GPIO_RTS))
974#define CTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \
975 UART_GPIO_CTS))
976static void mxs_auart_settermios(struct uart_port *u,
977 struct ktermios *termios,
978 struct ktermios *old)
979{
980 struct mxs_auart_port *s = to_auart_port(u);
981 u32 bm, ctrl, ctrl2, div;
982 unsigned int cflag, baud, baud_min, baud_max;
983
984 cflag = termios->c_cflag;
985
986 ctrl = AUART_LINECTRL_FEN;
987 ctrl2 = mxs_read(s, REG_CTRL2);
988
989 /* byte size */
990 switch (cflag & CSIZE) {
991 case CS5:
992 bm = 0;
993 break;
994 case CS6:
995 bm = 1;
996 break;
997 case CS7:
998 bm = 2;
999 break;
1000 case CS8:
1001 bm = 3;
1002 break;
1003 default:
1004 return;
1005 }
1006
1007 ctrl |= AUART_LINECTRL_WLEN(bm);
1008
1009 /* parity */
1010 if (cflag & PARENB) {
1011 ctrl |= AUART_LINECTRL_PEN;
1012 if ((cflag & PARODD) == 0)
1013 ctrl |= AUART_LINECTRL_EPS;
1014 if (cflag & CMSPAR)
1015 ctrl |= AUART_LINECTRL_SPS;
1016 }
1017
1018 u->read_status_mask = AUART_STAT_OERR;
1019
1020 if (termios->c_iflag & INPCK)
1021 u->read_status_mask |= AUART_STAT_PERR;
1022 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1023 u->read_status_mask |= AUART_STAT_BERR;
1024
1025 /*
1026 * Characters to ignore
1027 */
1028 u->ignore_status_mask = 0;
1029 if (termios->c_iflag & IGNPAR)
1030 u->ignore_status_mask |= AUART_STAT_PERR;
1031 if (termios->c_iflag & IGNBRK) {
1032 u->ignore_status_mask |= AUART_STAT_BERR;
1033 /*
1034 * If we're ignoring parity and break indicators,
1035 * ignore overruns too (for real raw support).
1036 */
1037 if (termios->c_iflag & IGNPAR)
1038 u->ignore_status_mask |= AUART_STAT_OERR;
1039 }
1040
1041 /*
1042 * ignore all characters if CREAD is not set
1043 */
1044 if (cflag & CREAD)
1045 ctrl2 |= AUART_CTRL2_RXE;
1046 else
1047 ctrl2 &= ~AUART_CTRL2_RXE;
1048
1049 /* figure out the stop bits requested */
1050 if (cflag & CSTOPB)
1051 ctrl |= AUART_LINECTRL_STP2;
1052
1053 /* figure out the hardware flow control settings */
1054 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
1055 if (cflag & CRTSCTS) {
1056 /*
1057 * The DMA has a bug(see errata:2836) in mx23.
1058 * So we can not implement the DMA for auart in mx23,
1059 * we can only implement the DMA support for auart
1060 * in mx28.
1061 */
1062 if (is_imx28_auart(s)
1063 && test_bit(MXS_AUART_RTSCTS, &s->flags)) {
1064 if (!mxs_auart_dma_init(s))
1065 /* enable DMA tranfer */
1066 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
1067 | AUART_CTRL2_DMAONERR;
1068 }
1069 /* Even if RTS is GPIO line RTSEN can be enabled because
1070 * the pinctrl configuration decides about RTS pin function */
1071 ctrl2 |= AUART_CTRL2_RTSEN;
1072 if (CTS_AT_AUART())
1073 ctrl2 |= AUART_CTRL2_CTSEN;
1074 }
1075
1076 /* set baud rate */
1077 if (is_asm9260_auart(s)) {
1078 baud = uart_get_baud_rate(u, termios, old,
1079 u->uartclk * 4 / 0x3FFFFF,
1080 u->uartclk / 16);
1081 div = u->uartclk * 4 / baud;
1082 } else {
1083 baud_min = DIV_ROUND_UP(u->uartclk * 32,
1084 AUART_LINECTRL_BAUD_DIV_MAX);
1085 baud_max = u->uartclk * 32 / AUART_LINECTRL_BAUD_DIV_MIN;
1086 baud = uart_get_baud_rate(u, termios, old, baud_min, baud_max);
1087 div = DIV_ROUND_CLOSEST(u->uartclk * 32, baud);
1088 }
1089
1090 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
1091 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
1092 mxs_write(ctrl, s, REG_LINECTRL);
1093
1094 mxs_write(ctrl2, s, REG_CTRL2);
1095
1096 uart_update_timeout(u, termios->c_cflag, baud);
1097
1098 /* prepare for the DMA RX. */
1099 if (auart_dma_enabled(s) &&
1100 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
1101 if (!mxs_auart_dma_prep_rx(s)) {
1102 /* Disable the normal RX interrupt. */
1103 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
1104 s, REG_INTR);
1105 } else {
1106 mxs_auart_dma_exit(s);
1107 dev_err(s->dev, "We can not start up the DMA.\n");
1108 }
1109 }
1110
1111 /* CTS flow-control and modem-status interrupts */
1112 if (UART_ENABLE_MS(u, termios->c_cflag))
1113 mxs_auart_enable_ms(u);
1114 else
1115 mxs_auart_disable_ms(u);
1116}
1117
1118static void mxs_auart_set_ldisc(struct uart_port *port,
1119 struct ktermios *termios)
1120{
1121 if (termios->c_line == N_PPS) {
1122 port->flags |= UPF_HARDPPS_CD;
1123 mxs_auart_enable_ms(port);
1124 } else {
1125 port->flags &= ~UPF_HARDPPS_CD;
1126 }
1127}
1128
1129static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
1130{
1131 u32 istat;
1132 struct mxs_auart_port *s = context;
1133 u32 mctrl_temp = s->mctrl_prev;
1134 u32 stat = mxs_read(s, REG_STAT);
1135
1136 istat = mxs_read(s, REG_INTR);
1137
1138 /* ack irq */
1139 mxs_clr(istat & (AUART_INTR_RTIS | AUART_INTR_TXIS | AUART_INTR_RXIS
1140 | AUART_INTR_CTSMIS), s, REG_INTR);
1141
1142 /*
1143 * Dealing with GPIO interrupt
1144 */
1145 if (irq == s->gpio_irq[UART_GPIO_CTS] ||
1146 irq == s->gpio_irq[UART_GPIO_DCD] ||
1147 irq == s->gpio_irq[UART_GPIO_DSR] ||
1148 irq == s->gpio_irq[UART_GPIO_RI])
1149 mxs_auart_modem_status(s,
1150 mctrl_gpio_get(s->gpios, &mctrl_temp));
1151
1152 if (istat & AUART_INTR_CTSMIS) {
1153 if (CTS_AT_AUART() && s->ms_irq_enabled)
1154 uart_handle_cts_change(&s->port,
1155 stat & AUART_STAT_CTS);
1156 mxs_clr(AUART_INTR_CTSMIS, s, REG_INTR);
1157 istat &= ~AUART_INTR_CTSMIS;
1158 }
1159
1160 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
1161 if (!auart_dma_enabled(s))
1162 mxs_auart_rx_chars(s);
1163 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
1164 }
1165
1166 if (istat & AUART_INTR_TXIS) {
1167 mxs_auart_tx_chars(s);
1168 istat &= ~AUART_INTR_TXIS;
1169 }
1170
1171 return IRQ_HANDLED;
1172}
1173
1174static void mxs_auart_reset_deassert(struct mxs_auart_port *s)
1175{
1176 int i;
1177 unsigned int reg;
1178
1179 mxs_clr(AUART_CTRL0_SFTRST, s, REG_CTRL0);
1180
1181 for (i = 0; i < 10000; i++) {
1182 reg = mxs_read(s, REG_CTRL0);
1183 if (!(reg & AUART_CTRL0_SFTRST))
1184 break;
1185 udelay(3);
1186 }
1187 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1188}
1189
1190static void mxs_auart_reset_assert(struct mxs_auart_port *s)
1191{
1192 int i;
1193 u32 reg;
1194
1195 reg = mxs_read(s, REG_CTRL0);
1196 /* if already in reset state, keep it untouched */
1197 if (reg & AUART_CTRL0_SFTRST)
1198 return;
1199
1200 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1201 mxs_set(AUART_CTRL0_SFTRST, s, REG_CTRL0);
1202
1203 for (i = 0; i < 1000; i++) {
1204 reg = mxs_read(s, REG_CTRL0);
1205 /* reset is finished when the clock is gated */
1206 if (reg & AUART_CTRL0_CLKGATE)
1207 return;
1208 udelay(10);
1209 }
1210
1211 dev_err(s->dev, "Failed to reset the unit.");
1212}
1213
1214static int mxs_auart_startup(struct uart_port *u)
1215{
1216 int ret;
1217 struct mxs_auart_port *s = to_auart_port(u);
1218
1219 ret = clk_prepare_enable(s->clk);
1220 if (ret)
1221 return ret;
1222
1223 if (uart_console(u)) {
1224 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1225 } else {
1226 /* reset the unit to a well known state */
1227 mxs_auart_reset_assert(s);
1228 mxs_auart_reset_deassert(s);
1229 }
1230
1231 mxs_set(AUART_CTRL2_UARTEN, s, REG_CTRL2);
1232
1233 mxs_write(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
1234 s, REG_INTR);
1235
1236 /* Reset FIFO size (it could have changed if DMA was enabled) */
1237 u->fifosize = MXS_AUART_FIFO_SIZE;
1238
1239 /*
1240 * Enable fifo so all four bytes of a DMA word are written to
1241 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
1242 */
1243 mxs_set(AUART_LINECTRL_FEN, s, REG_LINECTRL);
1244
1245 /* get initial status of modem lines */
1246 mctrl_gpio_get(s->gpios, &s->mctrl_prev);
1247
1248 s->ms_irq_enabled = false;
1249 return 0;
1250}
1251
1252static void mxs_auart_shutdown(struct uart_port *u)
1253{
1254 struct mxs_auart_port *s = to_auart_port(u);
1255
1256 mxs_auart_disable_ms(u);
1257
1258 if (auart_dma_enabled(s))
1259 mxs_auart_dma_exit(s);
1260
1261 if (uart_console(u)) {
1262 mxs_clr(AUART_CTRL2_UARTEN, s, REG_CTRL2);
1263
1264 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN |
1265 AUART_INTR_CTSMIEN, s, REG_INTR);
1266 mxs_set(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1267 } else {
1268 mxs_auart_reset_assert(s);
1269 }
1270
1271 clk_disable_unprepare(s->clk);
1272}
1273
1274static unsigned int mxs_auart_tx_empty(struct uart_port *u)
1275{
1276 struct mxs_auart_port *s = to_auart_port(u);
1277
1278 if ((mxs_read(s, REG_STAT) &
1279 (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE)
1280 return TIOCSER_TEMT;
1281
1282 return 0;
1283}
1284
1285static void mxs_auart_start_tx(struct uart_port *u)
1286{
1287 struct mxs_auart_port *s = to_auart_port(u);
1288
1289 /* enable transmitter */
1290 mxs_set(AUART_CTRL2_TXE, s, REG_CTRL2);
1291
1292 mxs_auart_tx_chars(s);
1293}
1294
1295static void mxs_auart_stop_tx(struct uart_port *u)
1296{
1297 struct mxs_auart_port *s = to_auart_port(u);
1298
1299 mxs_clr(AUART_CTRL2_TXE, s, REG_CTRL2);
1300}
1301
1302static void mxs_auart_stop_rx(struct uart_port *u)
1303{
1304 struct mxs_auart_port *s = to_auart_port(u);
1305
1306 mxs_clr(AUART_CTRL2_RXE, s, REG_CTRL2);
1307}
1308
1309static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
1310{
1311 struct mxs_auart_port *s = to_auart_port(u);
1312
1313 if (ctl)
1314 mxs_set(AUART_LINECTRL_BRK, s, REG_LINECTRL);
1315 else
1316 mxs_clr(AUART_LINECTRL_BRK, s, REG_LINECTRL);
1317}
1318
1319static const struct uart_ops mxs_auart_ops = {
1320 .tx_empty = mxs_auart_tx_empty,
1321 .start_tx = mxs_auart_start_tx,
1322 .stop_tx = mxs_auart_stop_tx,
1323 .stop_rx = mxs_auart_stop_rx,
1324 .enable_ms = mxs_auart_enable_ms,
1325 .break_ctl = mxs_auart_break_ctl,
1326 .set_mctrl = mxs_auart_set_mctrl,
1327 .get_mctrl = mxs_auart_get_mctrl,
1328 .startup = mxs_auart_startup,
1329 .shutdown = mxs_auart_shutdown,
1330 .set_termios = mxs_auart_settermios,
1331 .set_ldisc = mxs_auart_set_ldisc,
1332 .type = mxs_auart_type,
1333 .release_port = mxs_auart_release_port,
1334 .request_port = mxs_auart_request_port,
1335 .config_port = mxs_auart_config_port,
1336 .verify_port = mxs_auart_verify_port,
1337};
1338
1339static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
1340
1341#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1342static void mxs_auart_console_putchar(struct uart_port *port, int ch)
1343{
1344 struct mxs_auart_port *s = to_auart_port(port);
1345 unsigned int to = 1000;
1346
1347 while (mxs_read(s, REG_STAT) & AUART_STAT_TXFF) {
1348 if (!to--)
1349 break;
1350 udelay(1);
1351 }
1352
1353 mxs_write(ch, s, REG_DATA);
1354}
1355
1356static void
1357auart_console_write(struct console *co, const char *str, unsigned int count)
1358{
1359 struct mxs_auart_port *s;
1360 struct uart_port *port;
1361 unsigned int old_ctrl0, old_ctrl2;
1362 unsigned int to = 20000;
1363
1364 if (co->index >= MXS_AUART_PORTS || co->index < 0)
1365 return;
1366
1367 s = auart_port[co->index];
1368 port = &s->port;
1369
1370 clk_enable(s->clk);
1371
1372 /* First save the CR then disable the interrupts */
1373 old_ctrl2 = mxs_read(s, REG_CTRL2);
1374 old_ctrl0 = mxs_read(s, REG_CTRL0);
1375
1376 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1377 mxs_set(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, s, REG_CTRL2);
1378
1379 uart_console_write(port, str, count, mxs_auart_console_putchar);
1380
1381 /* Finally, wait for transmitter to become empty ... */
1382 while (mxs_read(s, REG_STAT) & AUART_STAT_BUSY) {
1383 udelay(1);
1384 if (!to--)
1385 break;
1386 }
1387
1388 /*
1389 * ... and restore the TCR if we waited long enough for the transmitter
1390 * to be idle. This might keep the transmitter enabled although it is
1391 * unused, but that is better than to disable it while it is still
1392 * transmitting.
1393 */
1394 if (!(mxs_read(s, REG_STAT) & AUART_STAT_BUSY)) {
1395 mxs_write(old_ctrl0, s, REG_CTRL0);
1396 mxs_write(old_ctrl2, s, REG_CTRL2);
1397 }
1398
1399 clk_disable(s->clk);
1400}
1401
1402static void __init
1403auart_console_get_options(struct mxs_auart_port *s, int *baud,
1404 int *parity, int *bits)
1405{
1406 struct uart_port *port = &s->port;
1407 unsigned int lcr_h, quot;
1408
1409 if (!(mxs_read(s, REG_CTRL2) & AUART_CTRL2_UARTEN))
1410 return;
1411
1412 lcr_h = mxs_read(s, REG_LINECTRL);
1413
1414 *parity = 'n';
1415 if (lcr_h & AUART_LINECTRL_PEN) {
1416 if (lcr_h & AUART_LINECTRL_EPS)
1417 *parity = 'e';
1418 else
1419 *parity = 'o';
1420 }
1421
1422 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
1423 *bits = 7;
1424 else
1425 *bits = 8;
1426
1427 quot = ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVINT_MASK))
1428 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
1429 quot |= ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
1430 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
1431 if (quot == 0)
1432 quot = 1;
1433
1434 *baud = (port->uartclk << 2) / quot;
1435}
1436
1437static int __init
1438auart_console_setup(struct console *co, char *options)
1439{
1440 struct mxs_auart_port *s;
1441 int baud = 9600;
1442 int bits = 8;
1443 int parity = 'n';
1444 int flow = 'n';
1445 int ret;
1446
1447 /*
1448 * Check whether an invalid uart number has been specified, and
1449 * if so, search for the first available port that does have
1450 * console support.
1451 */
1452 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
1453 co->index = 0;
1454 s = auart_port[co->index];
1455 if (!s)
1456 return -ENODEV;
1457
1458 ret = clk_prepare_enable(s->clk);
1459 if (ret)
1460 return ret;
1461
1462 if (options)
1463 uart_parse_options(options, &baud, &parity, &bits, &flow);
1464 else
1465 auart_console_get_options(s, &baud, &parity, &bits);
1466
1467 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
1468
1469 clk_disable_unprepare(s->clk);
1470
1471 return ret;
1472}
1473
1474static struct console auart_console = {
1475 .name = "ttyAPP",
1476 .write = auart_console_write,
1477 .device = uart_console_device,
1478 .setup = auart_console_setup,
1479 .flags = CON_PRINTBUFFER,
1480 .index = -1,
1481 .data = &auart_driver,
1482};
1483#endif
1484
1485static struct uart_driver auart_driver = {
1486 .owner = THIS_MODULE,
1487 .driver_name = "ttyAPP",
1488 .dev_name = "ttyAPP",
1489 .major = 0,
1490 .minor = 0,
1491 .nr = MXS_AUART_PORTS,
1492#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1493 .cons = &auart_console,
1494#endif
1495};
1496
1497static void mxs_init_regs(struct mxs_auart_port *s)
1498{
1499 if (is_asm9260_auart(s))
1500 s->vendor = &vendor_alphascale_asm9260;
1501 else
1502 s->vendor = &vendor_freescale_stmp37xx;
1503}
1504
1505static int mxs_get_clks(struct mxs_auart_port *s,
1506 struct platform_device *pdev)
1507{
1508 int err;
1509
1510 if (!is_asm9260_auart(s)) {
1511 s->clk = devm_clk_get(&pdev->dev, NULL);
1512 return PTR_ERR_OR_ZERO(s->clk);
1513 }
1514
1515 s->clk = devm_clk_get(s->dev, "mod");
1516 if (IS_ERR(s->clk)) {
1517 dev_err(s->dev, "Failed to get \"mod\" clk\n");
1518 return PTR_ERR(s->clk);
1519 }
1520
1521 s->clk_ahb = devm_clk_get(s->dev, "ahb");
1522 if (IS_ERR(s->clk_ahb)) {
1523 dev_err(s->dev, "Failed to get \"ahb\" clk\n");
1524 return PTR_ERR(s->clk_ahb);
1525 }
1526
1527 err = clk_prepare_enable(s->clk_ahb);
1528 if (err) {
1529 dev_err(s->dev, "Failed to enable ahb_clk!\n");
1530 return err;
1531 }
1532
1533 err = clk_set_rate(s->clk, clk_get_rate(s->clk_ahb));
1534 if (err) {
1535 dev_err(s->dev, "Failed to set rate!\n");
1536 goto disable_clk_ahb;
1537 }
1538
1539 err = clk_prepare_enable(s->clk);
1540 if (err) {
1541 dev_err(s->dev, "Failed to enable clk!\n");
1542 goto disable_clk_ahb;
1543 }
1544
1545 return 0;
1546
1547disable_clk_ahb:
1548 clk_disable_unprepare(s->clk_ahb);
1549 return err;
1550}
1551
1552/*
1553 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it
1554 * could successfully get all information from dt or a negative errno.
1555 */
1556static int serial_mxs_probe_dt(struct mxs_auart_port *s,
1557 struct platform_device *pdev)
1558{
1559 struct device_node *np = pdev->dev.of_node;
1560 int ret;
1561
1562 if (!np)
1563 /* no device tree device */
1564 return 1;
1565
1566 ret = of_alias_get_id(np, "serial");
1567 if (ret < 0) {
1568 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
1569 return ret;
1570 }
1571 s->port.line = ret;
1572
1573 if (of_get_property(np, "uart-has-rtscts", NULL) ||
1574 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
1575 set_bit(MXS_AUART_RTSCTS, &s->flags);
1576
1577 return 0;
1578}
1579
1580static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev)
1581{
1582 enum mctrl_gpio_idx i;
1583 struct gpio_desc *gpiod;
1584
1585 s->gpios = mctrl_gpio_init_noauto(dev, 0);
1586 if (IS_ERR(s->gpios))
1587 return PTR_ERR(s->gpios);
1588
1589 /* Block (enabled before) DMA option if RTS or CTS is GPIO line */
1590 if (!RTS_AT_AUART() || !CTS_AT_AUART()) {
1591 if (test_bit(MXS_AUART_RTSCTS, &s->flags))
1592 dev_warn(dev,
1593 "DMA and flow control via gpio may cause some problems. DMA disabled!\n");
1594 clear_bit(MXS_AUART_RTSCTS, &s->flags);
1595 }
1596
1597 for (i = 0; i < UART_GPIO_MAX; i++) {
1598 gpiod = mctrl_gpio_to_gpiod(s->gpios, i);
1599 if (gpiod && (gpiod_get_direction(gpiod) == 1))
1600 s->gpio_irq[i] = gpiod_to_irq(gpiod);
1601 else
1602 s->gpio_irq[i] = -EINVAL;
1603 }
1604
1605 return 0;
1606}
1607
1608static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s)
1609{
1610 enum mctrl_gpio_idx i;
1611
1612 for (i = 0; i < UART_GPIO_MAX; i++)
1613 if (s->gpio_irq[i] >= 0)
1614 free_irq(s->gpio_irq[i], s);
1615}
1616
1617static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s)
1618{
1619 int *irq = s->gpio_irq;
1620 enum mctrl_gpio_idx i;
1621 int err = 0;
1622
1623 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1624 if (irq[i] < 0)
1625 continue;
1626
1627 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1628 err = request_irq(irq[i], mxs_auart_irq_handle,
1629 IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s);
1630 if (err)
1631 dev_err(s->dev, "%s - Can't get %d irq\n",
1632 __func__, irq[i]);
1633 }
1634
1635 /*
1636 * If something went wrong, rollback.
1637 */
1638 while (err && (--i >= 0))
1639 if (irq[i] >= 0)
1640 free_irq(irq[i], s);
1641
1642 return err;
1643}
1644
1645static int mxs_auart_probe(struct platform_device *pdev)
1646{
1647 const struct of_device_id *of_id =
1648 of_match_device(mxs_auart_dt_ids, &pdev->dev);
1649 struct mxs_auart_port *s;
1650 u32 version;
1651 int ret, irq;
1652 struct resource *r;
1653
1654 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
1655 if (!s)
1656 return -ENOMEM;
1657
1658 s->port.dev = &pdev->dev;
1659 s->dev = &pdev->dev;
1660
1661 ret = serial_mxs_probe_dt(s, pdev);
1662 if (ret > 0)
1663 s->port.line = pdev->id < 0 ? 0 : pdev->id;
1664 else if (ret < 0)
1665 return ret;
1666 if (s->port.line >= ARRAY_SIZE(auart_port)) {
1667 dev_err(&pdev->dev, "serial%d out of range\n", s->port.line);
1668 return -EINVAL;
1669 }
1670
1671 if (of_id) {
1672 pdev->id_entry = of_id->data;
1673 s->devtype = pdev->id_entry->driver_data;
1674 }
1675
1676 ret = mxs_get_clks(s, pdev);
1677 if (ret)
1678 return ret;
1679
1680 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1681 if (!r) {
1682 ret = -ENXIO;
1683 goto out_disable_clks;
1684 }
1685
1686 s->port.mapbase = r->start;
1687 s->port.membase = ioremap(r->start, resource_size(r));
1688 s->port.ops = &mxs_auart_ops;
1689 s->port.iotype = UPIO_MEM;
1690 s->port.fifosize = MXS_AUART_FIFO_SIZE;
1691 s->port.uartclk = clk_get_rate(s->clk);
1692 s->port.type = PORT_IMX;
1693
1694 mxs_init_regs(s);
1695
1696 s->mctrl_prev = 0;
1697
1698 irq = platform_get_irq(pdev, 0);
1699 if (irq < 0) {
1700 ret = irq;
1701 goto out_disable_clks;
1702 }
1703
1704 s->port.irq = irq;
1705 ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0,
1706 dev_name(&pdev->dev), s);
1707 if (ret)
1708 goto out_disable_clks;
1709
1710 platform_set_drvdata(pdev, s);
1711
1712 ret = mxs_auart_init_gpios(s, &pdev->dev);
1713 if (ret) {
1714 dev_err(&pdev->dev, "Failed to initialize GPIOs.\n");
1715 goto out_disable_clks;
1716 }
1717
1718 /*
1719 * Get the GPIO lines IRQ
1720 */
1721 ret = mxs_auart_request_gpio_irq(s);
1722 if (ret)
1723 goto out_disable_clks;
1724
1725 auart_port[s->port.line] = s;
1726
1727 mxs_auart_reset_deassert(s);
1728
1729 ret = uart_add_one_port(&auart_driver, &s->port);
1730 if (ret)
1731 goto out_free_qpio_irq;
1732
1733 /* ASM9260 don't have version reg */
1734 if (is_asm9260_auart(s)) {
1735 dev_info(&pdev->dev, "Found APPUART ASM9260\n");
1736 } else {
1737 version = mxs_read(s, REG_VERSION);
1738 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
1739 (version >> 24) & 0xff,
1740 (version >> 16) & 0xff, version & 0xffff);
1741 }
1742
1743 return 0;
1744
1745out_free_qpio_irq:
1746 mxs_auart_free_gpio_irq(s);
1747 auart_port[pdev->id] = NULL;
1748
1749out_disable_clks:
1750 if (is_asm9260_auart(s)) {
1751 clk_disable_unprepare(s->clk);
1752 clk_disable_unprepare(s->clk_ahb);
1753 }
1754 return ret;
1755}
1756
1757static int mxs_auart_remove(struct platform_device *pdev)
1758{
1759 struct mxs_auart_port *s = platform_get_drvdata(pdev);
1760
1761 uart_remove_one_port(&auart_driver, &s->port);
1762 auart_port[pdev->id] = NULL;
1763 mxs_auart_free_gpio_irq(s);
1764 if (is_asm9260_auart(s)) {
1765 clk_disable_unprepare(s->clk);
1766 clk_disable_unprepare(s->clk_ahb);
1767 }
1768
1769 return 0;
1770}
1771
1772static struct platform_driver mxs_auart_driver = {
1773 .probe = mxs_auart_probe,
1774 .remove = mxs_auart_remove,
1775 .driver = {
1776 .name = "mxs-auart",
1777 .of_match_table = mxs_auart_dt_ids,
1778 },
1779};
1780
1781static int __init mxs_auart_init(void)
1782{
1783 int r;
1784
1785 r = uart_register_driver(&auart_driver);
1786 if (r)
1787 goto out;
1788
1789 r = platform_driver_register(&mxs_auart_driver);
1790 if (r)
1791 goto out_err;
1792
1793 return 0;
1794out_err:
1795 uart_unregister_driver(&auart_driver);
1796out:
1797 return r;
1798}
1799
1800static void __exit mxs_auart_exit(void)
1801{
1802 platform_driver_unregister(&mxs_auart_driver);
1803 uart_unregister_driver(&auart_driver);
1804}
1805
1806module_init(mxs_auart_init);
1807module_exit(mxs_auart_exit);
1808MODULE_LICENSE("GPL");
1809MODULE_DESCRIPTION("Freescale MXS application uart driver");
1810MODULE_ALIAS("platform:mxs-auart");