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1/*
2 * Freescale STMP37XX/STMP378X Application UART driver
3 *
4 * Author: dmitry pervushin <dimka@embeddedalley.com>
5 *
6 * Copyright 2008-2010 Freescale Semiconductor, Inc.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/init.h>
20#include <linux/console.h>
21#include <linux/interrupt.h>
22#include <linux/module.h>
23#include <linux/slab.h>
24#include <linux/wait.h>
25#include <linux/tty.h>
26#include <linux/tty_driver.h>
27#include <linux/tty_flip.h>
28#include <linux/serial.h>
29#include <linux/serial_core.h>
30#include <linux/platform_device.h>
31#include <linux/device.h>
32#include <linux/clk.h>
33#include <linux/delay.h>
34#include <linux/io.h>
35
36#include <asm/cacheflush.h>
37
38#define MXS_AUART_PORTS 5
39
40#define AUART_CTRL0 0x00000000
41#define AUART_CTRL0_SET 0x00000004
42#define AUART_CTRL0_CLR 0x00000008
43#define AUART_CTRL0_TOG 0x0000000c
44#define AUART_CTRL1 0x00000010
45#define AUART_CTRL1_SET 0x00000014
46#define AUART_CTRL1_CLR 0x00000018
47#define AUART_CTRL1_TOG 0x0000001c
48#define AUART_CTRL2 0x00000020
49#define AUART_CTRL2_SET 0x00000024
50#define AUART_CTRL2_CLR 0x00000028
51#define AUART_CTRL2_TOG 0x0000002c
52#define AUART_LINECTRL 0x00000030
53#define AUART_LINECTRL_SET 0x00000034
54#define AUART_LINECTRL_CLR 0x00000038
55#define AUART_LINECTRL_TOG 0x0000003c
56#define AUART_LINECTRL2 0x00000040
57#define AUART_LINECTRL2_SET 0x00000044
58#define AUART_LINECTRL2_CLR 0x00000048
59#define AUART_LINECTRL2_TOG 0x0000004c
60#define AUART_INTR 0x00000050
61#define AUART_INTR_SET 0x00000054
62#define AUART_INTR_CLR 0x00000058
63#define AUART_INTR_TOG 0x0000005c
64#define AUART_DATA 0x00000060
65#define AUART_STAT 0x00000070
66#define AUART_DEBUG 0x00000080
67#define AUART_VERSION 0x00000090
68#define AUART_AUTOBAUD 0x000000a0
69
70#define AUART_CTRL0_SFTRST (1 << 31)
71#define AUART_CTRL0_CLKGATE (1 << 30)
72
73#define AUART_CTRL2_CTSEN (1 << 15)
74#define AUART_CTRL2_RTS (1 << 11)
75#define AUART_CTRL2_RXE (1 << 9)
76#define AUART_CTRL2_TXE (1 << 8)
77#define AUART_CTRL2_UARTEN (1 << 0)
78
79#define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
80#define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
81#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
82#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
83#define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
84#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
85#define AUART_LINECTRL_WLEN_MASK 0x00000060
86#define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
87#define AUART_LINECTRL_FEN (1 << 4)
88#define AUART_LINECTRL_STP2 (1 << 3)
89#define AUART_LINECTRL_EPS (1 << 2)
90#define AUART_LINECTRL_PEN (1 << 1)
91#define AUART_LINECTRL_BRK (1 << 0)
92
93#define AUART_INTR_RTIEN (1 << 22)
94#define AUART_INTR_TXIEN (1 << 21)
95#define AUART_INTR_RXIEN (1 << 20)
96#define AUART_INTR_CTSMIEN (1 << 17)
97#define AUART_INTR_RTIS (1 << 6)
98#define AUART_INTR_TXIS (1 << 5)
99#define AUART_INTR_RXIS (1 << 4)
100#define AUART_INTR_CTSMIS (1 << 1)
101
102#define AUART_STAT_BUSY (1 << 29)
103#define AUART_STAT_CTS (1 << 28)
104#define AUART_STAT_TXFE (1 << 27)
105#define AUART_STAT_TXFF (1 << 25)
106#define AUART_STAT_RXFE (1 << 24)
107#define AUART_STAT_OERR (1 << 19)
108#define AUART_STAT_BERR (1 << 18)
109#define AUART_STAT_PERR (1 << 17)
110#define AUART_STAT_FERR (1 << 16)
111
112static struct uart_driver auart_driver;
113
114struct mxs_auart_port {
115 struct uart_port port;
116
117 unsigned int flags;
118 unsigned int ctrl;
119
120 unsigned int irq;
121
122 struct clk *clk;
123 struct device *dev;
124};
125
126static void mxs_auart_stop_tx(struct uart_port *u);
127
128#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
129
130static inline void mxs_auart_tx_chars(struct mxs_auart_port *s)
131{
132 struct circ_buf *xmit = &s->port.state->xmit;
133
134 while (!(readl(s->port.membase + AUART_STAT) &
135 AUART_STAT_TXFF)) {
136 if (s->port.x_char) {
137 s->port.icount.tx++;
138 writel(s->port.x_char,
139 s->port.membase + AUART_DATA);
140 s->port.x_char = 0;
141 continue;
142 }
143 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
144 s->port.icount.tx++;
145 writel(xmit->buf[xmit->tail],
146 s->port.membase + AUART_DATA);
147 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
148 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
149 uart_write_wakeup(&s->port);
150 } else
151 break;
152 }
153 if (uart_circ_empty(&(s->port.state->xmit)))
154 writel(AUART_INTR_TXIEN,
155 s->port.membase + AUART_INTR_CLR);
156 else
157 writel(AUART_INTR_TXIEN,
158 s->port.membase + AUART_INTR_SET);
159
160 if (uart_tx_stopped(&s->port))
161 mxs_auart_stop_tx(&s->port);
162}
163
164static void mxs_auart_rx_char(struct mxs_auart_port *s)
165{
166 int flag;
167 u32 stat;
168 u8 c;
169
170 c = readl(s->port.membase + AUART_DATA);
171 stat = readl(s->port.membase + AUART_STAT);
172
173 flag = TTY_NORMAL;
174 s->port.icount.rx++;
175
176 if (stat & AUART_STAT_BERR) {
177 s->port.icount.brk++;
178 if (uart_handle_break(&s->port))
179 goto out;
180 } else if (stat & AUART_STAT_PERR) {
181 s->port.icount.parity++;
182 } else if (stat & AUART_STAT_FERR) {
183 s->port.icount.frame++;
184 }
185
186 /*
187 * Mask off conditions which should be ingored.
188 */
189 stat &= s->port.read_status_mask;
190
191 if (stat & AUART_STAT_BERR) {
192 flag = TTY_BREAK;
193 } else if (stat & AUART_STAT_PERR)
194 flag = TTY_PARITY;
195 else if (stat & AUART_STAT_FERR)
196 flag = TTY_FRAME;
197
198 if (stat & AUART_STAT_OERR)
199 s->port.icount.overrun++;
200
201 if (uart_handle_sysrq_char(&s->port, c))
202 goto out;
203
204 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
205out:
206 writel(stat, s->port.membase + AUART_STAT);
207}
208
209static void mxs_auart_rx_chars(struct mxs_auart_port *s)
210{
211 struct tty_struct *tty = s->port.state->port.tty;
212 u32 stat = 0;
213
214 for (;;) {
215 stat = readl(s->port.membase + AUART_STAT);
216 if (stat & AUART_STAT_RXFE)
217 break;
218 mxs_auart_rx_char(s);
219 }
220
221 writel(stat, s->port.membase + AUART_STAT);
222 tty_flip_buffer_push(tty);
223}
224
225static int mxs_auart_request_port(struct uart_port *u)
226{
227 return 0;
228}
229
230static int mxs_auart_verify_port(struct uart_port *u,
231 struct serial_struct *ser)
232{
233 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
234 return -EINVAL;
235 return 0;
236}
237
238static void mxs_auart_config_port(struct uart_port *u, int flags)
239{
240}
241
242static const char *mxs_auart_type(struct uart_port *u)
243{
244 struct mxs_auart_port *s = to_auart_port(u);
245
246 return dev_name(s->dev);
247}
248
249static void mxs_auart_release_port(struct uart_port *u)
250{
251}
252
253static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
254{
255 struct mxs_auart_port *s = to_auart_port(u);
256
257 u32 ctrl = readl(u->membase + AUART_CTRL2);
258
259 ctrl &= ~AUART_CTRL2_RTS;
260 if (mctrl & TIOCM_RTS)
261 ctrl |= AUART_CTRL2_RTS;
262 s->ctrl = mctrl;
263 writel(ctrl, u->membase + AUART_CTRL2);
264}
265
266static u32 mxs_auart_get_mctrl(struct uart_port *u)
267{
268 struct mxs_auart_port *s = to_auart_port(u);
269 u32 stat = readl(u->membase + AUART_STAT);
270 int ctrl2 = readl(u->membase + AUART_CTRL2);
271 u32 mctrl = s->ctrl;
272
273 mctrl &= ~TIOCM_CTS;
274 if (stat & AUART_STAT_CTS)
275 mctrl |= TIOCM_CTS;
276
277 if (ctrl2 & AUART_CTRL2_RTS)
278 mctrl |= TIOCM_RTS;
279
280 return mctrl;
281}
282
283static void mxs_auart_settermios(struct uart_port *u,
284 struct ktermios *termios,
285 struct ktermios *old)
286{
287 u32 bm, ctrl, ctrl2, div;
288 unsigned int cflag, baud;
289
290 cflag = termios->c_cflag;
291
292 ctrl = AUART_LINECTRL_FEN;
293 ctrl2 = readl(u->membase + AUART_CTRL2);
294
295 /* byte size */
296 switch (cflag & CSIZE) {
297 case CS5:
298 bm = 0;
299 break;
300 case CS6:
301 bm = 1;
302 break;
303 case CS7:
304 bm = 2;
305 break;
306 case CS8:
307 bm = 3;
308 break;
309 default:
310 return;
311 }
312
313 ctrl |= AUART_LINECTRL_WLEN(bm);
314
315 /* parity */
316 if (cflag & PARENB) {
317 ctrl |= AUART_LINECTRL_PEN;
318 if ((cflag & PARODD) == 0)
319 ctrl |= AUART_LINECTRL_EPS;
320 }
321
322 u->read_status_mask = 0;
323
324 if (termios->c_iflag & INPCK)
325 u->read_status_mask |= AUART_STAT_PERR;
326 if (termios->c_iflag & (BRKINT | PARMRK))
327 u->read_status_mask |= AUART_STAT_BERR;
328
329 /*
330 * Characters to ignore
331 */
332 u->ignore_status_mask = 0;
333 if (termios->c_iflag & IGNPAR)
334 u->ignore_status_mask |= AUART_STAT_PERR;
335 if (termios->c_iflag & IGNBRK) {
336 u->ignore_status_mask |= AUART_STAT_BERR;
337 /*
338 * If we're ignoring parity and break indicators,
339 * ignore overruns too (for real raw support).
340 */
341 if (termios->c_iflag & IGNPAR)
342 u->ignore_status_mask |= AUART_STAT_OERR;
343 }
344
345 /*
346 * ignore all characters if CREAD is not set
347 */
348 if (cflag & CREAD)
349 ctrl2 |= AUART_CTRL2_RXE;
350 else
351 ctrl2 &= ~AUART_CTRL2_RXE;
352
353 /* figure out the stop bits requested */
354 if (cflag & CSTOPB)
355 ctrl |= AUART_LINECTRL_STP2;
356
357 /* figure out the hardware flow control settings */
358 if (cflag & CRTSCTS)
359 ctrl2 |= AUART_CTRL2_CTSEN;
360 else
361 ctrl2 &= ~AUART_CTRL2_CTSEN;
362
363 /* set baud rate */
364 baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
365 div = u->uartclk * 32 / baud;
366 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
367 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
368
369 writel(ctrl, u->membase + AUART_LINECTRL);
370 writel(ctrl2, u->membase + AUART_CTRL2);
371}
372
373static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
374{
375 u32 istatus, istat;
376 struct mxs_auart_port *s = context;
377 u32 stat = readl(s->port.membase + AUART_STAT);
378
379 istatus = istat = readl(s->port.membase + AUART_INTR);
380
381 if (istat & AUART_INTR_CTSMIS) {
382 uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS);
383 writel(AUART_INTR_CTSMIS,
384 s->port.membase + AUART_INTR_CLR);
385 istat &= ~AUART_INTR_CTSMIS;
386 }
387
388 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
389 mxs_auart_rx_chars(s);
390 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
391 }
392
393 if (istat & AUART_INTR_TXIS) {
394 mxs_auart_tx_chars(s);
395 istat &= ~AUART_INTR_TXIS;
396 }
397
398 writel(istatus & (AUART_INTR_RTIS
399 | AUART_INTR_TXIS
400 | AUART_INTR_RXIS
401 | AUART_INTR_CTSMIS),
402 s->port.membase + AUART_INTR_CLR);
403
404 return IRQ_HANDLED;
405}
406
407static void mxs_auart_reset(struct uart_port *u)
408{
409 int i;
410 unsigned int reg;
411
412 writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
413
414 for (i = 0; i < 10000; i++) {
415 reg = readl(u->membase + AUART_CTRL0);
416 if (!(reg & AUART_CTRL0_SFTRST))
417 break;
418 udelay(3);
419 }
420 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
421}
422
423static int mxs_auart_startup(struct uart_port *u)
424{
425 struct mxs_auart_port *s = to_auart_port(u);
426
427 clk_enable(s->clk);
428
429 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
430
431 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
432
433 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
434 u->membase + AUART_INTR);
435
436 /*
437 * Enable fifo so all four bytes of a DMA word are written to
438 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
439 */
440 writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
441
442 return 0;
443}
444
445static void mxs_auart_shutdown(struct uart_port *u)
446{
447 struct mxs_auart_port *s = to_auart_port(u);
448
449 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
450
451 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
452
453 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
454 u->membase + AUART_INTR_CLR);
455
456 clk_disable(s->clk);
457}
458
459static unsigned int mxs_auart_tx_empty(struct uart_port *u)
460{
461 if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE)
462 return TIOCSER_TEMT;
463 else
464 return 0;
465}
466
467static void mxs_auart_start_tx(struct uart_port *u)
468{
469 struct mxs_auart_port *s = to_auart_port(u);
470
471 /* enable transmitter */
472 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
473
474 mxs_auart_tx_chars(s);
475}
476
477static void mxs_auart_stop_tx(struct uart_port *u)
478{
479 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
480}
481
482static void mxs_auart_stop_rx(struct uart_port *u)
483{
484 writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
485}
486
487static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
488{
489 if (ctl)
490 writel(AUART_LINECTRL_BRK,
491 u->membase + AUART_LINECTRL_SET);
492 else
493 writel(AUART_LINECTRL_BRK,
494 u->membase + AUART_LINECTRL_CLR);
495}
496
497static void mxs_auart_enable_ms(struct uart_port *port)
498{
499 /* just empty */
500}
501
502static struct uart_ops mxs_auart_ops = {
503 .tx_empty = mxs_auart_tx_empty,
504 .start_tx = mxs_auart_start_tx,
505 .stop_tx = mxs_auart_stop_tx,
506 .stop_rx = mxs_auart_stop_rx,
507 .enable_ms = mxs_auart_enable_ms,
508 .break_ctl = mxs_auart_break_ctl,
509 .set_mctrl = mxs_auart_set_mctrl,
510 .get_mctrl = mxs_auart_get_mctrl,
511 .startup = mxs_auart_startup,
512 .shutdown = mxs_auart_shutdown,
513 .set_termios = mxs_auart_settermios,
514 .type = mxs_auart_type,
515 .release_port = mxs_auart_release_port,
516 .request_port = mxs_auart_request_port,
517 .config_port = mxs_auart_config_port,
518 .verify_port = mxs_auart_verify_port,
519};
520
521static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
522
523#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
524static void mxs_auart_console_putchar(struct uart_port *port, int ch)
525{
526 unsigned int to = 1000;
527
528 while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
529 if (!to--)
530 break;
531 udelay(1);
532 }
533
534 writel(ch, port->membase + AUART_DATA);
535}
536
537static void
538auart_console_write(struct console *co, const char *str, unsigned int count)
539{
540 struct mxs_auart_port *s;
541 struct uart_port *port;
542 unsigned int old_ctrl0, old_ctrl2;
543 unsigned int to = 1000;
544
545 if (co->index > MXS_AUART_PORTS || co->index < 0)
546 return;
547
548 s = auart_port[co->index];
549 port = &s->port;
550
551 clk_enable(s->clk);
552
553 /* First save the CR then disable the interrupts */
554 old_ctrl2 = readl(port->membase + AUART_CTRL2);
555 old_ctrl0 = readl(port->membase + AUART_CTRL0);
556
557 writel(AUART_CTRL0_CLKGATE,
558 port->membase + AUART_CTRL0_CLR);
559 writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
560 port->membase + AUART_CTRL2_SET);
561
562 uart_console_write(port, str, count, mxs_auart_console_putchar);
563
564 /*
565 * Finally, wait for transmitter to become empty
566 * and restore the TCR
567 */
568 while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
569 if (!to--)
570 break;
571 udelay(1);
572 }
573
574 writel(old_ctrl0, port->membase + AUART_CTRL0);
575 writel(old_ctrl2, port->membase + AUART_CTRL2);
576
577 clk_disable(s->clk);
578}
579
580static void __init
581auart_console_get_options(struct uart_port *port, int *baud,
582 int *parity, int *bits)
583{
584 unsigned int lcr_h, quot;
585
586 if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
587 return;
588
589 lcr_h = readl(port->membase + AUART_LINECTRL);
590
591 *parity = 'n';
592 if (lcr_h & AUART_LINECTRL_PEN) {
593 if (lcr_h & AUART_LINECTRL_EPS)
594 *parity = 'e';
595 else
596 *parity = 'o';
597 }
598
599 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
600 *bits = 7;
601 else
602 *bits = 8;
603
604 quot = ((readl(port->membase + AUART_LINECTRL)
605 & AUART_LINECTRL_BAUD_DIVINT_MASK))
606 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
607 quot |= ((readl(port->membase + AUART_LINECTRL)
608 & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
609 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
610 if (quot == 0)
611 quot = 1;
612
613 *baud = (port->uartclk << 2) / quot;
614}
615
616static int __init
617auart_console_setup(struct console *co, char *options)
618{
619 struct mxs_auart_port *s;
620 int baud = 9600;
621 int bits = 8;
622 int parity = 'n';
623 int flow = 'n';
624 int ret;
625
626 /*
627 * Check whether an invalid uart number has been specified, and
628 * if so, search for the first available port that does have
629 * console support.
630 */
631 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
632 co->index = 0;
633 s = auart_port[co->index];
634 if (!s)
635 return -ENODEV;
636
637 clk_enable(s->clk);
638
639 if (options)
640 uart_parse_options(options, &baud, &parity, &bits, &flow);
641 else
642 auart_console_get_options(&s->port, &baud, &parity, &bits);
643
644 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
645
646 clk_disable(s->clk);
647
648 return ret;
649}
650
651static struct console auart_console = {
652 .name = "ttyAPP",
653 .write = auart_console_write,
654 .device = uart_console_device,
655 .setup = auart_console_setup,
656 .flags = CON_PRINTBUFFER,
657 .index = -1,
658 .data = &auart_driver,
659};
660#endif
661
662static struct uart_driver auart_driver = {
663 .owner = THIS_MODULE,
664 .driver_name = "ttyAPP",
665 .dev_name = "ttyAPP",
666 .major = 0,
667 .minor = 0,
668 .nr = MXS_AUART_PORTS,
669#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
670 .cons = &auart_console,
671#endif
672};
673
674static int __devinit mxs_auart_probe(struct platform_device *pdev)
675{
676 struct mxs_auart_port *s;
677 u32 version;
678 int ret = 0;
679 struct resource *r;
680
681 s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
682 if (!s) {
683 ret = -ENOMEM;
684 goto out;
685 }
686
687 s->clk = clk_get(&pdev->dev, NULL);
688 if (IS_ERR(s->clk)) {
689 ret = PTR_ERR(s->clk);
690 goto out_free;
691 }
692
693 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
694 if (!r) {
695 ret = -ENXIO;
696 goto out_free_clk;
697 }
698
699 s->port.mapbase = r->start;
700 s->port.membase = ioremap(r->start, resource_size(r));
701 s->port.ops = &mxs_auart_ops;
702 s->port.iotype = UPIO_MEM;
703 s->port.line = pdev->id < 0 ? 0 : pdev->id;
704 s->port.fifosize = 16;
705 s->port.uartclk = clk_get_rate(s->clk);
706 s->port.type = PORT_IMX;
707 s->port.dev = s->dev = get_device(&pdev->dev);
708
709 s->flags = 0;
710 s->ctrl = 0;
711
712 s->irq = platform_get_irq(pdev, 0);
713 s->port.irq = s->irq;
714 ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s);
715 if (ret)
716 goto out_free_clk;
717
718 platform_set_drvdata(pdev, s);
719
720 auart_port[pdev->id] = s;
721
722 mxs_auart_reset(&s->port);
723
724 ret = uart_add_one_port(&auart_driver, &s->port);
725 if (ret)
726 goto out_free_irq;
727
728 version = readl(s->port.membase + AUART_VERSION);
729 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
730 (version >> 24) & 0xff,
731 (version >> 16) & 0xff, version & 0xffff);
732
733 return 0;
734
735out_free_irq:
736 auart_port[pdev->id] = NULL;
737 free_irq(s->irq, s);
738out_free_clk:
739 clk_put(s->clk);
740out_free:
741 kfree(s);
742out:
743 return ret;
744}
745
746static int __devexit mxs_auart_remove(struct platform_device *pdev)
747{
748 struct mxs_auart_port *s = platform_get_drvdata(pdev);
749
750 uart_remove_one_port(&auart_driver, &s->port);
751
752 auart_port[pdev->id] = NULL;
753
754 clk_put(s->clk);
755 free_irq(s->irq, s);
756 kfree(s);
757
758 return 0;
759}
760
761static struct platform_driver mxs_auart_driver = {
762 .probe = mxs_auart_probe,
763 .remove = __devexit_p(mxs_auart_remove),
764 .driver = {
765 .name = "mxs-auart",
766 .owner = THIS_MODULE,
767 },
768};
769
770static int __init mxs_auart_init(void)
771{
772 int r;
773
774 r = uart_register_driver(&auart_driver);
775 if (r)
776 goto out;
777
778 r = platform_driver_register(&mxs_auart_driver);
779 if (r)
780 goto out_err;
781
782 return 0;
783out_err:
784 uart_unregister_driver(&auart_driver);
785out:
786 return r;
787}
788
789static void __exit mxs_auart_exit(void)
790{
791 platform_driver_unregister(&mxs_auart_driver);
792 uart_unregister_driver(&auart_driver);
793}
794
795module_init(mxs_auart_init);
796module_exit(mxs_auart_exit);
797MODULE_LICENSE("GPL");
798MODULE_DESCRIPTION("Freescale MXS application uart driver");
1/*
2 * Application UART driver for:
3 * Freescale STMP37XX/STMP378X
4 * Alphascale ASM9260
5 *
6 * Author: dmitry pervushin <dimka@embeddedalley.com>
7 *
8 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
9 * Provide Alphascale ASM9260 support.
10 * Copyright 2008-2010 Freescale Semiconductor, Inc.
11 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
12 *
13 * The code contained herein is licensed under the GNU General Public
14 * License. You may obtain a copy of the GNU General Public License
15 * Version 2 or later at the following locations:
16 */
17
18#if defined(CONFIG_SERIAL_MXS_AUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19#define SUPPORT_SYSRQ
20#endif
21
22#include <linux/kernel.h>
23#include <linux/errno.h>
24#include <linux/init.h>
25#include <linux/console.h>
26#include <linux/interrupt.h>
27#include <linux/module.h>
28#include <linux/slab.h>
29#include <linux/wait.h>
30#include <linux/tty.h>
31#include <linux/tty_driver.h>
32#include <linux/tty_flip.h>
33#include <linux/serial.h>
34#include <linux/serial_core.h>
35#include <linux/platform_device.h>
36#include <linux/device.h>
37#include <linux/clk.h>
38#include <linux/delay.h>
39#include <linux/io.h>
40#include <linux/of_device.h>
41#include <linux/dma-mapping.h>
42#include <linux/dmaengine.h>
43
44#include <asm/cacheflush.h>
45
46#include <linux/gpio.h>
47#include <linux/gpio/consumer.h>
48#include <linux/err.h>
49#include <linux/irq.h>
50#include "serial_mctrl_gpio.h"
51
52#define MXS_AUART_PORTS 5
53#define MXS_AUART_FIFO_SIZE 16
54
55#define SET_REG 0x4
56#define CLR_REG 0x8
57#define TOG_REG 0xc
58
59#define AUART_CTRL0 0x00000000
60#define AUART_CTRL1 0x00000010
61#define AUART_CTRL2 0x00000020
62#define AUART_LINECTRL 0x00000030
63#define AUART_LINECTRL2 0x00000040
64#define AUART_INTR 0x00000050
65#define AUART_DATA 0x00000060
66#define AUART_STAT 0x00000070
67#define AUART_DEBUG 0x00000080
68#define AUART_VERSION 0x00000090
69#define AUART_AUTOBAUD 0x000000a0
70
71#define AUART_CTRL0_SFTRST (1 << 31)
72#define AUART_CTRL0_CLKGATE (1 << 30)
73#define AUART_CTRL0_RXTO_ENABLE (1 << 27)
74#define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
75#define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
76
77#define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
78
79#define AUART_CTRL2_DMAONERR (1 << 26)
80#define AUART_CTRL2_TXDMAE (1 << 25)
81#define AUART_CTRL2_RXDMAE (1 << 24)
82
83#define AUART_CTRL2_CTSEN (1 << 15)
84#define AUART_CTRL2_RTSEN (1 << 14)
85#define AUART_CTRL2_RTS (1 << 11)
86#define AUART_CTRL2_RXE (1 << 9)
87#define AUART_CTRL2_TXE (1 << 8)
88#define AUART_CTRL2_UARTEN (1 << 0)
89
90#define AUART_LINECTRL_BAUD_DIV_MAX 0x003fffc0
91#define AUART_LINECTRL_BAUD_DIV_MIN 0x000000ec
92#define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
93#define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
94#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
95#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
96#define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
97#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
98#define AUART_LINECTRL_WLEN_MASK 0x00000060
99#define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
100#define AUART_LINECTRL_FEN (1 << 4)
101#define AUART_LINECTRL_STP2 (1 << 3)
102#define AUART_LINECTRL_EPS (1 << 2)
103#define AUART_LINECTRL_PEN (1 << 1)
104#define AUART_LINECTRL_BRK (1 << 0)
105
106#define AUART_INTR_RTIEN (1 << 22)
107#define AUART_INTR_TXIEN (1 << 21)
108#define AUART_INTR_RXIEN (1 << 20)
109#define AUART_INTR_CTSMIEN (1 << 17)
110#define AUART_INTR_RTIS (1 << 6)
111#define AUART_INTR_TXIS (1 << 5)
112#define AUART_INTR_RXIS (1 << 4)
113#define AUART_INTR_CTSMIS (1 << 1)
114
115#define AUART_STAT_BUSY (1 << 29)
116#define AUART_STAT_CTS (1 << 28)
117#define AUART_STAT_TXFE (1 << 27)
118#define AUART_STAT_TXFF (1 << 25)
119#define AUART_STAT_RXFE (1 << 24)
120#define AUART_STAT_OERR (1 << 19)
121#define AUART_STAT_BERR (1 << 18)
122#define AUART_STAT_PERR (1 << 17)
123#define AUART_STAT_FERR (1 << 16)
124#define AUART_STAT_RXCOUNT_MASK 0xffff
125
126/*
127 * Start of Alphascale asm9260 defines
128 * This list contains only differences of existing bits
129 * between imx2x and asm9260
130 */
131#define ASM9260_HW_CTRL0 0x0000
132/*
133 * RW. Tell the UART to execute the RX DMA Command. The
134 * UART will clear this bit at the end of receive execution.
135 */
136#define ASM9260_BM_CTRL0_RXDMA_RUN BIT(28)
137/* RW. 0 use FIFO for status register; 1 use DMA */
138#define ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS BIT(25)
139/*
140 * RW. RX TIMEOUT Enable. Valid for FIFO and DMA.
141 * Warning: If this bit is set to 0, the RX timeout will not affect receive DMA
142 * operation. If this bit is set to 1, a receive timeout will cause the receive
143 * DMA logic to terminate by filling the remaining DMA bytes with garbage data.
144 */
145#define ASM9260_BM_CTRL0_RXTO_ENABLE BIT(24)
146/*
147 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before
148 * asserting timeout on the RX input. If the RXFIFO is not empty and the RX
149 * input is idle, then the watchdog counter will decrement each bit-time. Note
150 * 7-bit-time is added to the programmed value, so a value of zero will set
151 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also
152 * note that the counter is reloaded at the end of each frame, so if the frame
153 * is 10 bits long and the timeout counter value is zero, then timeout will
154 * occur (when FIFO is not empty) even if the RX input is not idle. The default
155 * value is 0x3 (31 bit-time).
156 */
157#define ASM9260_BM_CTRL0_RXTO_MASK (0xff << 16)
158/* TIMEOUT = (100*7+1)*(1/BAUD) */
159#define ASM9260_BM_CTRL0_DEFAULT_RXTIMEOUT (20 << 16)
160
161/* TX ctrl register */
162#define ASM9260_HW_CTRL1 0x0010
163/*
164 * RW. Tell the UART to execute the TX DMA Command. The
165 * UART will clear this bit at the end of transmit execution.
166 */
167#define ASM9260_BM_CTRL1_TXDMA_RUN BIT(28)
168
169#define ASM9260_HW_CTRL2 0x0020
170/*
171 * RW. Receive Interrupt FIFO Level Select.
172 * The trigger points for the receive interrupt are as follows:
173 * ONE_EIGHTHS = 0x0 Trigger on FIFO full to at least 2 of 16 entries.
174 * ONE_QUARTER = 0x1 Trigger on FIFO full to at least 4 of 16 entries.
175 * ONE_HALF = 0x2 Trigger on FIFO full to at least 8 of 16 entries.
176 * THREE_QUARTERS = 0x3 Trigger on FIFO full to at least 12 of 16 entries.
177 * SEVEN_EIGHTHS = 0x4 Trigger on FIFO full to at least 14 of 16 entries.
178 */
179#define ASM9260_BM_CTRL2_RXIFLSEL (7 << 20)
180#define ASM9260_BM_CTRL2_DEFAULT_RXIFLSEL (3 << 20)
181/* RW. Same as RXIFLSEL */
182#define ASM9260_BM_CTRL2_TXIFLSEL (7 << 16)
183#define ASM9260_BM_CTRL2_DEFAULT_TXIFLSEL (2 << 16)
184/* RW. Set DTR. When this bit is 1, the output is 0. */
185#define ASM9260_BM_CTRL2_DTR BIT(10)
186/* RW. Loop Back Enable */
187#define ASM9260_BM_CTRL2_LBE BIT(7)
188#define ASM9260_BM_CTRL2_PORT_ENABLE BIT(0)
189
190#define ASM9260_HW_LINECTRL 0x0030
191/*
192 * RW. Stick Parity Select. When bits 1, 2, and 7 of this register are set, the
193 * parity bit is transmitted and checked as a 0. When bits 1 and 7 are set,
194 * and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this
195 * bit is cleared stick parity is disabled.
196 */
197#define ASM9260_BM_LCTRL_SPS BIT(7)
198/* RW. Word length */
199#define ASM9260_BM_LCTRL_WLEN (3 << 5)
200#define ASM9260_BM_LCTRL_CHRL_5 (0 << 5)
201#define ASM9260_BM_LCTRL_CHRL_6 (1 << 5)
202#define ASM9260_BM_LCTRL_CHRL_7 (2 << 5)
203#define ASM9260_BM_LCTRL_CHRL_8 (3 << 5)
204
205/*
206 * Interrupt register.
207 * contains the interrupt enables and the interrupt status bits
208 */
209#define ASM9260_HW_INTR 0x0040
210/* Tx FIFO EMPTY Raw Interrupt enable */
211#define ASM9260_BM_INTR_TFEIEN BIT(27)
212/* Overrun Error Interrupt Enable. */
213#define ASM9260_BM_INTR_OEIEN BIT(26)
214/* Break Error Interrupt Enable. */
215#define ASM9260_BM_INTR_BEIEN BIT(25)
216/* Parity Error Interrupt Enable. */
217#define ASM9260_BM_INTR_PEIEN BIT(24)
218/* Framing Error Interrupt Enable. */
219#define ASM9260_BM_INTR_FEIEN BIT(23)
220
221/* nUARTDSR Modem Interrupt Enable. */
222#define ASM9260_BM_INTR_DSRMIEN BIT(19)
223/* nUARTDCD Modem Interrupt Enable. */
224#define ASM9260_BM_INTR_DCDMIEN BIT(18)
225/* nUARTRI Modem Interrupt Enable. */
226#define ASM9260_BM_INTR_RIMIEN BIT(16)
227/* Auto-Boud Timeout */
228#define ASM9260_BM_INTR_ABTO BIT(13)
229#define ASM9260_BM_INTR_ABEO BIT(12)
230/* Tx FIFO EMPTY Raw Interrupt state */
231#define ASM9260_BM_INTR_TFEIS BIT(11)
232/* Overrun Error */
233#define ASM9260_BM_INTR_OEIS BIT(10)
234/* Break Error */
235#define ASM9260_BM_INTR_BEIS BIT(9)
236/* Parity Error */
237#define ASM9260_BM_INTR_PEIS BIT(8)
238/* Framing Error */
239#define ASM9260_BM_INTR_FEIS BIT(7)
240#define ASM9260_BM_INTR_DSRMIS BIT(3)
241#define ASM9260_BM_INTR_DCDMIS BIT(2)
242#define ASM9260_BM_INTR_RIMIS BIT(0)
243
244/*
245 * RW. In DMA mode, up to 4 Received/Transmit characters can be accessed at a
246 * time. In PIO mode, only one character can be accessed at a time. The status
247 * register contains the receive data flags and valid bits.
248 */
249#define ASM9260_HW_DATA 0x0050
250
251#define ASM9260_HW_STAT 0x0060
252/* RO. If 1, UARTAPP is present in this product. */
253#define ASM9260_BM_STAT_PRESENT BIT(31)
254/* RO. If 1, HISPEED is present in this product. */
255#define ASM9260_BM_STAT_HISPEED BIT(30)
256/* RO. Receive FIFO Full. */
257#define ASM9260_BM_STAT_RXFULL BIT(26)
258
259/* RO. The UART Debug Register contains the state of the DMA signals. */
260#define ASM9260_HW_DEBUG 0x0070
261/* DMA Command Run Status */
262#define ASM9260_BM_DEBUG_TXDMARUN BIT(5)
263#define ASM9260_BM_DEBUG_RXDMARUN BIT(4)
264/* DMA Command End Status */
265#define ASM9260_BM_DEBUG_TXCMDEND BIT(3)
266#define ASM9260_BM_DEBUG_RXCMDEND BIT(2)
267/* DMA Request Status */
268#define ASM9260_BM_DEBUG_TXDMARQ BIT(1)
269#define ASM9260_BM_DEBUG_RXDMARQ BIT(0)
270
271#define ASM9260_HW_ILPR 0x0080
272
273#define ASM9260_HW_RS485CTRL 0x0090
274/*
275 * RW. This bit reverses the polarity of the direction control signal on the RTS
276 * (or DTR) pin.
277 * If 0, The direction control pin will be driven to logic ‘0’ when the
278 * transmitter has data to be sent. It will be driven to logic ‘1’ after the
279 * last bit of data has been transmitted.
280 */
281#define ASM9260_BM_RS485CTRL_ONIV BIT(5)
282/* RW. Enable Auto Direction Control. */
283#define ASM9260_BM_RS485CTRL_DIR_CTRL BIT(4)
284/*
285 * RW. If 0 and DIR_CTRL = 1, pin RTS is used for direction control.
286 * If 1 and DIR_CTRL = 1, pin DTR is used for direction control.
287 */
288#define ASM9260_BM_RS485CTRL_PINSEL BIT(3)
289/* RW. Enable Auto Address Detect (AAD). */
290#define ASM9260_BM_RS485CTRL_AADEN BIT(2)
291/* RW. Disable receiver. */
292#define ASM9260_BM_RS485CTRL_RXDIS BIT(1)
293/* RW. Enable RS-485/EIA-485 Normal Multidrop Mode (NMM) */
294#define ASM9260_BM_RS485CTRL_RS485EN BIT(0)
295
296#define ASM9260_HW_RS485ADRMATCH 0x00a0
297/* Contains the address match value. */
298#define ASM9260_BM_RS485ADRMATCH_MASK (0xff << 0)
299
300#define ASM9260_HW_RS485DLY 0x00b0
301/*
302 * RW. Contains the direction control (RTS or DTR) delay value. This delay time
303 * is in periods of the baud clock.
304 */
305#define ASM9260_BM_RS485DLY_MASK (0xff << 0)
306
307#define ASM9260_HW_AUTOBAUD 0x00c0
308/* WO. Auto-baud time-out interrupt clear bit. */
309#define ASM9260_BM_AUTOBAUD_TO_INT_CLR BIT(9)
310/* WO. End of auto-baud interrupt clear bit. */
311#define ASM9260_BM_AUTOBAUD_EO_INT_CLR BIT(8)
312/* Restart in case of timeout (counter restarts at next UART Rx falling edge) */
313#define ASM9260_BM_AUTOBAUD_AUTORESTART BIT(2)
314/* Auto-baud mode select bit. 0 - Mode 0, 1 - Mode 1. */
315#define ASM9260_BM_AUTOBAUD_MODE BIT(1)
316/*
317 * Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
318 * automatically cleared after auto-baud completion.
319 */
320#define ASM9260_BM_AUTOBAUD_START BIT(0)
321
322#define ASM9260_HW_CTRL3 0x00d0
323#define ASM9260_BM_CTRL3_OUTCLK_DIV_MASK (0xffff << 16)
324/*
325 * RW. Provide clk over OUTCLK pin. In case of asm9260 it can be configured on
326 * pins 137 and 144.
327 */
328#define ASM9260_BM_CTRL3_MASTERMODE BIT(6)
329/* RW. Baud Rate Mode: 1 - Enable sync mode. 0 - async mode. */
330#define ASM9260_BM_CTRL3_SYNCMODE BIT(4)
331/* RW. 1 - MSB bit send frist; 0 - LSB bit frist. */
332#define ASM9260_BM_CTRL3_MSBF BIT(2)
333/* RW. 1 - sample rate = 8 x Baudrate; 0 - sample rate = 16 x Baudrate. */
334#define ASM9260_BM_CTRL3_BAUD8 BIT(1)
335/* RW. 1 - Set word length to 9bit. 0 - use ASM9260_BM_LCTRL_WLEN */
336#define ASM9260_BM_CTRL3_9BIT BIT(0)
337
338#define ASM9260_HW_ISO7816_CTRL 0x00e0
339/* RW. Enable High Speed mode. */
340#define ASM9260_BM_ISO7816CTRL_HS BIT(12)
341/* Disable Successive Receive NACK */
342#define ASM9260_BM_ISO7816CTRL_DS_NACK BIT(8)
343#define ASM9260_BM_ISO7816CTRL_MAX_ITER_MASK (0xff << 4)
344/* Receive NACK Inhibit */
345#define ASM9260_BM_ISO7816CTRL_INACK BIT(3)
346#define ASM9260_BM_ISO7816CTRL_NEG_DATA BIT(2)
347/* RW. 1 - ISO7816 mode; 0 - USART mode */
348#define ASM9260_BM_ISO7816CTRL_ENABLE BIT(0)
349
350#define ASM9260_HW_ISO7816_ERRCNT 0x00f0
351/* Parity error counter. Will be cleared after reading */
352#define ASM9260_BM_ISO7816_NB_ERRORS_MASK (0xff << 0)
353
354#define ASM9260_HW_ISO7816_STATUS 0x0100
355/* Max number of Repetitions Reached */
356#define ASM9260_BM_ISO7816_STAT_ITERATION BIT(0)
357
358/* End of Alphascale asm9260 defines */
359
360static struct uart_driver auart_driver;
361
362enum mxs_auart_type {
363 IMX23_AUART,
364 IMX28_AUART,
365 ASM9260_AUART,
366};
367
368struct vendor_data {
369 const u16 *reg_offset;
370};
371
372enum {
373 REG_CTRL0,
374 REG_CTRL1,
375 REG_CTRL2,
376 REG_LINECTRL,
377 REG_LINECTRL2,
378 REG_INTR,
379 REG_DATA,
380 REG_STAT,
381 REG_DEBUG,
382 REG_VERSION,
383 REG_AUTOBAUD,
384
385 /* The size of the array - must be last */
386 REG_ARRAY_SIZE,
387};
388
389static const u16 mxs_asm9260_offsets[REG_ARRAY_SIZE] = {
390 [REG_CTRL0] = ASM9260_HW_CTRL0,
391 [REG_CTRL1] = ASM9260_HW_CTRL1,
392 [REG_CTRL2] = ASM9260_HW_CTRL2,
393 [REG_LINECTRL] = ASM9260_HW_LINECTRL,
394 [REG_INTR] = ASM9260_HW_INTR,
395 [REG_DATA] = ASM9260_HW_DATA,
396 [REG_STAT] = ASM9260_HW_STAT,
397 [REG_DEBUG] = ASM9260_HW_DEBUG,
398 [REG_AUTOBAUD] = ASM9260_HW_AUTOBAUD,
399};
400
401static const u16 mxs_stmp37xx_offsets[REG_ARRAY_SIZE] = {
402 [REG_CTRL0] = AUART_CTRL0,
403 [REG_CTRL1] = AUART_CTRL1,
404 [REG_CTRL2] = AUART_CTRL2,
405 [REG_LINECTRL] = AUART_LINECTRL,
406 [REG_LINECTRL2] = AUART_LINECTRL2,
407 [REG_INTR] = AUART_INTR,
408 [REG_DATA] = AUART_DATA,
409 [REG_STAT] = AUART_STAT,
410 [REG_DEBUG] = AUART_DEBUG,
411 [REG_VERSION] = AUART_VERSION,
412 [REG_AUTOBAUD] = AUART_AUTOBAUD,
413};
414
415static const struct vendor_data vendor_alphascale_asm9260 = {
416 .reg_offset = mxs_asm9260_offsets,
417};
418
419static const struct vendor_data vendor_freescale_stmp37xx = {
420 .reg_offset = mxs_stmp37xx_offsets,
421};
422
423struct mxs_auart_port {
424 struct uart_port port;
425
426#define MXS_AUART_DMA_ENABLED 0x2
427#define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
428#define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
429#define MXS_AUART_RTSCTS 4 /* bit 4 */
430 unsigned long flags;
431 unsigned int mctrl_prev;
432 enum mxs_auart_type devtype;
433 const struct vendor_data *vendor;
434
435 struct clk *clk;
436 struct clk *clk_ahb;
437 struct device *dev;
438
439 /* for DMA */
440 struct scatterlist tx_sgl;
441 struct dma_chan *tx_dma_chan;
442 void *tx_dma_buf;
443
444 struct scatterlist rx_sgl;
445 struct dma_chan *rx_dma_chan;
446 void *rx_dma_buf;
447
448 struct mctrl_gpios *gpios;
449 int gpio_irq[UART_GPIO_MAX];
450 bool ms_irq_enabled;
451};
452
453static const struct platform_device_id mxs_auart_devtype[] = {
454 { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART },
455 { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART },
456 { .name = "as-auart-asm9260", .driver_data = ASM9260_AUART },
457 { /* sentinel */ }
458};
459MODULE_DEVICE_TABLE(platform, mxs_auart_devtype);
460
461static const struct of_device_id mxs_auart_dt_ids[] = {
462 {
463 .compatible = "fsl,imx28-auart",
464 .data = &mxs_auart_devtype[IMX28_AUART]
465 }, {
466 .compatible = "fsl,imx23-auart",
467 .data = &mxs_auart_devtype[IMX23_AUART]
468 }, {
469 .compatible = "alphascale,asm9260-auart",
470 .data = &mxs_auart_devtype[ASM9260_AUART]
471 }, { /* sentinel */ }
472};
473MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
474
475static inline int is_imx28_auart(struct mxs_auart_port *s)
476{
477 return s->devtype == IMX28_AUART;
478}
479
480static inline int is_asm9260_auart(struct mxs_auart_port *s)
481{
482 return s->devtype == ASM9260_AUART;
483}
484
485static inline bool auart_dma_enabled(struct mxs_auart_port *s)
486{
487 return s->flags & MXS_AUART_DMA_ENABLED;
488}
489
490static unsigned int mxs_reg_to_offset(const struct mxs_auart_port *uap,
491 unsigned int reg)
492{
493 return uap->vendor->reg_offset[reg];
494}
495
496static unsigned int mxs_read(const struct mxs_auart_port *uap,
497 unsigned int reg)
498{
499 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
500
501 return readl_relaxed(addr);
502}
503
504static void mxs_write(unsigned int val, struct mxs_auart_port *uap,
505 unsigned int reg)
506{
507 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
508
509 writel_relaxed(val, addr);
510}
511
512static void mxs_set(unsigned int val, struct mxs_auart_port *uap,
513 unsigned int reg)
514{
515 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
516
517 writel_relaxed(val, addr + SET_REG);
518}
519
520static void mxs_clr(unsigned int val, struct mxs_auart_port *uap,
521 unsigned int reg)
522{
523 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
524
525 writel_relaxed(val, addr + CLR_REG);
526}
527
528static void mxs_auart_stop_tx(struct uart_port *u);
529
530#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
531
532static void mxs_auart_tx_chars(struct mxs_auart_port *s);
533
534static void dma_tx_callback(void *param)
535{
536 struct mxs_auart_port *s = param;
537 struct circ_buf *xmit = &s->port.state->xmit;
538
539 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
540
541 /* clear the bit used to serialize the DMA tx. */
542 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
543 smp_mb__after_atomic();
544
545 /* wake up the possible processes. */
546 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
547 uart_write_wakeup(&s->port);
548
549 mxs_auart_tx_chars(s);
550}
551
552static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
553{
554 struct dma_async_tx_descriptor *desc;
555 struct scatterlist *sgl = &s->tx_sgl;
556 struct dma_chan *channel = s->tx_dma_chan;
557 u32 pio;
558
559 /* [1] : send PIO. Note, the first pio word is CTRL1. */
560 pio = AUART_CTRL1_XFER_COUNT(size);
561 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
562 1, DMA_TRANS_NONE, 0);
563 if (!desc) {
564 dev_err(s->dev, "step 1 error\n");
565 return -EINVAL;
566 }
567
568 /* [2] : set DMA buffer. */
569 sg_init_one(sgl, s->tx_dma_buf, size);
570 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
571 desc = dmaengine_prep_slave_sg(channel, sgl,
572 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
573 if (!desc) {
574 dev_err(s->dev, "step 2 error\n");
575 return -EINVAL;
576 }
577
578 /* [3] : submit the DMA */
579 desc->callback = dma_tx_callback;
580 desc->callback_param = s;
581 dmaengine_submit(desc);
582 dma_async_issue_pending(channel);
583 return 0;
584}
585
586static void mxs_auart_tx_chars(struct mxs_auart_port *s)
587{
588 struct circ_buf *xmit = &s->port.state->xmit;
589
590 if (auart_dma_enabled(s)) {
591 u32 i = 0;
592 int size;
593 void *buffer = s->tx_dma_buf;
594
595 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
596 return;
597
598 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
599 size = min_t(u32, UART_XMIT_SIZE - i,
600 CIRC_CNT_TO_END(xmit->head,
601 xmit->tail,
602 UART_XMIT_SIZE));
603 memcpy(buffer + i, xmit->buf + xmit->tail, size);
604 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
605
606 i += size;
607 if (i >= UART_XMIT_SIZE)
608 break;
609 }
610
611 if (uart_tx_stopped(&s->port))
612 mxs_auart_stop_tx(&s->port);
613
614 if (i) {
615 mxs_auart_dma_tx(s, i);
616 } else {
617 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
618 smp_mb__after_atomic();
619 }
620 return;
621 }
622
623
624 while (!(mxs_read(s, REG_STAT) & AUART_STAT_TXFF)) {
625 if (s->port.x_char) {
626 s->port.icount.tx++;
627 mxs_write(s->port.x_char, s, REG_DATA);
628 s->port.x_char = 0;
629 continue;
630 }
631 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
632 s->port.icount.tx++;
633 mxs_write(xmit->buf[xmit->tail], s, REG_DATA);
634 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
635 } else
636 break;
637 }
638 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
639 uart_write_wakeup(&s->port);
640
641 if (uart_circ_empty(&(s->port.state->xmit)))
642 mxs_clr(AUART_INTR_TXIEN, s, REG_INTR);
643 else
644 mxs_set(AUART_INTR_TXIEN, s, REG_INTR);
645
646 if (uart_tx_stopped(&s->port))
647 mxs_auart_stop_tx(&s->port);
648}
649
650static void mxs_auart_rx_char(struct mxs_auart_port *s)
651{
652 int flag;
653 u32 stat;
654 u8 c;
655
656 c = mxs_read(s, REG_DATA);
657 stat = mxs_read(s, REG_STAT);
658
659 flag = TTY_NORMAL;
660 s->port.icount.rx++;
661
662 if (stat & AUART_STAT_BERR) {
663 s->port.icount.brk++;
664 if (uart_handle_break(&s->port))
665 goto out;
666 } else if (stat & AUART_STAT_PERR) {
667 s->port.icount.parity++;
668 } else if (stat & AUART_STAT_FERR) {
669 s->port.icount.frame++;
670 }
671
672 /*
673 * Mask off conditions which should be ingored.
674 */
675 stat &= s->port.read_status_mask;
676
677 if (stat & AUART_STAT_BERR) {
678 flag = TTY_BREAK;
679 } else if (stat & AUART_STAT_PERR)
680 flag = TTY_PARITY;
681 else if (stat & AUART_STAT_FERR)
682 flag = TTY_FRAME;
683
684 if (stat & AUART_STAT_OERR)
685 s->port.icount.overrun++;
686
687 if (uart_handle_sysrq_char(&s->port, c))
688 goto out;
689
690 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
691out:
692 mxs_write(stat, s, REG_STAT);
693}
694
695static void mxs_auart_rx_chars(struct mxs_auart_port *s)
696{
697 u32 stat = 0;
698
699 for (;;) {
700 stat = mxs_read(s, REG_STAT);
701 if (stat & AUART_STAT_RXFE)
702 break;
703 mxs_auart_rx_char(s);
704 }
705
706 mxs_write(stat, s, REG_STAT);
707 tty_flip_buffer_push(&s->port.state->port);
708}
709
710static int mxs_auart_request_port(struct uart_port *u)
711{
712 return 0;
713}
714
715static int mxs_auart_verify_port(struct uart_port *u,
716 struct serial_struct *ser)
717{
718 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
719 return -EINVAL;
720 return 0;
721}
722
723static void mxs_auart_config_port(struct uart_port *u, int flags)
724{
725}
726
727static const char *mxs_auart_type(struct uart_port *u)
728{
729 struct mxs_auart_port *s = to_auart_port(u);
730
731 return dev_name(s->dev);
732}
733
734static void mxs_auart_release_port(struct uart_port *u)
735{
736}
737
738static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
739{
740 struct mxs_auart_port *s = to_auart_port(u);
741
742 u32 ctrl = mxs_read(s, REG_CTRL2);
743
744 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
745 if (mctrl & TIOCM_RTS) {
746 if (uart_cts_enabled(u))
747 ctrl |= AUART_CTRL2_RTSEN;
748 else
749 ctrl |= AUART_CTRL2_RTS;
750 }
751
752 mxs_write(ctrl, s, REG_CTRL2);
753
754 mctrl_gpio_set(s->gpios, mctrl);
755}
756
757#define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS)
758static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl)
759{
760 u32 mctrl_diff;
761
762 mctrl_diff = mctrl ^ s->mctrl_prev;
763 s->mctrl_prev = mctrl;
764 if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled &&
765 s->port.state != NULL) {
766 if (mctrl_diff & TIOCM_RI)
767 s->port.icount.rng++;
768 if (mctrl_diff & TIOCM_DSR)
769 s->port.icount.dsr++;
770 if (mctrl_diff & TIOCM_CD)
771 uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD);
772 if (mctrl_diff & TIOCM_CTS)
773 uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS);
774
775 wake_up_interruptible(&s->port.state->port.delta_msr_wait);
776 }
777 return mctrl;
778}
779
780static u32 mxs_auart_get_mctrl(struct uart_port *u)
781{
782 struct mxs_auart_port *s = to_auart_port(u);
783 u32 stat = mxs_read(s, REG_STAT);
784 u32 mctrl = 0;
785
786 if (stat & AUART_STAT_CTS)
787 mctrl |= TIOCM_CTS;
788
789 return mctrl_gpio_get(s->gpios, &mctrl);
790}
791
792/*
793 * Enable modem status interrupts
794 */
795static void mxs_auart_enable_ms(struct uart_port *port)
796{
797 struct mxs_auart_port *s = to_auart_port(port);
798
799 /*
800 * Interrupt should not be enabled twice
801 */
802 if (s->ms_irq_enabled)
803 return;
804
805 s->ms_irq_enabled = true;
806
807 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
808 enable_irq(s->gpio_irq[UART_GPIO_CTS]);
809 /* TODO: enable AUART_INTR_CTSMIEN otherwise */
810
811 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
812 enable_irq(s->gpio_irq[UART_GPIO_DSR]);
813
814 if (s->gpio_irq[UART_GPIO_RI] >= 0)
815 enable_irq(s->gpio_irq[UART_GPIO_RI]);
816
817 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
818 enable_irq(s->gpio_irq[UART_GPIO_DCD]);
819}
820
821/*
822 * Disable modem status interrupts
823 */
824static void mxs_auart_disable_ms(struct uart_port *port)
825{
826 struct mxs_auart_port *s = to_auart_port(port);
827
828 /*
829 * Interrupt should not be disabled twice
830 */
831 if (!s->ms_irq_enabled)
832 return;
833
834 s->ms_irq_enabled = false;
835
836 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
837 disable_irq(s->gpio_irq[UART_GPIO_CTS]);
838 /* TODO: disable AUART_INTR_CTSMIEN otherwise */
839
840 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
841 disable_irq(s->gpio_irq[UART_GPIO_DSR]);
842
843 if (s->gpio_irq[UART_GPIO_RI] >= 0)
844 disable_irq(s->gpio_irq[UART_GPIO_RI]);
845
846 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
847 disable_irq(s->gpio_irq[UART_GPIO_DCD]);
848}
849
850static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
851static void dma_rx_callback(void *arg)
852{
853 struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
854 struct tty_port *port = &s->port.state->port;
855 int count;
856 u32 stat;
857
858 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
859
860 stat = mxs_read(s, REG_STAT);
861 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
862 AUART_STAT_PERR | AUART_STAT_FERR);
863
864 count = stat & AUART_STAT_RXCOUNT_MASK;
865 tty_insert_flip_string(port, s->rx_dma_buf, count);
866
867 mxs_write(stat, s, REG_STAT);
868 tty_flip_buffer_push(port);
869
870 /* start the next DMA for RX. */
871 mxs_auart_dma_prep_rx(s);
872}
873
874static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
875{
876 struct dma_async_tx_descriptor *desc;
877 struct scatterlist *sgl = &s->rx_sgl;
878 struct dma_chan *channel = s->rx_dma_chan;
879 u32 pio[1];
880
881 /* [1] : send PIO */
882 pio[0] = AUART_CTRL0_RXTO_ENABLE
883 | AUART_CTRL0_RXTIMEOUT(0x80)
884 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
885 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
886 1, DMA_TRANS_NONE, 0);
887 if (!desc) {
888 dev_err(s->dev, "step 1 error\n");
889 return -EINVAL;
890 }
891
892 /* [2] : send DMA request */
893 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
894 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
895 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
896 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
897 if (!desc) {
898 dev_err(s->dev, "step 2 error\n");
899 return -1;
900 }
901
902 /* [3] : submit the DMA, but do not issue it. */
903 desc->callback = dma_rx_callback;
904 desc->callback_param = s;
905 dmaengine_submit(desc);
906 dma_async_issue_pending(channel);
907 return 0;
908}
909
910static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
911{
912 if (s->tx_dma_chan) {
913 dma_release_channel(s->tx_dma_chan);
914 s->tx_dma_chan = NULL;
915 }
916 if (s->rx_dma_chan) {
917 dma_release_channel(s->rx_dma_chan);
918 s->rx_dma_chan = NULL;
919 }
920
921 kfree(s->tx_dma_buf);
922 kfree(s->rx_dma_buf);
923 s->tx_dma_buf = NULL;
924 s->rx_dma_buf = NULL;
925}
926
927static void mxs_auart_dma_exit(struct mxs_auart_port *s)
928{
929
930 mxs_clr(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
931 s, REG_CTRL2);
932
933 mxs_auart_dma_exit_channel(s);
934 s->flags &= ~MXS_AUART_DMA_ENABLED;
935 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
936 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
937}
938
939static int mxs_auart_dma_init(struct mxs_auart_port *s)
940{
941 if (auart_dma_enabled(s))
942 return 0;
943
944 /* init for RX */
945 s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx");
946 if (!s->rx_dma_chan)
947 goto err_out;
948 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
949 if (!s->rx_dma_buf)
950 goto err_out;
951
952 /* init for TX */
953 s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx");
954 if (!s->tx_dma_chan)
955 goto err_out;
956 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
957 if (!s->tx_dma_buf)
958 goto err_out;
959
960 /* set the flags */
961 s->flags |= MXS_AUART_DMA_ENABLED;
962 dev_dbg(s->dev, "enabled the DMA support.");
963
964 /* The DMA buffer is now the FIFO the TTY subsystem can use */
965 s->port.fifosize = UART_XMIT_SIZE;
966
967 return 0;
968
969err_out:
970 mxs_auart_dma_exit_channel(s);
971 return -EINVAL;
972
973}
974
975#define RTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \
976 UART_GPIO_RTS))
977#define CTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \
978 UART_GPIO_CTS))
979static void mxs_auart_settermios(struct uart_port *u,
980 struct ktermios *termios,
981 struct ktermios *old)
982{
983 struct mxs_auart_port *s = to_auart_port(u);
984 u32 bm, ctrl, ctrl2, div;
985 unsigned int cflag, baud, baud_min, baud_max;
986
987 cflag = termios->c_cflag;
988
989 ctrl = AUART_LINECTRL_FEN;
990 ctrl2 = mxs_read(s, REG_CTRL2);
991
992 /* byte size */
993 switch (cflag & CSIZE) {
994 case CS5:
995 bm = 0;
996 break;
997 case CS6:
998 bm = 1;
999 break;
1000 case CS7:
1001 bm = 2;
1002 break;
1003 case CS8:
1004 bm = 3;
1005 break;
1006 default:
1007 return;
1008 }
1009
1010 ctrl |= AUART_LINECTRL_WLEN(bm);
1011
1012 /* parity */
1013 if (cflag & PARENB) {
1014 ctrl |= AUART_LINECTRL_PEN;
1015 if ((cflag & PARODD) == 0)
1016 ctrl |= AUART_LINECTRL_EPS;
1017 }
1018
1019 u->read_status_mask = AUART_STAT_OERR;
1020
1021 if (termios->c_iflag & INPCK)
1022 u->read_status_mask |= AUART_STAT_PERR;
1023 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1024 u->read_status_mask |= AUART_STAT_BERR;
1025
1026 /*
1027 * Characters to ignore
1028 */
1029 u->ignore_status_mask = 0;
1030 if (termios->c_iflag & IGNPAR)
1031 u->ignore_status_mask |= AUART_STAT_PERR;
1032 if (termios->c_iflag & IGNBRK) {
1033 u->ignore_status_mask |= AUART_STAT_BERR;
1034 /*
1035 * If we're ignoring parity and break indicators,
1036 * ignore overruns too (for real raw support).
1037 */
1038 if (termios->c_iflag & IGNPAR)
1039 u->ignore_status_mask |= AUART_STAT_OERR;
1040 }
1041
1042 /*
1043 * ignore all characters if CREAD is not set
1044 */
1045 if (cflag & CREAD)
1046 ctrl2 |= AUART_CTRL2_RXE;
1047 else
1048 ctrl2 &= ~AUART_CTRL2_RXE;
1049
1050 /* figure out the stop bits requested */
1051 if (cflag & CSTOPB)
1052 ctrl |= AUART_LINECTRL_STP2;
1053
1054 /* figure out the hardware flow control settings */
1055 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
1056 if (cflag & CRTSCTS) {
1057 /*
1058 * The DMA has a bug(see errata:2836) in mx23.
1059 * So we can not implement the DMA for auart in mx23,
1060 * we can only implement the DMA support for auart
1061 * in mx28.
1062 */
1063 if (is_imx28_auart(s)
1064 && test_bit(MXS_AUART_RTSCTS, &s->flags)) {
1065 if (!mxs_auart_dma_init(s))
1066 /* enable DMA tranfer */
1067 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
1068 | AUART_CTRL2_DMAONERR;
1069 }
1070 /* Even if RTS is GPIO line RTSEN can be enabled because
1071 * the pinctrl configuration decides about RTS pin function */
1072 ctrl2 |= AUART_CTRL2_RTSEN;
1073 if (CTS_AT_AUART())
1074 ctrl2 |= AUART_CTRL2_CTSEN;
1075 }
1076
1077 /* set baud rate */
1078 if (is_asm9260_auart(s)) {
1079 baud = uart_get_baud_rate(u, termios, old,
1080 u->uartclk * 4 / 0x3FFFFF,
1081 u->uartclk / 16);
1082 div = u->uartclk * 4 / baud;
1083 } else {
1084 baud_min = DIV_ROUND_UP(u->uartclk * 32,
1085 AUART_LINECTRL_BAUD_DIV_MAX);
1086 baud_max = u->uartclk * 32 / AUART_LINECTRL_BAUD_DIV_MIN;
1087 baud = uart_get_baud_rate(u, termios, old, baud_min, baud_max);
1088 div = DIV_ROUND_CLOSEST(u->uartclk * 32, baud);
1089 }
1090
1091 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
1092 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
1093 mxs_write(ctrl, s, REG_LINECTRL);
1094
1095 mxs_write(ctrl2, s, REG_CTRL2);
1096
1097 uart_update_timeout(u, termios->c_cflag, baud);
1098
1099 /* prepare for the DMA RX. */
1100 if (auart_dma_enabled(s) &&
1101 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
1102 if (!mxs_auart_dma_prep_rx(s)) {
1103 /* Disable the normal RX interrupt. */
1104 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
1105 s, REG_INTR);
1106 } else {
1107 mxs_auart_dma_exit(s);
1108 dev_err(s->dev, "We can not start up the DMA.\n");
1109 }
1110 }
1111
1112 /* CTS flow-control and modem-status interrupts */
1113 if (UART_ENABLE_MS(u, termios->c_cflag))
1114 mxs_auart_enable_ms(u);
1115 else
1116 mxs_auart_disable_ms(u);
1117}
1118
1119static void mxs_auart_set_ldisc(struct uart_port *port,
1120 struct ktermios *termios)
1121{
1122 if (termios->c_line == N_PPS) {
1123 port->flags |= UPF_HARDPPS_CD;
1124 mxs_auart_enable_ms(port);
1125 } else {
1126 port->flags &= ~UPF_HARDPPS_CD;
1127 }
1128}
1129
1130static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
1131{
1132 u32 istat;
1133 struct mxs_auart_port *s = context;
1134 u32 mctrl_temp = s->mctrl_prev;
1135 u32 stat = mxs_read(s, REG_STAT);
1136
1137 istat = mxs_read(s, REG_INTR);
1138
1139 /* ack irq */
1140 mxs_clr(istat & (AUART_INTR_RTIS | AUART_INTR_TXIS | AUART_INTR_RXIS
1141 | AUART_INTR_CTSMIS), s, REG_INTR);
1142
1143 /*
1144 * Dealing with GPIO interrupt
1145 */
1146 if (irq == s->gpio_irq[UART_GPIO_CTS] ||
1147 irq == s->gpio_irq[UART_GPIO_DCD] ||
1148 irq == s->gpio_irq[UART_GPIO_DSR] ||
1149 irq == s->gpio_irq[UART_GPIO_RI])
1150 mxs_auart_modem_status(s,
1151 mctrl_gpio_get(s->gpios, &mctrl_temp));
1152
1153 if (istat & AUART_INTR_CTSMIS) {
1154 if (CTS_AT_AUART() && s->ms_irq_enabled)
1155 uart_handle_cts_change(&s->port,
1156 stat & AUART_STAT_CTS);
1157 mxs_clr(AUART_INTR_CTSMIS, s, REG_INTR);
1158 istat &= ~AUART_INTR_CTSMIS;
1159 }
1160
1161 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
1162 if (!auart_dma_enabled(s))
1163 mxs_auart_rx_chars(s);
1164 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
1165 }
1166
1167 if (istat & AUART_INTR_TXIS) {
1168 mxs_auart_tx_chars(s);
1169 istat &= ~AUART_INTR_TXIS;
1170 }
1171
1172 return IRQ_HANDLED;
1173}
1174
1175static void mxs_auart_reset_deassert(struct mxs_auart_port *s)
1176{
1177 int i;
1178 unsigned int reg;
1179
1180 mxs_clr(AUART_CTRL0_SFTRST, s, REG_CTRL0);
1181
1182 for (i = 0; i < 10000; i++) {
1183 reg = mxs_read(s, REG_CTRL0);
1184 if (!(reg & AUART_CTRL0_SFTRST))
1185 break;
1186 udelay(3);
1187 }
1188 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1189}
1190
1191static void mxs_auart_reset_assert(struct mxs_auart_port *s)
1192{
1193 int i;
1194 u32 reg;
1195
1196 reg = mxs_read(s, REG_CTRL0);
1197 /* if already in reset state, keep it untouched */
1198 if (reg & AUART_CTRL0_SFTRST)
1199 return;
1200
1201 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1202 mxs_set(AUART_CTRL0_SFTRST, s, REG_CTRL0);
1203
1204 for (i = 0; i < 1000; i++) {
1205 reg = mxs_read(s, REG_CTRL0);
1206 /* reset is finished when the clock is gated */
1207 if (reg & AUART_CTRL0_CLKGATE)
1208 return;
1209 udelay(10);
1210 }
1211
1212 dev_err(s->dev, "Failed to reset the unit.");
1213}
1214
1215static int mxs_auart_startup(struct uart_port *u)
1216{
1217 int ret;
1218 struct mxs_auart_port *s = to_auart_port(u);
1219
1220 ret = clk_prepare_enable(s->clk);
1221 if (ret)
1222 return ret;
1223
1224 if (uart_console(u)) {
1225 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1226 } else {
1227 /* reset the unit to a well known state */
1228 mxs_auart_reset_assert(s);
1229 mxs_auart_reset_deassert(s);
1230 }
1231
1232 mxs_set(AUART_CTRL2_UARTEN, s, REG_CTRL2);
1233
1234 mxs_write(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
1235 s, REG_INTR);
1236
1237 /* Reset FIFO size (it could have changed if DMA was enabled) */
1238 u->fifosize = MXS_AUART_FIFO_SIZE;
1239
1240 /*
1241 * Enable fifo so all four bytes of a DMA word are written to
1242 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
1243 */
1244 mxs_set(AUART_LINECTRL_FEN, s, REG_LINECTRL);
1245
1246 /* get initial status of modem lines */
1247 mctrl_gpio_get(s->gpios, &s->mctrl_prev);
1248
1249 s->ms_irq_enabled = false;
1250 return 0;
1251}
1252
1253static void mxs_auart_shutdown(struct uart_port *u)
1254{
1255 struct mxs_auart_port *s = to_auart_port(u);
1256
1257 mxs_auart_disable_ms(u);
1258
1259 if (auart_dma_enabled(s))
1260 mxs_auart_dma_exit(s);
1261
1262 if (uart_console(u)) {
1263 mxs_clr(AUART_CTRL2_UARTEN, s, REG_CTRL2);
1264
1265 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN |
1266 AUART_INTR_CTSMIEN, s, REG_INTR);
1267 mxs_set(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1268 } else {
1269 mxs_auart_reset_assert(s);
1270 }
1271
1272 clk_disable_unprepare(s->clk);
1273}
1274
1275static unsigned int mxs_auart_tx_empty(struct uart_port *u)
1276{
1277 struct mxs_auart_port *s = to_auart_port(u);
1278
1279 if ((mxs_read(s, REG_STAT) &
1280 (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE)
1281 return TIOCSER_TEMT;
1282
1283 return 0;
1284}
1285
1286static void mxs_auart_start_tx(struct uart_port *u)
1287{
1288 struct mxs_auart_port *s = to_auart_port(u);
1289
1290 /* enable transmitter */
1291 mxs_set(AUART_CTRL2_TXE, s, REG_CTRL2);
1292
1293 mxs_auart_tx_chars(s);
1294}
1295
1296static void mxs_auart_stop_tx(struct uart_port *u)
1297{
1298 struct mxs_auart_port *s = to_auart_port(u);
1299
1300 mxs_clr(AUART_CTRL2_TXE, s, REG_CTRL2);
1301}
1302
1303static void mxs_auart_stop_rx(struct uart_port *u)
1304{
1305 struct mxs_auart_port *s = to_auart_port(u);
1306
1307 mxs_clr(AUART_CTRL2_RXE, s, REG_CTRL2);
1308}
1309
1310static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
1311{
1312 struct mxs_auart_port *s = to_auart_port(u);
1313
1314 if (ctl)
1315 mxs_set(AUART_LINECTRL_BRK, s, REG_LINECTRL);
1316 else
1317 mxs_clr(AUART_LINECTRL_BRK, s, REG_LINECTRL);
1318}
1319
1320static const struct uart_ops mxs_auart_ops = {
1321 .tx_empty = mxs_auart_tx_empty,
1322 .start_tx = mxs_auart_start_tx,
1323 .stop_tx = mxs_auart_stop_tx,
1324 .stop_rx = mxs_auart_stop_rx,
1325 .enable_ms = mxs_auart_enable_ms,
1326 .break_ctl = mxs_auart_break_ctl,
1327 .set_mctrl = mxs_auart_set_mctrl,
1328 .get_mctrl = mxs_auart_get_mctrl,
1329 .startup = mxs_auart_startup,
1330 .shutdown = mxs_auart_shutdown,
1331 .set_termios = mxs_auart_settermios,
1332 .set_ldisc = mxs_auart_set_ldisc,
1333 .type = mxs_auart_type,
1334 .release_port = mxs_auart_release_port,
1335 .request_port = mxs_auart_request_port,
1336 .config_port = mxs_auart_config_port,
1337 .verify_port = mxs_auart_verify_port,
1338};
1339
1340static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
1341
1342#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1343static void mxs_auart_console_putchar(struct uart_port *port, int ch)
1344{
1345 struct mxs_auart_port *s = to_auart_port(port);
1346 unsigned int to = 1000;
1347
1348 while (mxs_read(s, REG_STAT) & AUART_STAT_TXFF) {
1349 if (!to--)
1350 break;
1351 udelay(1);
1352 }
1353
1354 mxs_write(ch, s, REG_DATA);
1355}
1356
1357static void
1358auart_console_write(struct console *co, const char *str, unsigned int count)
1359{
1360 struct mxs_auart_port *s;
1361 struct uart_port *port;
1362 unsigned int old_ctrl0, old_ctrl2;
1363 unsigned int to = 20000;
1364
1365 if (co->index >= MXS_AUART_PORTS || co->index < 0)
1366 return;
1367
1368 s = auart_port[co->index];
1369 port = &s->port;
1370
1371 clk_enable(s->clk);
1372
1373 /* First save the CR then disable the interrupts */
1374 old_ctrl2 = mxs_read(s, REG_CTRL2);
1375 old_ctrl0 = mxs_read(s, REG_CTRL0);
1376
1377 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1378 mxs_set(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, s, REG_CTRL2);
1379
1380 uart_console_write(port, str, count, mxs_auart_console_putchar);
1381
1382 /* Finally, wait for transmitter to become empty ... */
1383 while (mxs_read(s, REG_STAT) & AUART_STAT_BUSY) {
1384 udelay(1);
1385 if (!to--)
1386 break;
1387 }
1388
1389 /*
1390 * ... and restore the TCR if we waited long enough for the transmitter
1391 * to be idle. This might keep the transmitter enabled although it is
1392 * unused, but that is better than to disable it while it is still
1393 * transmitting.
1394 */
1395 if (!(mxs_read(s, REG_STAT) & AUART_STAT_BUSY)) {
1396 mxs_write(old_ctrl0, s, REG_CTRL0);
1397 mxs_write(old_ctrl2, s, REG_CTRL2);
1398 }
1399
1400 clk_disable(s->clk);
1401}
1402
1403static void __init
1404auart_console_get_options(struct mxs_auart_port *s, int *baud,
1405 int *parity, int *bits)
1406{
1407 struct uart_port *port = &s->port;
1408 unsigned int lcr_h, quot;
1409
1410 if (!(mxs_read(s, REG_CTRL2) & AUART_CTRL2_UARTEN))
1411 return;
1412
1413 lcr_h = mxs_read(s, REG_LINECTRL);
1414
1415 *parity = 'n';
1416 if (lcr_h & AUART_LINECTRL_PEN) {
1417 if (lcr_h & AUART_LINECTRL_EPS)
1418 *parity = 'e';
1419 else
1420 *parity = 'o';
1421 }
1422
1423 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
1424 *bits = 7;
1425 else
1426 *bits = 8;
1427
1428 quot = ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVINT_MASK))
1429 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
1430 quot |= ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
1431 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
1432 if (quot == 0)
1433 quot = 1;
1434
1435 *baud = (port->uartclk << 2) / quot;
1436}
1437
1438static int __init
1439auart_console_setup(struct console *co, char *options)
1440{
1441 struct mxs_auart_port *s;
1442 int baud = 9600;
1443 int bits = 8;
1444 int parity = 'n';
1445 int flow = 'n';
1446 int ret;
1447
1448 /*
1449 * Check whether an invalid uart number has been specified, and
1450 * if so, search for the first available port that does have
1451 * console support.
1452 */
1453 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
1454 co->index = 0;
1455 s = auart_port[co->index];
1456 if (!s)
1457 return -ENODEV;
1458
1459 ret = clk_prepare_enable(s->clk);
1460 if (ret)
1461 return ret;
1462
1463 if (options)
1464 uart_parse_options(options, &baud, &parity, &bits, &flow);
1465 else
1466 auart_console_get_options(s, &baud, &parity, &bits);
1467
1468 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
1469
1470 clk_disable_unprepare(s->clk);
1471
1472 return ret;
1473}
1474
1475static struct console auart_console = {
1476 .name = "ttyAPP",
1477 .write = auart_console_write,
1478 .device = uart_console_device,
1479 .setup = auart_console_setup,
1480 .flags = CON_PRINTBUFFER,
1481 .index = -1,
1482 .data = &auart_driver,
1483};
1484#endif
1485
1486static struct uart_driver auart_driver = {
1487 .owner = THIS_MODULE,
1488 .driver_name = "ttyAPP",
1489 .dev_name = "ttyAPP",
1490 .major = 0,
1491 .minor = 0,
1492 .nr = MXS_AUART_PORTS,
1493#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1494 .cons = &auart_console,
1495#endif
1496};
1497
1498static void mxs_init_regs(struct mxs_auart_port *s)
1499{
1500 if (is_asm9260_auart(s))
1501 s->vendor = &vendor_alphascale_asm9260;
1502 else
1503 s->vendor = &vendor_freescale_stmp37xx;
1504}
1505
1506static int mxs_get_clks(struct mxs_auart_port *s,
1507 struct platform_device *pdev)
1508{
1509 int err;
1510
1511 if (!is_asm9260_auart(s)) {
1512 s->clk = devm_clk_get(&pdev->dev, NULL);
1513 return PTR_ERR_OR_ZERO(s->clk);
1514 }
1515
1516 s->clk = devm_clk_get(s->dev, "mod");
1517 if (IS_ERR(s->clk)) {
1518 dev_err(s->dev, "Failed to get \"mod\" clk\n");
1519 return PTR_ERR(s->clk);
1520 }
1521
1522 s->clk_ahb = devm_clk_get(s->dev, "ahb");
1523 if (IS_ERR(s->clk_ahb)) {
1524 dev_err(s->dev, "Failed to get \"ahb\" clk\n");
1525 return PTR_ERR(s->clk_ahb);
1526 }
1527
1528 err = clk_prepare_enable(s->clk_ahb);
1529 if (err) {
1530 dev_err(s->dev, "Failed to enable ahb_clk!\n");
1531 return err;
1532 }
1533
1534 err = clk_set_rate(s->clk, clk_get_rate(s->clk_ahb));
1535 if (err) {
1536 dev_err(s->dev, "Failed to set rate!\n");
1537 goto disable_clk_ahb;
1538 }
1539
1540 err = clk_prepare_enable(s->clk);
1541 if (err) {
1542 dev_err(s->dev, "Failed to enable clk!\n");
1543 goto disable_clk_ahb;
1544 }
1545
1546 return 0;
1547
1548disable_clk_ahb:
1549 clk_disable_unprepare(s->clk_ahb);
1550 return err;
1551}
1552
1553/*
1554 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it
1555 * could successfully get all information from dt or a negative errno.
1556 */
1557static int serial_mxs_probe_dt(struct mxs_auart_port *s,
1558 struct platform_device *pdev)
1559{
1560 struct device_node *np = pdev->dev.of_node;
1561 int ret;
1562
1563 if (!np)
1564 /* no device tree device */
1565 return 1;
1566
1567 ret = of_alias_get_id(np, "serial");
1568 if (ret < 0) {
1569 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
1570 return ret;
1571 }
1572 s->port.line = ret;
1573
1574 if (of_get_property(np, "uart-has-rtscts", NULL) ||
1575 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
1576 set_bit(MXS_AUART_RTSCTS, &s->flags);
1577
1578 return 0;
1579}
1580
1581static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev)
1582{
1583 enum mctrl_gpio_idx i;
1584 struct gpio_desc *gpiod;
1585
1586 s->gpios = mctrl_gpio_init_noauto(dev, 0);
1587 if (IS_ERR(s->gpios))
1588 return PTR_ERR(s->gpios);
1589
1590 /* Block (enabled before) DMA option if RTS or CTS is GPIO line */
1591 if (!RTS_AT_AUART() || !CTS_AT_AUART()) {
1592 if (test_bit(MXS_AUART_RTSCTS, &s->flags))
1593 dev_warn(dev,
1594 "DMA and flow control via gpio may cause some problems. DMA disabled!\n");
1595 clear_bit(MXS_AUART_RTSCTS, &s->flags);
1596 }
1597
1598 for (i = 0; i < UART_GPIO_MAX; i++) {
1599 gpiod = mctrl_gpio_to_gpiod(s->gpios, i);
1600 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN))
1601 s->gpio_irq[i] = gpiod_to_irq(gpiod);
1602 else
1603 s->gpio_irq[i] = -EINVAL;
1604 }
1605
1606 return 0;
1607}
1608
1609static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s)
1610{
1611 enum mctrl_gpio_idx i;
1612
1613 for (i = 0; i < UART_GPIO_MAX; i++)
1614 if (s->gpio_irq[i] >= 0)
1615 free_irq(s->gpio_irq[i], s);
1616}
1617
1618static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s)
1619{
1620 int *irq = s->gpio_irq;
1621 enum mctrl_gpio_idx i;
1622 int err = 0;
1623
1624 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1625 if (irq[i] < 0)
1626 continue;
1627
1628 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1629 err = request_irq(irq[i], mxs_auart_irq_handle,
1630 IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s);
1631 if (err)
1632 dev_err(s->dev, "%s - Can't get %d irq\n",
1633 __func__, irq[i]);
1634 }
1635
1636 /*
1637 * If something went wrong, rollback.
1638 */
1639 while (err && (--i >= 0))
1640 if (irq[i] >= 0)
1641 free_irq(irq[i], s);
1642
1643 return err;
1644}
1645
1646static int mxs_auart_probe(struct platform_device *pdev)
1647{
1648 const struct of_device_id *of_id =
1649 of_match_device(mxs_auart_dt_ids, &pdev->dev);
1650 struct mxs_auart_port *s;
1651 u32 version;
1652 int ret, irq;
1653 struct resource *r;
1654
1655 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
1656 if (!s)
1657 return -ENOMEM;
1658
1659 s->port.dev = &pdev->dev;
1660 s->dev = &pdev->dev;
1661
1662 ret = serial_mxs_probe_dt(s, pdev);
1663 if (ret > 0)
1664 s->port.line = pdev->id < 0 ? 0 : pdev->id;
1665 else if (ret < 0)
1666 return ret;
1667
1668 if (of_id) {
1669 pdev->id_entry = of_id->data;
1670 s->devtype = pdev->id_entry->driver_data;
1671 }
1672
1673 ret = mxs_get_clks(s, pdev);
1674 if (ret)
1675 return ret;
1676
1677 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1678 if (!r)
1679 return -ENXIO;
1680
1681 s->port.mapbase = r->start;
1682 s->port.membase = ioremap(r->start, resource_size(r));
1683 s->port.ops = &mxs_auart_ops;
1684 s->port.iotype = UPIO_MEM;
1685 s->port.fifosize = MXS_AUART_FIFO_SIZE;
1686 s->port.uartclk = clk_get_rate(s->clk);
1687 s->port.type = PORT_IMX;
1688
1689 mxs_init_regs(s);
1690
1691 s->mctrl_prev = 0;
1692
1693 irq = platform_get_irq(pdev, 0);
1694 if (irq < 0)
1695 return irq;
1696
1697 s->port.irq = irq;
1698 ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0,
1699 dev_name(&pdev->dev), s);
1700 if (ret)
1701 return ret;
1702
1703 platform_set_drvdata(pdev, s);
1704
1705 ret = mxs_auart_init_gpios(s, &pdev->dev);
1706 if (ret) {
1707 dev_err(&pdev->dev, "Failed to initialize GPIOs.\n");
1708 return ret;
1709 }
1710
1711 /*
1712 * Get the GPIO lines IRQ
1713 */
1714 ret = mxs_auart_request_gpio_irq(s);
1715 if (ret)
1716 return ret;
1717
1718 auart_port[s->port.line] = s;
1719
1720 mxs_auart_reset_deassert(s);
1721
1722 ret = uart_add_one_port(&auart_driver, &s->port);
1723 if (ret)
1724 goto out_free_gpio_irq;
1725
1726 /* ASM9260 don't have version reg */
1727 if (is_asm9260_auart(s)) {
1728 dev_info(&pdev->dev, "Found APPUART ASM9260\n");
1729 } else {
1730 version = mxs_read(s, REG_VERSION);
1731 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
1732 (version >> 24) & 0xff,
1733 (version >> 16) & 0xff, version & 0xffff);
1734 }
1735
1736 return 0;
1737
1738out_free_gpio_irq:
1739 mxs_auart_free_gpio_irq(s);
1740 auart_port[pdev->id] = NULL;
1741 return ret;
1742}
1743
1744static int mxs_auart_remove(struct platform_device *pdev)
1745{
1746 struct mxs_auart_port *s = platform_get_drvdata(pdev);
1747
1748 uart_remove_one_port(&auart_driver, &s->port);
1749 auart_port[pdev->id] = NULL;
1750 mxs_auart_free_gpio_irq(s);
1751
1752 return 0;
1753}
1754
1755static struct platform_driver mxs_auart_driver = {
1756 .probe = mxs_auart_probe,
1757 .remove = mxs_auart_remove,
1758 .driver = {
1759 .name = "mxs-auart",
1760 .of_match_table = mxs_auart_dt_ids,
1761 },
1762};
1763
1764static int __init mxs_auart_init(void)
1765{
1766 int r;
1767
1768 r = uart_register_driver(&auart_driver);
1769 if (r)
1770 goto out;
1771
1772 r = platform_driver_register(&mxs_auart_driver);
1773 if (r)
1774 goto out_err;
1775
1776 return 0;
1777out_err:
1778 uart_unregister_driver(&auart_driver);
1779out:
1780 return r;
1781}
1782
1783static void __exit mxs_auart_exit(void)
1784{
1785 platform_driver_unregister(&mxs_auart_driver);
1786 uart_unregister_driver(&auart_driver);
1787}
1788
1789module_init(mxs_auart_init);
1790module_exit(mxs_auart_exit);
1791MODULE_LICENSE("GPL");
1792MODULE_DESCRIPTION("Freescale MXS application uart driver");
1793MODULE_ALIAS("platform:mxs-auart");