1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 *  Support for Versatile FPGA-based IRQ controllers
  4 */
  5#include <linux/bitops.h>
  6#include <linux/irq.h>
  7#include <linux/io.h>
  8#include <linux/irqchip.h>
  9#include <linux/irqchip/versatile-fpga.h>
 10#include <linux/irqdomain.h>
 11#include <linux/module.h>
 12#include <linux/of.h>
 13#include <linux/of_address.h>
 14#include <linux/of_irq.h>
 15
 16#include <asm/exception.h>
 17#include <asm/mach/irq.h>
 18
 19#define IRQ_STATUS		0x00
 20#define IRQ_RAW_STATUS		0x04
 21#define IRQ_ENABLE_SET		0x08
 22#define IRQ_ENABLE_CLEAR	0x0c
 23#define INT_SOFT_SET		0x10
 24#define INT_SOFT_CLEAR		0x14
 25#define FIQ_STATUS		0x20
 26#define FIQ_RAW_STATUS		0x24
 27#define FIQ_ENABLE		0x28
 28#define FIQ_ENABLE_SET		0x28
 29#define FIQ_ENABLE_CLEAR	0x2C
 30
 31#define PIC_ENABLES             0x20	/* set interrupt pass through bits */
 32
 33/**
 34 * struct fpga_irq_data - irq data container for the FPGA IRQ controller
 35 * @base: memory offset in virtual memory
 36 * @chip: chip container for this instance
 37 * @domain: IRQ domain for this instance
 38 * @valid: mask for valid IRQs on this controller
 39 * @used_irqs: number of active IRQs on this controller
 40 */
 41struct fpga_irq_data {
 42	void __iomem *base;
 43	struct irq_chip chip;
 44	u32 valid;
 45	struct irq_domain *domain;
 46	u8 used_irqs;
 47};
 48
 49/* we cannot allocate memory when the controllers are initially registered */
 50static struct fpga_irq_data fpga_irq_devices[CONFIG_VERSATILE_FPGA_IRQ_NR];
 51static int fpga_irq_id;
 52
 53static void fpga_irq_mask(struct irq_data *d)
 54{
 55	struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
 56	u32 mask = 1 << d->hwirq;
 57
 58	writel(mask, f->base + IRQ_ENABLE_CLEAR);
 59}
 60
 61static void fpga_irq_unmask(struct irq_data *d)
 62{
 63	struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
 64	u32 mask = 1 << d->hwirq;
 65
 66	writel(mask, f->base + IRQ_ENABLE_SET);
 67}
 68
 69static void fpga_irq_handle(struct irq_desc *desc)
 70{
 71	struct fpga_irq_data *f = irq_desc_get_handler_data(desc);
 72	u32 status = readl(f->base + IRQ_STATUS);
 73
 74	if (status == 0) {
 75		do_bad_IRQ(desc);
 76		return;
 77	}
 78
 79	do {
 80		unsigned int irq = ffs(status) - 1;
 81
 82		status &= ~(1 << irq);
 83		generic_handle_irq(irq_find_mapping(f->domain, irq));
 84	} while (status);
 85}
 86
 87/*
 88 * Handle each interrupt in a single FPGA IRQ controller.  Returns non-zero
 89 * if we've handled at least one interrupt.  This does a single read of the
 90 * status register and handles all interrupts in order from LSB first.
 91 */
 92static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs)
 93{
 94	int handled = 0;
 95	int irq;
 96	u32 status;
 97
 98	while ((status  = readl(f->base + IRQ_STATUS))) {
 99		irq = ffs(status) - 1;
100		handle_domain_irq(f->domain, irq, regs);
101		handled = 1;
102	}
103
104	return handled;
105}
106
107/*
108 * Keep iterating over all registered FPGA IRQ controllers until there are
109 * no pending interrupts.
110 */
111asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs)
112{
113	int i, handled;
114
115	do {
116		for (i = 0, handled = 0; i < fpga_irq_id; ++i)
117			handled |= handle_one_fpga(&fpga_irq_devices[i], regs);
118	} while (handled);
119}
120
121static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
122		irq_hw_number_t hwirq)
123{
124	struct fpga_irq_data *f = d->host_data;
125
126	/* Skip invalid IRQs, only register handlers for the real ones */
127	if (!(f->valid & BIT(hwirq)))
128		return -EPERM;
129	irq_set_chip_data(irq, f);
130	irq_set_chip_and_handler(irq, &f->chip,
131				handle_level_irq);
132	irq_set_probe(irq);
133	return 0;
134}
135
136static const struct irq_domain_ops fpga_irqdomain_ops = {
137	.map = fpga_irqdomain_map,
138	.xlate = irq_domain_xlate_onetwocell,
139};
140
141void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
142			  int parent_irq, u32 valid, struct device_node *node)
143{
144	struct fpga_irq_data *f;
145	int i;
146
147	if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
148		pr_err("%s: too few FPGA IRQ controllers, increase CONFIG_VERSATILE_FPGA_IRQ_NR\n", __func__);
149		return;
150	}
151	f = &fpga_irq_devices[fpga_irq_id];
152	f->base = base;
153	f->chip.name = name;
154	f->chip.irq_ack = fpga_irq_mask;
155	f->chip.irq_mask = fpga_irq_mask;
156	f->chip.irq_unmask = fpga_irq_unmask;
157	f->valid = valid;
158
159	if (parent_irq != -1) {
160		irq_set_chained_handler_and_data(parent_irq, fpga_irq_handle,
161						 f);
162	}
163
164	/* This will also allocate irq descriptors */
165	f->domain = irq_domain_add_simple(node, fls(valid), irq_start,
166					  &fpga_irqdomain_ops, f);
167
168	/* This will allocate all valid descriptors in the linear case */
169	for (i = 0; i < fls(valid); i++)
170		if (valid & BIT(i)) {
171			if (!irq_start)
172				irq_create_mapping(f->domain, i);
173			f->used_irqs++;
174		}
175
176	pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs",
177		fpga_irq_id, name, base, f->used_irqs);
178	if (parent_irq != -1)
179		pr_cont(", parent IRQ: %d\n", parent_irq);
180	else
181		pr_cont("\n");
182
183	fpga_irq_id++;
184}
185
186#ifdef CONFIG_OF
187int __init fpga_irq_of_init(struct device_node *node,
188			    struct device_node *parent)
189{
190	void __iomem *base;
191	u32 clear_mask;
192	u32 valid_mask;
193	int parent_irq;
194
195	if (WARN_ON(!node))
196		return -ENODEV;
197
198	base = of_iomap(node, 0);
199	WARN(!base, "unable to map fpga irq registers\n");
200
201	if (of_property_read_u32(node, "clear-mask", &clear_mask))
202		clear_mask = 0;
203
204	if (of_property_read_u32(node, "valid-mask", &valid_mask))
205		valid_mask = 0;
206
207	/* Some chips are cascaded from a parent IRQ */
208	parent_irq = irq_of_parse_and_map(node, 0);
209	if (!parent_irq) {
210		set_handle_irq(fpga_handle_irq);
211		parent_irq = -1;
212	}
213
214	fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node);
215
216	writel(clear_mask, base + IRQ_ENABLE_CLEAR);
217	writel(clear_mask, base + FIQ_ENABLE_CLEAR);
218
219	/*
220	 * On Versatile AB/PB, some secondary interrupts have a direct
221	 * pass-thru to the primary controller for IRQs 20 and 22-31 which need
222	 * to be enabled. See section 3.10 of the Versatile AB user guide.
223	 */
224	if (of_device_is_compatible(node, "arm,versatile-sic"))
225		writel(0xffd00000, base + PIC_ENABLES);
226
227	return 0;
228}
229IRQCHIP_DECLARE(arm_fpga, "arm,versatile-fpga-irq", fpga_irq_of_init);
230IRQCHIP_DECLARE(arm_fpga_sic, "arm,versatile-sic", fpga_irq_of_init);
231IRQCHIP_DECLARE(ox810se_rps, "oxsemi,ox810se-rps-irq", fpga_irq_of_init);
232#endif