Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * This file is part of STM32 ADC driver
4 *
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
7 *
8 * Inspired from: fsl-imx25-tsadc
9 *
10 */
11
12#include <linux/clk.h>
13#include <linux/interrupt.h>
14#include <linux/irqchip/chained_irq.h>
15#include <linux/irqdesc.h>
16#include <linux/irqdomain.h>
17#include <linux/module.h>
18#include <linux/of_device.h>
19#include <linux/regulator/consumer.h>
20#include <linux/slab.h>
21
22#include "stm32-adc-core.h"
23
24/* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
25#define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
26#define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04)
27
28/* STM32F4_ADC_CSR - bit fields */
29#define STM32F4_EOC3 BIT(17)
30#define STM32F4_EOC2 BIT(9)
31#define STM32F4_EOC1 BIT(1)
32
33/* STM32F4_ADC_CCR - bit fields */
34#define STM32F4_ADC_ADCPRE_SHIFT 16
35#define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16)
36
37/* STM32 F4 maximum analog clock rate (from datasheet) */
38#define STM32F4_ADC_MAX_CLK_RATE 36000000
39
40/* STM32H7 - common registers for all ADC instances */
41#define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
42#define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08)
43
44/* STM32H7_ADC_CSR - bit fields */
45#define STM32H7_EOC_SLV BIT(18)
46#define STM32H7_EOC_MST BIT(2)
47
48/* STM32H7_ADC_CCR - bit fields */
49#define STM32H7_PRESC_SHIFT 18
50#define STM32H7_PRESC_MASK GENMASK(21, 18)
51#define STM32H7_CKMODE_SHIFT 16
52#define STM32H7_CKMODE_MASK GENMASK(17, 16)
53
54/* STM32 H7 maximum analog clock rate (from datasheet) */
55#define STM32H7_ADC_MAX_CLK_RATE 36000000
56
57/**
58 * stm32_adc_common_regs - stm32 common registers, compatible dependent data
59 * @csr: common status register offset
60 * @eoc1: adc1 end of conversion flag in @csr
61 * @eoc2: adc2 end of conversion flag in @csr
62 * @eoc3: adc3 end of conversion flag in @csr
63 */
64struct stm32_adc_common_regs {
65 u32 csr;
66 u32 eoc1_msk;
67 u32 eoc2_msk;
68 u32 eoc3_msk;
69};
70
71struct stm32_adc_priv;
72
73/**
74 * stm32_adc_priv_cfg - stm32 core compatible configuration data
75 * @regs: common registers for all instances
76 * @clk_sel: clock selection routine
77 */
78struct stm32_adc_priv_cfg {
79 const struct stm32_adc_common_regs *regs;
80 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
81};
82
83/**
84 * struct stm32_adc_priv - stm32 ADC core private data
85 * @irq: irq for ADC block
86 * @domain: irq domain reference
87 * @aclk: clock reference for the analog circuitry
88 * @bclk: bus clock common for all ADCs, depends on part used
89 * @vref: regulator reference
90 * @cfg: compatible configuration data
91 * @common: common data for all ADC instances
92 */
93struct stm32_adc_priv {
94 int irq;
95 struct irq_domain *domain;
96 struct clk *aclk;
97 struct clk *bclk;
98 struct regulator *vref;
99 const struct stm32_adc_priv_cfg *cfg;
100 struct stm32_adc_common common;
101};
102
103static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
104{
105 return container_of(com, struct stm32_adc_priv, common);
106}
107
108/* STM32F4 ADC internal common clock prescaler division ratios */
109static int stm32f4_pclk_div[] = {2, 4, 6, 8};
110
111/**
112 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
113 * @priv: stm32 ADC core private data
114 * Select clock prescaler used for analog conversions, before using ADC.
115 */
116static int stm32f4_adc_clk_sel(struct platform_device *pdev,
117 struct stm32_adc_priv *priv)
118{
119 unsigned long rate;
120 u32 val;
121 int i;
122
123 /* stm32f4 has one clk input for analog (mandatory), enforce it here */
124 if (!priv->aclk) {
125 dev_err(&pdev->dev, "No 'adc' clock found\n");
126 return -ENOENT;
127 }
128
129 rate = clk_get_rate(priv->aclk);
130 if (!rate) {
131 dev_err(&pdev->dev, "Invalid clock rate: 0\n");
132 return -EINVAL;
133 }
134
135 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
136 if ((rate / stm32f4_pclk_div[i]) <= STM32F4_ADC_MAX_CLK_RATE)
137 break;
138 }
139 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
140 dev_err(&pdev->dev, "adc clk selection failed\n");
141 return -EINVAL;
142 }
143
144 priv->common.rate = rate / stm32f4_pclk_div[i];
145 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
146 val &= ~STM32F4_ADC_ADCPRE_MASK;
147 val |= i << STM32F4_ADC_ADCPRE_SHIFT;
148 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
149
150 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
151 priv->common.rate / 1000);
152
153 return 0;
154}
155
156/**
157 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
158 * @ckmode: ADC clock mode, Async or sync with prescaler.
159 * @presc: prescaler bitfield for async clock mode
160 * @div: prescaler division ratio
161 */
162struct stm32h7_adc_ck_spec {
163 u32 ckmode;
164 u32 presc;
165 int div;
166};
167
168static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
169 /* 00: CK_ADC[1..3]: Asynchronous clock modes */
170 { 0, 0, 1 },
171 { 0, 1, 2 },
172 { 0, 2, 4 },
173 { 0, 3, 6 },
174 { 0, 4, 8 },
175 { 0, 5, 10 },
176 { 0, 6, 12 },
177 { 0, 7, 16 },
178 { 0, 8, 32 },
179 { 0, 9, 64 },
180 { 0, 10, 128 },
181 { 0, 11, 256 },
182 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
183 { 1, 0, 1 },
184 { 2, 0, 2 },
185 { 3, 0, 4 },
186};
187
188static int stm32h7_adc_clk_sel(struct platform_device *pdev,
189 struct stm32_adc_priv *priv)
190{
191 u32 ckmode, presc, val;
192 unsigned long rate;
193 int i, div;
194
195 /* stm32h7 bus clock is common for all ADC instances (mandatory) */
196 if (!priv->bclk) {
197 dev_err(&pdev->dev, "No 'bus' clock found\n");
198 return -ENOENT;
199 }
200
201 /*
202 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
203 * So, choice is to have bus clock mandatory and adc clock optional.
204 * If optional 'adc' clock has been found, then try to use it first.
205 */
206 if (priv->aclk) {
207 /*
208 * Asynchronous clock modes (e.g. ckmode == 0)
209 * From spec: PLL output musn't exceed max rate
210 */
211 rate = clk_get_rate(priv->aclk);
212 if (!rate) {
213 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
214 return -EINVAL;
215 }
216
217 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
218 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
219 presc = stm32h7_adc_ckmodes_spec[i].presc;
220 div = stm32h7_adc_ckmodes_spec[i].div;
221
222 if (ckmode)
223 continue;
224
225 if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
226 goto out;
227 }
228 }
229
230 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
231 rate = clk_get_rate(priv->bclk);
232 if (!rate) {
233 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
234 return -EINVAL;
235 }
236
237 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
238 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
239 presc = stm32h7_adc_ckmodes_spec[i].presc;
240 div = stm32h7_adc_ckmodes_spec[i].div;
241
242 if (!ckmode)
243 continue;
244
245 if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
246 goto out;
247 }
248
249 dev_err(&pdev->dev, "adc clk selection failed\n");
250 return -EINVAL;
251
252out:
253 /* rate used later by each ADC instance to control BOOST mode */
254 priv->common.rate = rate / div;
255
256 /* Set common clock mode and prescaler */
257 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
258 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
259 val |= ckmode << STM32H7_CKMODE_SHIFT;
260 val |= presc << STM32H7_PRESC_SHIFT;
261 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
262
263 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
264 ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
265
266 return 0;
267}
268
269/* STM32F4 common registers definitions */
270static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
271 .csr = STM32F4_ADC_CSR,
272 .eoc1_msk = STM32F4_EOC1,
273 .eoc2_msk = STM32F4_EOC2,
274 .eoc3_msk = STM32F4_EOC3,
275};
276
277/* STM32H7 common registers definitions */
278static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
279 .csr = STM32H7_ADC_CSR,
280 .eoc1_msk = STM32H7_EOC_MST,
281 .eoc2_msk = STM32H7_EOC_SLV,
282};
283
284/* ADC common interrupt for all instances */
285static void stm32_adc_irq_handler(struct irq_desc *desc)
286{
287 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
288 struct irq_chip *chip = irq_desc_get_chip(desc);
289 u32 status;
290
291 chained_irq_enter(chip, desc);
292 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
293
294 if (status & priv->cfg->regs->eoc1_msk)
295 generic_handle_irq(irq_find_mapping(priv->domain, 0));
296
297 if (status & priv->cfg->regs->eoc2_msk)
298 generic_handle_irq(irq_find_mapping(priv->domain, 1));
299
300 if (status & priv->cfg->regs->eoc3_msk)
301 generic_handle_irq(irq_find_mapping(priv->domain, 2));
302
303 chained_irq_exit(chip, desc);
304};
305
306static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
307 irq_hw_number_t hwirq)
308{
309 irq_set_chip_data(irq, d->host_data);
310 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
311
312 return 0;
313}
314
315static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
316{
317 irq_set_chip_and_handler(irq, NULL, NULL);
318 irq_set_chip_data(irq, NULL);
319}
320
321static const struct irq_domain_ops stm32_adc_domain_ops = {
322 .map = stm32_adc_domain_map,
323 .unmap = stm32_adc_domain_unmap,
324 .xlate = irq_domain_xlate_onecell,
325};
326
327static int stm32_adc_irq_probe(struct platform_device *pdev,
328 struct stm32_adc_priv *priv)
329{
330 struct device_node *np = pdev->dev.of_node;
331
332 priv->irq = platform_get_irq(pdev, 0);
333 if (priv->irq < 0) {
334 dev_err(&pdev->dev, "failed to get irq\n");
335 return priv->irq;
336 }
337
338 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
339 &stm32_adc_domain_ops,
340 priv);
341 if (!priv->domain) {
342 dev_err(&pdev->dev, "Failed to add irq domain\n");
343 return -ENOMEM;
344 }
345
346 irq_set_chained_handler(priv->irq, stm32_adc_irq_handler);
347 irq_set_handler_data(priv->irq, priv);
348
349 return 0;
350}
351
352static void stm32_adc_irq_remove(struct platform_device *pdev,
353 struct stm32_adc_priv *priv)
354{
355 int hwirq;
356
357 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
358 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
359 irq_domain_remove(priv->domain);
360 irq_set_chained_handler(priv->irq, NULL);
361}
362
363static int stm32_adc_probe(struct platform_device *pdev)
364{
365 struct stm32_adc_priv *priv;
366 struct device *dev = &pdev->dev;
367 struct device_node *np = pdev->dev.of_node;
368 struct resource *res;
369 int ret;
370
371 if (!pdev->dev.of_node)
372 return -ENODEV;
373
374 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
375 if (!priv)
376 return -ENOMEM;
377
378 priv->cfg = (const struct stm32_adc_priv_cfg *)
379 of_match_device(dev->driver->of_match_table, dev)->data;
380
381 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
382 priv->common.base = devm_ioremap_resource(&pdev->dev, res);
383 if (IS_ERR(priv->common.base))
384 return PTR_ERR(priv->common.base);
385 priv->common.phys_base = res->start;
386
387 priv->vref = devm_regulator_get(&pdev->dev, "vref");
388 if (IS_ERR(priv->vref)) {
389 ret = PTR_ERR(priv->vref);
390 dev_err(&pdev->dev, "vref get failed, %d\n", ret);
391 return ret;
392 }
393
394 ret = regulator_enable(priv->vref);
395 if (ret < 0) {
396 dev_err(&pdev->dev, "vref enable failed\n");
397 return ret;
398 }
399
400 ret = regulator_get_voltage(priv->vref);
401 if (ret < 0) {
402 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
403 goto err_regulator_disable;
404 }
405 priv->common.vref_mv = ret / 1000;
406 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
407
408 priv->aclk = devm_clk_get(&pdev->dev, "adc");
409 if (IS_ERR(priv->aclk)) {
410 ret = PTR_ERR(priv->aclk);
411 if (ret == -ENOENT) {
412 priv->aclk = NULL;
413 } else {
414 dev_err(&pdev->dev, "Can't get 'adc' clock\n");
415 goto err_regulator_disable;
416 }
417 }
418
419 if (priv->aclk) {
420 ret = clk_prepare_enable(priv->aclk);
421 if (ret < 0) {
422 dev_err(&pdev->dev, "adc clk enable failed\n");
423 goto err_regulator_disable;
424 }
425 }
426
427 priv->bclk = devm_clk_get(&pdev->dev, "bus");
428 if (IS_ERR(priv->bclk)) {
429 ret = PTR_ERR(priv->bclk);
430 if (ret == -ENOENT) {
431 priv->bclk = NULL;
432 } else {
433 dev_err(&pdev->dev, "Can't get 'bus' clock\n");
434 goto err_aclk_disable;
435 }
436 }
437
438 if (priv->bclk) {
439 ret = clk_prepare_enable(priv->bclk);
440 if (ret < 0) {
441 dev_err(&pdev->dev, "adc clk enable failed\n");
442 goto err_aclk_disable;
443 }
444 }
445
446 ret = priv->cfg->clk_sel(pdev, priv);
447 if (ret < 0)
448 goto err_bclk_disable;
449
450 ret = stm32_adc_irq_probe(pdev, priv);
451 if (ret < 0)
452 goto err_bclk_disable;
453
454 platform_set_drvdata(pdev, &priv->common);
455
456 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
457 if (ret < 0) {
458 dev_err(&pdev->dev, "failed to populate DT children\n");
459 goto err_irq_remove;
460 }
461
462 return 0;
463
464err_irq_remove:
465 stm32_adc_irq_remove(pdev, priv);
466
467err_bclk_disable:
468 if (priv->bclk)
469 clk_disable_unprepare(priv->bclk);
470
471err_aclk_disable:
472 if (priv->aclk)
473 clk_disable_unprepare(priv->aclk);
474
475err_regulator_disable:
476 regulator_disable(priv->vref);
477
478 return ret;
479}
480
481static int stm32_adc_remove(struct platform_device *pdev)
482{
483 struct stm32_adc_common *common = platform_get_drvdata(pdev);
484 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
485
486 of_platform_depopulate(&pdev->dev);
487 stm32_adc_irq_remove(pdev, priv);
488 if (priv->bclk)
489 clk_disable_unprepare(priv->bclk);
490 if (priv->aclk)
491 clk_disable_unprepare(priv->aclk);
492 regulator_disable(priv->vref);
493
494 return 0;
495}
496
497static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
498 .regs = &stm32f4_adc_common_regs,
499 .clk_sel = stm32f4_adc_clk_sel,
500};
501
502static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
503 .regs = &stm32h7_adc_common_regs,
504 .clk_sel = stm32h7_adc_clk_sel,
505};
506
507static const struct of_device_id stm32_adc_of_match[] = {
508 {
509 .compatible = "st,stm32f4-adc-core",
510 .data = (void *)&stm32f4_adc_priv_cfg
511 }, {
512 .compatible = "st,stm32h7-adc-core",
513 .data = (void *)&stm32h7_adc_priv_cfg
514 }, {
515 },
516};
517MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
518
519static struct platform_driver stm32_adc_driver = {
520 .probe = stm32_adc_probe,
521 .remove = stm32_adc_remove,
522 .driver = {
523 .name = "stm32-adc-core",
524 .of_match_table = stm32_adc_of_match,
525 },
526};
527module_platform_driver(stm32_adc_driver);
528
529MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
530MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
531MODULE_LICENSE("GPL v2");
532MODULE_ALIAS("platform:stm32-adc-core");