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1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
30#include <acpi/button.h>
31#include <linux/dmi.h>
32#include <linux/i2c.h>
33#include <linux/slab.h>
34#include "drmP.h"
35#include "drm.h"
36#include "drm_crtc.h"
37#include "drm_edid.h"
38#include "intel_drv.h"
39#include "i915_drm.h"
40#include "i915_drv.h"
41#include <linux/acpi.h>
42
43/* Private structure for the integrated LVDS support */
44struct intel_lvds {
45 struct intel_encoder base;
46
47 struct edid *edid;
48
49 int fitting_mode;
50 u32 pfit_control;
51 u32 pfit_pgm_ratios;
52 bool pfit_dirty;
53
54 struct drm_display_mode *fixed_mode;
55};
56
57static struct intel_lvds *to_intel_lvds(struct drm_encoder *encoder)
58{
59 return container_of(encoder, struct intel_lvds, base.base);
60}
61
62static struct intel_lvds *intel_attached_lvds(struct drm_connector *connector)
63{
64 return container_of(intel_attached_encoder(connector),
65 struct intel_lvds, base);
66}
67
68/**
69 * Sets the power state for the panel.
70 */
71static void intel_lvds_enable(struct intel_lvds *intel_lvds)
72{
73 struct drm_device *dev = intel_lvds->base.base.dev;
74 struct drm_i915_private *dev_priv = dev->dev_private;
75 u32 ctl_reg, lvds_reg, stat_reg;
76
77 if (HAS_PCH_SPLIT(dev)) {
78 ctl_reg = PCH_PP_CONTROL;
79 lvds_reg = PCH_LVDS;
80 stat_reg = PCH_PP_STATUS;
81 } else {
82 ctl_reg = PP_CONTROL;
83 lvds_reg = LVDS;
84 stat_reg = PP_STATUS;
85 }
86
87 I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN);
88
89 if (intel_lvds->pfit_dirty) {
90 /*
91 * Enable automatic panel scaling so that non-native modes
92 * fill the screen. The panel fitter should only be
93 * adjusted whilst the pipe is disabled, according to
94 * register description and PRM.
95 */
96 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
97 intel_lvds->pfit_control,
98 intel_lvds->pfit_pgm_ratios);
99
100 I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios);
101 I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control);
102 intel_lvds->pfit_dirty = false;
103 }
104
105 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
106 POSTING_READ(lvds_reg);
107 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
108 DRM_ERROR("timed out waiting for panel to power on\n");
109
110 intel_panel_enable_backlight(dev);
111}
112
113static void intel_lvds_disable(struct intel_lvds *intel_lvds)
114{
115 struct drm_device *dev = intel_lvds->base.base.dev;
116 struct drm_i915_private *dev_priv = dev->dev_private;
117 u32 ctl_reg, lvds_reg, stat_reg;
118
119 if (HAS_PCH_SPLIT(dev)) {
120 ctl_reg = PCH_PP_CONTROL;
121 lvds_reg = PCH_LVDS;
122 stat_reg = PCH_PP_STATUS;
123 } else {
124 ctl_reg = PP_CONTROL;
125 lvds_reg = LVDS;
126 stat_reg = PP_STATUS;
127 }
128
129 intel_panel_disable_backlight(dev);
130
131 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
132 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
133 DRM_ERROR("timed out waiting for panel to power off\n");
134
135 if (intel_lvds->pfit_control) {
136 I915_WRITE(PFIT_CONTROL, 0);
137 intel_lvds->pfit_dirty = true;
138 }
139
140 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN);
141 POSTING_READ(lvds_reg);
142}
143
144static void intel_lvds_dpms(struct drm_encoder *encoder, int mode)
145{
146 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
147
148 if (mode == DRM_MODE_DPMS_ON)
149 intel_lvds_enable(intel_lvds);
150 else
151 intel_lvds_disable(intel_lvds);
152
153 /* XXX: We never power down the LVDS pairs. */
154}
155
156static int intel_lvds_mode_valid(struct drm_connector *connector,
157 struct drm_display_mode *mode)
158{
159 struct intel_lvds *intel_lvds = intel_attached_lvds(connector);
160 struct drm_display_mode *fixed_mode = intel_lvds->fixed_mode;
161
162 if (mode->hdisplay > fixed_mode->hdisplay)
163 return MODE_PANEL;
164 if (mode->vdisplay > fixed_mode->vdisplay)
165 return MODE_PANEL;
166
167 return MODE_OK;
168}
169
170static void
171centre_horizontally(struct drm_display_mode *mode,
172 int width)
173{
174 u32 border, sync_pos, blank_width, sync_width;
175
176 /* keep the hsync and hblank widths constant */
177 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
178 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
179 sync_pos = (blank_width - sync_width + 1) / 2;
180
181 border = (mode->hdisplay - width + 1) / 2;
182 border += border & 1; /* make the border even */
183
184 mode->crtc_hdisplay = width;
185 mode->crtc_hblank_start = width + border;
186 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
187
188 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
189 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
190}
191
192static void
193centre_vertically(struct drm_display_mode *mode,
194 int height)
195{
196 u32 border, sync_pos, blank_width, sync_width;
197
198 /* keep the vsync and vblank widths constant */
199 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
200 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
201 sync_pos = (blank_width - sync_width + 1) / 2;
202
203 border = (mode->vdisplay - height + 1) / 2;
204
205 mode->crtc_vdisplay = height;
206 mode->crtc_vblank_start = height + border;
207 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
208
209 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
210 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
211}
212
213static inline u32 panel_fitter_scaling(u32 source, u32 target)
214{
215 /*
216 * Floating point operation is not supported. So the FACTOR
217 * is defined, which can avoid the floating point computation
218 * when calculating the panel ratio.
219 */
220#define ACCURACY 12
221#define FACTOR (1 << ACCURACY)
222 u32 ratio = source * FACTOR / target;
223 return (FACTOR * ratio + FACTOR/2) / FACTOR;
224}
225
226static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
227 struct drm_display_mode *mode,
228 struct drm_display_mode *adjusted_mode)
229{
230 struct drm_device *dev = encoder->dev;
231 struct drm_i915_private *dev_priv = dev->dev_private;
232 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
233 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
234 struct drm_encoder *tmp_encoder;
235 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
236 int pipe;
237
238 /* Should never happen!! */
239 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
240 DRM_ERROR("Can't support LVDS on pipe A\n");
241 return false;
242 }
243
244 /* Should never happen!! */
245 list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, head) {
246 if (tmp_encoder != encoder && tmp_encoder->crtc == encoder->crtc) {
247 DRM_ERROR("Can't enable LVDS and another "
248 "encoder on the same pipe\n");
249 return false;
250 }
251 }
252
253 /*
254 * We have timings from the BIOS for the panel, put them in
255 * to the adjusted mode. The CRTC will be set up for this mode,
256 * with the panel scaling set up to source from the H/VDisplay
257 * of the original mode.
258 */
259 intel_fixed_panel_mode(intel_lvds->fixed_mode, adjusted_mode);
260
261 if (HAS_PCH_SPLIT(dev)) {
262 intel_pch_panel_fitting(dev, intel_lvds->fitting_mode,
263 mode, adjusted_mode);
264 return true;
265 }
266
267 /* Native modes don't need fitting */
268 if (adjusted_mode->hdisplay == mode->hdisplay &&
269 adjusted_mode->vdisplay == mode->vdisplay)
270 goto out;
271
272 /* 965+ wants fuzzy fitting */
273 if (INTEL_INFO(dev)->gen >= 4)
274 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
275 PFIT_FILTER_FUZZY);
276
277 /*
278 * Enable automatic panel scaling for non-native modes so that they fill
279 * the screen. Should be enabled before the pipe is enabled, according
280 * to register description and PRM.
281 * Change the value here to see the borders for debugging
282 */
283 for_each_pipe(pipe)
284 I915_WRITE(BCLRPAT(pipe), 0);
285
286 switch (intel_lvds->fitting_mode) {
287 case DRM_MODE_SCALE_CENTER:
288 /*
289 * For centered modes, we have to calculate border widths &
290 * heights and modify the values programmed into the CRTC.
291 */
292 centre_horizontally(adjusted_mode, mode->hdisplay);
293 centre_vertically(adjusted_mode, mode->vdisplay);
294 border = LVDS_BORDER_ENABLE;
295 break;
296
297 case DRM_MODE_SCALE_ASPECT:
298 /* Scale but preserve the aspect ratio */
299 if (INTEL_INFO(dev)->gen >= 4) {
300 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
301 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
302
303 /* 965+ is easy, it does everything in hw */
304 if (scaled_width > scaled_height)
305 pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR;
306 else if (scaled_width < scaled_height)
307 pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER;
308 else if (adjusted_mode->hdisplay != mode->hdisplay)
309 pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
310 } else {
311 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
312 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
313 /*
314 * For earlier chips we have to calculate the scaling
315 * ratio by hand and program it into the
316 * PFIT_PGM_RATIO register
317 */
318 if (scaled_width > scaled_height) { /* pillar */
319 centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay);
320
321 border = LVDS_BORDER_ENABLE;
322 if (mode->vdisplay != adjusted_mode->vdisplay) {
323 u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
324 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
325 bits << PFIT_VERT_SCALE_SHIFT);
326 pfit_control |= (PFIT_ENABLE |
327 VERT_INTERP_BILINEAR |
328 HORIZ_INTERP_BILINEAR);
329 }
330 } else if (scaled_width < scaled_height) { /* letter */
331 centre_vertically(adjusted_mode, scaled_width / mode->hdisplay);
332
333 border = LVDS_BORDER_ENABLE;
334 if (mode->hdisplay != adjusted_mode->hdisplay) {
335 u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
336 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
337 bits << PFIT_VERT_SCALE_SHIFT);
338 pfit_control |= (PFIT_ENABLE |
339 VERT_INTERP_BILINEAR |
340 HORIZ_INTERP_BILINEAR);
341 }
342 } else
343 /* Aspects match, Let hw scale both directions */
344 pfit_control |= (PFIT_ENABLE |
345 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
346 VERT_INTERP_BILINEAR |
347 HORIZ_INTERP_BILINEAR);
348 }
349 break;
350
351 case DRM_MODE_SCALE_FULLSCREEN:
352 /*
353 * Full scaling, even if it changes the aspect ratio.
354 * Fortunately this is all done for us in hw.
355 */
356 if (mode->vdisplay != adjusted_mode->vdisplay ||
357 mode->hdisplay != adjusted_mode->hdisplay) {
358 pfit_control |= PFIT_ENABLE;
359 if (INTEL_INFO(dev)->gen >= 4)
360 pfit_control |= PFIT_SCALING_AUTO;
361 else
362 pfit_control |= (VERT_AUTO_SCALE |
363 VERT_INTERP_BILINEAR |
364 HORIZ_AUTO_SCALE |
365 HORIZ_INTERP_BILINEAR);
366 }
367 break;
368
369 default:
370 break;
371 }
372
373out:
374 /* If not enabling scaling, be consistent and always use 0. */
375 if ((pfit_control & PFIT_ENABLE) == 0) {
376 pfit_control = 0;
377 pfit_pgm_ratios = 0;
378 }
379
380 /* Make sure pre-965 set dither correctly */
381 if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither)
382 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
383
384 if (pfit_control != intel_lvds->pfit_control ||
385 pfit_pgm_ratios != intel_lvds->pfit_pgm_ratios) {
386 intel_lvds->pfit_control = pfit_control;
387 intel_lvds->pfit_pgm_ratios = pfit_pgm_ratios;
388 intel_lvds->pfit_dirty = true;
389 }
390 dev_priv->lvds_border_bits = border;
391
392 /*
393 * XXX: It would be nice to support lower refresh rates on the
394 * panels to reduce power consumption, and perhaps match the
395 * user's requested refresh rate.
396 */
397
398 return true;
399}
400
401static void intel_lvds_prepare(struct drm_encoder *encoder)
402{
403 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
404
405 /*
406 * Prior to Ironlake, we must disable the pipe if we want to adjust
407 * the panel fitter. However at all other times we can just reset
408 * the registers regardless.
409 */
410 if (!HAS_PCH_SPLIT(encoder->dev) && intel_lvds->pfit_dirty)
411 intel_lvds_disable(intel_lvds);
412}
413
414static void intel_lvds_commit(struct drm_encoder *encoder)
415{
416 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
417
418 /* Always do a full power on as we do not know what state
419 * we were left in.
420 */
421 intel_lvds_enable(intel_lvds);
422}
423
424static void intel_lvds_mode_set(struct drm_encoder *encoder,
425 struct drm_display_mode *mode,
426 struct drm_display_mode *adjusted_mode)
427{
428 /*
429 * The LVDS pin pair will already have been turned on in the
430 * intel_crtc_mode_set since it has a large impact on the DPLL
431 * settings.
432 */
433}
434
435/**
436 * Detect the LVDS connection.
437 *
438 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
439 * connected and closed means disconnected. We also send hotplug events as
440 * needed, using lid status notification from the input layer.
441 */
442static enum drm_connector_status
443intel_lvds_detect(struct drm_connector *connector, bool force)
444{
445 struct drm_device *dev = connector->dev;
446 enum drm_connector_status status;
447
448 status = intel_panel_detect(dev);
449 if (status != connector_status_unknown)
450 return status;
451
452 return connector_status_connected;
453}
454
455/**
456 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
457 */
458static int intel_lvds_get_modes(struct drm_connector *connector)
459{
460 struct intel_lvds *intel_lvds = intel_attached_lvds(connector);
461 struct drm_device *dev = connector->dev;
462 struct drm_display_mode *mode;
463
464 if (intel_lvds->edid)
465 return drm_add_edid_modes(connector, intel_lvds->edid);
466
467 mode = drm_mode_duplicate(dev, intel_lvds->fixed_mode);
468 if (mode == NULL)
469 return 0;
470
471 drm_mode_probed_add(connector, mode);
472 return 1;
473}
474
475static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
476{
477 DRM_DEBUG_KMS("Skipping forced modeset for %s\n", id->ident);
478 return 1;
479}
480
481/* The GPU hangs up on these systems if modeset is performed on LID open */
482static const struct dmi_system_id intel_no_modeset_on_lid[] = {
483 {
484 .callback = intel_no_modeset_on_lid_dmi_callback,
485 .ident = "Toshiba Tecra A11",
486 .matches = {
487 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
488 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
489 },
490 },
491
492 { } /* terminating entry */
493};
494
495/*
496 * Lid events. Note the use of 'modeset_on_lid':
497 * - we set it on lid close, and reset it on open
498 * - we use it as a "only once" bit (ie we ignore
499 * duplicate events where it was already properly
500 * set/reset)
501 * - the suspend/resume paths will also set it to
502 * zero, since they restore the mode ("lid open").
503 */
504static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
505 void *unused)
506{
507 struct drm_i915_private *dev_priv =
508 container_of(nb, struct drm_i915_private, lid_notifier);
509 struct drm_device *dev = dev_priv->dev;
510 struct drm_connector *connector = dev_priv->int_lvds_connector;
511
512 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
513 return NOTIFY_OK;
514
515 /*
516 * check and update the status of LVDS connector after receiving
517 * the LID nofication event.
518 */
519 if (connector)
520 connector->status = connector->funcs->detect(connector,
521 false);
522
523 /* Don't force modeset on machines where it causes a GPU lockup */
524 if (dmi_check_system(intel_no_modeset_on_lid))
525 return NOTIFY_OK;
526 if (!acpi_lid_open()) {
527 dev_priv->modeset_on_lid = 1;
528 return NOTIFY_OK;
529 }
530
531 if (!dev_priv->modeset_on_lid)
532 return NOTIFY_OK;
533
534 dev_priv->modeset_on_lid = 0;
535
536 mutex_lock(&dev->mode_config.mutex);
537 drm_helper_resume_force_mode(dev);
538 mutex_unlock(&dev->mode_config.mutex);
539
540 return NOTIFY_OK;
541}
542
543/**
544 * intel_lvds_destroy - unregister and free LVDS structures
545 * @connector: connector to free
546 *
547 * Unregister the DDC bus for this connector then free the driver private
548 * structure.
549 */
550static void intel_lvds_destroy(struct drm_connector *connector)
551{
552 struct drm_device *dev = connector->dev;
553 struct drm_i915_private *dev_priv = dev->dev_private;
554
555 intel_panel_destroy_backlight(dev);
556
557 if (dev_priv->lid_notifier.notifier_call)
558 acpi_lid_notifier_unregister(&dev_priv->lid_notifier);
559 drm_sysfs_connector_remove(connector);
560 drm_connector_cleanup(connector);
561 kfree(connector);
562}
563
564static int intel_lvds_set_property(struct drm_connector *connector,
565 struct drm_property *property,
566 uint64_t value)
567{
568 struct intel_lvds *intel_lvds = intel_attached_lvds(connector);
569 struct drm_device *dev = connector->dev;
570
571 if (property == dev->mode_config.scaling_mode_property) {
572 struct drm_crtc *crtc = intel_lvds->base.base.crtc;
573
574 if (value == DRM_MODE_SCALE_NONE) {
575 DRM_DEBUG_KMS("no scaling not supported\n");
576 return -EINVAL;
577 }
578
579 if (intel_lvds->fitting_mode == value) {
580 /* the LVDS scaling property is not changed */
581 return 0;
582 }
583 intel_lvds->fitting_mode = value;
584 if (crtc && crtc->enabled) {
585 /*
586 * If the CRTC is enabled, the display will be changed
587 * according to the new panel fitting mode.
588 */
589 drm_crtc_helper_set_mode(crtc, &crtc->mode,
590 crtc->x, crtc->y, crtc->fb);
591 }
592 }
593
594 return 0;
595}
596
597static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
598 .dpms = intel_lvds_dpms,
599 .mode_fixup = intel_lvds_mode_fixup,
600 .prepare = intel_lvds_prepare,
601 .mode_set = intel_lvds_mode_set,
602 .commit = intel_lvds_commit,
603};
604
605static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
606 .get_modes = intel_lvds_get_modes,
607 .mode_valid = intel_lvds_mode_valid,
608 .best_encoder = intel_best_encoder,
609};
610
611static const struct drm_connector_funcs intel_lvds_connector_funcs = {
612 .dpms = drm_helper_connector_dpms,
613 .detect = intel_lvds_detect,
614 .fill_modes = drm_helper_probe_single_connector_modes,
615 .set_property = intel_lvds_set_property,
616 .destroy = intel_lvds_destroy,
617};
618
619static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
620 .destroy = intel_encoder_destroy,
621};
622
623static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
624{
625 DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident);
626 return 1;
627}
628
629/* These systems claim to have LVDS, but really don't */
630static const struct dmi_system_id intel_no_lvds[] = {
631 {
632 .callback = intel_no_lvds_dmi_callback,
633 .ident = "Apple Mac Mini (Core series)",
634 .matches = {
635 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
636 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
637 },
638 },
639 {
640 .callback = intel_no_lvds_dmi_callback,
641 .ident = "Apple Mac Mini (Core 2 series)",
642 .matches = {
643 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
644 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
645 },
646 },
647 {
648 .callback = intel_no_lvds_dmi_callback,
649 .ident = "MSI IM-945GSE-A",
650 .matches = {
651 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
652 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
653 },
654 },
655 {
656 .callback = intel_no_lvds_dmi_callback,
657 .ident = "Dell Studio Hybrid",
658 .matches = {
659 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
660 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
661 },
662 },
663 {
664 .callback = intel_no_lvds_dmi_callback,
665 .ident = "Dell OptiPlex FX170",
666 .matches = {
667 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
668 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
669 },
670 },
671 {
672 .callback = intel_no_lvds_dmi_callback,
673 .ident = "AOpen Mini PC",
674 .matches = {
675 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
676 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
677 },
678 },
679 {
680 .callback = intel_no_lvds_dmi_callback,
681 .ident = "AOpen Mini PC MP915",
682 .matches = {
683 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
684 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
685 },
686 },
687 {
688 .callback = intel_no_lvds_dmi_callback,
689 .ident = "AOpen i915GMm-HFS",
690 .matches = {
691 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
692 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
693 },
694 },
695 {
696 .callback = intel_no_lvds_dmi_callback,
697 .ident = "Aopen i945GTt-VFA",
698 .matches = {
699 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
700 },
701 },
702 {
703 .callback = intel_no_lvds_dmi_callback,
704 .ident = "Clientron U800",
705 .matches = {
706 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
707 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
708 },
709 },
710 {
711 .callback = intel_no_lvds_dmi_callback,
712 .ident = "Asus EeeBox PC EB1007",
713 .matches = {
714 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
715 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
716 },
717 },
718
719 { } /* terminating entry */
720};
721
722/**
723 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
724 * @dev: drm device
725 * @connector: LVDS connector
726 *
727 * Find the reduced downclock for LVDS in EDID.
728 */
729static void intel_find_lvds_downclock(struct drm_device *dev,
730 struct drm_display_mode *fixed_mode,
731 struct drm_connector *connector)
732{
733 struct drm_i915_private *dev_priv = dev->dev_private;
734 struct drm_display_mode *scan;
735 int temp_downclock;
736
737 temp_downclock = fixed_mode->clock;
738 list_for_each_entry(scan, &connector->probed_modes, head) {
739 /*
740 * If one mode has the same resolution with the fixed_panel
741 * mode while they have the different refresh rate, it means
742 * that the reduced downclock is found for the LVDS. In such
743 * case we can set the different FPx0/1 to dynamically select
744 * between low and high frequency.
745 */
746 if (scan->hdisplay == fixed_mode->hdisplay &&
747 scan->hsync_start == fixed_mode->hsync_start &&
748 scan->hsync_end == fixed_mode->hsync_end &&
749 scan->htotal == fixed_mode->htotal &&
750 scan->vdisplay == fixed_mode->vdisplay &&
751 scan->vsync_start == fixed_mode->vsync_start &&
752 scan->vsync_end == fixed_mode->vsync_end &&
753 scan->vtotal == fixed_mode->vtotal) {
754 if (scan->clock < temp_downclock) {
755 /*
756 * The downclock is already found. But we
757 * expect to find the lower downclock.
758 */
759 temp_downclock = scan->clock;
760 }
761 }
762 }
763 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
764 /* We found the downclock for LVDS. */
765 dev_priv->lvds_downclock_avail = 1;
766 dev_priv->lvds_downclock = temp_downclock;
767 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
768 "Normal clock %dKhz, downclock %dKhz\n",
769 fixed_mode->clock, temp_downclock);
770 }
771}
772
773/*
774 * Enumerate the child dev array parsed from VBT to check whether
775 * the LVDS is present.
776 * If it is present, return 1.
777 * If it is not present, return false.
778 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
779 */
780static bool lvds_is_present_in_vbt(struct drm_device *dev,
781 u8 *i2c_pin)
782{
783 struct drm_i915_private *dev_priv = dev->dev_private;
784 int i;
785
786 if (!dev_priv->child_dev_num)
787 return true;
788
789 for (i = 0; i < dev_priv->child_dev_num; i++) {
790 struct child_device_config *child = dev_priv->child_dev + i;
791
792 /* If the device type is not LFP, continue.
793 * We have to check both the new identifiers as well as the
794 * old for compatibility with some BIOSes.
795 */
796 if (child->device_type != DEVICE_TYPE_INT_LFP &&
797 child->device_type != DEVICE_TYPE_LFP)
798 continue;
799
800 if (child->i2c_pin)
801 *i2c_pin = child->i2c_pin;
802
803 /* However, we cannot trust the BIOS writers to populate
804 * the VBT correctly. Since LVDS requires additional
805 * information from AIM blocks, a non-zero addin offset is
806 * a good indicator that the LVDS is actually present.
807 */
808 if (child->addin_offset)
809 return true;
810
811 /* But even then some BIOS writers perform some black magic
812 * and instantiate the device without reference to any
813 * additional data. Trust that if the VBT was written into
814 * the OpRegion then they have validated the LVDS's existence.
815 */
816 if (dev_priv->opregion.vbt)
817 return true;
818 }
819
820 return false;
821}
822
823/**
824 * intel_lvds_init - setup LVDS connectors on this device
825 * @dev: drm device
826 *
827 * Create the connector, register the LVDS DDC bus, and try to figure out what
828 * modes we can display on the LVDS panel (if present).
829 */
830bool intel_lvds_init(struct drm_device *dev)
831{
832 struct drm_i915_private *dev_priv = dev->dev_private;
833 struct intel_lvds *intel_lvds;
834 struct intel_encoder *intel_encoder;
835 struct intel_connector *intel_connector;
836 struct drm_connector *connector;
837 struct drm_encoder *encoder;
838 struct drm_display_mode *scan; /* *modes, *bios_mode; */
839 struct drm_crtc *crtc;
840 u32 lvds;
841 int pipe;
842 u8 pin;
843
844 /* Skip init on machines we know falsely report LVDS */
845 if (dmi_check_system(intel_no_lvds))
846 return false;
847
848 pin = GMBUS_PORT_PANEL;
849 if (!lvds_is_present_in_vbt(dev, &pin)) {
850 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
851 return false;
852 }
853
854 if (HAS_PCH_SPLIT(dev)) {
855 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
856 return false;
857 if (dev_priv->edp.support) {
858 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
859 return false;
860 }
861 }
862
863 intel_lvds = kzalloc(sizeof(struct intel_lvds), GFP_KERNEL);
864 if (!intel_lvds) {
865 return false;
866 }
867
868 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
869 if (!intel_connector) {
870 kfree(intel_lvds);
871 return false;
872 }
873
874 if (!HAS_PCH_SPLIT(dev)) {
875 intel_lvds->pfit_control = I915_READ(PFIT_CONTROL);
876 }
877
878 intel_encoder = &intel_lvds->base;
879 encoder = &intel_encoder->base;
880 connector = &intel_connector->base;
881 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
882 DRM_MODE_CONNECTOR_LVDS);
883
884 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
885 DRM_MODE_ENCODER_LVDS);
886
887 intel_connector_attach_encoder(intel_connector, intel_encoder);
888 intel_encoder->type = INTEL_OUTPUT_LVDS;
889
890 intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT);
891 intel_encoder->crtc_mask = (1 << 1);
892 if (INTEL_INFO(dev)->gen >= 5)
893 intel_encoder->crtc_mask |= (1 << 0);
894 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
895 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
896 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
897 connector->interlace_allowed = false;
898 connector->doublescan_allowed = false;
899
900 /* create the scaling mode property */
901 drm_mode_create_scaling_mode_property(dev);
902 /*
903 * the initial panel fitting mode will be FULL_SCREEN.
904 */
905
906 drm_connector_attach_property(&intel_connector->base,
907 dev->mode_config.scaling_mode_property,
908 DRM_MODE_SCALE_ASPECT);
909 intel_lvds->fitting_mode = DRM_MODE_SCALE_ASPECT;
910 /*
911 * LVDS discovery:
912 * 1) check for EDID on DDC
913 * 2) check for VBT data
914 * 3) check to see if LVDS is already on
915 * if none of the above, no panel
916 * 4) make sure lid is open
917 * if closed, act like it's not there for now
918 */
919
920 /*
921 * Attempt to get the fixed panel mode from DDC. Assume that the
922 * preferred mode is the right one.
923 */
924 intel_lvds->edid = drm_get_edid(connector,
925 &dev_priv->gmbus[pin].adapter);
926 if (intel_lvds->edid) {
927 if (drm_add_edid_modes(connector,
928 intel_lvds->edid)) {
929 drm_mode_connector_update_edid_property(connector,
930 intel_lvds->edid);
931 } else {
932 kfree(intel_lvds->edid);
933 intel_lvds->edid = NULL;
934 }
935 }
936 if (!intel_lvds->edid) {
937 /* Didn't get an EDID, so
938 * Set wide sync ranges so we get all modes
939 * handed to valid_mode for checking
940 */
941 connector->display_info.min_vfreq = 0;
942 connector->display_info.max_vfreq = 200;
943 connector->display_info.min_hfreq = 0;
944 connector->display_info.max_hfreq = 200;
945 }
946
947 list_for_each_entry(scan, &connector->probed_modes, head) {
948 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
949 intel_lvds->fixed_mode =
950 drm_mode_duplicate(dev, scan);
951 intel_find_lvds_downclock(dev,
952 intel_lvds->fixed_mode,
953 connector);
954 goto out;
955 }
956 }
957
958 /* Failed to get EDID, what about VBT? */
959 if (dev_priv->lfp_lvds_vbt_mode) {
960 intel_lvds->fixed_mode =
961 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
962 if (intel_lvds->fixed_mode) {
963 intel_lvds->fixed_mode->type |=
964 DRM_MODE_TYPE_PREFERRED;
965 goto out;
966 }
967 }
968
969 /*
970 * If we didn't get EDID, try checking if the panel is already turned
971 * on. If so, assume that whatever is currently programmed is the
972 * correct mode.
973 */
974
975 /* Ironlake: FIXME if still fail, not try pipe mode now */
976 if (HAS_PCH_SPLIT(dev))
977 goto failed;
978
979 lvds = I915_READ(LVDS);
980 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
981 crtc = intel_get_crtc_for_pipe(dev, pipe);
982
983 if (crtc && (lvds & LVDS_PORT_EN)) {
984 intel_lvds->fixed_mode = intel_crtc_mode_get(dev, crtc);
985 if (intel_lvds->fixed_mode) {
986 intel_lvds->fixed_mode->type |=
987 DRM_MODE_TYPE_PREFERRED;
988 goto out;
989 }
990 }
991
992 /* If we still don't have a mode after all that, give up. */
993 if (!intel_lvds->fixed_mode)
994 goto failed;
995
996out:
997 if (HAS_PCH_SPLIT(dev)) {
998 u32 pwm;
999
1000 pipe = (I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) ? 1 : 0;
1001
1002 /* make sure PWM is enabled and locked to the LVDS pipe */
1003 pwm = I915_READ(BLC_PWM_CPU_CTL2);
1004 if (pipe == 0 && (pwm & PWM_PIPE_B))
1005 I915_WRITE(BLC_PWM_CPU_CTL2, pwm & ~PWM_ENABLE);
1006 if (pipe)
1007 pwm |= PWM_PIPE_B;
1008 else
1009 pwm &= ~PWM_PIPE_B;
1010 I915_WRITE(BLC_PWM_CPU_CTL2, pwm | PWM_ENABLE);
1011
1012 pwm = I915_READ(BLC_PWM_PCH_CTL1);
1013 pwm |= PWM_PCH_ENABLE;
1014 I915_WRITE(BLC_PWM_PCH_CTL1, pwm);
1015 /*
1016 * Unlock registers and just
1017 * leave them unlocked
1018 */
1019 I915_WRITE(PCH_PP_CONTROL,
1020 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1021 } else {
1022 /*
1023 * Unlock registers and just
1024 * leave them unlocked
1025 */
1026 I915_WRITE(PP_CONTROL,
1027 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
1028 }
1029 dev_priv->lid_notifier.notifier_call = intel_lid_notify;
1030 if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) {
1031 DRM_DEBUG_KMS("lid notifier registration failed\n");
1032 dev_priv->lid_notifier.notifier_call = NULL;
1033 }
1034 /* keep the LVDS connector */
1035 dev_priv->int_lvds_connector = connector;
1036 drm_sysfs_connector_add(connector);
1037
1038 intel_panel_setup_backlight(dev);
1039
1040 return true;
1041
1042failed:
1043 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1044 drm_connector_cleanup(connector);
1045 drm_encoder_cleanup(encoder);
1046 kfree(intel_lvds);
1047 kfree(intel_connector);
1048 return false;
1049}
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
30#include <acpi/button.h>
31#include <linux/dmi.h>
32#include <linux/i2c.h>
33#include <linux/slab.h>
34#include <linux/vga_switcheroo.h>
35#include <drm/drmP.h>
36#include <drm/drm_atomic_helper.h>
37#include <drm/drm_crtc.h>
38#include <drm/drm_edid.h>
39#include "intel_drv.h"
40#include <drm/i915_drm.h>
41#include "i915_drv.h"
42#include <linux/acpi.h>
43
44/* Private structure for the integrated LVDS support */
45struct intel_lvds_connector {
46 struct intel_connector base;
47
48 struct notifier_block lid_notifier;
49};
50
51struct intel_lvds_pps {
52 /* 100us units */
53 int t1_t2;
54 int t3;
55 int t4;
56 int t5;
57 int tx;
58
59 int divider;
60
61 int port;
62 bool powerdown_on_reset;
63};
64
65struct intel_lvds_encoder {
66 struct intel_encoder base;
67
68 bool is_dual_link;
69 i915_reg_t reg;
70 u32 a3_power;
71
72 struct intel_lvds_pps init_pps;
73 u32 init_lvds_val;
74
75 struct intel_lvds_connector *attached_connector;
76};
77
78static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
79{
80 return container_of(encoder, struct intel_lvds_encoder, base.base);
81}
82
83static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
84{
85 return container_of(connector, struct intel_lvds_connector, base.base);
86}
87
88static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
89 enum pipe *pipe)
90{
91 struct drm_device *dev = encoder->base.dev;
92 struct drm_i915_private *dev_priv = to_i915(dev);
93 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
94 u32 tmp;
95 bool ret;
96
97 if (!intel_display_power_get_if_enabled(dev_priv,
98 encoder->power_domain))
99 return false;
100
101 ret = false;
102
103 tmp = I915_READ(lvds_encoder->reg);
104
105 if (!(tmp & LVDS_PORT_EN))
106 goto out;
107
108 if (HAS_PCH_CPT(dev_priv))
109 *pipe = PORT_TO_PIPE_CPT(tmp);
110 else
111 *pipe = PORT_TO_PIPE(tmp);
112
113 ret = true;
114
115out:
116 intel_display_power_put(dev_priv, encoder->power_domain);
117
118 return ret;
119}
120
121static void intel_lvds_get_config(struct intel_encoder *encoder,
122 struct intel_crtc_state *pipe_config)
123{
124 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
125 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
126 u32 tmp, flags = 0;
127
128 pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS);
129
130 tmp = I915_READ(lvds_encoder->reg);
131 if (tmp & LVDS_HSYNC_POLARITY)
132 flags |= DRM_MODE_FLAG_NHSYNC;
133 else
134 flags |= DRM_MODE_FLAG_PHSYNC;
135 if (tmp & LVDS_VSYNC_POLARITY)
136 flags |= DRM_MODE_FLAG_NVSYNC;
137 else
138 flags |= DRM_MODE_FLAG_PVSYNC;
139
140 pipe_config->base.adjusted_mode.flags |= flags;
141
142 if (INTEL_GEN(dev_priv) < 5)
143 pipe_config->gmch_pfit.lvds_border_bits =
144 tmp & LVDS_BORDER_ENABLE;
145
146 /* gen2/3 store dither state in pfit control, needs to match */
147 if (INTEL_GEN(dev_priv) < 4) {
148 tmp = I915_READ(PFIT_CONTROL);
149
150 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
151 }
152
153 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
154}
155
156static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
157 struct intel_lvds_pps *pps)
158{
159 u32 val;
160
161 pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
162
163 val = I915_READ(PP_ON_DELAYS(0));
164 pps->port = (val & PANEL_PORT_SELECT_MASK) >>
165 PANEL_PORT_SELECT_SHIFT;
166 pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >>
167 PANEL_POWER_UP_DELAY_SHIFT;
168 pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >>
169 PANEL_LIGHT_ON_DELAY_SHIFT;
170
171 val = I915_READ(PP_OFF_DELAYS(0));
172 pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >>
173 PANEL_POWER_DOWN_DELAY_SHIFT;
174 pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >>
175 PANEL_LIGHT_OFF_DELAY_SHIFT;
176
177 val = I915_READ(PP_DIVISOR(0));
178 pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >>
179 PP_REFERENCE_DIVIDER_SHIFT;
180 val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >>
181 PANEL_POWER_CYCLE_DELAY_SHIFT;
182 /*
183 * Remove the BSpec specified +1 (100ms) offset that accounts for a
184 * too short power-cycle delay due to the asynchronous programming of
185 * the register.
186 */
187 if (val)
188 val--;
189 /* Convert from 100ms to 100us units */
190 pps->t4 = val * 1000;
191
192 if (INTEL_GEN(dev_priv) <= 4 &&
193 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
194 DRM_DEBUG_KMS("Panel power timings uninitialized, "
195 "setting defaults\n");
196 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
197 pps->t1_t2 = 40 * 10;
198 pps->t5 = 200 * 10;
199 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
200 pps->t3 = 35 * 10;
201 pps->tx = 200 * 10;
202 }
203
204 DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
205 "divider %d port %d powerdown_on_reset %d\n",
206 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
207 pps->divider, pps->port, pps->powerdown_on_reset);
208}
209
210static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
211 struct intel_lvds_pps *pps)
212{
213 u32 val;
214
215 val = I915_READ(PP_CONTROL(0));
216 WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
217 if (pps->powerdown_on_reset)
218 val |= PANEL_POWER_RESET;
219 I915_WRITE(PP_CONTROL(0), val);
220
221 I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) |
222 (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) |
223 (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT));
224 I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) |
225 (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT));
226
227 val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT;
228 val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) <<
229 PANEL_POWER_CYCLE_DELAY_SHIFT;
230 I915_WRITE(PP_DIVISOR(0), val);
231}
232
233static void intel_pre_enable_lvds(struct intel_encoder *encoder,
234 const struct intel_crtc_state *pipe_config,
235 const struct drm_connector_state *conn_state)
236{
237 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
238 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
239 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
240 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
241 int pipe = crtc->pipe;
242 u32 temp;
243
244 if (HAS_PCH_SPLIT(dev_priv)) {
245 assert_fdi_rx_pll_disabled(dev_priv, pipe);
246 assert_shared_dpll_disabled(dev_priv,
247 pipe_config->shared_dpll);
248 } else {
249 assert_pll_disabled(dev_priv, pipe);
250 }
251
252 intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps);
253
254 temp = lvds_encoder->init_lvds_val;
255 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
256
257 if (HAS_PCH_CPT(dev_priv)) {
258 temp &= ~PORT_TRANS_SEL_MASK;
259 temp |= PORT_TRANS_SEL_CPT(pipe);
260 } else {
261 if (pipe == 1) {
262 temp |= LVDS_PIPEB_SELECT;
263 } else {
264 temp &= ~LVDS_PIPEB_SELECT;
265 }
266 }
267
268 /* set the corresponsding LVDS_BORDER bit */
269 temp &= ~LVDS_BORDER_ENABLE;
270 temp |= pipe_config->gmch_pfit.lvds_border_bits;
271
272 /*
273 * Set the B0-B3 data pairs corresponding to whether we're going to
274 * set the DPLLs for dual-channel mode or not.
275 */
276 if (lvds_encoder->is_dual_link)
277 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
278 else
279 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
280
281 /*
282 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
283 * appropriately here, but we need to look more thoroughly into how
284 * panels behave in the two modes. For now, let's just maintain the
285 * value we got from the BIOS.
286 */
287 temp &= ~LVDS_A3_POWER_MASK;
288 temp |= lvds_encoder->a3_power;
289
290 /*
291 * Set the dithering flag on LVDS as needed, note that there is no
292 * special lvds dither control bit on pch-split platforms, dithering is
293 * only controlled through the PIPECONF reg.
294 */
295 if (IS_GEN4(dev_priv)) {
296 /*
297 * Bspec wording suggests that LVDS port dithering only exists
298 * for 18bpp panels.
299 */
300 if (pipe_config->dither && pipe_config->pipe_bpp == 18)
301 temp |= LVDS_ENABLE_DITHER;
302 else
303 temp &= ~LVDS_ENABLE_DITHER;
304 }
305 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
306 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
307 temp |= LVDS_HSYNC_POLARITY;
308 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
309 temp |= LVDS_VSYNC_POLARITY;
310
311 I915_WRITE(lvds_encoder->reg, temp);
312}
313
314/*
315 * Sets the power state for the panel.
316 */
317static void intel_enable_lvds(struct intel_encoder *encoder,
318 const struct intel_crtc_state *pipe_config,
319 const struct drm_connector_state *conn_state)
320{
321 struct drm_device *dev = encoder->base.dev;
322 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
323 struct drm_i915_private *dev_priv = to_i915(dev);
324
325 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
326
327 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
328 POSTING_READ(lvds_encoder->reg);
329
330 if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 5000))
331 DRM_ERROR("timed out waiting for panel to power on\n");
332
333 intel_panel_enable_backlight(pipe_config, conn_state);
334}
335
336static void intel_disable_lvds(struct intel_encoder *encoder,
337 const struct intel_crtc_state *old_crtc_state,
338 const struct drm_connector_state *old_conn_state)
339{
340 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
341 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
342
343 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
344 if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000))
345 DRM_ERROR("timed out waiting for panel to power off\n");
346
347 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
348 POSTING_READ(lvds_encoder->reg);
349}
350
351static void gmch_disable_lvds(struct intel_encoder *encoder,
352 const struct intel_crtc_state *old_crtc_state,
353 const struct drm_connector_state *old_conn_state)
354
355{
356 intel_panel_disable_backlight(old_conn_state);
357
358 intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
359}
360
361static void pch_disable_lvds(struct intel_encoder *encoder,
362 const struct intel_crtc_state *old_crtc_state,
363 const struct drm_connector_state *old_conn_state)
364{
365 intel_panel_disable_backlight(old_conn_state);
366}
367
368static void pch_post_disable_lvds(struct intel_encoder *encoder,
369 const struct intel_crtc_state *old_crtc_state,
370 const struct drm_connector_state *old_conn_state)
371{
372 intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
373}
374
375static enum drm_mode_status
376intel_lvds_mode_valid(struct drm_connector *connector,
377 struct drm_display_mode *mode)
378{
379 struct intel_connector *intel_connector = to_intel_connector(connector);
380 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
381 int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
382
383 if (mode->hdisplay > fixed_mode->hdisplay)
384 return MODE_PANEL;
385 if (mode->vdisplay > fixed_mode->vdisplay)
386 return MODE_PANEL;
387 if (fixed_mode->clock > max_pixclk)
388 return MODE_CLOCK_HIGH;
389
390 return MODE_OK;
391}
392
393static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
394 struct intel_crtc_state *pipe_config,
395 struct drm_connector_state *conn_state)
396{
397 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
398 struct intel_lvds_encoder *lvds_encoder =
399 to_lvds_encoder(&intel_encoder->base);
400 struct intel_connector *intel_connector =
401 &lvds_encoder->attached_connector->base;
402 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
403 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
404 unsigned int lvds_bpp;
405
406 /* Should never happen!! */
407 if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
408 DRM_ERROR("Can't support LVDS on pipe A\n");
409 return false;
410 }
411
412 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
413 lvds_bpp = 8*3;
414 else
415 lvds_bpp = 6*3;
416
417 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
418 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
419 pipe_config->pipe_bpp, lvds_bpp);
420 pipe_config->pipe_bpp = lvds_bpp;
421 }
422
423 /*
424 * We have timings from the BIOS for the panel, put them in
425 * to the adjusted mode. The CRTC will be set up for this mode,
426 * with the panel scaling set up to source from the H/VDisplay
427 * of the original mode.
428 */
429 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
430 adjusted_mode);
431
432 if (HAS_PCH_SPLIT(dev_priv)) {
433 pipe_config->has_pch_encoder = true;
434
435 intel_pch_panel_fitting(intel_crtc, pipe_config,
436 conn_state->scaling_mode);
437 } else {
438 intel_gmch_panel_fitting(intel_crtc, pipe_config,
439 conn_state->scaling_mode);
440
441 }
442
443 /*
444 * XXX: It would be nice to support lower refresh rates on the
445 * panels to reduce power consumption, and perhaps match the
446 * user's requested refresh rate.
447 */
448
449 return true;
450}
451
452/*
453 * Detect the LVDS connection.
454 *
455 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
456 * connected and closed means disconnected. We also send hotplug events as
457 * needed, using lid status notification from the input layer.
458 */
459static enum drm_connector_status
460intel_lvds_detect(struct drm_connector *connector, bool force)
461{
462 struct drm_i915_private *dev_priv = to_i915(connector->dev);
463 enum drm_connector_status status;
464
465 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
466 connector->base.id, connector->name);
467
468 status = intel_panel_detect(dev_priv);
469 if (status != connector_status_unknown)
470 return status;
471
472 return connector_status_connected;
473}
474
475/*
476 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
477 */
478static int intel_lvds_get_modes(struct drm_connector *connector)
479{
480 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
481 struct drm_device *dev = connector->dev;
482 struct drm_display_mode *mode;
483
484 /* use cached edid if we have one */
485 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
486 return drm_add_edid_modes(connector, lvds_connector->base.edid);
487
488 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
489 if (mode == NULL)
490 return 0;
491
492 drm_mode_probed_add(connector, mode);
493 return 1;
494}
495
496static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
497{
498 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
499 return 1;
500}
501
502/* The GPU hangs up on these systems if modeset is performed on LID open */
503static const struct dmi_system_id intel_no_modeset_on_lid[] = {
504 {
505 .callback = intel_no_modeset_on_lid_dmi_callback,
506 .ident = "Toshiba Tecra A11",
507 .matches = {
508 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
509 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
510 },
511 },
512
513 { } /* terminating entry */
514};
515
516/*
517 * Lid events. Note the use of 'modeset':
518 * - we set it to MODESET_ON_LID_OPEN on lid close,
519 * and set it to MODESET_DONE on open
520 * - we use it as a "only once" bit (ie we ignore
521 * duplicate events where it was already properly set)
522 * - the suspend/resume paths will set it to
523 * MODESET_SUSPENDED and ignore the lid open event,
524 * because they restore the mode ("lid open").
525 */
526static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
527 void *unused)
528{
529 struct intel_lvds_connector *lvds_connector =
530 container_of(nb, struct intel_lvds_connector, lid_notifier);
531 struct drm_connector *connector = &lvds_connector->base.base;
532 struct drm_device *dev = connector->dev;
533 struct drm_i915_private *dev_priv = to_i915(dev);
534
535 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
536 return NOTIFY_OK;
537
538 mutex_lock(&dev_priv->modeset_restore_lock);
539 if (dev_priv->modeset_restore == MODESET_SUSPENDED)
540 goto exit;
541 /*
542 * check and update the status of LVDS connector after receiving
543 * the LID nofication event.
544 */
545 connector->status = connector->funcs->detect(connector, false);
546
547 /* Don't force modeset on machines where it causes a GPU lockup */
548 if (dmi_check_system(intel_no_modeset_on_lid))
549 goto exit;
550 if (!acpi_lid_open()) {
551 /* do modeset on next lid open event */
552 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
553 goto exit;
554 }
555
556 if (dev_priv->modeset_restore == MODESET_DONE)
557 goto exit;
558
559 /*
560 * Some old platform's BIOS love to wreak havoc while the lid is closed.
561 * We try to detect this here and undo any damage. The split for PCH
562 * platforms is rather conservative and a bit arbitrary expect that on
563 * those platforms VGA disabling requires actual legacy VGA I/O access,
564 * and as part of the cleanup in the hw state restore we also redisable
565 * the vga plane.
566 */
567 if (!HAS_PCH_SPLIT(dev_priv))
568 intel_display_resume(dev);
569
570 dev_priv->modeset_restore = MODESET_DONE;
571
572exit:
573 mutex_unlock(&dev_priv->modeset_restore_lock);
574 return NOTIFY_OK;
575}
576
577static int
578intel_lvds_connector_register(struct drm_connector *connector)
579{
580 struct intel_lvds_connector *lvds = to_lvds_connector(connector);
581 int ret;
582
583 ret = intel_connector_register(connector);
584 if (ret)
585 return ret;
586
587 lvds->lid_notifier.notifier_call = intel_lid_notify;
588 if (acpi_lid_notifier_register(&lvds->lid_notifier)) {
589 DRM_DEBUG_KMS("lid notifier registration failed\n");
590 lvds->lid_notifier.notifier_call = NULL;
591 }
592
593 return 0;
594}
595
596static void
597intel_lvds_connector_unregister(struct drm_connector *connector)
598{
599 struct intel_lvds_connector *lvds = to_lvds_connector(connector);
600
601 if (lvds->lid_notifier.notifier_call)
602 acpi_lid_notifier_unregister(&lvds->lid_notifier);
603
604 intel_connector_unregister(connector);
605}
606
607/**
608 * intel_lvds_destroy - unregister and free LVDS structures
609 * @connector: connector to free
610 *
611 * Unregister the DDC bus for this connector then free the driver private
612 * structure.
613 */
614static void intel_lvds_destroy(struct drm_connector *connector)
615{
616 struct intel_lvds_connector *lvds_connector =
617 to_lvds_connector(connector);
618
619 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
620 kfree(lvds_connector->base.edid);
621
622 intel_panel_fini(&lvds_connector->base.panel);
623
624 drm_connector_cleanup(connector);
625 kfree(connector);
626}
627
628static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
629 .get_modes = intel_lvds_get_modes,
630 .mode_valid = intel_lvds_mode_valid,
631 .atomic_check = intel_digital_connector_atomic_check,
632};
633
634static const struct drm_connector_funcs intel_lvds_connector_funcs = {
635 .detect = intel_lvds_detect,
636 .fill_modes = drm_helper_probe_single_connector_modes,
637 .atomic_get_property = intel_digital_connector_atomic_get_property,
638 .atomic_set_property = intel_digital_connector_atomic_set_property,
639 .late_register = intel_lvds_connector_register,
640 .early_unregister = intel_lvds_connector_unregister,
641 .destroy = intel_lvds_destroy,
642 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
643 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
644};
645
646static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
647 .destroy = intel_encoder_destroy,
648};
649
650static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
651{
652 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
653 return 1;
654}
655
656/* These systems claim to have LVDS, but really don't */
657static const struct dmi_system_id intel_no_lvds[] = {
658 {
659 .callback = intel_no_lvds_dmi_callback,
660 .ident = "Apple Mac Mini (Core series)",
661 .matches = {
662 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
663 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
664 },
665 },
666 {
667 .callback = intel_no_lvds_dmi_callback,
668 .ident = "Apple Mac Mini (Core 2 series)",
669 .matches = {
670 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
671 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
672 },
673 },
674 {
675 .callback = intel_no_lvds_dmi_callback,
676 .ident = "MSI IM-945GSE-A",
677 .matches = {
678 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
679 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
680 },
681 },
682 {
683 .callback = intel_no_lvds_dmi_callback,
684 .ident = "Dell Studio Hybrid",
685 .matches = {
686 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
687 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
688 },
689 },
690 {
691 .callback = intel_no_lvds_dmi_callback,
692 .ident = "Dell OptiPlex FX170",
693 .matches = {
694 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
695 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
696 },
697 },
698 {
699 .callback = intel_no_lvds_dmi_callback,
700 .ident = "AOpen Mini PC",
701 .matches = {
702 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
703 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
704 },
705 },
706 {
707 .callback = intel_no_lvds_dmi_callback,
708 .ident = "AOpen Mini PC MP915",
709 .matches = {
710 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
711 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
712 },
713 },
714 {
715 .callback = intel_no_lvds_dmi_callback,
716 .ident = "AOpen i915GMm-HFS",
717 .matches = {
718 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
719 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
720 },
721 },
722 {
723 .callback = intel_no_lvds_dmi_callback,
724 .ident = "AOpen i45GMx-I",
725 .matches = {
726 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
727 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
728 },
729 },
730 {
731 .callback = intel_no_lvds_dmi_callback,
732 .ident = "Aopen i945GTt-VFA",
733 .matches = {
734 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
735 },
736 },
737 {
738 .callback = intel_no_lvds_dmi_callback,
739 .ident = "Clientron U800",
740 .matches = {
741 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
742 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
743 },
744 },
745 {
746 .callback = intel_no_lvds_dmi_callback,
747 .ident = "Clientron E830",
748 .matches = {
749 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
750 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
751 },
752 },
753 {
754 .callback = intel_no_lvds_dmi_callback,
755 .ident = "Asus EeeBox PC EB1007",
756 .matches = {
757 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
758 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
759 },
760 },
761 {
762 .callback = intel_no_lvds_dmi_callback,
763 .ident = "Asus AT5NM10T-I",
764 .matches = {
765 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
766 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
767 },
768 },
769 {
770 .callback = intel_no_lvds_dmi_callback,
771 .ident = "Hewlett-Packard HP t5740",
772 .matches = {
773 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
774 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
775 },
776 },
777 {
778 .callback = intel_no_lvds_dmi_callback,
779 .ident = "Hewlett-Packard t5745",
780 .matches = {
781 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
782 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
783 },
784 },
785 {
786 .callback = intel_no_lvds_dmi_callback,
787 .ident = "Hewlett-Packard st5747",
788 .matches = {
789 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
790 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
791 },
792 },
793 {
794 .callback = intel_no_lvds_dmi_callback,
795 .ident = "MSI Wind Box DC500",
796 .matches = {
797 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
798 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
799 },
800 },
801 {
802 .callback = intel_no_lvds_dmi_callback,
803 .ident = "Gigabyte GA-D525TUD",
804 .matches = {
805 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
806 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
807 },
808 },
809 {
810 .callback = intel_no_lvds_dmi_callback,
811 .ident = "Supermicro X7SPA-H",
812 .matches = {
813 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
814 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
815 },
816 },
817 {
818 .callback = intel_no_lvds_dmi_callback,
819 .ident = "Fujitsu Esprimo Q900",
820 .matches = {
821 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
822 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
823 },
824 },
825 {
826 .callback = intel_no_lvds_dmi_callback,
827 .ident = "Intel D410PT",
828 .matches = {
829 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
830 DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
831 },
832 },
833 {
834 .callback = intel_no_lvds_dmi_callback,
835 .ident = "Intel D425KT",
836 .matches = {
837 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
838 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
839 },
840 },
841 {
842 .callback = intel_no_lvds_dmi_callback,
843 .ident = "Intel D510MO",
844 .matches = {
845 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
846 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
847 },
848 },
849 {
850 .callback = intel_no_lvds_dmi_callback,
851 .ident = "Intel D525MW",
852 .matches = {
853 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
854 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
855 },
856 },
857 {
858 .callback = intel_no_lvds_dmi_callback,
859 .ident = "Radiant P845",
860 .matches = {
861 DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
862 DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
863 },
864 },
865
866 { } /* terminating entry */
867};
868
869static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
870{
871 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
872 return 1;
873}
874
875static const struct dmi_system_id intel_dual_link_lvds[] = {
876 {
877 .callback = intel_dual_link_lvds_callback,
878 .ident = "Apple MacBook Pro 15\" (2010)",
879 .matches = {
880 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
881 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
882 },
883 },
884 {
885 .callback = intel_dual_link_lvds_callback,
886 .ident = "Apple MacBook Pro 15\" (2011)",
887 .matches = {
888 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
889 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
890 },
891 },
892 {
893 .callback = intel_dual_link_lvds_callback,
894 .ident = "Apple MacBook Pro 15\" (2012)",
895 .matches = {
896 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
897 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
898 },
899 },
900 { } /* terminating entry */
901};
902
903struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev)
904{
905 struct intel_encoder *intel_encoder;
906
907 for_each_intel_encoder(dev, intel_encoder)
908 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
909 return intel_encoder;
910
911 return NULL;
912}
913
914bool intel_is_dual_link_lvds(struct drm_device *dev)
915{
916 struct intel_encoder *encoder = intel_get_lvds_encoder(dev);
917
918 return encoder && to_lvds_encoder(&encoder->base)->is_dual_link;
919}
920
921static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
922{
923 struct drm_device *dev = lvds_encoder->base.base.dev;
924 unsigned int val;
925 struct drm_i915_private *dev_priv = to_i915(dev);
926
927 /* use the module option value if specified */
928 if (i915_modparams.lvds_channel_mode > 0)
929 return i915_modparams.lvds_channel_mode == 2;
930
931 /* single channel LVDS is limited to 112 MHz */
932 if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock
933 > 112999)
934 return true;
935
936 if (dmi_check_system(intel_dual_link_lvds))
937 return true;
938
939 /*
940 * BIOS should set the proper LVDS register value at boot, but
941 * in reality, it doesn't set the value when the lid is closed;
942 * we need to check "the value to be set" in VBT when LVDS
943 * register is uninitialized.
944 */
945 val = I915_READ(lvds_encoder->reg);
946 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
947 val = dev_priv->vbt.bios_lvds_val;
948
949 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
950}
951
952static bool intel_lvds_supported(struct drm_i915_private *dev_priv)
953{
954 /*
955 * With the introduction of the PCH we gained a dedicated
956 * LVDS presence pin, use it.
957 */
958 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
959 return true;
960
961 /*
962 * Otherwise LVDS was only attached to mobile products,
963 * except for the inglorious 830gm
964 */
965 if (INTEL_GEN(dev_priv) <= 4 &&
966 IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
967 return true;
968
969 return false;
970}
971
972/**
973 * intel_lvds_init - setup LVDS connectors on this device
974 * @dev_priv: i915 device
975 *
976 * Create the connector, register the LVDS DDC bus, and try to figure out what
977 * modes we can display on the LVDS panel (if present).
978 */
979void intel_lvds_init(struct drm_i915_private *dev_priv)
980{
981 struct drm_device *dev = &dev_priv->drm;
982 struct intel_lvds_encoder *lvds_encoder;
983 struct intel_encoder *intel_encoder;
984 struct intel_lvds_connector *lvds_connector;
985 struct intel_connector *intel_connector;
986 struct drm_connector *connector;
987 struct drm_encoder *encoder;
988 struct drm_display_mode *scan; /* *modes, *bios_mode; */
989 struct drm_display_mode *fixed_mode = NULL;
990 struct drm_display_mode *downclock_mode = NULL;
991 struct edid *edid;
992 i915_reg_t lvds_reg;
993 u32 lvds;
994 u8 pin;
995 u32 allowed_scalers;
996
997 if (!intel_lvds_supported(dev_priv))
998 return;
999
1000 /* Skip init on machines we know falsely report LVDS */
1001 if (dmi_check_system(intel_no_lvds))
1002 return;
1003
1004 if (HAS_PCH_SPLIT(dev_priv))
1005 lvds_reg = PCH_LVDS;
1006 else
1007 lvds_reg = LVDS;
1008
1009 lvds = I915_READ(lvds_reg);
1010
1011 if (HAS_PCH_SPLIT(dev_priv)) {
1012 if ((lvds & LVDS_DETECTED) == 0)
1013 return;
1014 if (dev_priv->vbt.edp.support) {
1015 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
1016 return;
1017 }
1018 }
1019
1020 pin = GMBUS_PIN_PANEL;
1021 if (!intel_bios_is_lvds_present(dev_priv, &pin)) {
1022 if ((lvds & LVDS_PORT_EN) == 0) {
1023 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
1024 return;
1025 }
1026 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
1027 }
1028
1029 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
1030 if (!lvds_encoder)
1031 return;
1032
1033 lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL);
1034 if (!lvds_connector) {
1035 kfree(lvds_encoder);
1036 return;
1037 }
1038
1039 if (intel_connector_init(&lvds_connector->base) < 0) {
1040 kfree(lvds_connector);
1041 kfree(lvds_encoder);
1042 return;
1043 }
1044
1045 lvds_encoder->attached_connector = lvds_connector;
1046
1047 intel_encoder = &lvds_encoder->base;
1048 encoder = &intel_encoder->base;
1049 intel_connector = &lvds_connector->base;
1050 connector = &intel_connector->base;
1051 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
1052 DRM_MODE_CONNECTOR_LVDS);
1053
1054 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
1055 DRM_MODE_ENCODER_LVDS, "LVDS");
1056
1057 intel_encoder->enable = intel_enable_lvds;
1058 intel_encoder->pre_enable = intel_pre_enable_lvds;
1059 intel_encoder->compute_config = intel_lvds_compute_config;
1060 if (HAS_PCH_SPLIT(dev_priv)) {
1061 intel_encoder->disable = pch_disable_lvds;
1062 intel_encoder->post_disable = pch_post_disable_lvds;
1063 } else {
1064 intel_encoder->disable = gmch_disable_lvds;
1065 }
1066 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
1067 intel_encoder->get_config = intel_lvds_get_config;
1068 intel_connector->get_hw_state = intel_connector_get_hw_state;
1069
1070 intel_connector_attach_encoder(intel_connector, intel_encoder);
1071
1072 intel_encoder->type = INTEL_OUTPUT_LVDS;
1073 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
1074 intel_encoder->port = PORT_NONE;
1075 intel_encoder->cloneable = 0;
1076 if (HAS_PCH_SPLIT(dev_priv))
1077 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1078 else if (IS_GEN4(dev_priv))
1079 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1080 else
1081 intel_encoder->crtc_mask = (1 << 1);
1082
1083 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1084 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1085 connector->interlace_allowed = false;
1086 connector->doublescan_allowed = false;
1087
1088 lvds_encoder->reg = lvds_reg;
1089
1090 /* create the scaling mode property */
1091 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT);
1092 allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN);
1093 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1094 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
1095 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1096
1097 intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps);
1098 lvds_encoder->init_lvds_val = lvds;
1099
1100 /*
1101 * LVDS discovery:
1102 * 1) check for EDID on DDC
1103 * 2) check for VBT data
1104 * 3) check to see if LVDS is already on
1105 * if none of the above, no panel
1106 * 4) make sure lid is open
1107 * if closed, act like it's not there for now
1108 */
1109
1110 /*
1111 * Attempt to get the fixed panel mode from DDC. Assume that the
1112 * preferred mode is the right one.
1113 */
1114 mutex_lock(&dev->mode_config.mutex);
1115 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
1116 edid = drm_get_edid_switcheroo(connector,
1117 intel_gmbus_get_adapter(dev_priv, pin));
1118 else
1119 edid = drm_get_edid(connector,
1120 intel_gmbus_get_adapter(dev_priv, pin));
1121 if (edid) {
1122 if (drm_add_edid_modes(connector, edid)) {
1123 drm_mode_connector_update_edid_property(connector,
1124 edid);
1125 } else {
1126 kfree(edid);
1127 edid = ERR_PTR(-EINVAL);
1128 }
1129 } else {
1130 edid = ERR_PTR(-ENOENT);
1131 }
1132 lvds_connector->base.edid = edid;
1133
1134 list_for_each_entry(scan, &connector->probed_modes, head) {
1135 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
1136 DRM_DEBUG_KMS("using preferred mode from EDID: ");
1137 drm_mode_debug_printmodeline(scan);
1138
1139 fixed_mode = drm_mode_duplicate(dev, scan);
1140 if (fixed_mode)
1141 goto out;
1142 }
1143 }
1144
1145 /* Failed to get EDID, what about VBT? */
1146 if (dev_priv->vbt.lfp_lvds_vbt_mode) {
1147 DRM_DEBUG_KMS("using mode from VBT: ");
1148 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
1149
1150 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
1151 if (fixed_mode) {
1152 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1153 connector->display_info.width_mm = fixed_mode->width_mm;
1154 connector->display_info.height_mm = fixed_mode->height_mm;
1155 goto out;
1156 }
1157 }
1158
1159 /*
1160 * If we didn't get EDID, try checking if the panel is already turned
1161 * on. If so, assume that whatever is currently programmed is the
1162 * correct mode.
1163 */
1164 fixed_mode = intel_encoder_current_mode(intel_encoder);
1165 if (fixed_mode) {
1166 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1167 drm_mode_debug_printmodeline(fixed_mode);
1168 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1169 }
1170
1171 /* If we still don't have a mode after all that, give up. */
1172 if (!fixed_mode)
1173 goto failed;
1174
1175out:
1176 mutex_unlock(&dev->mode_config.mutex);
1177
1178 intel_panel_init(&intel_connector->panel, fixed_mode, NULL,
1179 downclock_mode);
1180 intel_panel_setup_backlight(connector, INVALID_PIPE);
1181
1182 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1183 DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1184 lvds_encoder->is_dual_link ? "dual" : "single");
1185
1186 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1187
1188 return;
1189
1190failed:
1191 mutex_unlock(&dev->mode_config.mutex);
1192
1193 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1194 drm_connector_cleanup(connector);
1195 drm_encoder_cleanup(encoder);
1196 kfree(lvds_encoder);
1197 kfree(lvds_connector);
1198 return;
1199}